Reporting of delayed status reports

Abstract

Aspects of the present disclosure relate to reporting of DSRs. In one aspect, a UE triggers reporting of a DSR and sends the DSR to a base station. The DSR indicates a delay state for the first set of LCGs. The first set of LCGs includes one or more LCGs.

Description

Technical Field

[0001] This disclosure relates to wireless communications, and more particularly to user equipment (UE), base stations, and methods for supporting delay status reports (DSR). Background Technology

[0002] A wireless communication system may include one or more network communication devices (such as base stations), which may also be referred to as eNodeB (eNB), next-generation NodeB (gNB), or other suitable terms. Each network communication device (such as a base station) may support wireless communication for one or more user communication devices, which may also be referred to as UE, or other suitable terms. The wireless communication system may support wireless communication with one or more user communication devices by utilizing the resources of the wireless communication system (e.g., time resources (e.g., symbols, time slots, subframes, frames, etc.) or frequency resources (e.g., subcarriers, carriers)). Additionally, the wireless communication system may support wireless communication across a variety of radio access technologies, including third-generation (3G) radio access technology, fourth-generation (4G) radio access technology, fifth-generation (5G) radio access technology, and other suitable radio access technologies above 5G (e.g., sixth-generation (6G)).

[0003] The DSR (Distributed Response Scheduler) reporting procedure is used to provide the base station with the delay status of uplink (UL) data. This delay status includes the remaining time of the UL data, based on the value of its associated timer at the moment the first symbol of the Physical Uplink Shared Channel (PUSCH) transmission in which the DSR is sent, and the amount of data associated with the reported remaining time. DSR reporting can improve UL scheduling. The Buffer Status Report (BSR) procedure is used to provide the base station with information about the amount of UL data. Summary of the Invention

[0004] This disclosure relates to a UE, base station, and method for supporting DSR reporting. Through this UE, base station, and method, DSR can be reported for multiple logical channel groups (LCGs).

[0005] Some implementations of the UE described herein may include: a processor and a transceiver coupled to the processor, wherein the processor is configured to: trigger a DSR report; and transmit a DSR indicating a delay state for a first set of LCGs, the first set of LCGs including one or more LCGs, to a base station via the transceiver.

[0006] In some implementations, each LCG in the first set has a corresponding DSR that can be used for transmission. Alternatively, in some implementations, each LCG in the first set is configured with a report of the corresponding DSR and has data that can be used for transmission. Alternatively, in some implementations, each LCG in the first set has data that can be used for transmission.

[0007] In some implementations, the DSR includes a first field comprising a first bit diagram, and each bit in the first bit diagram is associated with an LCG, and each bit in at least one bit indicates at least one of the following: whether the corresponding LCG has data available for transmission, or whether a report of the corresponding DSR for the corresponding LCG has been triggered, or whether a third field for the corresponding LCG is present in the DSR, the third field indicating the amount of data in the dataset available for transmission in the corresponding LCG.

[0008] In some implementations, LCG is configured for use with the UE, or is configured to allow reporting of DSR.

[0009] In some implementations, the DSR includes a second field comprising a second bitmap, each bit in which is associated with an LCG, and at least one bit in which each bit indicates whether a report of the corresponding DSR for the corresponding LCG has been triggered.

[0010] In some implementations, the DSR includes a third field, and the third field indicates one of the following: a first amount of data in a first dataset available for transmission in a corresponding LCG, the remaining time of the data in the first dataset being less than a first remaining time threshold for the corresponding LCG; a second amount of data in a second dataset available for transmission in a corresponding LCG, the remaining time of the data in the second dataset being less than the first remaining time threshold, and being the shortest remaining time among the remaining times of data available for transmission in a LCG; a third amount of data available for transmission in a corresponding LCG, where the corresponding DSR is not triggered, or the reporting of the corresponding DSR is not configured for the corresponding LCG; or a fourth amount of data in a third dataset available for transmission in a corresponding LCG, the remaining time of the data in the third dataset being the shortest remaining time among the remaining times of data available for transmission in a corresponding LCG, where the corresponding DSR is not triggered, or the reporting of the corresponding DSR is not configured for the corresponding LCG.

[0011] In some implementations, the processor is also configured to: trigger a report based on the determination of the DSR and trigger a report of the buffer status report (BSR), and send at least one of the DSR and BSR in descending order of priority.

[0012] In some implementations, the processor is also configured to: determine the first priority of the DSR as the first highest priority of the logical channel (LCH) with a delay state available for transmission in a first set of LCGs with a delay state available for transmission; and determine the second priority of the BSR as the second highest priority of the LCH with data available for transmission in a second set of LCHs with data available for transmission, the second set of LCGs including one or more LCGs.

[0013] In some implementations, the processor is also configured to determine the priority of the DSR and BSR based on their types.

[0014] In some implementations, the processor is also configured to: trigger a report based on a determined DSR for a first set of LCGs, and trigger a report based on a determined BSR for a second set of LCGs; in each LCG in the first set and the second set of LCGs, transmit at least one of the DSR and BSR in descending order of the highest priority logical channel; the second set of LCGs includes one or more LCGs.

[0015] In some implementations, the first set of LCGs includes multiple LCGs, and the processor is also configured to include the amount of data associated with the latency state for the multiple LCGs in the DSR in descending order of priority.

[0016] In some implementations, the processor is also configured to determine the priority of an LCG among multiple LCGs as the highest priority of the logical channel (LCH) among the LCGs that has a delay state available for transmission.

[0017] In some implementations, multiple LCGs include a first LCG and a second LCG, and the processor is configured to include the amount of data associated with the latency state for the multiple LCGs by: based on determining that a first priority of the first LCG is equal to a second priority of the second LCG, including the amount of data associated with the remaining time of data in the first LCG and the second LCG in the DSR in ascending order of one of the following: the shortest remaining time of data in the first LCG and the second LCG, or a remaining time threshold associated with the first LCG and the second LCG.

[0018] In some implementations, the first set of LCGs includes multiple LCGs, and the processor is also configured to include the amount of data associated with the remaining time of data in the multiple LCGs in the DSR in ascending order of one of the following: the shortest remaining time of data in the multiple LCGs, or the remaining time threshold associated with the multiple LCGs.

[0019] In some implementations, the first set of LCGs includes multiple LCGs, and the processor is further configured to include the amount of data associated with the remaining time in the DSR, in descending order of priority of the multiple LCGs, after including the remaining time of data in the multiple LCGs in the DSR.

[0020] In some implementations, the first set of LCGs includes multiple LCGs, and the processor is also configured to include the amount of data associated with the remaining time in the DSR in descending order of the priority of the multiple LCGs before including the remaining time of the data in the multiple LCGs in the DSR in descending order of the priority of the multiple LCGs.

[0021] In some implementations, the first set of LCGs includes multiple LCGs, and the processor is further configured to exclude at least one of the remaining time and data volume for an LCG based on both the remaining time and the amount of data associated with the remaining time, which determine that the uplink grant is insufficient to accommodate data for one of the multiple LCGs.

[0022] Some implementations of a base station described herein may include: a processor and a transceiver coupled to the processor, wherein the processor is configured to: transmit a DSR to a UE via the transceiver; and receive, via the transceiver, a DSR from the UE indicating a delay state for a first set of LCGs, the first set of LCGs including one or more LCGs.

[0023] Some implementations of a method described herein may include: triggering a DSR report at the UE; and sending a DSR to the base station indicating the delay status for a first set of LCGs, the first set of LCGs including one or more LCGs.

[0024] Some implementations of a method described herein may include: sending a configuration DSR to the UE; and receiving from the UE a DSR indicating a delay state for a first set of LCGs, the first set of LCGs comprising one or more LCGs.

[0025] Some implementations of a processor described herein may include: at least one memory and a controller coupled to the at least one memory and configured such that the controller: triggers a report of a DSR; and sends a DSR to a base station indicating the delay state for a first set of LCGs, the first set of LCGs including one or more LCGs.

[0026] It should be understood that this summary portion is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to be used to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0027] Figure 1 Examples of wireless communication systems supporting DSR reports according to various aspects of this disclosure are shown;

[0028] Figure 2 A signaling diagram illustrating an example process for reporting support of DSR according to various aspects of this disclosure is shown;

[0029] Figure 3 Examples of the format of DSR according to various aspects of this disclosure are shown;

[0030] Figure 4 Examples of the remaining time available for data transmission in an LCG according to various aspects of this disclosure are shown;

[0031] Figures 5 to 7 Examples of the format of DSR according to various aspects of this disclosure are shown respectively;

[0032] Figure 8 An example of a portion of an LCG with a DSR report configured according to various aspects of this disclosure is shown;

[0033] Figure 9 Examples of prioritizing between DSR and BSR for each LCG according to various aspects of this disclosure are shown;

[0034] Figure 10A , Figure 10B and Figure 10C Examples of prioritizing DSRs for multiple LCGs according to various aspects of this disclosure are shown respectively;

[0035] Figure 11 Examples of devices supporting DSR reporting and discarding based on synchronous transport sets, according to some aspects of this disclosure, are shown; and

[0036] Figure 12 Examples of processors supporting DSR drop reports based on synchronous transport sets are shown, according to various aspects of this disclosure; and

[0037] Figure 13 and Figure 14 Flowcharts of methods for supporting DSR reporting according to various aspects of this disclosure are shown respectively. Detailed Implementation

[0038] The principles of this disclosure will now be described with reference to some embodiments. It should be understood that these embodiments are described for illustrative purposes only and to assist those skilled in the art in understanding and implementing this disclosure, and do not imply any limitation on the scope of this disclosure. The disclosure described herein can be implemented in various ways other than those described below.

[0039] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0040] References to "an embodiment," "example embodiment," and "embodiment," etc., in this disclosure indicate that the described embodiments may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment(s). Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, those skilled in the art will recognize that, whether explicitly described or not, incorporating other embodiments to affect such a feature, structure, or characteristic is within their knowledge.

[0041] It should be understood that although the terms “first” and “second”, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may also be referred to as a second element without departing from the scope of the embodiments, and similarly, a second element may also be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the listed terms.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. As used herein, the singular forms “a,” “an,” and “the” also include the plural forms unless the context clearly indicates otherwise. It will also be understood that the terms “comprises,” “comprising,” “has,” “having,” “includes,” and / or “including” as used herein specify the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof.

[0043] As described above, the DSR reporting procedure is used to provide the base station with the latency status of UL data. A new, separate MAC CE for DSR reporting can be defined. For example, DSR reporting may not be coupled with Buffer Status Report (BSR) reporting. Furthermore, the UE can support threshold-based DSR reporting. If DSR is triggered for a Logical Channel Group (LCG), and if more than one LCG has data available for transmission, it is necessary to define which LCGs' DSRs the UE reports and how to design the DSR format.

[0044] In view of the above, this disclosure provides a solution for reporting DSRs. In this solution, the UE triggers the reporting of a DSR and sends the DSR to the base station. The DSR indicates the delay status for a first set of LCGs. The first set of LCGs includes one or more LCGs.

[0045] Various aspects of this disclosure are described in the context of wireless communication systems.

[0046] Figure 1 An example of a wireless communication system 100 supporting DSR reports according to various aspects of this disclosure is shown. The wireless communication system 100 may include at least one network entity 102 (also referred to as a network device (NE)), one or more terminal devices or UEs 104, a core network 106, and a packet data network 108. The wireless communication system 100 may support various radio access technologies. In some implementations, the wireless communication system 100 may be a 4G network, such as an LTE network or an advanced LTE (LTE-A) network. In some other implementations, the wireless communication system 100 may be a 5G network, such as an NR network. In other implementations, the wireless communication system 100 may be a combination of 4G and 5G networks, or other suitable radio access technologies, including IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), and IEEE 802.20. The wireless communication system 100 may support radio access technologies beyond 5G. In addition, the wireless communication system 100 can support technologies such as Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), or Code Division Multiple Access (CDMA).

[0047] Network entity 102 can be collectively referred to as network entity 102, or it can be referred to as network entity 102 alone.

[0048] Network entities 102 may be distributed throughout a geographic area to form a wireless communication system 100. One or more of the network entities 102 described herein may be, include, or may be referred to as network nodes, base stations (BS), network elements, radio access network (RAN) nodes, base transceiver stations, access points, NodeBs, eNodeBs (eNBs), next-generation NodeBs (gNBs), or other suitable terms. Network entities 102 and UE 104 may communicate via communication link 110, which may be a wireless or wired connection. For example, network entities 102 and UE 104 may perform wireless communication (e.g., receive signaling, send signaling) via a Uu interface.

[0049] Network entity 102 can provide a geographic coverage area 112 for which network entity 102 can support services (e.g., voice, video, packet data, messaging, broadcasting, etc.) for one or more UEs 104 within the geographic coverage area 112. For example, network entity 102 and UE 104 can support wireless communication of signals associated with services (e.g., voice, video, packet data, messaging, broadcasting, etc.) based on one or more wireless access technologies. In some implementations, network entity 102 can be mobile, for example, a satellite associated with a non-terrestrial network. In some implementations, different geographic coverage areas 112 associated with the same or different radio access technologies can overlap, but different geographic coverage areas 112 can be associated with different network entities 102. The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0050] One or more UEs 104 may be distributed throughout the geographic area of ​​the wireless communication system 100. UE 104 may include or be referred to as a mobile device, wireless device, remote device, remote unit, handheld device, or subscriber device, or some other suitable term. In some implementations, UE 104 may be referred to as a unit, station, terminal, or client, etc. Alternatively or additionally, UE 104 may be referred to as an Internet of Things (IoT) device, an Internet of Everything (IoE) device, or a Machine Type Communication (MTC) device, etc. In some implementations, UE 104 may be stationary within the wireless communication system 100. In some other implementations, UE 104 may be mobile within the wireless communication system 100.

[0051] One or more UEs 104 can be devices of different forms or with different capabilities. Figure 1Examples of UE 104 are shown below. UE 104 can communicate with various types of devices, such as network entity 102, other UEs 104, or network devices (e.g., core network 106, packet data network 108, relay devices, integrated access and backhaul (IAB) nodes, or another network device), such as... Figure 1 As shown. Alternatively or concurrently, UE 104 may support communication with other network entities 102 or UE 104 that may act as relays in wireless communication system 100.

[0052] UE 104 can also support direct wireless communication with other UE 104s via communication link 114. For example, UE 104 can support direct wireless communication with another UE 104 via a device-to-device (D2D) communication link. In some implementations, such as vehicle-to-vehicle (V2V) deployments, vehicle-to-everything (V2X) deployments, or cellular V2X deployments, communication link 114 may be referred to as a side link. For example, UE 104 can support direct wireless communication with another UE 104 via a PC5 interface.

[0053] Network entity 102 may support communication with core network 106, or with another network entity 102, or both. For example, network entity 102 may interface with core network 106 via one or more backhaul links 116 (e.g., via S1, N2, N2, or another network interface). Network entities 102 may communicate with each other via backhaul links 116 (e.g., via X2, Xn, or another network interface). In some implementations, network entities 102 may communicate directly with each other (e.g., between network entities 102). In some other implementations, network entities 102 may communicate with each other or indirectly (e.g., via core network 106). In some implementations, one or more network entities 102 may include sub-components, such as access network entities, which may be examples of access node controllers (ANCs). An ANC may communicate with one or more UEs 104 via one or more other access network transport entities (which may be referred to as radio headends, smart radio headends, or transmit-receive points (TRPs)).

[0054] In some implementations, network entity 102 can be configured with a decomposed architecture that can utilize protocol stacks physically or logically distributed across two or more network entities 102, such as an Integrated Access Backhaul (IAB) network, an Open Radio Access Network (O-RAN) (e.g., a network configuration sponsored by the O-RAN Alliance), or a Virtualized RAN (vRAN) (e.g., a Cloud RAN (C-RAN)). For example, network entity 102 may include one or more of the following: a Central Unit (CU), a Distributed Unit (DU), a Radio Unit (RU), a RAN Intelligent Controller (RIC) (e.g., a near-real-time RIC, a non-real-time RIC), a Service Management and Orchestration (SMO) system, or any combination thereof.

[0055] An RU can also be referred to as a radio headend, intelligent radio headend, remote radio headend (RRH), remote radio unit (RRU), or transmit-receive point (TRP). In a decomposed RAN architecture, one or more components of network entity 102 can be co-located, or one or more components of network entity 102 can be located in distributed locations (e.g., separate physical locations). In some implementations, one or more network entities 102 in a decomposed RAN architecture can be implemented as virtual units (e.g., virtual CU (VCU), virtual DU (VDU), virtual RU (VRU)).

[0056] The functional splitting among CU, DU, and RU can be flexible and can support different functions depending on the functions performed at the CU, DU, or RU (e.g., network layer functions, protocol layer functions, baseband functions, radio frequency functions, and any combination thereof). For example, protocol stack functional splitting can be adopted between CU and DU, allowing the CU to support one or more layers of the protocol stack, and the DU to support one or more different layers of the protocol stack. In some implementations, the CU can host upper-layer protocol layer (e.g., Layer 3 (L3), Layer 2 (L2)) functions and signaling (e.g., Radio Resource Control (RRC), Service Data Adaptation Protocol (SDAP), Packet Data Convergence Protocol (PDCP)). The CU can be connected to one or more DUs or RUs, and one or more DUs or RUs can host lower-layer protocol layer functions and signaling, such as Layer 1 (L1) (e.g., Physical (PHY) layer) or L2 (e.g., Radio Link Control (RLC) layer, Media Access Control (MAC) layer), and each can be at least partially controlled by the CU 160.

[0057] Alternatively or concurrently, functional splitting of the protocol stack can be employed between the DU and RU, allowing the DU to support one or more layers of the protocol stack, and the RU to support one or more different layers of the protocol stack. The DU can support one or more different cells (e.g., via one or more RUs). In some implementations, functional splitting between the CU and DU, or between the DU and RU, can be within the protocol layer (e.g., some functions of the protocol layer can be performed by one of the CU, DU, or RU, while other functions of the protocol layer are performed by different items in the CU, DU, or RU).

[0058] The CU can be further functionally decomposed into CU control plane (CU-CP) and CU user plane (CU-UP) functions. The CU can be connected to one or more DUs via mid-range communication links (e.g., F1, F1-c, F1-u), and the DUs can be connected to one or more RUs via fronthaul communication links (e.g., open fronthaul (FH) interfaces). In some implementations, the mid-range or fronthaul communication links can be implemented based on interfaces (e.g., channels) between layers of a protocol stack supported by the respective network entity 102 communicating via such communication links.

[0059] Core network 106 can support user authentication, access authorization, tracking, connectivity, and other access, routing, or mobility functions. Core network 106 can be an evolved packet core (EPC) or a 5G core (5GC), which may include control plane entities that manage access and mobility (e.g., a mobility management entity (MME), access and mobility management functions (AMF)) and user plane entities that route packets or interconnects to external networks (e.g., a serving gateway (S-GW), a packet data network (PDN) gateway (P-GW), or a user plane function (UPF)). In some implementations, the control plane entities may manage non-access stratum (NAS) functions, such as mobility, authentication, and bearer management (e.g., data bearers, signaling bearers, etc.) for one or more UEs 104 served by one or more network entities 102 associated with core network 106.

[0060] Core network 106 can communicate with packet data network 108 via one or more backhaul links 116 (e.g., via S1, N2, N2, or another network interface). Packet data network 108 may include application server 118. In some implementations, one or more UEs 104 may communicate with application server 118. UE 104 may establish a session (e.g., Protocol Data Unit (PDU) session, etc.) with core network 106 via network entity 102. Core network 106 can use the established session (e.g., an established PDU session) to route services (e.g., control information, data, etc.) between UE 104 and application server 118. A PDU session may be an example of a logical connection between UE 104 and core network 106 (e.g., one or more network functions of core network 106).

[0061] In the wireless communication system 100, network entity 102 and UE 104 can use the resources of the wireless communication system 100 (e.g., time resources (e.g., symbols, time slots, subframes, frames, etc.) or frequency resources (e.g., subcarriers, carriers)) to perform various operations (e.g., wireless communication). In some implementations, network entity 102 and UE 104 can support different resource structures. For example, network entity 102 and UE 104 can support different frame structures. In some implementations, such as in 4G, network entity 102 and UE 104 can support a single frame structure. In some other implementations, such as in 5G and other suitable radio access technologies, network entity 102 and UE 104 can support various frame structures (i.e., multiple frame structures). Network entity 102 and UE 104 can support various frame structures based on one or more digital technologies.

[0062] One or more digital technologies may be supported in the wireless communication system 100, and the digital technologies may include subcarrier spacing and cyclic prefixes. A first digital technology (e.g., μ = 0) may be associated with a first subcarrier spacing (e.g., 15 kHz) and a normal cyclic prefix. In some implementations, the first digital technology (e.g., μ = 0) associated with the first subcarrier spacing (e.g., 15 kHz) may utilize one time slot per subframe. A second digital technology (e.g., μ = 1) may be associated with a second subcarrier spacing (e.g., 30 kHz) and a normal cyclic prefix. A third digital technology (e.g., μ = 2) may be associated with a third subcarrier spacing (e.g., 60 kHz) and a normal cyclic prefix or an extended cyclic prefix. A fourth digital technology (e.g., μ = 3) may be associated with a fourth subcarrier spacing (e.g., 120 kHz) and a normal cyclic prefix. A fifth digital technology (e.g., μ = 4) may be associated with a fifth subcarrier spacing (e.g., 240 kHz) and a normal cyclic prefix.

[0063] The time intervals of resources (e.g., communication resources) can be organized according to frames (also called radio frames). Each frame can have a duration, for example, 10 milliseconds (ms). In some implementations, each frame can include multiple subframes. For example, each frame can include 10 subframes, and each subframe can have a duration, for example, 1 ms. In some implementations, each frame can have the same duration. In some implementations, each subframe of a frame can have the same duration.

[0064] Alternatively or concurrently, the time intervals of resources (e.g., communication resources) can be organized according to time slots. For example, a subframe may include a certain number (e.g., quantity) of time slots. The number of time slots in each subframe may also depend on one or more digital technologies supported in the wireless communication system 100. For example, a first, second, third, fourth, and fifth digital technology (i.e., μ=0, μ=1, μ=2, μ=3, μ=4) associated with corresponding subcarrier intervals of 15 kHz, 30 kHz, 60 kHz, 120 kHz, and 240 kHz may utilize a single time slot per subframe, two time slots per subframe, four time slots per subframe, eight time slots per subframe, and 16 time slots per subframe, respectively. Each time slot may include a certain number (e.g., quantity) of symbols (e.g., OFDM symbols). In some implementations, the number (e.g., quantity) of time slots for a subframe may depend on the digital technology. For a common cyclic prefix, a time slot may include 14 symbols. For an extended cyclic prefix (e.g., applicable to a 60 kHz subcarrier spacing), a time slot may include 12 symbols. For both regular and extended cyclic prefixes, the relationship between the number of symbols per time slot, the number of time slots per subframe, and the number of time slots per frame can depend on the digital technique. It should be understood that references to a first digital technique (e.g., μ = 0) associated with a first subcarrier spacing (e.g., 15 kHz) can be used interchangeably between subframes and time slots.

[0065] In wireless communication system 100, the electromagnetic (EM) spectrum can be divided into various categories, frequency bands, frequency channels, etc., based on frequency or wavelength. By way of example, wireless communication system 100 can support one or more operating frequency bands, such as frequency range names FR1 (510MHz-7.125GHz), FR2 (24.25GHz-52.6GHz), FR3 (7.125GHz-24.25GHz), FR4 (52.6GHz-114.25GHz), FR4a or FR4-1 (52.6GHz-71GHz), and FR5 (114.25GHz-300GHz). In some implementations, network entity 102 and UE 104 can perform wireless communication on one or more operating frequency bands. In some implementations, FR1 can be used by network entity 102 and UE 104, as well as other devices or apparatuses, for cellular communication traffic (e.g., control information, data). In some implementations, FR2 can be used by network entity 102 and UE 104, as well as other devices or apparatuses, for short-range, high-data-rate capabilities.

[0066] FR1 can be associated with one or more digital technologies (e.g., at least three digital technologies). For example, FR1 can be associated with: a first digital technology (e.g., μ = 0) that includes a subcarrier spacing of 15 kHz; a second digital technology (e.g., μ = 1) that includes a subcarrier spacing of 30 kHz; and a third digital technology (e.g., μ = 2) that includes a subcarrier spacing of 60 kHz. FR2 can be associated with one or more digital technologies (e.g., at least two digital technologies). For example, FR2 can be associated with: a third digital technology (e.g., μ = 2) that includes a subcarrier spacing of 60 kHz; and a fourth digital technology (e.g., μ = 3) that includes a subcarrier spacing of 120 kHz.

[0067] Figure 2 A signaling diagram illustrating an example process 200 for reporting support of DSR according to various aspects of this disclosure is shown. Process 200 may involve Figure 1 UE 104 and base station 102 are shown in the diagram. For discussion purposes, references will be made to... Figure 1 Describe the process 200.

[0068] like Figure 2 As shown, UE 104 receives the configuration of 210DSR from base station 102.

[0069] In some implementations, the DSR configuration may include a remaining time threshold for triggering a DSR report for the LCG.

[0070] Furthermore, UE 104 triggers the 220DSR report based on the DSR configuration.

[0071] In some implementations, if the LCG is configured to allow DSR reporting, then UE 104 triggers a DSR report when the remaining time of UL data in the LCG becomes less than or equal to its associated LCG remaining time threshold. If the DSR report is triggered for the LCG, then the LCG has a DSR available for transmission.

[0072] In some implementations, if no DSR corresponding to an LCG is triggered, and the remaining time of the UL data in the LCG becomes less than or equal to its associated LCG remaining time threshold, then UE 104 triggers the reporting of a DSR for an LCG that is allowed to report DSRs.

[0073] In some implementations, if the UL data of an LCH in an LCG becomes available to the UE's MAC entity, and the remaining time of the UL data becomes less than or equal to the remaining time threshold of its associated LCG, and the UL data has a priority higher than any LCH containing available UL data, or has a triggering DSR belonging to the LCG, then UE 104 triggers the reporting of a DSR for the LCG that is allowed to report DSRs.

[0074] In some implementations, if the UL data of the LCH in the LCG becomes available to the UE's MAC entity, and the remaining time of the UL data becomes less than or equal to the remaining time threshold of its associated LCG, and the UL data has a priority higher than any LCH containing available UL data, or has a triggering DSR belonging to any LCG that is allowed to report DSR, then UE 104 triggers the reporting of a DSR for the LCG that is allowed to report DSR.

[0075] In some implementations, if no DSR corresponding to an LCH is triggered, and the remaining time of UL data in an LCG becomes less than or equal to its associated LCG remaining time threshold, UE 104 triggers a DSR report for the LCH in an LCG that is allowed to report DSRs. In some implementations, if UL data of an LCH becomes available to UE 104's MAC entity, and the remaining time of the UL data becomes less than or equal to its associated LCG remaining time threshold, and the UL data has a higher priority than any LCH containing available UL data, or has a triggering DSR belonging to any LCG that is allowed to report DSRs, then UE 104 triggers a DSR report for the LCH in an LCG that is allowed to report DSRs.

[0076] In some implementations, the UL data in the LCG represents the UL data that can be transmitted in the PDCP entity and / or RLC entity of UE 104.

[0077] In some implementations, UE 104 calculates the remaining time based on the value of the PDCP discard timer. These calculated values ​​can then be reported for different PDU sets in different logical channels.

[0078] In some implementations, upon receiving a PDCP SDU from the upper layer, the sending PDCP entity starts a discard timer associated with that PDCP SDU. When the discard timer for the PDCP SDU expires, or when the successful delivery of the PDCP SDU is confirmed by a PDCP status report, the sending PDCP entity should discard the PDCP SDU and the corresponding PDCP data PDU.

[0079] In some implementations, UE 104 may receive a PDU set discard indication for DRB from base station 102. This indication specifies that if any PDU in the PDU set is not successfully transmitted to base station 102, then all PDUs in the PDU set must be discarded. In such implementations, PDUs in the PDU set may have the same remaining time. For example, the remaining time of a PDU may be the same as the remaining time of the PDU in the PDU set that first arrives at UE 104's PDCP entity.

[0080] Then, UE 104 sends a 230DSR to base station 102. The DSR indicates the delay status for the first set of LCGs. The first set of LCGs includes one or more LCGs.

[0081] In some implementations, each LCG in the first set has a corresponding DSR available for transmission. In other words, reporting of the corresponding DSR is triggered for each LCG in the first set. In such an implementation, UE 104 reports the DSRs of all LCGs, where the reporting of a DSR is triggered if it is for an LCG. In this way, the overhead of reporting DSRs can be reduced compared to reporting DSRs for all LCGs configured to allow reporting DSRs, where some LCGs' DSRs are not triggered.

[0082] For example,

[0083]

[0084] In such an implementation, if only one LCG has a DSR available for transmission, UE 104 reports the DSR for that LCG. The DSR can be a short DSR, which only includes the DSR for one LCG.

[0085] Alternatively, in such an implementation, if more than one LCG has a DSR available for transmission when a Media Access Control (MAC) PDU containing a DSR is to be constructed, then UE 104 reports the DSRs for all LCGs with DSRs available for transmission. The DSR can be a long DSR, which includes DSRs for more than one LCG.

[0086] In some implementations, if the data volume of the LCG triggered by the DSR is zero, the UE may not report the DS for that LCG.

[0087] In some implementations, if the remaining time of the LCG triggered by the DSR is zero, the UE may not report the DS for that LCG.

[0088] In some implementations, UE 104 may send a MAC control element (CE) for DSR to base station 102. For the sake of brevity, the MAC CE for DSR will also be referred to as DSR MAC CE in the following text.

[0089] In some implementations, the data available for transmission is the data to be transmitted in the PDCP entity and / or RLC entity.

[0090] If a DSR report for an LCG is triggered and not canceled, it indicates that the LCG has a usable and pending DSR or DS. In some implementations, if an LCG has a DS available for transmission, the LCG has UL data, and the remaining time of at least one piece of data in the LCG becomes less than or equal to its associated remaining time threshold. In some implementations, if an LCG has a DSR or a delay state (DS) available for transmission, it indicates or implies that the LCG has data available for transmission in the PDCP entity and / or RLC entity, and the remaining time of one piece of data in the LCG becomes less than or equal to its associated LCG remaining time threshold. In some implementations, UL data in the LCG represents usable and pending UL data in the PDCP and / or RLC of the LCG.

[0091] In the following text, reference will be made to Figures 3 to 5 Some examples describing the DSR format.

[0092] Figure 3 Example 300 of the format of a DSR according to various aspects of this disclosure is shown. In example 300, the DSR may include a first field comprising a first bit diagram. Each bit in the first bit diagram is associated with an LCG, and at least one bit in the first bit diagram indicates whether the corresponding LCG has data available for transmission. Hereinafter, the first field is also referred to as the LCG.i Field.

[0093] In some implementations, LCG i The field can indicate LCG i Does it have data available for transmission, where i is the LCGID configured for UE 104?

[0094] For example, there are three LCGs configured for UE 104: LCG#1, LCG#2, and LCG#3. Only LCG#2 and LCG#3 are configured with DSR reporting. i In the fields, LCG1 corresponds to LCG#1, LCG2 corresponds to LCG#2, and LCG3 corresponds to LCG#3.

[0095] In some implementations, LCG i The field can indicate LCG i Whether there is data available for transmission, where i is the ascending order of the LCG identifier (ID) in the LCG configured for UE 104.

[0096] In some implementations, the first and third fields are used to further indicate the delay status for the LCG.

[0097] In some implementations, the first, third, and fourth fields are used to further indicate the delay status for the LCG.

[0098] In some implementations, the first, second, and third fields are used to further indicate the delay status for the LCG.

[0099] In some implementations, the first, second, third, and fourth fields are used to further indicate the delay status for the LCG.

[0100] For example, there are three LCGs configured for UE 104: LCG#1, LCG#2, and LCG#3. Only LCG#2 and LCG#3 are configured with DSR reporting. i In the field, LCG0 corresponds to LCG#1, LCG1 corresponds to LCG#2, and LCG2 corresponds to LCG#3.

[0101] Alternatively, in some implementations, LCG i The field can indicate LCG i Whether there is data available for transmission, where i is the ascending LCGID in an LCG configured to allow DSR reporting.

[0102] For example, there are three LCGs configured for UE 104: LCG#1, LCG#2, and LCG#3. Only LCG#2 and LCG#3 are configured to allow DSR reporting. i In the field, LCG0 corresponds to LCG#2, and LCG1 corresponds to LCG#3.

[0103] Continue to refer to Figure 3 The DSR may also include a second field, which includes a second bitmap. Each bit in the second bitmap is associated with an LCG, and at least one bit in each bit indicates whether a report of the corresponding DSR for the corresponding LCG in the LCG has been triggered. Hereinafter, the second field is also referred to as D... i Field. D i The field can indicate the target LCG i Whether the DSR report is triggered. DSR is set to 1. i Field indication for LCG i The DSR report was triggered. The DSR value was set to 0. i Field indication for LCG i The DSR report was not triggered. In other words, DSR... i The field can indicate the LCG i The presence or absence of a delayed state.

[0104] like Figure 3 As shown, the DSR can also include a third field for the LCG. For LCG i, the third field is also called the buffer size field i. The third field is used to indicate the buffer status for the LCG. The buffer size field i can indicate the buffer status for the LCG when the DSR report is triggered. i And the amount of data to be calculated. In this case, D i The field can indicate the presence or absence of a third field for LCG i. For example, if D i =1 and LCG i =1, or if D i =1, then for LCG i The buffer size field i exists. The third field is used to further indicate the latency status for the LCG.

[0105] Optionally, the DSR may also include a fourth field for the LCG. The presence of the fourth field indicates the shortest remaining time or shortest value range associated with the amount of data for the LCG. The shortest remaining time or shortest value range can be identified by a code index in the table. The fourth field is used to further indicate the latency status for the LCG.

[0106] The third field can indicate the first amount of data in a corresponding LCG within the first set that is available for transmission in the first dataset. The remaining time for the data in the first dataset available for transmission is less than a first remaining time threshold for the corresponding LCG within the first set. Alternatively, the third field can indicate the second amount of data in a corresponding LCG within the first set that is available for transmission in the second dataset. The remaining time for the data in the second set is less than the first remaining time threshold and is the shortest remaining time among the remaining times for data available for transmission in one LCG within the first set. This will be referenced later. Figure 4 Describe it.

[0107] DSR may also include T i Field. T i The field indicates the buffer size table information for the buffer size ID in the buffer size field i.

[0108] Figure 4 Example 400 illustrates the remaining time of data available for transmission in an LCG according to various aspects of this disclosure. In example 400, LCG #1 has packets #0 to 9 available for transmission. Among the packets #0 to 9 available for transmission, the remaining time of packets #0 to 7 is less than or equal to a first remaining time threshold for LCG #1. That is, the first packet set includes packets #0 to 7. A third field may indicate a first amount of data in the first packet set.

[0109] Alternatively, in some implementations, the first packet set may include a second packet subset and a third packet subset. The second packet subset includes packets #0 to #4, and the third packet subset includes packets #5 to #7. The remaining time for packets #0 to #4 is less than or equal to the remaining time for packets #5 to #7. In other words, among the remaining time available for transmission in LCG#1 for packets #0 to #9, the remaining time for packets #0 to #4 is the shortest. In such an implementation, the third field may indicate a second data volume for the second packet subset.

[0110] Figure 5 Example 500 of the format of a DSR according to various aspects of this disclosure is shown. In example 500, the DSR may include a first field (i.e., LCG). i (Fields). The first field in Example 500 has the combined functionality of the first and second fields in Example 300.

[0111] Specifically, the first field includes a first bit diagram. Each bit in the first bit diagram is associated with an LCG, and at least one bit in each bit indicates whether a report for the corresponding DSR for the corresponding LCG within the LCG has been triggered. And / or, at least one bit in the first bit diagram indicates whether a third field exists in the DSR for the corresponding LCG within the LCG. The third field indicates the amount of data in the dataset available for transmission within the corresponding LCG within the LCG.

[0112] For example, LCG i The field can indicate the LCG i Whether the DSR report is triggered, where i is the LCGID, or i is the ascending order of the LCGIDs in the LCG configured for UE 104. Alternatively, LCG i The field can indicate the LCG i Whether a DSR report is triggered, where i is the ascending order of LCG IDs among the LCGs configured to allow DSR reporting. LCGs set to 1... i Field indication for LCG i The DSR report was triggered. The LCG was set to 0. i Field indication for LCG i The DSR report was not triggered. LCG i The field can also indicate the target LCG. i The third field indicates whether it is present or absent. LCGs set to 1 i Field indication for LCG i The existence of the third field. The LCG is set to 0. i Field indication for LCG i The absence of the third field.

[0113] like Figure 5 As shown, the DSR can also include a third field. This third field is also known as the buffer size field i for LCG i. The buffer size field i indicates the buffer size for LCG i when the DSR report is triggered. i And the amount of data to be calculated. For example, if LCG i =1, then for LCG i The buffer size field i exists.

[0114] The third field can indicate the first amount of data in a first dataset available for transmission in a corresponding LCG within the first set of LCGs. The remaining time for the data in the first dataset is less than a first remaining time threshold for the corresponding LCG within the LCG. Alternatively, the third field can indicate the second amount of data in a second dataset available for transmission in a corresponding LCG within the first set of LCGs. The remaining time for the data in the second dataset is less than the first remaining time threshold and is the shortest remaining time among the remaining times of data available for transmission in one LCG, as referenced above. Figure 4 As stated above.

[0115] Alternatively, in some implementations, the first field includes a first bit diagram. Each bit in the first bit diagram is associated with an LCG in the LCG, and at least one bit in each bit indicates whether a report for the corresponding DSR for the corresponding LCG in the LCG has been triggered. Alternatively or additionally, at least one bit in the first bit diagram indicates whether a report for the corresponding LCG in the DSR has been triggered. i The presence or absence of a delayed state.

[0116] For example, each bit indicates whether the DSR contains the third and fourth fields for the corresponding LCG in the LCG. LCG i The field can also indicate the target LCG. i The presence or absence of the third and fourth fields. LCGs set to 1. i Field indication for LCG i The existence of the third and fourth fields. LCG set to 0. i Field indication for LCG i The absence of the third and fourth fields.

[0117] DSR may also include T i Field. T i The field indicates the buffer size table information for the buffer size ID in the buffer size field i for LCGi.

[0118] Alternatively, in some implementations, each LCG in the first set can be configured to report a corresponding DSR and has available and pending data. In this case, the DSR reporting may or may not be triggered for one of the LCGs. In such an implementation, if only one LCG among those configured to allow DSR reporting has data available for transmission, then UE 104 reports a DSR for that LCG. The DSR can be a short DSR.

[0119] Alternatively, if more than one LCG has data available for transmission, or more than one LCG has a DSR available for transmission, when a MAC PDU containing a DSR is to be constructed, then UE 104 reports the DSRs of all LCGs that have data available for transmission and are configured to allow DSR reporting. The DSR can be a long DSR. In this case, DSR reporting may or may not be triggered for one of the LCGs.

[0120] For example,

[0121]

[0122]

[0123] Figure 6 Example 600 of the format of a DSR according to various aspects of this disclosure is shown. In example 600, the DSR may include a first field comprising a first bit diagram. Each bit in the first bit diagram is associated with an LCG, and at least one bit in the first bit diagram indicates whether the corresponding LCG has data available for transmission. Hereinafter, the first field is also referred to as the LCG. i Field.

[0124] In some implementations, each bit in the first bit diagram is associated with an LCG, and at least one bit in the first bit diagram indicates the presence or absence of the third field of the corresponding LCG. i The field can indicate LCG i The presence or absence of the third field, where i is the LCGID, or i is the ascending order of the LCG identifier (ID) in the LCG configured for UE 104.

[0125] In some implementations, LCG i The field can indicate LCG i Whether there is data available for transmission, where i is the LCGID, or i is the ascending order of the LCG identifier (ID) in the LCG configured for UE 104.

[0126] Alternatively, in some implementations, LCG i The field can indicate LCG i Whether there is data available for transmission, where i is the ascending LCG ID in the LCG configured to allow DSR reporting.

[0127] In Example 600, the DSR may also include a second field comprising a second bitmap. Each bit in the second bitmap is associated with an LCG, and at least one bit in the bitmap indicates whether a report for the corresponding DSR for the corresponding LCG has been triggered. Hereinafter, the second field is also referred to as D... i Field. D i The field can indicate the LCG i Whether the DSR report is triggered. DSR is set to 1. i Field indication for LCG i The DSR report was triggered. The DSR value was set to 0. i Field indication for LCG i The DSR report was not triggered. In other words, DSR... i The field can indicate the LCG i The presence or absence of a delayed state.

[0128] In Example 600, the DSR may also include a third field. This third field is also referred to as the buffer size field i for LCGi.

[0129] In some implementations, similar to the third field in Example 300, the third field may indicate a first amount of data in a first dataset available for transmission in a corresponding LCG within the first set of LCGs. The remaining time for data in the first dataset is less than a first remaining time threshold for the corresponding LCG within the LCG. Alternatively, the third field may indicate a second amount of data in a second dataset available for transmission in a corresponding LCG within the first set of LCGs. The remaining time for data in the second dataset is less than the first remaining time threshold and is the shortest remaining time among the remaining times for data available for transmission in one LCG within the LCG.

[0130] For example, if the DSR report is triggered for an LCG, i.e., D0=1 and LCG0=1, the third field indicates the amount of data in the LCG with remaining time less than or equal to the remaining time threshold, or the total amount of data available for transmission in the LCG corresponding to the shortest remaining time.

[0131] Alternatively, in some implementations, if the report of the corresponding DSR is not triggered for the corresponding LCG, the third field may indicate the third amount of data available for transmission in the corresponding LCG.

[0132] For example, if the DSR is not triggered for the LCG, i.e., D0=0 and LCG0=1, the third field indicates the total amount of data calculated for the LCG.

[0133] Alternatively, in some implementations, the third field may indicate the fourth amount of data in the third dataset available for transmission in the corresponding LCG, and if the report of the corresponding DSR is not triggered for the corresponding LCG, the third field may indicate that the remaining time of the data in the third dataset is the shortest remaining time of the data available for transmission in the corresponding LCG.

[0134] For example, if the DSR is not triggered for the LCG, i.e., D0 = 0 and LCG0 = 1, the third field indicates the amount of data calculated for the LCG corresponding to the shortest remaining time. Optionally, a fourth field exists to indicate the shortest remaining time or the range of shortest values ​​associated with the amount of data for the LCG. The shortest remaining time or the range of shortest values ​​can be identified by a code index in the table.

[0135] DSR may also include T i Field. T i The field indicates the buffer size table information for the buffer size ID in the buffer size field i.

[0136] In some implementations, each bit in the second bitmap is associated with an LCG, and at least one bit in the bitmap indicates the presence or absence of the third and fourth fields of the corresponding LCG. i The field can indicate LCG i The presence or absence of the third and fourth fields, where i is the LCGID, or i is the ascending order of the LCGID in the LCG configured for UE 104.

[0137] In the following text, the second field is also referred to as D. i Field. D i The field can indicate the LCG i Whether the DSR report is triggered. DSR is set to 1. i Field indication for LCG i The DSR report was triggered. The DSR value was set to 0. i Field indication for LCG i The DSR report was not triggered. In other words, DSR... i The field can indicate the LCG i The presence or absence of the fourth field. For example, if D0 = 0 and LCG0 = 1, then the third field of LCG exists in the DSR, but the fourth field does not exist. For example, if D0 = 1 and LCG0 = 1, then both the third and fourth fields exist in the DSR.

[0138] Alternatively, in some implementations, if a DSR report is triggered for one of the LCGs, then each LCG in the first set has data available for transmission.

[0139] In some implementations, if a DSR report is triggered, and if more than one LCG has data available for transmission when the MAC PDU containing the DSR is to be constructed, or if more than one LCG has a DSR available for transmission, then UE 104 reports the DSRs of all LCGs that have data available for transmission (and are configured or not configured to allow DSR reports).

[0140] Figure 7 Example 700 of the format of a DSR according to various aspects of this disclosure is shown. In example 700, the DSR may include a first field (i.e., LCG). i The first field includes a first bit diagram. Each bit in at least one bit of the first bit diagram indicates whether a third field (i.e., buffer size field i) exists in the DSR for a corresponding LCG in the LCG. For example, LCG i This field can indicate whether there is a target for LCG in the DSR. i The buffer size field i, where i is LCG i, or the LCGID in the LCG configured for UE 104 in ascending order.

[0141] In Example 700, the DSR may also include a second field (i.e., D... i The second field includes a second bitmap. Each bit in the second bitmap is associated with an LCG, and at least one bit in each bit indicates whether a report for the corresponding DSR for the corresponding LCG in the LCG has been triggered. For example, D i The field can indicate the LCG i Whether the DSR report is triggered. DSR is set to 1. i Field indication for LCG i The DSR report was triggered. The DSR value was set to 0. i Field indication for LCG i The DSR report was not triggered or configured.

[0142] Alternatively, in some implementations, the DSR may also include a second field (i.e., D... i The second field includes a second bitmap. Each bit in the second bitmap is associated with an LCG, and at least one bit in each bit indicates whether a report for the corresponding DSR for the corresponding LCG in the LCG has been triggered. For example, Di The field can indicate the LCG i Whether the DSR report is triggered. DSR is set to 1. i Field indication for LCG i The DSR report was triggered. The DSR value was set to 0. i Field indication for LCG i The DSR report was not triggered or configured. In other words, DSR... i The field can indicate the LCG i The presence or absence of the fourth field. D is set to 1. i The field indicates whether there is a target for LCG in the DSR. i The fourth field. D is set to 0. i This field indicates whether a fourth field exists in the DSR. For example, if D0 = 0 and LCG0 = 1, then the fourth field for LCG is absent. If D0 = 1 and LCG0 = 1, then the fourth field for LCG exists.

[0143] In Example 700, the DSR may also include a third field (i.e., the buffer size field i). Optionally, the presence of a fourth field may indicate the shortest remaining time or the shortest value range associated with the amount of data for the LCG. The shortest remaining time or the shortest value range can be identified by a code index in the table.

[0144] In some implementations, similar to the third field in Example 300, the third field may indicate a first amount of data in a first dataset available for transmission in a corresponding LCG within the first set of LCGs. The remaining time for data in the first dataset is less than a first remaining time threshold for the corresponding LCG within the LCG. Alternatively, the third field may indicate a second amount of data in a second dataset available for transmission in a corresponding LCG within the first set of LCGs. The remaining time for data in the second dataset is less than the first remaining time threshold and is the shortest remaining time among the remaining times for data available for transmission in one LCG within the LCG.

[0145] For example, if the DSR report is triggered for an LCG (i.e., D0=1 and LCG0=1), the third field indicates the amount of data in the LCG with remaining time less than or equal to the remaining time threshold, or the total amount of data available for transmission in the LCG corresponding to the shortest remaining time. Optionally, the presence of the fourth field can indicate the shortest remaining time or the shortest value range associated with the amount of data for the LCG. The shortest remaining time or the shortest value range can be identified by a code index in the table.

[0146] Alternatively, in some implementations, if the report of the corresponding DSR is not triggered, or if the report of the corresponding DSR is not configured for the corresponding LCG in the LCG, the third field may indicate the third amount of data available for transmission in the corresponding LCG in the LCG.

[0147] For example, if DSR is not triggered for LCG, i.e., D0=0 and LCG0=1, the third field indicates the total amount of data calculated for LCG. In this case, DSR reporting is configured for LCG.

[0148] Alternatively, in some implementations, the third field may indicate the fourth amount of data in the third dataset available for transmission in the corresponding LCG within the LCG, and if the corresponding DSR report is not triggered or the corresponding DSR report is not configured for the corresponding LCG within the LCG, then the remaining time of the data in the third dataset is the shortest remaining time of the data available for transmission in the corresponding LCG within the LCG.

[0149] For example, if the DSR is not triggered for the LCG, i.e., D0 = 0 and LCG0 = 1, the third field indicates the amount of data calculated for the LCG corresponding to the shortest remaining time. Optionally, a fourth field exists to indicate the shortest remaining time or the shortest value range associated with the amount of data for the LCG. The shortest remaining time or the shortest value range can be identified by a code index in a table. In some implementations, both the DSR report and the BSR report can be triggered. In such an implementation, UE 104 can send at least one of the DSR and BSR in descending order of priority. UE 104 can prioritize the DSR MAC CE and BSR MAC CE with higher priority during MAC PDU assembly. For example, if the UL authorization is insufficient to accommodate both the DSR and BSR, UE 104 can prioritize the DSR MAC CE and BSR MAC CE with higher priority during MAC PDU assembly.

[0150] In some implementations, UE 104 may determine the first priority of the DSR as the highest priority of the LCH with a delay state available for transmission within a first set of LCGs with a delay state available for transmission. Furthermore, UE 104 may determine the second priority of the BSR as the second highest priority of the logical channel (LCH) with data available for transmission within a second set of LCGs with data available for transmission. This second set of LCGs includes one or more LCGs.

[0151] Figure 8 An example of a portion of an LCG with a DSR report configured according to various aspects of this disclosure is shown. Figure 8 In the example, LCG#1 has a higher priority than LCG#2, and LCG#2 has a higher priority than LCG#3. LCG#1 and LCG#3 are configured with BSR reports. DSR is triggered for LCG#3, and BSR is triggered for both LCG#1 and LCG#3. UE 104 can prioritize BSRs for transmission.

[0152] In some implementations, UE 104 may prioritize the LCG with a delay state available for transmission as the highest priority among the LCGs and the LCH with a delay state available for transmission.

[0153] In some implementations, if the first priority of the DSR is equal to the second priority of the BSR, then UE 104 can prioritize either the DSR or the BSR based on its implementation. Alternatively, UE 104 can predefine whether to prioritize the DSR or the BSR.

[0154] Alternatively, in some implementations, UE 104 may determine the priority of DSR and BSR based on their types.

[0155] In some implementations, the DSR type can be one of the following: regular DSR, periodic DSR, or filled DSR.

[0156] In some implementations, if a DSR report is triggered when the remaining time of UL data in the LCG of UE 104 becomes less than or equal to its associated remaining time threshold, the triggered DSR can be a regular DSR.

[0157] In some implementations, UL resources are allocated, and the number of padding bits is equal to or greater than the size of the DSR MAC CE plus its sub-header; the DSR is referred to as the padding DSR.

[0158] In some implementations, the priority between regular / periodic / filled DSRs and traditional regular / periodic / filled BSRs or new enhanced BSRs (EBSRs) can be defined as shown in Table 1.

[0159] Table 1

[0160]

[0161]

[0162] In Table 1, ">" indicates that the priority of BSR is higher than that of DSR, or the priority of DSR is higher than that of BSR; "=" indicates that the priority of BSR is equal to that of DSR; and "<" indicates that the priority of BSR is lower than that of DSR, or the priority of DSR is lower than that of BSR.

[0163] In some implementations, it is not preferable that the priority of the regular DSR is equal to the priority of the filling BSR.

[0164] In some implementations, it is not preferable to prioritize the regular DSR over the padding BSR.

[0165] In some implementations, it is not preferable to prioritize filling DSRs over regular BSRs.

[0166] In some implementations, it is not preferable to fill the DSR with the same priority as the regular BSR.

[0167] In some implementations, it is not preferable to prioritize periodic DSRs over filling BSRs.

[0168] In some implementations, it is not preferable that the priority of the periodic DSR is equal to the priority of the filling BSR.

[0169] Alternatively, in some implementations, if a DSR report is triggered for a first set of LCGs and a BSR report is triggered for a second set of LCGs, then UE 104 may send at least one of the DSR and BSR in descending order of the highest priority logical channel in each LCG of the first set of LCGs and the second set of LCGs, wherein the second set of LCGs includes one or more LCGs.

[0170] In such an implementation, the highest priority logical channel in each LCG within the first set of LCGs has a delay state available for transmission. In such an implementation, the highest priority logical channel in each LCG within the second set of LCGs has data available for transmission.

[0171] In this implementation, UE 104 can determine the first priority of the DSR as the highest priority of the LCH with a delay state available for transmission within a first set of LCGs with a delay state available for transmission. Furthermore, UE 104 can determine the second priority of the BSR as the highest priority of the LCH with data available for transmission within a second set of LCGs with data available for transmission. This second set of LCGs includes one or more LCGs.

[0172] Figure 9Examples of prioritization between DSR and BSR for each LCG are shown according to various aspects of this disclosure. Figure 9 In the example, LCG#1 has a higher priority than LCG#2, and LCG#2 has a higher priority than LCG#3. UE 104 first prioritizes the DSR and BSR for LCG#1, then prioritizes the BSR for LCG#2, and finally prioritizes the DSR and BSR for LCG#3.

[0173] In some implementations, as referenced above Figure 3 ,as well as Figures 5 to 7 The DSR may exclude the fourth field. The fourth field includes a value indicating the remaining time or remaining time range of the data in the LCG.

[0174] Alternatively, in some implementations, the DSR may include a fourth field. The fourth field includes a value indicating the remaining time or remaining time range of the data in the LCG. Therefore, the fourth field is also referred to as the delay status field. In the following description, some implementations of this disclosure will be illustrated using a DSR that includes a fourth field as an example. For example, this value could be the shortest remaining time for the data in the LCG.

[0175] In some implementations, the first set of LCGs may include multiple LCGs. If DSRs of multiple LCGs are triggered, UE 104 may include the amount of data associated with the delay state for each LCG in the DSR, in descending order of priority. In other words, UE 104 may prioritize the DSRs of LCGs in descending order of priority. This implementation is executed if the UL authorization is insufficient to accommodate all DSRs.

[0176] In some implementations, UE 104 may determine the priority of the LCG as the highest priority of the LCH within the LCG. The LCH with the highest priority may or may not have data available for transmission. Alternatively, the LCH with the highest priority may or may not have a delay state available for transmission. Preferably, the LCH with the highest priority may have a delay state available for transmission.

[0177] Figure 10A Examples of prioritizing DSRs for multiple LCGs according to various aspects of this disclosure are shown. Figure 10AIn the example, DSRs for LCG#1, LCG#2, and LCG#3 are triggered. LCG#1 has a higher priority than LCG#2, and LCG#2 has the same priority as LCG#3. UE 104 may first include the amount of data associated with the delay state for LCG#1, and then include the amount of data associated with the delay states for LCG#2 and LCG#3.

[0178] In some implementations, multiple LCGs may include a first LCG and a second LCG. If the first priority of the first LCG is equal to the second priority of the second LCG, then UE 104 may include the amount of data associated with the remaining time of the data in the first and second LCGs in the DSR in ascending order of the shortest remaining time of the data in the first and second LCGs. For example, in Figure 10A In the example, the priority of LCG#2 is equal to the priority of LCG#3. If the shortest remaining time of data in LCG#2 is less than the shortest remaining time of data in LCG#3, then UE 104 may first include the amount of data associated with the delay state of LCG#2, and then include the amount of data associated with the delay state of LCG#3. If the shortest remaining time of data in LCG#2 is greater than the shortest remaining time of data in LCG#3, then UE 104 may first include the amount of data associated with the delay state of LCG#3, and then include the amount of data associated with the delay state of LCG#2.

[0179] In some implementations, multiple LCGs may include a first LCG and a second LCG. If the first priority of the first LCG is equal to the second priority of the second LCG, then UE 104 may include the amount of data associated with the remaining time of data in the first and second LCGs in the DSR in ascending order of the remaining time thresholds associated with the first and second LCGs. For example, in Figure 10A In the example, LCG#2 has the same priority as LCG#3. If the remaining time threshold associated with LCG#2 is less than the remaining time threshold associated with LCG#3, UE 104 may first include the amount of data associated with the delay state of LCG#2, and then include the amount of data associated with the delay state of LCG#3. If the remaining time threshold associated with LCG#2 is greater than the remaining time threshold associated with LCG#3, UE 104 may first include the amount of data associated with the delay state of LCG#3, and then include the amount of data associated with the delay state of LCG#2.

[0180] In some implementations, if DSRs of multiple LCGs are triggered, UE 104 may disregard the priority of the LCGs. In such an implementation, UE 104 may include the amount of data associated with the remaining time of data in multiple LCGs in the DSR in ascending order of the shortest remaining time of data in the multiple LCGs. This implementation is executed if the UL authorization is insufficient to accommodate all DSRs.

[0181] For example, DSRs for LCG#1, LCG#2, and LCG#3 are triggered. LCG#1 has a higher priority than LCG#2, and LCG#2 has the same priority as LCG#3. The remaining time for data in LCG#2 is greater than the remaining time for data in LCG#3, and the remaining time for data in LCG#3 is greater than the remaining time for data in LCG#1. UE 104 may first include the amount of data associated with the remaining time of data in LCG#1, then include the amount of data associated with the remaining time of data in LCG#3, and finally include the amount of data associated with the remaining time of data in LCG#2.

[0182] Alternatively, in some implementations, if DSRs for multiple LCGs are triggered, UE 104 may disregard the priority of the LCGs. In such an implementation, UE 104 may include the amount of data associated with the remaining time of data in multiple LCGs in the DSR in ascending order of the remaining time thresholds of the multiple LCGs. This implementation is executed if the UL authorization is insufficient to accommodate all DSRs.

[0183] For example, DSRs for LCG#1, LCG#2, and LCG#3 are triggered. LCG#1 has a higher priority than LCG#2, and LCG#2 has the same priority as LCG#3. The remaining time threshold for LCG#2 is greater than the remaining data time threshold for LCG#3, and the remaining time threshold for LCG#3 is greater than the remaining data time threshold for LCG#1. UE 104 may first include the amount of data associated with the remaining time of data in LCG#1, then include the amount of data associated with the remaining time of data in LCG#3, and finally include the amount of data associated with the remaining time of data in LCG#2.

[0184] Alternatively, in some implementations, if DSRs of multiple LCGs are triggered and the UL authorization is insufficient to accommodate all DSRs, UE 104 may first include the remaining time of data in the multiple LCGs in the DSR in descending order of priority, and then include the amount of data associated with the remaining time in the DSR in descending order of priority. In other words, UE 104 may first include the delay status field of the multiple LCGs in the DSR in descending order of priority, and then include the buffer size field of the multiple LCGs in the DSR in descending order of priority. This will refer to... Figure 10B Describe it.

[0185] Figure 10B Examples of prioritizing DSRs for multiple LCGs according to various aspects of this disclosure are shown. Figure 10B In the example, DSRs for LCG#1, LCG#2, and LCG#3 are triggered. LCG#1 has a higher priority than LCG#2, and LCG#2 has a higher priority than LCG#3. UE 104 may first include the delay status field of LCG#1, then the delay status field of LCG#2, and finally the delay status field of LCG#3. Later, UE 104 may first include the buffer size field of LCG#1, then the buffer size field of LCG#2.

[0186] Alternatively, in some implementations, if DSRs of multiple LCGs are triggered, UE 104 may first include the amount of data associated with remaining time in the DSR in descending order of priority of the multiple LCGs, and then include the remaining time of data in the multiple LCGs in the DSR in ascending order of priority of the multiple LCGs. In other words, UE 104 may first include the buffer size field of the multiple LCGs in the DSR in descending order of priority of the multiple LCGs, and then include the delay status field of the multiple LCGs in the DSR in descending order of priority of the multiple LCGs. This will refer to... Figure 10C This is described. If the UL authorization is insufficient to accommodate all DSRs, this implementation takes effect.

[0187] Figure 10C Examples of prioritizing DSRs for multiple LCGs according to various aspects of this disclosure are shown. Figure 10CIn the example, DSRs for LCG#1, LCG#2, and LCG#3 are triggered. LCG#1 has a higher priority than LCG#2, and LCG#2 has a higher priority than LCG#3. UE 104 may first include the buffer size field of LCG#1, and then include the buffer size field of LCG#2. Later, UE 104 may first include the delay status field of LCG#1, then include the delay status field of LCG#2, and finally include the delay status field of LCG#3.

[0188] Alternatively, in some implementations, if a DSR for multiple LCGs is triggered, and the UL authorization is insufficient to accommodate both the remaining time and the amount of data associated with the remaining time for one of the multiple LCGs, then UE 104 may exclude at least one of the remaining time and the amount of data for the LCG. For example, neither the remaining time nor the amount of data for the LCG may be included in the DSR. Alternatively, only the remaining time for the LCG may be included in the DSR. Alternatively, only the amount of data for the LCG may be included in the DSR.

[0189] In some implementations, if both EBSR MAC CE and BSR MAC CE are allowed to be reported in the MAC PDU, UE 104 may need to prioritize EBSR MAC CE and legacy BSR MAC CE during MAC PDU assembly (if both are triggered). This implementation performs this if the UL authorization is insufficient to accommodate all BSRs and EBSRs. The MAC sub-PDU includes the EBSR MAC CE and the MAC sub-header, with fields in the MAC CE or MAC sub-header indicating new BS table information. For example, except for fixed-size MAC CEs, the MAC sub-header consists of the header fields R / F / LCID / (eLCID) / L. The MAC sub-header for fixed-size MAC CEs consists of two header fields, R / LCID / (eLCID). The Logical Channel ID field identifies the logical channel instance corresponding to the type of the corresponding MAC CE.

[0190] In some implementations, the new buffer size table should include support for a narrower range (i.e., granularity) than the traditional buffer size table. The network can configure which BSR table(s) the LCG is eligible to use. The new table has a buffer size level (in bytes) for the 8-bit buffer size field. UE 104 determines which BSR table (i.e., the traditional table or another table) the LCG should use.

[0191] In some implementations, the first EBSR MAC CE may have additional fields to indicate either new buffer size table information or traditional buffer size table information corresponding to the buffer size for the LCG. For example, a bitmap field indicates the buffer size table corresponding to the LCG in the MAC CE, with bit i corresponding to the buffer size table in the MAC CE corresponding to LCGi.

[0192] Alternatively, in some implementations, if a new table is determined to be used for the BSR, the second EBSR MAC CE can use the traditional BSR MAC CE format, where the MAC subheader associated with the BSR MAC CE has a newly assigned LCHID. The new LCHID differs from the LCH ID in the MAC subheader associated with the traditional BSR MAC CE(s). Table 2 provides examples of the new LCHIDs.

[0193] Table 2

[0194]

[0195] In some implementations, if only one MAC CE in the MAC PDU is used for data volume reporting, then either the EBSR format or the traditional BSR format can be used. For example, the EBSR format can be either the first EBSR format or the second EBSR format.

[0196] In some implementations, if UE 104 determines that a new buffer size table should be used for at least LCGs when a BSR is triggered, and at least two LCGs have data available for transmission when a MAC PDU containing a BSR is to be constructed, then a first EBSR format is selected, i.e., a long first EBSR is reported for all LCGs with data available for transmission.

[0197] For example, if UE 104 triggers a regular BSR, there exists more than one LCG with data available for transmission, and a new BS table is determined for the BSR of one LCG, while the old BS table is determined for the BSR of another LCG. The UE reports a long first EBSR for all LCGs with data available for transmission. By using the first EBSR format, reporting two BSR MAC CEs to the NW can be avoided, and lower signaling overhead is expected.

[0198] For example, if UE 104 triggers a padding BSR, then when the BSR is to be constructed, there exists more than one LCG with data available for transmission, and if the new BS table is determined to be a BSR for at least one LCG, and if the number of padding bits is equal to or greater than the size of the long first EBSR plus its subheadings, the UE reports the long first EBSL for all LCGs with data available for transmission.

[0199] For example, if UE 104 triggers a padding BSR, when the BSR is to be constructed, there is more than one LCG with data available for transmission, and if the new BS table is determined to be a BSR for at least one LCG, and if the number of padding bits is greater than the size of the short first EBSR plus its sub-header, but less than the size of the long first EBSR plus its sub-header, and the UE reports the long truncated first EBSR of the LCG(multiple) LCGs with data available for transmission in descending order of the highest priority logical channel (with or without data available for transmission) in each of these LCG(multiple) LCGs, and in ascending order of LCGID if the priorities are the same.

[0200] For example,

[0201]

[0202]

[0203] In some implementations, the legacy BSR format is selected if UE 104 determines that the old buffer size table should be used for all LCGs when BSR is triggered.

[0204] In some implementations, if the EBSR MAC CE used for data volume reporting (e.g., a second EBSR) and the traditional MAC CE are allowed in the MAC PDU, then UE 104 can use the reference by replacing the DSR with the EBSR. Figure 8 and Figure 9 A similar solution as described above.

[0205] In this implementation, UE 104 can transmit at least one of the EBSR and BSR in descending order of priority between the EBSR and the traditional BSR. UE 104 can prioritize the EBSR MAC CE and BSR MAC CE with higher priority during MAC PDU assembly. For example, if the UL authorization is insufficient to accommodate both the EBSR and BSR, UE 104 can prioritize the EBSR MAC CE (e.g., a second EBSR) and BSR MAC CE with higher priority during MAC PDU assembly. The UE reports the buffer status for the first set of LCGs in the EBSR. The UE reports the buffer status for the second set of LCGs in the traditional BSR.

[0206] In some implementations, UE 104 may determine the first priority of the EBSR as the first highest priority of the LCH with data available for transmission in the first set of LCGs. Furthermore, UE 104 may determine the second priority of the conventional BSR as the second highest priority of the logical channel (LCH) with data available for transmission in the second set of LCGs.

[0207] In some implementations, if the first priority of the EBSR is equal to the second priority of the BSR, then UE 104 can prioritize either the EBSR or the BSR based on its implementation. Alternatively, it can be predefined that UE 104 prioritizes either the EBSR or the BSR.

[0208] In some implementations, for a regular BSR triggered for more than one LCG, the UE reports the EBSR format based on the number of LCGs, which has data available for transmission and selects a new buffer size table.

[0209] For example,

[0210]

[0211] In some implementations, for a regular BSR triggered for more than one LCG, the UE reports the EBSR format based on the number of LCGs, which has data available for transmission and selects a traditional buffer size table.

[0212] For example,

[0213]

[0214] Alternatively, in some implementations, UE 104 may determine the priority of EBSR and BSR based on their types.

[0215] In some implementations, the EBSR type can be one of the following: regular EBSR, periodic EBSR, or filling EBSR, depending on which type of EBSR is triggered according to the traditional BSR triggering event in TS 38.321.

[0216] In some implementations, the priority between regular / periodic / filled EBSRs and traditional regular / periodic / filled BSRs can be defined as shown in Table 2.

[0217] Table 2

[0218] Standard BSR Periodic BSR Fill BSR Conventional EBSR >, ==, or < >, ==, or < >, ==, or < Fill EBSR >, ==, or < >, ==, or < >, ==, or < Periodic EBSR >, ==, or < >, ==, or < >, ==, or <

[0219] In Table 2, ">" indicates that the priority of BSR is higher than that of DSR or DSR is higher than that of BSR, "=" indicates that the priority of BSR is equal to that of DSR, and "<" indicates that the priority of BSR is lower than that of DSR or DSR is lower than that of BSR.

[0220] In some implementations, it is not preferable that the priority of the regular EBSR is equal to the priority of the padding BSR.

[0221] In some implementations, it is not preferable to have a lower priority for a regular EBSR than for a padding BSR.

[0222] In some implementations, it is not preferable to prioritize filling EBSRs over regular BSRs.

[0223] In some implementations, it is not preferable to fill the EBSR with the same priority as the regular BSR.

[0224] In some implementations, it is not preferable to prioritize periodic EBSRs over filling BSRs.

[0225] In some implementations, it is not preferable that the priority of the periodic EBSR is equal to the priority of the filling BSR.

[0226] Alternatively, in some implementations, if an EBSR report is triggered for a first set of LCGs and a BSR report is triggered for a second set of LCGs, then UE 104 may send at least one of the EBSR and BSR in descending order of the highest priority logical channel in each LCG of the first set of LCGs and the second set of LCGs, wherein the second set of LCGs includes one or more LCGs.

[0227] In such an implementation, the highest priority logical channel in each LCG within the first set of LCGs has data available for transmission. In such an implementation, the highest priority logical channel in each LCG within the second set of LCGs has data available for transmission.

[0228] In this implementation, UE 104 can determine the first priority of the EBSR as the first highest priority of the LCH with data available for transmission within a first set of LCGs with data available for transmission. Furthermore, UE 104 can determine the second priority of the EBSR as the second highest priority of the LCH with data available for transmission within a second set of LCGs with data available for transmission. This second set of LCGs includes one or more LCGs. Figure 11An example of device 1100 supporting delay reporting and discarding based on a synchronous transmission set according to various aspects of this disclosure is shown. Device 1100 may be an example of base station 102 or UE 104 as described herein. Device 1100 may support wireless communication with one or more network entities 102, UE 104, or any combination thereof. Device 1100 may include components for bidirectional communication, including components for transmitting and receiving communications, such as processor 1102, memory 1104, transceiver 1106, and optionally I / O controller 1108. These components may communicate electronically or be otherwise coupled (e.g., operational ground, communication ground, functional ground, electronic ground, electrical ground) via one or more interfaces (e.g., bus).

[0229] Processor 1102, memory 1104, transceiver 1106, or various combinations thereof or various components thereof may be examples of components for performing various aspects of the present disclosure described herein. For example, processor 1102, memory 1104, transceiver 1106, or various combinations thereof or components thereof may support methods for performing one or more of the operations described herein.

[0230] In some implementations, processor 1102, memory 1104, transceiver 1106, or various combinations or components thereof may be implemented in hardware (e.g., in a communication management circuitry system). The hardware may include a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, configured to or otherwise supporting components for performing the functions described in this disclosure. In some implementations, processor 1102 and memory 1104 coupled to processor 1102 may be configured to perform one or more functions described herein (e.g., by executing instructions stored in memory 1104 by processor 1102).

[0231] For example, according to the examples disclosed herein, processor 1102 may support wireless communication at device 1100. Processor 1102 may be configured to operate to support components for performing: triggering a DSR report at the UE; and sending a DSR to a base station indicating the delay state for a first set of LCGs, the first set of LCGs including one or more LCGs.

[0232] Alternatively, in some implementations, processor 1102 may be configured to support components for performing: sending a DSR to the UE for configuration; and receiving from the UE a DSR indicating a delay state for a first set of LCGs, the first set of LCGs comprising one or more LCGs.

[0233] Processor 1102 may include intelligent hardware devices (e.g., general-purpose processors, DSPs, CPUs, microcontrollers, ASICs, FPGAs, programmable logic devices, discrete gate or transistor logic components, discrete hardware components, or any combination thereof). In some implementations, processor 1102 may be configured to use a memory controller to operate a memory array. In some other implementations, the memory controller may be integrated into processor 1102. Processor 1102 may be configured to execute computer-readable instructions stored in memory (e.g., memory 1104) to cause device 1100 to perform various functions of this disclosure.

[0234] Memory 1104 may include random access memory (RAM) and read-only memory (ROM). Memory 1104 may store computer-readable, computer-executable code, including instructions that, when executed by processor 1102, cause device 1100 to perform the various functions described herein. The code may be stored in a non-transitory computer-readable medium, such as system memory or another type of memory. In some implementations, the code may not be directly executed by processor 1102, but may cause a computer (e.g., when compiled and executed) to perform the functions described herein. In some implementations, memory 1104 may include a basic I / O system (BIOS) that controls basic hardware or software operations, such as interaction with peripheral components or devices.

[0235] I / O controller 1108 can manage input and output signals for device 1100. I / O controller 1108 can also manage peripheral devices not integrated into device M02. In some implementations, I / O controller 1108 can represent a physical connection or port to an external peripheral device. In some implementations, I / O controller 1108 can utilize an operating system, such as... MS Or other known operating systems. In some implementations, the I / O controller 1108 may be implemented as part of a processor, such as processor 1106. In some implementations, a user may interact with device 1100 via the I / O controller 1108 or via hardware components controlled by the I / O controller 1108.

[0236] In some implementations, device 1100 may include a single antenna 1110. However, in other implementations, device 1100 may have more than one antenna 1110 (i.e., multiple antennas), including multiple antenna panels or antenna arrays, which may be able to transmit or receive multiple wireless transmissions concurrently. Transceiver 1106 may communicate bidirectionally via one or more antennas 1110, wired or wireless links, as described herein. For example, transceiver 1106 may represent a wireless transceiver and may communicate bidirectionally with another wireless transceiver. Transceiver 1106 may also include a modem for modulating packets, providing modulated packets to one or more antennas 1110 for transmission, and demodulating packets received from one or more antennas 1110. Transceiver 1106 may include one or more transmit chains, one or more receive chains, or combinations thereof.

[0237] The transmission chain can be configured to generate and transmit signals (e.g., control information, data, packets). The transmission chain may include at least one modulator for modulating data onto a carrier signal, preparing the signal for transmission over a wireless medium. The at least one modulator may be configured to support one or more techniques, such as amplitude modulation (AM), frequency modulation (FM), or digital modulation schemes such as phase shift keying (PSK) or quadrature amplitude modulation (QAM). The transmission chain may also include at least one power amplifier configured to amplify the modulated signal to an appropriate power level suitable for transmission over a wireless medium. The transmission chain may also include one or more antennas 1110 for transmitting the amplified signal into the air or wireless medium.

[0238] The receiver chain can be configured to receive signals (e.g., control information, data, packets) via a wireless medium. For example, the receiver chain may include one or more antennas 1110 for receiving signals over the air or via a wireless medium. The receiver chain may include at least one amplifier (e.g., a low-noise amplifier (LNA)) configured to amplify the received signal. The receiver chain may include at least one demodulator configured to demodulate the received signal and acquire transmitted data by reversing the modulation technique applied during signal transmission. The receiver chain may include at least one decoder for decoding the demodulated signal to receive the transmitted data.

[0239] Figure 12An example of a processor 1200 supporting delay reporting and discarding based on a synchronous transfer set is shown according to various aspects of this disclosure. Processor 1200 may be an example of a processor configured to perform various operations according to the examples described herein. Processor 1200 may include a controller 1202 configured to perform various operations according to the examples described herein. Processor 1200 may optionally include at least one memory 1204, such as an L1 / L2 / L3 cache memory. Additionally or alternatively, processor 1200 may optionally include one or more arithmetic logic units (ALUs) 1206. One or more of these components may be electronically communicated or otherwise coupled (e.g., operative ground, communicative ground, functional ground, electronic ground, electrical ground) via one or more interfaces (e.g., buses).

[0240] Processor 1200 may be a processor chipset and includes a protocol stack (e.g., a software stack) executed by the processor chipset to perform various operations (e.g., receive, acquire, retrieve, send, output, forward, store, determine, identify, access, write, read) according to the examples described herein. The processor chipset may include one or more cores, one or more cache memories (e.g., memory local to the processor chipset or included in the processor chipset (e.g., processor 1200)) or other memories (e.g., random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), etc.).

[0241] Controller 1202 can be configured to manage and coordinate various operations of processor 1200 (e.g., signaling, receiving, acquiring, retrieving, sending, outputting, forwarding, storing, determining, identifying, accessing, writing, and reading) to enable processor 1200 to support various operations according to the examples described herein. For example, controller 1202 can operate as a control unit of processor 1200 to generate control signals that manage the operation of various components of processor 1200. These control signals include enabling or disabling functional units, selecting data paths, initiating memory accesses, and coordinating operation timing.

[0242] Controller 1202 can be configured to fetch (e.g., fetch, retrieve, receive) instructions from memory 1204 and determine subsequent instructions(s) to be executed, enabling processor 1200 to support various operations according to the examples described herein. Controller 1202 can be configured to track the memory addresses of instructions associated with memory 1204. Controller 1202 can be configured to decode instructions to determine the operations to be performed and the operands involved. For example, controller 1202 can be configured to interpret instructions and determine control signals to be output to other components of processor 1200, enabling processor 1200 to support various operations according to the examples described herein. Additionally or alternatively, controller 1202 can be configured to manage data flow within processor 1200. Controller 1202 can be configured to control data transfers between registers, arithmetic logic unit (ALU), and other functional units of processor 1200.

[0243] Memory 1204 may include one or more cache memories (e.g., memory local to processor 1200 or included therein, such as RAM, ROM, DRAM, SDRAM, SRAM, MRAM, flash memory, etc.). In some implementations, memory 1204 may reside within or on the processor chipset (e.g., locally to processor 1200). In some other implementations, memory 1204 may reside outside the processor chipset (e.g., remotely from processor 1200).

[0244] Memory 1204 may store computer-readable, computer-executable code, including instructions that, when executed by processor 1200, cause processor 1200 to perform the various functions described herein. The code may be stored in a non-transitory computer-readable medium, such as system memory or another type of memory. Controller 1202 and / or processor 1200 may be configured to execute computer-readable instructions stored in memory 1204 to cause processor 1200 to perform various functions. For example, processor 1200 and / or controller 1202 may be coupled to or coupled to memory 1204, and processor 1200, controller 1202, and memory 1204 may be configured to perform the various functions described herein. In some examples, processor 1200 may include multiple processors, and memory 1204 may include multiple memories. One or more of the multiple processors may be coupled to one or more of the multiple memories, which may be configured individually or collectively to perform the various functions described herein.

[0245] One or more ALU 1206s can be configured to support a variety of operations, as described in the examples herein. In some implementations, one or more ALU 1206s may reside within or on a processor chipset (e.g., processor 1200). In some other implementations, one or more ALU 1206s may reside outside the processor chipset (e.g., processor 1200). One or more ALU 1206s can perform one or more computations on data, such as addition, subtraction, multiplication, and division. For example, one or more ALU 1206s can receive input operands and an opcode that determines the operation to be performed. One or more ALU 1206s are configured with various logic and arithmetic circuitry, including adders, subtractors, shifters, and logic gates, to process and manipulate data according to the operations. Alternatively or concurrently, one or more ALU 1206 may support logical operations such as AND, OR, XOR, NOR, and NAND, enabling one or more ALU 1206 to handle conditional operations, comparisons, and bitwise operations.

[0246] Processor 1200 may support wireless communication based on the examples disclosed herein. Processor 1200 may be configured to operate to support components for performing: triggering a DSR report at the UE; and sending a DSR to a base station indicating the delay state for a first set of LCGs, the first set of LCGs comprising one or more LCGs.

[0247] Alternatively, in some implementations, processor 1200 may be configured to support components for performing: sending a DSR to the UE; and receiving from the UE a DSR indicating a delay state for a first set of LCGs, the first set of LCGs comprising one or more LCGs.

[0248] Figure 13 A flowchart of a method 1300 for supporting delay reporting according to various aspects of this disclosure is shown. Operation of method 1300 may be implemented by the device or components thereof described herein. For example, operation of method 1300 may be performed by the UE 104 described herein. In some implementations, the device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively or additionally, the device may use dedicated hardware to perform aspects of the described functions.

[0249] At 1310, the method may include a report that triggers the DSR. The operation at 1310 can be performed according to the examples described herein. In some implementations, aspects of the operation at 1310 may be derived from references. Figure 1 The aforementioned device is used to perform this action.

[0250] At 1320, the method may include sending a DSR to the base station indicating a delay state for a first set of LCGs. The first set of LCGs includes one or more LCGs. The operation of 1320 can be performed according to the examples described herein. In some implementations, aspects of the operation of 1320 may be derived from references... Figure 1 The aforementioned device is used to perform this action.

[0251] Figure 14 A flowchart of a method 1400 supporting delay reporting according to various aspects of this disclosure is shown. Operation of method 1400 may be implemented by the device or components thereof described herein. For example, operation of method 1400 may be performed by the base station 102 described herein. In some implementations, the device may execute a set of instructions to control the functional elements of the device to perform the described functions. Alternatively or additionally, the device may use dedicated hardware to perform aspects of the described functions.

[0252] At 1410, the method may include configuration for sending the DSR to the UE. The operation at 1410 can be performed according to the examples described herein. In some implementations, aspects of the operation at 1410 may be derived from references. Figure 1 The aforementioned device is used to perform this action.

[0253] At 1420, the method may include receiving from the UE a DSR indicating a delay state for a first set of LCGs, the first set of LCGs comprising one or more LCGs. The operation of 1420 can be performed according to the examples described herein. In some implementations, aspects of the operation of 1420 may be derived from references... Figure 1 The aforementioned device is used to perform this action.

[0254] It should be noted that, for reference Figures 2 to 10C The implementation of this disclosure described herein is also applicable to device 1100, process 1200, and methods 1300 and 1400.

[0255] It should be noted that the methods described in this paper describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are also possible. Furthermore, aspects from two or more methods can be combined.

[0256] The various illustrative blocks and components disclosed herein can be designed to implement or execute the functions described herein using a general-purpose processor, DSP, ASIC, CPU, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or any combination thereof. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0257] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions can also be physically located in various locations, including being distributed such that portions of the functions are implemented at different physical locations.

[0258] Computer-readable media include both non-transitory computer storage media and communication media, with communication media including any medium that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available medium that can be accessed by a general-purpose or special-purpose computer. By way of example, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable ROM (EEPROM), flash memory, optical disc (CD) ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor.

[0259] As used herein, including in the claims, the article “a” preceding an element is unrestricted and should be understood to mean “at least one” or “one or more” of those elements. The terms “a,” “at least one,” “one or more,” and “at least one of one or more” are interchangeable. As used herein, including in the claims, the word “or” used in a list of items (e.g., a list of items beginning with phrases such as “at least one of…” or “one or more of…” or “one or two of…”) indicates a list of inclusion, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase “based on” should not be construed as a reference to a closed set of conditions. For example, an example step described as “based on condition A” may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase “based on” should be interpreted in the same manner as the phrase “at least partially based on.” Furthermore, as used herein, including in the claims, “set” may include one or more elements.

[0260] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A user equipment (UE), comprising: processor; as well as A transceiver, the transceiver being coupled to the processor, The processor is configured as follows: Triggering Delayed Status Report (DSR) reports; and The transceiver transmits the DSR, which indicates the delay state for a first set of logical channel groups (LCGs), to the base station. The first set of LCGs includes one or more LCGs.

2. The UE of claim 1, wherein each LCG in the first set has a corresponding DSR available for transmission; or Each LCG in the first set is configured with a corresponding DSR report and has data available for transmission; or Each of the LCGs in the first set has data that can be transmitted.

3. The UE of claim 1, wherein the DSR includes a first field, the first field includes a first bit map, and each bit in the first bit map is associated with an LCG in an LCG, and each bit in at least one of the bits indicates at least one of the following: Does a corresponding LCG in the LCG have data available for transmission, or Whether the report for the corresponding DSR of the corresponding LCG in the LCG is triggered, or The presence of a third field in the DSR for the corresponding LCG within the LCG indicates the amount of data in the dataset that can be transmitted within the corresponding LCG.

4. The UE of claim 3, wherein the LCG is configured for the UE or configured with DSR permission reporting.

5. The UE of claim 1, wherein the DSR includes a second field, the second field including a second bitmap, each bit in the second bitmap being associated with an LCG, and each bit in at least one of the bits indicating whether a report of a corresponding DSR for a corresponding LCG in the LCG is triggered.

6. The UE according to claim 1 or 3, wherein the DSR includes a third field, and the third field indicates one of the following: The first amount of data in a first dataset available for transmission in a corresponding LCG of the LCG, wherein the remaining time of the data in the first dataset is lower than a first remaining time threshold for the corresponding LCG of the LCG. The second data volume of the second dataset available for transmission in a corresponding LCG within the LCG, wherein the remaining time of the data in the second dataset is less than the first remaining time threshold, and is the shortest remaining time among the remaining times of the data available for transmission in the LCG within the LCG. The third data volume available for transmission in the corresponding LCG of the LCG, the corresponding DSR is not triggered, or the report of the corresponding DSR is not configured for the corresponding LCG of the LCG, or The fourth data volume of the third dataset available for transmission in the corresponding LCG of the LCG, wherein the remaining time of the data in the third dataset is the shortest remaining time of the data available for transmission in the corresponding LCG of the LCG, the corresponding DSR is not triggered, or the report of the corresponding DSR is not configured for the corresponding LCG of the LCG.

7. The UE according to claim 1, wherein the processor is further configured to: Based on the determination that the report of the DSR is triggered and the report of the Buffer Status Report (BSR) is triggered, at least one of the DSR and the BSR is sent in descending order of priority.

8. The UE of claim 7, wherein the processor is further configured to: The first priority of the DSR is determined as the first highest priority of the logical channel (LCH) with a usable delay state in the first set of the LCGs; and The second priority of the BSR is determined as the second highest priority of the LCH with data available for transmission in the second set of LCHs with data available for transmission, wherein the second set of LCGs includes one or more LCGs.

9. The UE according to claim 7, wherein the processor is further configured to: The priority of the DSR and the BSR is determined based on their types.

10. The UE of claim 1, wherein the processor is further configured to: Based on the fact that the report of the DSR is triggered for the first set of LCGs and the report of the Buffer Status Report (BSR) is triggered for the second set of LCGs, at least one of the DSR and the BSR is sent in descending order of the highest priority logical channel in each LCG in the first set and the second set of LCGs, and the second set of LCGs includes one or more LCGs.

11. The UE of claim 1, wherein the first set of LCGs comprises a plurality of LCGs, and the processor is further configured to: The amount of data associated with the delay state of the plurality of LCGs is included in the DSR in descending order of priority of the plurality of LCGs.

12. The UE of claim 11, wherein the processor is further configured to: The priority of an LCG among the plurality of LCGs is determined as the highest priority of the logical channel (LCH) among the LCGs that has a delay state available for transmission.

13. The UE of claim 11, wherein the plurality of LCGs includes a first LCG and a second LCG, and the processor is configured to include the amount of data associated with the latency state for the plurality of LCGs by: Based on the determination that the first priority of the first LCG is equal to the second priority of the second LCG, the amount of data associated with the remaining time of the data in the first LCG and the second LCG is included in the DSR in ascending order of one of the following: The shortest remaining time for the data in the first LCG and the second LCG, or The remaining time threshold associated with the first LCG and the second LCG.

14. The UE of claim 1, wherein the first set of LCGs comprises a plurality of LCGs, and the processor is further configured to: The amount of data associated with the remaining time of data in the plurality of LCGs is included in the DSR in ascending order of one of the following: The shortest remaining time for the data in the multiple LCGs, or The remaining time threshold associated with the plurality of LCGs.

15. The UE of claim 1, wherein the first set of LCGs comprises a plurality of LCGs, and the processor is further configured to: After including the remaining time of data in the plurality of LCGs in the DSR in descending order of their priority, the amount of data associated with the remaining time is included in the DSR in descending order of the priority of the plurality of LCGs.

16. The UE of claim 1, wherein the first set of LCGs comprises a plurality of LCGs, and the processor is further configured to: Before including the remaining time of data in the plurality of LCGs in the DSR in descending order of their priority, the amount of data associated with the remaining time is included in the DSR in descending order of the priority of the plurality of LCGs.

17. The UE of claim 1, wherein the first set of LCGs comprises a plurality of LCGs, and the processor is further configured to: Based on the determination that the uplink grant is insufficient to accommodate data for one of the plurality of LCGs, the remaining time and the amount of data associated with the remaining time, at least one of the remaining time and the amount of data for the LCG is excluded.

18. A base station, comprising: processor; as well as A transceiver, the transceiver being coupled to the processor, The processor is configured as follows: Configuration for sending Delay Status Reports (DSRs) to User Equipment (UE) via the transceiver; and The transceiver receives from the UE a DSR indicating the delay state for a first set of logical channel groups (LCGs), the first set of LCGs comprising one or more LCGs.

19. A processor for wireless communication, comprising: At least one memory; as well as A controller, coupled to the at least one memory, and configured such that the controller: Trigger Delayed Status Report (DSR) reporting; as well as The DSR is sent to the base station indicating the delay status for a first set of logical channel groups (LCGs), the first set of LCGs comprising one or more LCGs.

20. A method for wireless communication, comprising: At the user equipment (UE), a delay status report (DSR) is triggered; as well as The DSR is sent to the base station indicating the delay status for a first set of logical channel groups (LCGs), the first set of LCGs comprising one or more LCGs.

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