CBIT-based ATP fault detection method and electronic equipment

Abstract

The invention relates to an ATP fault detection method based on CBIT and electronic equipment. The method comprises the steps that a programming language header file of a CBIT detection module is introduced into codes of an ATP system; the ATP system defines an initialization function based on service logic, wherein the initialization function comprises semaphores required for creating an ATP internal process and ATP service logic and semaphores required for CBIT detection; defining a standard interface function interacting with the CBIT detection module in the ATP system; when the ATP system executes the service logic, the CBIT detection module is triggered to execute dynamic fault detection of the ATP system based on a set operation cycle framework and a standard interface function, and fault processing is carried out according to a detection result. Compared with the prior art, the method has the advantages of greatly reducing limitation on ATP development codes, improving fault detection efficiency and accuracy and the like.

Description

Technical Field

[0001] This invention relates to the field of rail transit technology, and in particular to a fault detection method for a CBIT-based automatic train protection system. Background Technology

[0002] In the rail transit sector, the Automatic Train Protection (ATP) system is a critical piece of equipment ensuring train operation safety, and the stability and reliability of its hardware and software are paramount. During train operation, hardware failures in the ATP system can prevent it from correctly and promptly processing operational commands, such as Emergency Brake (EB) commands, door opening commands, and escape commands, thus impacting operational safety. Therefore, fault detection algorithms are necessary during train operation to check for random hardware failures and ensure safe operation.

[0003] Existing fault detection algorithms for ATP systems employ specialized tools to process the C source code of the ATP system, transforming it into redundant coding. Specifically, redundant coding involves first encoding the C source code, adding signature verification to arithmetic and logical operations, ultimately converting it into redundant code. Redundant coding ensures that random hardware failures during train operation occur with a probability meeting the highest Safety Integrity Level 4 (SIL4), leading to coding errors that can be detected by the train system. However, this method imposes numerous restrictions on ATP system developers, such as limitations on defining global variables, writing functions, and using pointers compared to standard programming languages ​​(e.g., but not limited to C and C++), reducing the development efficiency and coding quality of the ATP system.

[0004] A search revealed Chinese invention patent application publication number CN104298599A, which discloses an online self-inspection and slice recovery method for embedded software runtime faults. This method employs a combined offline and online code runtime fault detection mechanism, while simultaneously providing online recovery code segment data. The recovery method specifically includes the following steps: 1) an offline verification processing stage for code segment data; and 2) a real-time detection and online recovery stage for code segments. Multiple sets of redundant code data are used, and checksums are generated offline and compared with online generated checksums, improving the reliability of the detection results. This existing patent application suffers from numerous coding restrictions during the development phase and low development efficiency.

[0005] Achieving both efficiency and accuracy in ATP fault detection has become a technical problem that needs to be solved. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the existing technology and provide an ATP fault detection method and electronic device based on CBIT.

[0007] The objective of this invention can be achieved through the following technical solutions:

[0008] According to one aspect of the present invention, a CBIT-based ATP fault detection method is provided, the method comprising:

[0009] Include the programming language header file for the CBIT detection module in the ATP system code;

[0010] The ATP system is initialized using a defined initialization function; the initialization function includes creating ATP internal processes, semaphores required for ATP business logic, and semaphores required for CBIT detection.

[0011] Define standard interface functions in the ATP system for interaction between the ATP system and the CBIT detection module;

[0012] While the ATP system executes business logic, it triggers the CBIT detection module to perform real-time fault detection of the ATP system based on the set operating cycle framework and defined standard interface functions, and handles faults according to the detection results.

[0013] Preferably, the header file defines the interface function prototype, data structure prototype, and fault detection-related configuration macros of the CBIT detection module, wherein the configuration macros include the detection area, detection flag, and detection result of the ATP system.

[0014] More preferably, the configuration macro definition also includes a dynamic parameter configuration mechanism for the detection region importance coefficient and system operating load of the ATP system.

[0015] Preferably, the ATP system initialization process includes:

[0016] Step S21: Based on the functional requirements of the ATP system, create the internal processes of the ATP system;

[0017] Step S22: While creating the semaphores required for the ATP system business logic, simultaneously create all the semaphores required for CBIT detection.

[0018] More preferably, the ATP internal process includes a main task process, a background task process, and a fault handling process;

[0019] The main task process is responsible for executing the core business functions of speed monitoring and vehicle permit processing;

[0020] Background task processes are used to handle background data loading and processing of non-real-time tasks;

[0021] The fault handling process is used to deal with various faults that occur during operation.

[0022] More preferably, the ATP system initialization process further includes setting detection-related parameters, including detection range, detection frequency, detection sequence, and detection type.

[0023] Preferably, the standard interface functions include an initialization interface function, a detection start function, a detection result acquisition and processing function, a periodic synchronization function, and a fault information transmission function.

[0024] More preferably, the initialization interface function is used to transfer detection-related parameters and detection process settings between the ATP system and the CBIT detection module.

[0025] More preferably, the detection start function is used by the ATP system to determine whether the detection conditions have been met based on the business situation. If yes, the detection start function is called to trigger CBIT to execute the detection according to the detection plan; if no, the ATP system continues to execute the business logic.

[0026] After the detection task is completed, the ATP system obtains the detection results by calling the detection result acquisition and processing function, and takes corresponding countermeasures for faults.

[0027] More preferably, during the operation of the ATP system, the CBIT detection module obtains the operating cycle information of the ATP system at that time by calling the cycle synchronization function, and adjusts the detection rhythm according to the obtained cycle information and preset rules.

[0028] More preferably, when a fault or abnormal condition is detected, the CBIT detection module transmits fault-related information to the ATP system through the fault information transmission function.

[0029] Preferably, the operating cycle framework is as follows: the ATP system sets an operating cycle based on a fixed duration, divides each cycle into several execution interrupts, each execution interrupt corresponds to an execution interrupt number, and rationally allocates different functional modules to the corresponding execution interrupts.

[0030] More preferably, the real-time fault detection process of the ATP system includes: in each operating cycle, the ATP system executes business logic and determines whether it matches the CBIT detection timing. If it does, the CBIT detection module performs detection on the system's core resources according to the test plan; otherwise, it continues to execute business logic until all business operations in this cycle are completed.

[0031] More preferably, determining whether a CBIT detection timing is matched involves the system continuously monitoring the current execution interrupt number and comparing it with a pre-set detection trigger interrupt number. If the two are equal, the CBIT detection module is started to perform the corresponding detection work according to the detection trigger interrupt number.

[0032] According to another aspect of the present invention, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the method described thereon.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] 1) This invention introduces the CBIT header file, defines an initialization function, and, based on a set runtime framework and defined standard interface functions, triggers the CBIT detection module to perform real-time fault detection while the ATP system executes business logic. This method does not impose strict restrictions on the code writing of developers, improves the efficiency of function development and system iteration, and is conducive to timely detection and accurate location of faults.

[0035] 2) The detection function of this invention is flexible and customizable: In order to adapt to the needs of the non-fixed detection range and method of redundancy code detection, developers can freely select the process to be detected, such as the main software process, background task process, fault handling process, etc., in the configuration stage of the initialization function, and set the detection range and detection frequency, adjust the detection type and detection order according to actual needs to meet diverse customized detection needs.

[0036] 3) The CBIT-based detection method of this invention is designed for the ATP system, which operates with a fixed time period and a fixed number of interrupts per period. By using macro definitions to precisely bind specific interrupts to trigger detection, the core system resources such as CPU, code segment, stack, and data segment are monitored at high frequency in each period. This method can quickly detect and accurately locate faults, thereby improving the accuracy and efficiency of fault diagnosis.

[0037] 4) This invention can build a complete fault response mechanism in the ATP system through the standard interface function with CBIT. By using different CBIT error types, faults can be divided into different levels. Depending on the level, the ATP system can take different response strategies to achieve flexible and efficient fault handling. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating the CBIT-based ATP system fault detection method of the present invention.

[0039] Figure 2This is a schematic diagram of the hierarchical collaborative architecture of the ATP system and CBIT detection module, operating system and hardware in this invention;

[0040] Figure 3 This is a schematic diagram of the process by which CBIT performs real-time detection during the operation of the ATP system in this invention. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0042] To address the aforementioned shortcomings, the ATP system can employ a fault detection method based on Continuous Built-in Test (CBIT). This method enables real-time monitoring of the train's hardware status during operation, facilitating timely detection and accurate fault location. The CBIT fault detection method is characterized by not altering the original coding structure; it only requires the introduction of a specific CBIT file. The ATP system and CBIT software exchange information through interface functions, such as... Figure 2 As shown. This solution places no strict restrictions on the code writing for ATP system developers, facilitating feature development and system iteration.

[0043] This embodiment relates to an ATP fault detection method based on CBIT, which integrates the ATP system and the CBIT fault detection module through a modular, loosely coupled design. Figure 1 This method is implemented through the following steps:

[0044] Step S1: Include the programming language header file for the CBIT fault detection module in the ATP system's project code. This header file defines the interface function prototypes of the CBIT module, the data structure prototypes used, and fault detection-related configuration macros (such as detection area, detection flags, detection results, etc.). Specifically, the configuration macros introduce a dynamic parameter configuration mechanism based on the importance coefficient of the detection area and the system's operating load. The values ​​of the detection area importance coefficient and the system's operating load are set by the ATP system developers.

[0045] Step S2: Based on its existing business logic, the ATP system defines an initialization function, which completes the initialization and creation of internal processes and initializes the semaphores required for CBIT detection.

[0046] Step S3: Configure standard interface functions in the ATP system: Define specific operations such as initialization of detection parameters, acquisition of periodic synchronization status, and fault information processing within the interface functions; define the integration and interaction logic between the ATP system and the CBIT detection module. To avoid the execution of CBIT affecting the normal operating efficiency of the ATP system software, CBIT parameters are dynamically configured. An innovative dynamic detection window adaptive algorithm is introduced in setting the detection memory step size, adjusting the single detection memory size in real time through a system load awareness mechanism.

[0047] Step S4: Set the detection timing: After completing subsequent business logic, the ATP system selects an appropriate time to execute CBIT parameter initialization, CBIT detection execution, and other operations based on the operating characteristics of the ATP system. It then runs the detection logic defined in the previous steps and obtains the results. The variable memory used for CBIT online detection employs a word-oriented Abraham algorithm and uses multiple sets of test data to achieve higher diagnostic coverage.

[0048] In step S2, the initialization process of the ATP system is as follows:

[0049] Step S21: Based on the functional requirements of the Automatic Train Protection (ATP) system, the ATP system creates a main task process, a background task process, a fault handling process, and a map loading process. The main task process is responsible for core business functions such as speed monitoring and train operation permit processing; the background task process handles non-real-time or auxiliary tasks such as background data loading and processing; and the fault handling process is used to handle various faults that occur during operation and record downtime logs. Parameters such as detection range, detection frequency, detection sequence, and detection type can also be set. These features form the basic operational framework of the ATP system.

[0050] Step S22: The ATP system performs semaphore initialization and creation. While creating the semaphores required for the ATP system's business logic, all semaphores required for CBIT detection are simultaneously created. These semaphores serve as key resources for detection access control between the ATP system and the CBIT detection module, coordinating their interactive operations and ensuring the orderly execution of fault detection operations.

[0051] In step S3, as Figure 2 The complete CBIT standard interface functions in the ATP system include:

[0052] 1. Initialization Interface Function. The ATP system uses this interface to pass necessary parameters and complete the initial setup and parameter planning of the detection process. The initialization interface function is mainly used to identify the relevant processes that need to be monitored in the ATP system and establish the relationship between processes and detection range; at the same time, it sets the key elements of fault detection, laying the foundation for subsequent fault detection work.

[0053] 2. Detection Start Function. When the CBIT detection module calls this function, it needs to pass in specific detection parameters, which are the key factors triggering the detection action. During function execution, the CBIT detection module enters the corresponding waiting state to obtain operation permissions based on the set parameters. When the ATP system determines that the software has reached the detection execution interruption number and the current business logic load supports CBIT detection, the ATP system releases the corresponding permissions. After obtaining permissions, the CBIT detection module calls the appropriate detection module according to the pre-arranged detection plan to carry out targeted fault diagnosis.

[0054] Regarding the parameter correspondence, for example: if the first parameter is set to perform memory detection and the second parameter is the size of a single memory detection, CBIT will enter a waiting state. Once CBIT starts running, it will execute the corresponding detection mode.

[0055] 3. Detection Result Acquisition and Processing Function. After the CBIT detection module completes its detection task, the ATP system calls this function to acquire relevant data about the detection results. This data includes various information related to the detection status and faults. Based on pre-determined processing criteria, the ATP system takes corresponding measures for detected faults, such as issuing warning signals or activating backup systems.

[0056] 4. Periodic Synchronization Function. During the operation of the ATP system, the CBIT detection module calls this function to obtain the current operating period information of the ATP system (including...). Figure 2 (The cycle number). Based on this cycle information, the CBIT detection module adjusts its own detection rhythm to ensure that the detection operation is coordinated with the operating cycle of the ATP system. Based on the acquired cycle information and preset rules, it determines whether to start the corresponding fault detection, thus achieving a dynamic fault detection mode.

[0057] 5. Fault Information Transmission Function. When the CBIT detection module detects a hardware fault or abnormal condition, it transmits fault-related information to the ATP system through this function. This information includes the error identifier and a general description of the fault. Based on pre-defined error handling procedures, the ATP system performs actions such as recording fault details and switching to backup components according to the received fault information, thereby achieving effective fault control and handling.

[0058] In step S4, CBIT performs real-time fault detection while the ATP system is running, as follows: Figure 3 ,include:

[0059] Step S41: Constructing the operating cycle framework: The ATP system sets an operating cycle based on a fixed duration. Within each cycle (each cycle corresponds to a cycle number), several execution interrupts are divided. Each execution interrupt corresponds to an execution interrupt number. Different functional modules are reasonably allocated to the corresponding interrupts to build the basic time framework for system operation.

[0060] Step S42, Business Processing and Detection Trigger: In each operating cycle, the ATP system processes various business tasks sequentially, including data processing, signal analysis, and information interaction. Simultaneously, the system continuously monitors the current execution interruption number and compares it with a pre-set detection trigger interruption number. If they match, the corresponding detection task of the CBIT detection module is initiated, and step S43 is executed; otherwise, the system continues to the next stage of business processing until all business operations for this cycle are completed.

[0061] Step S43: Core Resource Cyclic Monitoring: The pre-planned detection trigger interrupt numbers correspond to the detection tasks of different core resources in the system, such as performance detection, integrity detection, and status detection. Based on the matching status of the execution phase, the CBIT detection module performs periodic detection on the system's core resources in sequence, achieving high-frequency, comprehensive monitoring of core resources. After the detection is completed, proceed to step S44.

[0062] Step S44, Result Processing and Cycle Iteration: After the CBIT detection module completes the detection, the ATP system obtains the detection results and classifies the detected problems according to predetermined rules. The CBIT detection module feeds back the problem information to the ATP system, prompting the system to take countermeasures such as warnings, module switching, or system protection. After the CBIT detection ends, if the current cycle has not ended, the ATP system continues to process the remaining execution stages of the business within that cycle; when all execution stages within the cycle are completed (i.e., the current cycle ends), the next operating cycle begins (cycle number increments), and the process returns to step S42 to repeat the above process. By using different CBIT error types, faults are classified into different levels. Depending on the level, the ATP system can adopt different response strategies to achieve flexible and efficient fault handling.

[0063] The aforementioned solutions impose fewer restrictions on developers and can improve development efficiency. Redundancy code detection imposes many restrictions on programmers, disabling common programming structures and increasing development difficulty and time costs. In contrast, the CBIT detection method does not restrict developers from using normal C programming syntax. In the development of the ATP system, developers can freely use various syntaxes to implement functions, reducing logical errors caused by alternative solutions, greatly improving development efficiency, shortening project development cycles, reducing development costs, and avoiding reduced code readability and reusability due to alternative solutions, thus improving code quality.

[0064] The electronic device of this invention includes a central processing unit (CPU), which can perform various appropriate actions and processes according to computer program instructions stored in read-only memory (ROM) or loaded from a storage unit into random access memory (RAM). The RAM may also store various programs and data required for device operation. The CPU, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0065] Multiple components in the device are connected to the I / O interface, including: input units such as keyboards and mice; output units such as various types of displays and speakers; storage units such as disks and optical discs; and communication units such as network interface cards (NICs), modems, and wireless transceivers. The communication unit allows the device to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0066] The processing unit performs the various methods and processes described above. For example, in some embodiments, the methods may be implemented as computer software programs tangibly contained in a machine-readable medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and / or installed on the device via ROM and / or a communication unit. When the computer program is loaded into RAM and executed by the CPU, one or more steps of the methods described above may be performed. Alternatively, in other embodiments, the CPU may be configured to execute the methods by any other suitable means (e.g., by means of firmware).

[0067] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0068] The program code used to implement the methods of the present invention can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code can be executed entirely on the machine, partially on the machine, as a standalone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0069] In the context of this invention, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0070] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A CBIT-based ATP fault detection method, characterized in that, The method includes: Include the programming language header file for the CBIT detection module in the ATP system code; The ATP system is initialized using a defined initialization function; the initialization function includes creating ATP internal processes, semaphores required for ATP business logic, and semaphores required for CBIT detection. Define standard interface functions for interaction with the CBIT detection module in the ATP system; While the ATP system executes business logic, it triggers the CBIT detection module to perform real-time fault detection of the ATP system based on the set operating cycle framework and defined standard interface functions, and handles faults according to the detection results.

2. The ATP fault detection method based on CBIT according to claim 1, characterized in that, The header file defines the interface function prototype, data structure prototype, and fault detection-related configuration macros of the CBIT detection module. The configuration macros include the detection area, detection flag, and detection result of the ATP system.

3. The ATP fault detection method based on CBIT according to claim 2, characterized in that, The configuration macro definitions also include a dynamic parameter configuration mechanism for the detection region importance coefficient of the ATP system and the system operating load.

4. The ATP fault detection method based on CBIT according to claim 1, characterized in that, The ATP system initialization process includes: Step S21: Based on the functional requirements of the ATP system, create the internal processes of the ATP system; Step S22: While creating the semaphores required for the ATP system business logic, simultaneously create all the semaphores required for CBIT detection.

5. The ATP fault detection method based on CBIT according to claim 4, characterized in that, The ATP internal processes include a main task process, a background task process, and a fault handling process; The main task process is responsible for executing the core business functions of speed monitoring and vehicle permit processing; Background task processes are used to handle background data loading and processing of non-real-time tasks; The fault handling process is used to deal with various faults that occur during operation.

6. The ATP fault detection method based on CBIT according to claim 4, characterized in that, The ATP system initialization process also includes setting detection-related parameters, including detection range, detection frequency, detection sequence, and detection type.

7. The ATP fault detection method based on CBIT according to claim 1, characterized in that, The standard interface functions include an initialization interface function, a detection start function, a detection result acquisition and processing function, a periodic synchronization function, and a fault information transmission function.

8. The ATP fault detection method based on CBIT according to claim 7, characterized in that, The initialization interface function is used to transfer detection-related parameters and detection process settings between the ATP system and the CBIT detection module.

9. The ATP fault detection method based on CBIT according to claim 7, characterized in that, The detection start function is used by the ATP system to determine whether the detection conditions have been met based on the business situation. If yes, the detection start function is called to trigger CBIT to execute the detection according to the detection plan; if no, the ATP system continues to execute the business logic. After the detection task is completed, the ATP system obtains the detection results by calling the detection result acquisition and processing function, and takes corresponding countermeasures for faults.

10. The ATP fault detection method based on CBIT according to claim 7, characterized in that, During the operation of the ATP system, the CBIT detection module obtains the operating cycle information of the ATP system at that time by calling the cycle synchronization function, and adjusts the detection rhythm according to the obtained cycle information and preset rules.

11. The ATP fault detection method based on CBIT according to claim 7, characterized in that, When a fault or abnormal condition is detected, the CBIT detection module transmits fault-related information to the ATP system through the aforementioned fault information transmission function.

12. The ATP fault detection method based on CBIT according to claim 1, characterized in that, The operational cycle framework is as follows: the ATP system sets an operational cycle based on a fixed duration, divides each cycle into several execution interrupts, and each execution interrupt corresponds to an execution interrupt number, so that different functional modules are reasonably allocated to the corresponding execution interrupts.

13. The ATP fault detection method based on CBIT according to claim 1, characterized in that, The real-time fault detection process of the ATP system includes: in each operating cycle, the ATP system executes business logic and determines whether it matches the CBIT detection timing. If it does, the CBIT detection module performs detection on the system's core resources according to the test plan; otherwise, it continues to execute business logic until all business operations in this cycle are completed.

14. The ATP fault detection method based on CBIT according to claim 13, characterized in that, The specific timing for determining whether a CBIT detection match is achieved is as follows: The system continuously monitors the current execution interrupt number and compares it with the pre-set detection trigger interrupt number. If the two are equal, the CBIT detection module is started to perform the corresponding detection work according to the detection trigger interrupt number.

15. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the program, it implements the method as described in any one of claims 1 to 14.

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