Fault injection system, method and device, computer equipment and storage medium

Abstract

The invention discloses a fault injection system, method and device, computer equipment and a storage medium, and relates to the technical field of system testing, and the system comprises a fault sequence acquisition module and a signal adjustment module; the server mainboard sends a fault injection command to a fault injection system and controls the fault injection system to perform fault injection operation; a fault sequence acquisition module of the fault injection system acquires a fault sequence; and a signal adjustment module of the fault injection system obtains the data transmission signal from the server mainboard, adjusts the data transmission signal by using the fault sequence to obtain a target signal containing the first fault information, and transmits the target signal to the to-be-tested device to complete fault injection. The problems that fault injection depends on an external control panel, the system architecture is complex, and the accuracy and the real-time performance of fault injection are poor can be solved. The system does not need to be externally connected with a control panel and an additional power supply, is simple in system architecture, does not need to additionally develop firmware, and supports the real-time adjustment of the fault injection process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of system testing, and in particular to a fault injection system, method, device, computer equipment and storage medium. BACKGROUND

[0002] Fault injection is a technique for testing system reliability and fault tolerance, which artificially introduces faults to evaluate the performance of the device under test under abnormal conditions, and is widely used in hardware verification, software testing, fault tolerance system evaluation and other fields.

[0003] Currently, fault injection requires an external control board, which connects the fault injection device and the system under test through a cable. The firmware and software need to be developed separately for the control board, which increases the complexity and cost of the fault injection system. In addition, the fault injection device and the control board need to be operated separately, and data transmission is performed through a cable, which results in poor accuracy and real-time performance of fault injection, making it difficult to meet the testing requirements of high-bandwidth interfaces. SUMMARY

[0004] Therefore, the present application provides a fault injection system, method, device, computer equipment and storage medium to solve the problem that fault injection relies on external control boards, the system architecture is complex, and the accuracy and real-time performance of fault injection are poor.

[0005] In a first aspect, the present application provides a fault injection system, which comprises a fault sequence acquisition module and a signal adjustment module.

[0006] The fault sequence acquisition module is connected to the server mainboard through a first predetermined interface, and is configured to acquire a fault sequence when receiving a fault injection command sent by the server mainboard through the first predetermined interface, and transmit the fault sequence to the signal adjustment module.

[0007] The signal adjustment module is connected to the server mainboard through the first predetermined interface, and is configured to acquire a data transmission signal from the server mainboard through the first predetermined interface, and adjust the data transmission signal using the fault sequence to obtain a target signal containing first fault information.

[0008] The signal adjustment module is connected to the device under test through a second predetermined interface, and is configured to transmit the target signal to the device under test through the second predetermined interface to complete fault injection.

[0009] In a second aspect, the present application provides a fault injection method, which is applied to a fault injection system, and comprises the following steps:

[0010] Acquiring a fault sequence when receiving a fault injection command sent by the server mainboard through a first predetermined interface.

[0011] The data transmission signal is obtained from the server mainboard through the first preset interface, and the data transmission signal is adjusted by using the fault sequence to obtain a target signal containing first fault information.

[0012] The target signal is transmitted to the device to be tested through the second preset interface to complete the fault injection.

[0013] In a third aspect, the present application provides a fault injection device, which comprises:

[0014] The sequence acquisition module is configured to acquire the fault sequence when the fault injection command sent by the server mainboard is received through the first preset interface.

[0015] The fault injection module is configured to obtain the data transmission signal from the server mainboard through the first preset interface, and adjust the data transmission signal by using the fault sequence to obtain a target signal containing first fault information.

[0016] The signal transmission module is configured to transmit the target signal to the device to be tested through the second preset interface to complete the fault injection.

[0017] In a fourth aspect, the present application provides a computer device, which comprises a memory and a processor, the memory and the processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the fault injection method of the second aspect or any of the corresponding embodiments thereof.

[0018] In a fifth aspect, the present application provides a computer readable storage medium, which stores computer instructions, and the computer instructions are used to make a computer execute the fault injection method of the second aspect or any of the corresponding embodiments thereof.

[0019] In a sixth aspect, the present application provides a computer program product, which comprises computer instructions, and the computer instructions are used to make a computer execute the fault injection method of the second aspect or any of the corresponding embodiments thereof.

[0020] Through the application, the server mainboard sends a fault injection command to the fault injection system to control the fault injection system to perform a fault injection operation; the fault sequence acquisition module of the fault injection system acquires a fault sequence; the signal adjustment module of the fault injection system acquires a data transmission signal from the server mainboard, and adjusts the data transmission signal to obtain a target signal containing first fault information by using the fault sequence, and transmits the target signal to the device to be tested to complete the fault injection. It can solve the problem that fault injection depends on external control boards, the system architecture is complex, and the accuracy and real-time performance of fault injection are poor. The system uses the firmware in the server to realize unified control and remote management of the fault injection system, and can control and monitor the fault injection process in real time. The system is highly integrated, the system architecture is simple, no external control board and additional power supply are needed, supports injection of multiple fault modes, and is suitable for rapid deployment and use in various environments. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the specific embodiments or related art of the present application, the drawings needed to be used in the specific embodiments or related art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0022] Figure 1 is a structural schematic diagram of a fault injection system according to an embodiment of the present application;

[0023] Figure 2 is a schematic diagram of the fault injection principle of the signal adjustment module according to an embodiment of the present application;

[0024] Figure 3 is a flowchart of a fault injection method according to an embodiment of the present application;

[0025] Figure 4 is a flowchart of another fault injection method according to an embodiment of the present application;

[0026] Figure 5 is a flowchart of generating a fault sequence according to an embodiment of the present application;

[0027] Figure 6 is a structural block diagram of a fault injection device according to an embodiment of the present application;

[0028] Figure 7 is a hardware structure schematic diagram of a computer device of an embodiment of the present application. DETAILED DESCRIPTION

[0029] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0030] Fault injection is a technique used to test system reliability and fault tolerance by artificially introducing faults to evaluate the performance of the device under test under abnormal conditions. It is widely used in hardware verification, software testing, fault-tolerant system evaluation, etc. With the increasing complexity and performance requirements of server systems, traditional fault injection methods such as external interference sources or control boards have deficiencies in accuracy, real-time performance and integration.

[0031] Traditional fault injection methods usually require an external control board to connect the fault injection device and the device under test through a cable. The control board needs to be developed with separate firmware and software, which increases the complexity and cost of the test system. In addition, the accuracy and real-time performance of the fault injection method through the control board are poor, and it is difficult to meet the testing requirements of high-bandwidth interfaces such as PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) interface. PCIe is an important high-speed data transmission interface in modern servers, and its stability and reliability are crucial to system performance. Therefore, the traditional fault injection method has a complex system architecture, relies on external devices and cables, and has high development and maintenance costs. The accuracy and real-time performance of fault injection are insufficient, and it is difficult to meet the testing requirements of high-bandwidth interfaces. The development and maintenance costs are high, and the compatibility is poor. It lacks integration and remote management capabilities, and the testing efficiency is low. The traditional fault injection method lacks flexibility and is difficult to simulate complex random fault scenarios.

[0032] Based on the above, the embodiment of the application provides a fault injection system, which is designed to be connected with a server mainboard through a PCIe golden finger and a PCIe slot, and connected with a to-be-tested device through the PCIe slot and the PCIe golden finger. The power supply and control signals of the fault injection system come from the server, and a power supply or control signals need not be separately provided. The server indicates the fault injection system to obtain a fault sequence through a control signal, adjusts a data transmission signal by using the fault sequence, obtains a signal containing fault information, and finally transmits the signal containing fault information to the to-be-tested device to test the to-be-tested device and complete fault injection. The BMC (Baseboard Management Controller) firmware in the server is used to realize unified control and remote management of the fault injection system, and test efficiency and flexibility are improved. The fault injection system significantly simplifies the system architecture, reduces cost and complexity, improves test efficiency and reliability, and is suitable for rapid deployment and use in various environments. The system has high integration, does not need an external control board and additional power supply, is plug and play, integrates power supply and control, simplifies the system architecture, reduces cost, does not need additional firmware development, shortens the development cycle, reduces maintenance cost, has high compatibility, can realize real-time control and monitoring, has modular design, and the like.

[0033] According to the embodiment of the application, a fault injection system is provided, as shown in the figure, which comprises a fault sequence acquisition module and a signal adjustment module. Figure 1 The fault sequence acquisition module is connected with the server mainboard through a first preset interface, and is configured to acquire a fault sequence when a fault injection command sent by the server mainboard is received through the first preset interface, and transmit the fault sequence to the signal adjustment module.

[0034] The signal adjustment module is connected with the server mainboard through the first preset interface, and is configured to acquire a data transmission signal from the server mainboard through the first preset interface, and adjust the data transmission signal by using the fault sequence to obtain a target signal containing first fault information.

[0035] The signal adjustment module is connected with the to-be-tested device through a second preset interface, and is configured to transmit the target signal to the to-be-tested device through the second preset interface to complete fault injection.

[0036] Specifically, as shown in the figure,

[0037] Specifically, as shown in the figure, Figure 1As shown, the fault injection system comprises a fault sequence acquisition module and a signal adjustment module. The first preset interface is, for example, a PCIe interface. The fault injection system is designed in the form of a standard PCIe HHHL (half-height half-length) card and is embedded between a server mainboard and a device under test (DUT). The fault injection system is connected to the server mainboard through a PCIe gold finger 2 and a PCIe slot 2. The second preset interface is, for example, a PCIe interface. The fault injection system is connected to the device under test through a PCIe gold finger 1 and a PCIe slot 1. For example, the fault injection system is connected to the server through a PCIe x16 gold finger of the fault injection system and a PCIe x16 slot of the server mainboard, and the fault injection system is connected to the device under test through a PCIe x16 gold finger of the device under test and a PCIe x16 slot of the fault injection system. The fault injection system is directly plugged into the server, and the device under test is plugged into the fault injection system, forming a chain connection. Here, PCIe x16 means that the PCIe interface can support 16 data transmission channels at the same time. Power supply and communication are realized through the PCIe interface of the server, without the need for additional power supply or control signals, for example, as shown in the figure. Figure 1 As shown, the server mainboard supplies power to the fault injection system through a P3V3_AUX power supply signal. The fault injection system is connected to the server through a standard PCIe interface, is compatible with multiple servers and devices under test, does not need to be customized for different devices, improves the universality and applicability of the system, is suitable for multiple test scenarios, and reduces development and maintenance costs.

[0038] A field-programmable gate array (FPGA) is present on the fault injection system. A fault sequence generation unit, a fault sequence transmission unit, and a switch control unit are set in the field-programmable gate array. The fault sequence generation unit and the fault sequence transmission unit are combined into a fault sequence acquisition module, and the switch control unit and a preset number of channel switches are combined into a signal adjustment module. The preset number is, for example, N, and the preset number means that the number of multiple is not limited.

[0039] The unified control and remote management of the fault injection system are realized by using the baseboard management controller firmware in the server, dynamic fault injection is realized, a unified control interface is provided by the baseboard management controller firmware, and a user can remotely control the fault injection system through a management interface of the server, the state and running condition of the fault injection are monitored in real time, remote debugging and data analysis are supported. The baseboard management controller firmware sends a fault injection command to the fault injection system through a first preset interface, for example, an SMBUS (System Management Bus) bus is used to send an SMBUS command, that is, the fault injection command, to the fault injection system. In the case where the fault injection system receives the fault injection command through the first preset interface, a fault sequence is obtained by using a fault sequence acquisition module, for example, a pseudo-random sequence (PRBS); or a sequence that is periodically repeated within a certain time, for example, 100100110010011001001…, that is, the fault sequence is 1001001 that is repeatedly generated within a certain time with a period of 7. The fault sequence acquisition module transmits the fault sequence to a signal adjustment module.

[0040] The signal adjustment module obtains a data transmission signal from the server mainboard through the first preset interface, and adjusts the data transmission signal according to the fault sequence, such as adjusting the closing or opening of the channel switch, to realize the fault injection function, obtain a target signal containing first fault information, control the opening and closing of the PCIe signal through a high-speed switch, and accurately control the duration, frequency and position of the fault. The period of the fault sequence is the same as the number of signal channels contained in the corresponding communication protocol of the second preset interface, for example: the communication protocol is PCIe protocol, containing 7 signal channels, containing 25 signal channels, etc. The specific number of signal channels is set according to actual needs. The signal channels respectively transmit PRESENT_N, PERST_N, WAKE_N, P3V3, P12V, etc. Among them, PRESENT_N is a device presence detection signal, which is used to indicate whether the PCIe device is inserted into the slot. When the device is inserted, the signal is usually low. When the device is pulled out, the signal becomes high. PERST_N is a global reset signal. The server mainboard triggers this signal to reset the device under test and initialize the hardware state. WAKE_N is a wake-up event signal. The device under test wakes up the host system in a low-power state through this signal. P12V is a 12V main power signal input. P3V3 is a 3.3V main power signal input. In addition, the server mainboard inputs P3V3_AUX signal to the field programmable gate array through the PCIe channel. This signal is to provide a 3.3V auxiliary (AUX) signal to the field programmable gate array. SMB_SCL is the system management bus serial clock line, and SMB_SDA is the system management bus serial data line.

[0041] The signal adjustment module adjusts the closing or opening of the channel switch according to the fault sequence to realize the fault injection function, for example: the preset interface contains 7 signal channels, and the fault sequence is 100100110010011001001… The fault sequence is a sequence with a period of 7. In a certain period of time, 1001001 is repeated continuously. In this fault sequence, the data bit corresponding to the first signal channel is 1, the data bit corresponding to the second signal channel is 0, and so on. The channel switch corresponding to the data bit 1 is opened, and the channel switch corresponding to the data bit 0 is closed. The above fault injection function can simulate complex random fault scenarios, and improve the authenticity and comprehensiveness of the test. By controlling the opening and closing mode of the switch, various power failure types can be simulated, such as power interruption, voltage drop, voltage spike, etc.

[0042] The signal adjustment module is connected with the device under test through the second preset interface. The signal adjustment module transmits the target signal to the device under test through the second preset interface to complete the fault injection.

[0043] The embodiment provides a fault injection system. A server mainboard sends a fault injection command to the fault injection system to control the fault injection system to perform a fault injection operation. A fault sequence acquisition module of the fault injection system acquires a fault sequence. A signal adjustment module of the fault injection system acquires a data transmission signal from the server mainboard, adjusts the data transmission signal by using the fault sequence to obtain a target signal containing first fault information, and transmits the target signal to a device to be tested to complete the fault injection. The system uses firmware in the server to realize unified control and remote management of the fault injection system, and can control and monitor the fault injection process in real time. The system is highly integrated, has a simple system architecture, does not need an external control board and an additional power supply, supports injection of various fault modes, and is suitable for rapid deployment and use in various environments. The system solves the problems of dependence of fault injection on an external control board, complexity of a system architecture, and poor accuracy and real-time performance of fault injection.

[0044] As an optional embodiment, the fault sequence acquisition module comprises a fault sequence generation unit and a fault sequence transmission unit.

[0045] The fault sequence generation unit is configured to acquire a sequence size parameter and a fault distribution parameter, and generate a fault sequence according to the sequence size parameter and the fault distribution parameter.

[0046] The fault sequence transmission unit is configured to transmit the fault sequence to the signal adjustment module.

[0047] Specifically, as shown in the figure, the fault sequence acquisition module comprises a fault sequence generation unit and a fault sequence transmission unit. Figure 1

[0048] The fault sequence generation unit acquires a sequence size parameter and a fault distribution parameter. For example, the fault sequence is a pseudo-random binary sequence, and the sequence size parameter comprises a PRBS order, an initial state and a generating polynomial. The PRBS order can determine the length, period and complexity of the fault sequence. For example, the PRBS order is n, the sequence period is 2n, and the complexity is 2n-1. The fault distribution parameter is used to determine the proportion of different fault types in the fault sequence. For example, the fault distribution parameter is a fault type distribution vector, and the length of the fault type distribution vector is equal to the number of fault types. The fault type distribution vector is used to determine the proportion of different fault types in the fault sequence. For example, the fault type distribution vector is [0.5, 0.5], which means that the proportion of the first fault type in the fault sequence is 0.5, and the proportion of the second fault type in the fault sequence is 0.5. n ​-1. The fault distribution parameter can control the density of faults in the fault sequence. For example, when the fault distribution parameter is m, the fault density is 50% when m=2, and the fault density is 1 / 256 when m=256. The fault sequence generation unit generates a fault sequence according to the sequence size parameter and the fault distribution parameter. For example, when the PRBS order in the sequence size parameter is 3, the period of the sequence is determined to be 7, and the fault density is determined to be 3 / 7 according to the fault distribution parameter. The generated fault sequence is 100100110010011001001…, and the fault sequence is a sequence with a period of 7, which continuously repeats 1001001 in a certain time. The fault density of the fault sequence is 3 / 7. By adjusting the sequence size parameter and the fault distribution parameter, the frequency, density, and duration of fault injection can be dynamically adjusted, and a fault sequence containing multiple fault modes can be generated. The fault modes include single-bit error, multi-bit error, burst error, etc. The fault sequence transmission unit transmits the fault sequence to the signal adjustment module.

[0049] In this embodiment, the fault sequence is generated according to the sequence size parameter and the fault distribution parameter. By adjusting the sequence size parameter and the fault distribution parameter, a fault sequence containing multiple fault modes is generated, which supports dynamic adjustment of the frequency, fault density, and duration of fault injection, so as to test the performance of the system under different fault densities and more comprehensively evaluate the robustness of the system. In addition, the generated fault sequence has randomness and controllability, which facilitates comprehensive testing of the device under test.

[0050] As an optional embodiment, the signal adjustment module includes a switch control unit and a preset number of channel switches.

[0051] The switch control unit is configured to determine whether there is a data bit with a value equal to a first preset value in the fault sequence, and to take the data bit with the value equal to the first preset value as a target data bit.

[0052] The switch control unit is further configured to take the channel switch corresponding to the target data bit as a to-be-disconnected channel switch, control the to-be-disconnected channel switch to be disconnected, and control the channel switches other than the to-be-disconnected channel switch to be connected.

[0053] Specifically, as Figure 2As shown, the switch control unit is arranged in the field programmable gate array, and a channel switch is added to each signal channel of the PCIe protocol. The channel switch can be a traditional switch or a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor). The signal channels include, for example, a REFCLK+ signal and a REFCLK- signal, which are differential reference clocks. The server mainboard provides a synchronous clock to the device under test through the pair of signals to ensure the accuracy of the data transmission timing. CLKREQ_N is a clock request signal. The device under test requests the server mainboard to start the reference clock through the signal for energy-saving management. The REFCLK+ and REFCLK- reference clock signals are used to synchronize the data transmission at both ends of the PCIe link. The REFCLK+ and REFCLK- are a pair of differential signals, which provide a stable clock source to ensure the accuracy of data transmission. CLKREQ_N is a clock request signal, which is used to control the clock frequency and power state of the device. When the device needs to wake up, the clock can be restarted through the signal. PCIE0 to PCIE16 are PCIe data channels. PRESENT_N is a device presence detection signal, which is used to indicate whether the PCIe device is inserted into the slot. When the device is inserted, the signal is usually low. When the device is removed, the signal becomes high. PERST_N is a global reset signal. The server mainboard triggers the signal to reset the device under test and initializes the hardware state. WAKE_N is a wake-up event signal. The device under test wakes up the host system in a low-power state through the signal. P12V is a 12V main power signal input. P3V3 is a 3.3V main power signal input. In addition, the server mainboard inputs a P3V3_AUX signal to the field programmable gate array through the PCIe channel. The signal is used to provide a 3.3V auxiliary signal to the field programmable gate array.

[0054] The switch control unit adjusts the closing or opening of the channel switch according to the fault sequence to realize the fault injection function. The first preset value is, for example, 1 or other values. The switch control unit determines whether there is a data bit with a value equal to the first preset value in the fault sequence, and takes the data bit with the value equal to the first preset value as a target data bit. For example, the first preset value is 1, the preset interface includes 7 signal channels, and the fault sequence is 100100110010011001001001… The fault sequence is a sequence with a period of 7, and 1001001 is repeated continuously in a certain time. In the fault sequence, the data bit corresponding to the first signal channel is 1, the data bit corresponding to the second signal channel is 0, and so on. The data bit with a value equal to 1 is taken as the target data bit. The switch control unit takes the channel switch corresponding to the target data bit as a to-be-opened channel switch, controls the to-be-opened channel switch to be opened, and controls the channel switches other than the to-be-opened channel switch to be closed. For example, in the fault sequence, the data bit corresponding to the first signal channel is 1, the data bit corresponding to the second signal channel is 0, and so on. The channel switch corresponding to the data bit with a value of 1 is opened, and the channel switch corresponding to the data bit with a value of 0 is closed.

[0055] The above fault injection function combines the PRBS sequence with the high-speed switch to control the on-off of the PCIe signal, and realizes high-precision fault injection. For example, the on-off state of the high-speed switch is controlled according to the bit value (0 or 1) of the PRBS sequence. Complex random fault scenarios can be simulated to improve the authenticity and comprehensiveness of the test. By controlling the on-off mode of the switch, various power failure types such as power interruption, voltage drop, and voltage spike can be simulated.

[0056] In the embodiment, the on-off state of the channel switch is controlled according to the data bit in the fault sequence to realize the addition of fault information to the data transmission signal, obtain the target signal, and complete the fault injection. The above fault injection method can adapt to the high-bandwidth characteristics of the high-bandwidth interface, can simulate complex random fault scenarios, and can improve the authenticity and comprehensiveness of the test. In addition, by adjusting the fault sequence, the fault density and mode can be dynamically adjusted to adapt to different test requirements. The fault sequence is combined with the channel switch to realize high-precision and real-time fault injection.

[0057] According to the embodiments of the present application, a fault injection method for a server is provided. It should be noted that the steps shown in the flowchart can be executed in a computer system such as a group of computer executable instructions, for example, a computer, a server, etc. Although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0058] In the embodiment, a fault injection method is provided, Figure 3is a flowchart of a fault injection method according to an embodiment of the present application, as shown in Figure 3 The flowchart includes the following steps:

[0059] Step S301, in the case where a fault injection command sent by a server mainboard is received through a first preset interface, a fault sequence is acquired.

[0060] Specifically, as shown in Figure 1 The fault injection system includes a fault sequence acquisition module and a signal adjustment module. The first preset interface is, for example, a PCIe interface. The fault injection system is connected to the server mainboard through a PCIe golden finger 2 and a PCIe slot 2. The second preset interface is, for example, a PCIe interface. The fault injection system is connected to the device to be tested through a PCIe golden finger 1 and a PCIe slot 1.

[0061] The baseboard management controller firmware in the server is used to realize unified control and remote management of the fault injection system, realize dynamic fault injection, provide a unified control interface through the baseboard management controller firmware, and users can remotely control the fault injection system through the management interface of the server, monitor the state and running condition of the fault injection in real time, support remote debugging and data analysis. The baseboard management controller firmware sends a fault injection command to the fault injection system through the first preset interface. In the case where the fault injection command is received through the first preset interface, the fault sequence acquisition module is used to acquire a fault sequence, which is, for example, a Pseudo-Random Binary Sequence (PRBS); or a sequence that is periodically repeated within a certain time, such as 100010011000100110001001…, that is, the fault sequence is 10001001 that is repeatedly transmitted within a certain time with a period of 8. The fault sequence acquisition module transmits the fault sequence to the signal adjustment module.

[0062] Step S302, a data transmission signal is acquired from the server mainboard through the first preset interface, and the data transmission signal is adjusted using the fault sequence to obtain a target signal containing first fault information.

[0063] Specifically, the signal adjustment module obtains the data transmission signal from the server mainboard through the first preset interface, and adjusts the data transmission signal by using the fault sequence, such as adjusting the closing or opening of the channel switch according to the fault sequence, to realize the fault injection function, obtain the target signal containing the first fault information, control the opening and closing of the PCIe signal by using the high-speed switch, and accurately control the duration, frequency and position of the fault. The period of the fault sequence is the same as the number of signal channels contained in the corresponding communication protocol of the second preset interface, for example: the communication protocol is PCIe protocol, containing 7 signal channels, containing 25 signal channels, etc. The signal adjustment module adjusts the closing or opening of the channel switch according to the fault sequence to realize the fault injection function, for example: the preset interface contains 7 signal channels, the fault sequence is 100100110010011001001…, the fault sequence is a sequence with a period of 7, and 1001001 is repeatedly turned on in a certain period of time. In the fault sequence, the data bit corresponding to the first signal channel is 1, the data bit corresponding to the second signal channel is 0, and so on. The channel switch corresponding to the data bit 1 is opened, and the channel switch corresponding to the data bit 0 is closed. The above fault injection function can simulate complex random fault scenarios, and improve the authenticity and comprehensiveness of the test. By controlling the opening and closing mode of the switch, various power failure types can be simulated, such as power interruption, voltage drop, voltage spike, etc.

[0064] In step S303, the target signal is transmitted to the device to be tested through the second preset interface, and the fault injection is completed.

[0065] Specifically, the signal adjustment module is connected to the device to be tested through the second preset interface, and the signal adjustment module transmits the target signal to the device to be tested through the second preset interface, and completes the fault injection.

[0066] The fault injection method provided in this embodiment is that the server mainboard sends a fault injection command to the fault injection system to control the fault injection system to perform a fault injection operation; the fault sequence acquisition module of the fault injection system acquires a fault sequence; and the signal adjustment module of the fault injection system obtains a data transmission signal from the server mainboard, adjusts the data transmission signal by using the fault sequence to obtain a target signal containing first fault information, and transmits the target signal to a device to be tested to complete the fault injection. This method uses the firmware in the server to realize unified control and remote management of the fault injection system, and can control and monitor the fault injection process in real time. This method does not need an external control board and an additional power supply during the fault injection process, supports injection of various fault modes, and is suitable for rapid deployment and use in various environments. The problem of dependence on external control boards, complex system architecture, and poor accuracy and real-time performance of fault injection is solved.

[0067] In this embodiment, another fault injection method is provided, Figure 4is a flowchart of another fault injection method applied to a solid state disk according to an embodiment of the present application, as shown in Figure 4 The flowchart includes the following steps:

[0068] In step S401, a fault sequence is obtained in a case where a fault injection command sent by a server mainboard is received through a first preset interface.

[0069] Specifically, the "obtaining a fault sequence" in step S401 includes steps S4011 to S4013.

[0070] In step S4011, a sequence size parameter and a fault distribution parameter are obtained.

[0071] In step S4012, a first intermediate sequence of a preset length is generated according to the sequence size parameter, wherein the preset length is contained in the sequence size parameter.

[0072] In step S4013, second fault information is added to the first intermediate sequence according to the fault distribution parameter to obtain the fault sequence.

[0073] Specifically, the fault sequence generation unit obtains a sequence size parameter and a fault distribution parameter. The sequence size parameter is, for example, that the fault sequence is a pseudo-random binary sequence, and the sequence size parameter includes a PRBS order, an initial state and a generating polynomial. The PRBS order can determine the length, period and complexity of the fault sequence. For example, the PRBS order is n, the sequence period is 2 n -1, and the complexity is 1 / 2n. The fault distribution parameter can control the density of faults in the fault sequence. The fault distribution parameter is, for example, that the fault distribution parameter is m, and when m = 2, the fault density is 50%; when m = 256, the fault density is 1 / 256.

[0074] The preset length is the required sequence length, such as 10000, 20000 or other numerical values. The fault sequence generation unit generates a first intermediate sequence of a preset length according to the sequence size parameter. For example, the PRBS order in the sequence size parameter is 3, the period of the sequence is determined to be 7, the first intermediate sequence is a sequence with a period of 7, the first intermediate sequence is 1000001100000110000011000001..., and 1000001 is repeated constantly within a certain time.

[0075] According to the fault distribution parameter, the fault density is determined, the second fault information is added in the first intermediate sequence, and the generated fault sequence meets the fault density requirement. For example, according to the fault distribution parameter, the fault density is determined to be 3 / 7, the first intermediate sequence is 1000001100000110000011000001…, the fault density of the current first intermediate sequence is 2 / 7, and therefore, the second fault information is added to the first intermediate sequence to generate a fault sequence 100100110010011001001…, 1 represents that the data bit has fault information, and the fault density of the fault sequence is 3 / 7. When the second fault information is added to the first intermediate sequence, the addition can be performed for each period respectively, such as modifying 1000001 to 1001001, or the fault information can be added to the first intermediate sequence as a whole.

[0076] In the embodiment, by adjusting the sequence size parameter and the fault distribution parameter, the frequency, density and duration of the fault injection are dynamically adjusted, the fault sequence containing multiple fault modes can be generated, and the fault modes are, for example, single-bit error, multi-bit error, burst error, etc. The fault sequence transmission unit transmits the fault sequence to the signal adjustment module.

[0077] As an optional embodiment, the above step S4013 includes steps A1 to A3.

[0078] Step A1, according to the fault distribution parameter, the initial data bit and the data bit sampling interval are determined.

[0079] Step A2, according to the initial data bit and the data bit sampling interval, a preset number of data bits in the first intermediate sequence are obtained as the to-be-adjusted data bits.

[0080] Step A3, the value of the to-be-adjusted data bit in the first intermediate sequence is modified to a first preset value to obtain a fault sequence.

[0081] Specifically, the PRBS value is set in the fault distribution parameter, and the fault density value = 1 / PRBS value. The fault density is used as the data bit sampling interval. In the fault distribution parameter, the initial data bit when modifying the first intermediate sequence is determined, and the initial data bit is, for example, the first data bit, the second data bit or other data bit meeting the actual requirement of the first intermediate sequence. According to the fault distribution parameter, the initial data bit and the data bit sampling interval are determined, for example, the initial data bit is determined to be the second data bit, and the data bit sampling interval is 7.

[0082] According to the initial data bit and the data bit sampling interval, a preset number of data bits in the first intermediate sequence are obtained as the to-be-adjusted data bits, for example, the first intermediate sequence is a pseudo-random sequence, such as 1000001100000110000011000001…, the initial data bit is the second data bit, and the value is 0; the second data bit, the ninth data bit, and the 16th data bit are taken as the to-be-adjusted data bits.

[0083] The first preset value indicates that the data bit has fault information, and the first preset value is, for example, 1 or other values. The values of the to-be-adjusted data bits in the first intermediate sequence are modified to the first preset values to obtain a fault sequence, for example, the first preset value is 1, the first intermediate sequence is 1000001100000110000011000001…, the to-be-adjusted data bits include the second data bit, the ninth data bit, and the 16th data bit, the values of the to-be-adjusted data bits are modified to 1, and the fault sequence obtained is 100100110010011001001…, 1 indicates that the data bit has fault information, and the fault density of the fault sequence is 3 / 7.

[0084] The above process is as shown in FIG. 1, setting a fault density value, determining a data bit sampling interval according to the fault density value, sampling a pseudo-random sequence according to the data bit sampling interval, generating a fault sequence, and outputting the fault sequence. Figure 5

[0085] In this embodiment, according to the initial data bit and the data bit sampling interval in the fault distribution parameter, the values of the to-be-adjusted data bits are modified to the first preset values to obtain a fault sequence, and flexible fault injection is realized. By adjusting the initial data bit and the data bit sampling interval, the fault density can be controlled, and the frequency and duration of dynamic adjustment of fault injection are supported.

[0086] As an optional embodiment, the above step S4012 includes steps B1 to B3.

[0087] Step B1, according to the sequence size parameter, determining a preset length, an initial sequence, a data iteration equation, a data output bit, and a data bit transformation strategy.

[0088] Step B2, taking the initial sequence as a to-be-processed sequence.

[0089] Step B3, taking the value of the data output bit of the to-be-processed sequence as output data.

[0090] Step B4, determining a feedback value according to the to-be-processed sequence and the data iteration equation.

[0091] Step B5, adjusting the to-be-processed sequence according to the data bit transformation strategy to obtain a second intermediate sequence.

[0092] ​Step B6, write the feedback value into the empty data bits of the second intermediate sequence to obtain a third intermediate sequence.

[0093] Step B7, write the output data into the fourth intermediate sequence.

[0094] Step B8, if the length of the fourth intermediate sequence is not equal to the preset length, take the third intermediate sequence as a to-be-processed sequence, and start to execute the subsequent steps from taking the value of the data output bit of the to-be-processed sequence as the output data until the length of the fourth intermediate sequence is equal to the preset length.

[0095] Step B9, if the length of the fourth intermediate sequence is equal to the preset length, take the fourth intermediate sequence as the first intermediate sequence.

[0096] Specifically, it is necessary to note that, in the process of generating the first intermediate sequence, the data is temporarily stored in the register. According to the sequence size parameter, the preset length, the initial sequence, the data iteration equation, the data output bit and the data bit transformation strategy are determined. According to the preset length, the initial sequence and the data iteration equation, the pseudo-random sequence generator is initialized, for example: the order of the PRBS sequence is set, and the preset length can be determined by the order; the initial state of the PRBS sequence is set, and the initial state includes the initial sequence; the data iteration equation is set as the generation polynomial, and the pseudo-random sequence generator is initialized according to the order, the initial state and the generation polynomial, for example: the PRBS generator. In addition, the data output bit is, for example: the lowest bit of the sequence; the data bit transformation strategy is, for example: right shift register, left shift register, etc.

[0097] The preset length is the required sequence length, such as 10000, 20000 or other numerical values. The initial sequence is, for example: the initial state in the sequence size parameter, and the initial state is the initial value of the register (such as 0000001, 1111111, etc.), and the same initial state generates the same sequence. The data iteration equation is, for example: the generation polynomial in the sequence size parameter, and the generation polynomial is the PRBS feedback logic, such as x 7 +x 6 +1, the feedback taps are data bit 6 and data bit 5, and x 7 +x 6 +1 means that the values of data bit 6 and data bit 5 are XORed. The data output bit flows in: taking the current lowest bit (LSB) of the register as an output bit of the PRBS sequence.

[0098] The initial sequence is taken as a to-be-processed sequence, and the value of the data output bit of the to-be-processed sequence is taken as the output data, for example: the to-be-processed sequence is 1111111, the data output bit is the current lowest bit of the register, i.e. the seventh data bit, and the output data is 1.

[0099] Based on the sequence to be processed and the data iteration equation, determine the feedback value. For example, if the data iteration equation is x... 7 +x 6 +1, read the values ​​of data bit 6 and data bit 5 of the sequence to be processed. The value of data bit 6 is 1 and the value of data bit 5 is 1. Perform an XOR operation: bit6 XOR bit5 = 1 XOR 1 = 0, then the feedback value is 0.

[0100] The sequence to be processed is adjusted according to the data bit transformation strategy to obtain the second intermediate sequence. For example, if the data bit transformation strategy is a right shift register, the entire register is shifted right by 1 bit, and the most significant bit (MSB) of the register becomes a null data bit, resulting in the second intermediate sequence a111111, where 'a' represents a null data bit. Alternatively, if the data bit transformation strategy is a left shift register, the entire register is shifted left by 1 bit, and the least significant bit of the register becomes a null data bit, resulting in the second intermediate sequence 111111a, where 'a' represents a null data bit. The feedback value is written into the null data bit of the second intermediate sequence to obtain the third intermediate sequence. For example, if the second intermediate sequence is a111111, where 'a' represents a null data bit, and the feedback value is 1, the third intermediate sequence is 0111111.

[0101] Write the output data into the fourth intermediate sequence. For example, if the fourth intermediate sequence is initially empty and the output data is 1, write the output data into the fourth intermediate sequence, and the fourth intermediate sequence will be 1. Then, if the output data is 1 again, write the output data into the fourth intermediate sequence, and the fourth intermediate sequence will be 11. Then, if the output data is 0 again, write the output data into the fourth intermediate sequence, and the fourth intermediate sequence will be 110.

[0102] The length of the fourth intermediate sequence is compared with the preset length. If the length of the fourth intermediate sequence is not equal to the preset length, the third intermediate sequence is used as the sequence to be processed in the next round of the loop, and steps B3 to B9 are repeated until the length of the fourth intermediate sequence equals the preset length. If the length of the fourth intermediate sequence equals the preset length, the fourth intermediate sequence is used as the first intermediate sequence.

[0103] The above process is as follows Figure 5 As shown, initialize the pseudo-random sequence generator. Generate a pseudo-random sequence based on the pseudo-random sequence generator. Determine if the pseudo-random sequence has reached the required length. If the pseudo-random sequence has not reached the required length, repeat the steps to generate the pseudo-random sequence. If the pseudo-random sequence has reached the required length, execute the fault information injection process in steps A1 to A3.

[0104] In the embodiment, the first intermediate sequence is generated according to a preset length in a sequence size parameter, an initial sequence, a data iteration equation, a data output bit, and a data bit transformation strategy. The frequency, duration, and distribution mode of the fault can be accurately controlled by adjusting the sequence size parameter; the first intermediate sequence generated has pseudo-randomness, can simulate a fault randomly occurring in an actual environment, and enables the subsequent fault injection process to more realistically test the stability and fault tolerance of the system in a complex environment; the same sequence size parameter generates the same first intermediate sequence, so that the fault injection experiment has repeatability, facilitating debugging and verification. The generation process of the first intermediate sequence and the subsequent fault injection process can be implemented by hardware, have high execution efficiency, and are suitable for real-time systems and high-bandwidth interfaces. Different sequence size parameters can be set to generate different first intermediate sequences to simulate various fault modes, and the method is suitable for different types of test scenarios and requirements.

[0105] In step S402, the data transmission signal is obtained from the server mainboard through the first preset interface, and the data transmission signal is adjusted by using the fault sequence to obtain a target signal containing first fault information.

[0106] Specifically, the specific implementation of the present step can refer to step S302 of the embodiment shown in Figure 3 The step S302 of the embodiment shown in

[0107] In step S403, the target signal is transmitted to the device to be tested through the second preset interface, and the fault injection is completed.

[0108] Specifically, the specific implementation of the present step can refer to step S303 of the embodiment shown in Figure 3 The step S303 of the embodiment shown in

[0109] The fault injection method provided in the embodiment includes the following steps: the server mainboard sends a fault injection command to the fault injection system to control the fault injection system to perform a fault injection operation; the fault sequence acquisition module of the fault injection system acquires a fault sequence; the signal adjustment module of the fault injection system obtains a data transmission signal from the server mainboard, adjusts the data transmission signal by using the fault sequence to obtain a target signal containing first fault information, and transmits the target signal to a device to be tested to complete the fault injection. The method uses the firmware in the server to realize unified control and remote management of the fault injection system, and can control and monitor the fault injection process in real time. The method does not require an external control board and an additional power supply during the fault injection process, supports injection of various fault modes, and is suitable for rapid deployment and use in various environments. The method solves the problems of dependence on an external control board, complex system architecture, and poor accuracy and real-time performance of fault injection.

[0110] As an optional embodiment, the step S4012 of "generating the first intermediate sequence with a preset length according to the sequence size parameter" can further include steps C1 and C2.

[0111] The step C1 includes determining the sequence parameter of the pseudo-random sequence to be generated according to the sequence size parameter; the sequence parameter includes the start-stop position and the sequence length.

[0112] The step C2 includes generating the first random sequence and generating the generation matrix of each bit in the second random sequence.

[0113] The step C3 includes generating the pseudo-random sequence according to the first random sequence and the generation matrix based on the sequence parameter, and taking the pseudo-random sequence as the first intermediate sequence.

[0114] Specifically, the sequence parameter of the pseudo-random sequence to be generated is determined according to the sequence size parameter; the sequence parameter includes the start-stop position and the sequence length, and the sequence parameter of the pseudo-random sequence is used as a reference for generating the pseudo-random sequence. For the second random sequence and its generation matrix, one bit in the sequence can correspond to one generation matrix, or all bits in the sequence can correspond to one generation matrix, and one bit in the sequence can correspond to one row in the generation matrix. The sequence length in the sequence parameter is the sequence length of the generated pseudo-random sequence; the required bits for generating the pseudo-random sequence are determined from the first random sequence and the generation matrix; and the positions of the required bits in the first random sequence and the generation matrix are determined according to the start-stop position in the sequence parameter.

[0115] If one bit in the second random sequence corresponds to one generation matrix, one bit in the second random sequence is generated based on each generation matrix respectively, and the generated bits constitute the second random sequence; if all bits in the second random sequence correspond to one generation matrix, and one bit in the second random sequence corresponds to one row in the generation matrix, each bit in the second random sequence is generated based on each row in the generation matrix respectively, and the generated bits constitute the second random sequence. When generating the second random sequence, each bit in the second random sequence can be generated simultaneously based on the generation matrix or each row in the generation matrix, the dependency relationship between the bits generated before and after in the same sequence is decoupled, and parallel calculation of different bits in the same sequence is realized. The start-stop position in the sequence parameter is taken as a reference point, bits equal in length to the sequence length in the sequence parameter are selected from the first random sequence and the second random sequence, and then the pseudo-random sequence is generated based on the preset algorithm using the selected bits, and the pseudo-random sequence is taken as the first intermediate sequence.

[0116] The generating pseudo-random sequence based on the sequence parameter, the first random sequence and the generating matrix can specifically include: obtaining a maximum sequence length of the pseudo-random sequence, and selecting a to-be-used matrix from the generating matrices according to the maximum sequence length; the number of rows of the to-be-used matrix is the same as the number of bits corresponding to the maximum sequence length; generating a second random sequence according to the sequence parameter and the to-be-used matrix; and performing exclusive or operation on the first random sequence and the second random sequence to generate the pseudo-random sequence, and taking the pseudo-random sequence as the first intermediate sequence.

[0117] In the embodiment, the generating pseudo-random sequence based on the sequence parameter of the pseudo-random sequence determined according to the user parameter, the first random sequence and the generating matrix of the second random sequence. By generating the second random sequence in the form of a matrix, parallel calculation of different bits in the same sequence can be realized, the number of calculation times of the bits is reduced, and the calculation delay in generating the pseudo-random sequence is reduced.

[0118] In the embodiment, a fault injection device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware or a combination of software and hardware is also possible and is contemplated.

[0119] The embodiment provides a fault injection device deployed on a server, as shown in the following Figure 6 The fault injection device comprises:

[0120] The sequence acquisition module 601 is configured to acquire a fault sequence when a fault injection command sent by a server mainboard is received through a first preset interface.

[0121] The fault injection module 602 is configured to acquire a data transmission signal from the server mainboard through the first preset interface, and adjust the data transmission signal by using the fault sequence to obtain a target signal containing first fault information.

[0122] The signal transmission module 603 is configured to transmit the target signal to a device to be tested through a second preset interface to complete fault injection.

[0123] As an optional embodiment, the sequence acquisition module 601 comprises:

[0124] The obtaining unit is configured to obtain a sequence size parameter and a fault distribution parameter.

[0125] The generating unit is configured to generate a first intermediate sequence with a preset length according to the sequence size parameter, wherein the preset length is contained in the sequence size parameter.

[0126] The fault information adding unit is configured to add the second fault information in the first intermediate sequence according to the fault distribution parameter to obtain the fault sequence.

[0127] As an optional embodiment, the fault information adding unit comprises:

[0128] The first determining sub-module is configured to determine the initial data bit and the data bit sampling interval according to the fault distribution parameter;

[0129] The obtaining sub-module is configured to obtain a preset number of data bits in the first intermediate sequence as the to-be-adjusted data bits according to the initial data bit and the data bit sampling interval;

[0130] The numerical value modifying sub-module is configured to modify the numerical value of the to-be-adjusted data bits in the first intermediate sequence to a first preset numerical value to obtain the fault sequence.

[0131] As an optional embodiment, the generating unit comprises:

[0132] The second determining sub-module is configured to determine the preset length, the initial sequence, the data iteration equation, the data output bit, and the data bit transformation strategy according to the sequence size parameter;

[0133] The first setting sub-module is configured to take the initial sequence as the to-be-processed sequence;

[0134] The second setting sub-module is configured to take the numerical value of the data output bit of the to-be-processed sequence as the output data;

[0135] The third determining sub-module is configured to determine the feedback value according to the to-be-processed sequence and the data iteration equation;

[0136] The first obtaining sub-module is configured to adjust the to-be-processed sequence according to the data bit transformation strategy to obtain a second intermediate sequence;

[0137] The second obtaining sub-module is configured to write the feedback value into the empty data bit of the second intermediate sequence to obtain a third intermediate sequence;

[0138] The writing sub-module is configured to write the output data into a fourth intermediate sequence;

[0139] The first judging sub-module is configured to, if the length of the fourth intermediate sequence is not equal to the preset length, take the third intermediate sequence as the to-be-processed sequence, and execute the subsequent steps from taking the numerical value of the data output bit of the to-be-processed sequence as the output data until the length of the fourth intermediate sequence is equal to the preset length;

[0140] The second judging sub-module is configured to, if the length of the fourth intermediate sequence is equal to the preset length, take the fourth intermediate sequence as the first intermediate sequence.

[0141] Further functional descriptions of the above modules are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0142] In this embodiment, the fault injection device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0143] This application also provides a computer device having the above-described features. Figure 6 The fault injection device shown.

[0144] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application, such as... Figure 7 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take a processor 10 as an example.

[0145] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include an integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field-programmable gate array (FPGA), a general-purpose array logic (GPA), or any combination thereof.

[0146] The memory 20 stores instructions executable by at least one processor 10 to cause at least one processor 10 to perform the method shown in the above embodiments.

[0147] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system, application programs required for at least one function, etc. The data storage area can store data created by the computer device, etc. In addition, the memory 20 can include a high-speed random access memory, and can also include a non-transitory memory such as at least one disk storage device, a flash memory device, or other non-transitory solid state memory device. In some alternative embodiments, the memory 20 can optionally include memory that is remotely located with respect to the processor 10, and that can be connected to the computer device through a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communications network, and combinations thereof.

[0148] The memory 20 can include a volatile memory, such as a random access memory, and can also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid state memory device. The memory 20 can also include a combination of the above-mentioned types of memory.

[0149] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0150] The embodiments of the present application also provide a computer readable storage medium. The above-mentioned method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or implemented as computer code stored in a remote storage medium or non-transitory machine readable storage medium and stored in a local storage medium through network download, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that the computer, processor, microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, processor, or hardware, the method shown in the above embodiments is implemented.

[0151] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, the method and / or technical solutions according to the present application can be called or provided. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source file, executable file, installation package file and the like, and accordingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0152] Although the embodiments of the present application are described in conjunction with the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the present application.

Claims

1. A fault injection system, characterized in that, The system includes: a fault sequence acquisition module and a signal adjustment module; The fault sequence acquisition module is connected to the server motherboard through a first preset interface. It is used to acquire a fault sequence and transmit the fault sequence to the signal adjustment module when a fault injection command sent by the server motherboard is received through the first preset interface. The signal adjustment module is connected to the server motherboard through the first preset interface, and is used to obtain data transmission signals from the server motherboard through the first preset interface, and adjust the data transmission signals using the fault sequence to obtain a target signal containing the first fault information. The signal adjustment module is connected to the device under test through a second preset interface, and is used to transmit the target signal to the device under test through the second preset interface to complete fault injection.

2. The system according to claim 1, characterized in that, The fault sequence acquisition module includes: a fault sequence generation unit and a fault sequence transmission unit; The fault sequence generation unit is used to obtain sequence size parameters and fault distribution parameters, and generate the fault sequence based on the sequence size parameters and fault distribution parameters. The fault sequence transmission unit is used to transmit the fault sequence to the signal adjustment module.

3. The system according to claim 1, characterized in that, The signal adjustment module includes: a switch control unit and a preset number of channel switches; The switch control unit is used to determine whether there is a data bit in the fault sequence whose value is equal to a first preset value, and to take the data bit whose value is equal to the first preset value as the target data bit; The switch control unit is further configured to use the channel switch corresponding to the target data bit as the channel switch to be disconnected, control the channel switch to be disconnected to be disconnected to be disconnected, and control the channel switches other than the channel switch to be disconnected to be closed.

4. A fault injection method, characterized in that, The method is applied to the fault injection system according to any one of claims 1 to 3, and the method includes: Upon receiving a fault injection command from the server motherboard via the first preset interface, obtain the fault sequence; The data transmission signal is obtained from the server motherboard through the first preset interface, and the data transmission signal is adjusted using the fault sequence to obtain a target signal containing the first fault information; The target signal is transmitted to the device under test through the second preset interface to complete the fault injection.

5. The method according to claim 4, characterized in that, The acquisition of the fault sequence includes: Obtain sequence size parameters and fault distribution parameters; Based on the sequence size parameter, a first intermediate sequence of a preset length is generated, wherein the preset length is included in the sequence size parameter; The fault sequence is obtained by adding second fault information to the first intermediate sequence based on the fault distribution parameters.

6. The method according to claim 5, characterized in that, The step of adding second fault information to the first intermediate sequence according to the fault distribution parameters to obtain the fault sequence includes: Based on the fault distribution parameters, determine the initial data bits and the data bit sampling interval; Based on the initial data bits and the data bit sampling interval, a preset number of data bits are obtained from the first intermediate sequence as data bits to be adjusted; In the first intermediate sequence, the value of the data bit to be adjusted is modified to a first preset value to obtain the fault sequence.

7. The method according to claim 5, characterized in that, The step of generating a first intermediate sequence of a preset length based on the sequence size parameter includes: Based on the sequence size parameter, determine the preset length, initial sequence, data iteration equation, data output bits, and data bit transformation strategy; The initial sequence is used as the sequence to be processed; The value of the data output bit of the sequence to be processed is used as the output data; The feedback value is determined based on the sequence to be processed and the data iteration equation; The sequence to be processed is adjusted according to the data bit transformation strategy to obtain a second intermediate sequence; The feedback value is written into the empty data bits of the second intermediate sequence to obtain the third intermediate sequence; Write the output data into the fourth intermediate sequence; If the length of the fourth intermediate sequence is not equal to the preset length, the third intermediate sequence is used as the sequence to be processed, and subsequent steps are executed starting from the value of the data output bit of the sequence to be processed as the output data, until the length of the fourth intermediate sequence is equal to the preset length. If the length of the fourth intermediate sequence is equal to the preset length, the fourth intermediate sequence is used as the first intermediate sequence.

8. A fault injection device, characterized in that, The device includes: The sequence acquisition module is used to acquire the fault sequence when a fault injection command sent by the server motherboard is received through the first preset interface; The fault injection module is used to obtain data transmission signals from the server motherboard through the first preset interface, and adjust the data transmission signals using the fault sequence to obtain a target signal containing first fault information. The signal transmission module is used to transmit the target signal to the device under test through the second preset interface to complete the fault injection.

9. A computer device, characterized in that, include: A memory and a processor are communicatively connected, the memory storing computer instructions, and the processor executing the computer instructions to perform the fault injection method of any one of claims 4 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the fault injection method according to any one of claims 4 to 7.

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