A timing monitoring circuit

Abstract

This invention relates to the field of power electronic device technology, and in particular to a timing monitoring circuit. This circuit forms a closed feedback loop through a first loop unit, a second loop unit, and a loop control unit. By configuring a delay mismatch time interval on the signal transmission path of the first initial test signal and / or the second initial test signal, the time difference between the first and second initial test signals is cyclically attenuated. This significantly simplifies the circuit structure and reduces the consumption of chip space and power resources. Furthermore, by amplifying the time difference between the first and second initial test signals through a phase comparison unit and an output unit, the signal gain is improved. It can be directly applied to scenarios requiring analog signals, solving the technical problems of existing timing monitoring circuits, such as high chip resource consumption, limited gain, and limited application scenarios. A timeout protection and reset mechanism is also constructed to improve the circuit's robustness.

Description

Technical Field

[0001] This invention relates to the field of power electronic device technology, and in particular to a timing monitoring circuit. Background Technology

[0002] As semiconductor processes advance to the deep submicron and even nanometer scale, chip integration density and operating frequencies have increased dramatically. High frequencies mean that the available transmission time window for a signal within a single clock cycle is extremely compressed, making timing requirements for circuits increasingly stringent. Process variations, voltage fluctuations, and temperature changes (i.e., PVT variations) can all cause unpredictable drift in signal delays, potentially eroding or even exhausting the design's timing margin, leading to setup time or hold time violations, and ultimately causing chip malfunctions. Therefore, the ability to monitor the timing margin of critical paths on the chip in real time and with precision is crucial for ensuring the yield and reliability of high-performance chips. This online timing monitoring solution can be used in scenarios such as chip factory testing, dynamic system frequency adjustment, and aging status early warning, achieving precise management of chip lifespan.

[0003] However, in order to achieve high accuracy and wide measurement range, existing timing monitoring circuits usually require a large number of delay unit arrays and decision unit arrays, which are complex and bulky, occupy more chip area and consume more power, and have limited gain. Moreover, the timing information output by existing timing monitoring circuits is difficult to apply directly to analog signal application scenarios, resulting in limited application scenarios. Summary of the Invention

[0004] This invention provides a timing monitoring circuit to solve the technical problems of existing timing monitoring circuits, such as high chip resource consumption, limited gain, and limited application scenarios.

[0005] This invention provides a timing monitoring circuit, comprising: a first loop unit, a second loop unit, a loop control unit, a phase comparison unit, and an output unit;

[0006] The first input terminal of the first loop unit is used to receive the first initial test signal; the output terminal of the first loop unit is connected to the second input terminal of the first loop unit and the first input terminal of the phase comparison unit, respectively, and is used to output the first internal loop signal.

[0007] The first input terminal of the second loop unit is used to receive the second initial test signal; the output terminal of the second loop unit is connected to the second input terminal of the second loop unit and the second input terminal of the phase comparison unit respectively, and is used to output the second internal loop signal.

[0008] The input terminal of the loop control unit is used to receive the first initial test signal and the second initial test signal respectively. The output terminal of the loop control unit is connected to the controlled terminals of the first loop unit and the second loop unit respectively. When the rising edge or falling edge of the first initial test signal is detected, the first loop unit is controlled to select the first internal loop signal; and when the rising edge of the second initial test signal is detected, the second loop unit is controlled to select the second internal loop signal.

[0009] The output terminal of the phase comparison unit is connected to the input terminal of the output unit, and is used to detect and control the output unit to output a pulse signal based on the time difference between the first internal loop signal and the second internal loop signal.

[0010] The signal transmission path formed by the timing monitoring circuit is configured with a delay mismatch time interval, which is used to cause the first initial test signal and the second initial test signal to have a transmission delay, and to cause the first internal loop signal and the second internal loop signal to have a transmission delay.

[0011] Optionally, the first loop unit includes: a first signal selector and a first pulse generator;

[0012] The first input terminal of the first signal selector is used to receive the first initial test signal;

[0013] The controlled terminal of the first signal selector is connected to the output terminal of the loop control unit;

[0014] The output of the first signal selector is connected to the input of the first pulse generator;

[0015] The output terminal of the first pulse generator is connected to the second input terminal of the first signal selector and the first input terminal of the phase comparison unit, respectively.

[0016] Optionally, the second loop unit includes: a second signal selector and a second pulse signal generator;

[0017] The first input terminal of the second signal selector is used to receive the second initial test signal;

[0018] The controlled terminal of the second signal selector is connected to the output terminal of the loop control unit;

[0019] The output of the second signal selector is connected to the input of the second pulse generator;

[0020] The output terminal of the second pulse generator is connected to the second input terminal of the second signal selector and the second input terminal of the phase comparison unit, respectively.

[0021] Optionally, the loop control unit includes: a first D flip-flop, a second D flip-flop, and an edge detection circuit;

[0022] The input terminal of the edge detection circuit is used to receive the first initial test signal;

[0023] The output of the edge detection circuit is connected to the clock terminal of the first D flip-flop;

[0024] The output terminal of the first D flip-flop is connected to the controlled terminal of the first signal selector;

[0025] The clock input of the second D flip-flop is used to receive the second initial test signal;

[0026] The output of the second D flip-flop is connected to the controlled terminal of the second signal selector;

[0027] The data terminals of the first and second D flip-flops are used to receive power supply voltage signals.

[0028] Optionally, the phase comparison unit includes: a timing detection subunit and a first logic gate circuit; the output unit includes: a third D flip-flop;

[0029] The input terminal of the timing detection subunit is used to receive the first initial test signal and the second initial test signal, respectively.

[0030] The output terminal of the timing detection subunit is connected to the data terminal of the third D flip-flop, and is used to output a target pulse signal to the third D flip-flop when the time difference between the first initial test signal and the second initial test signal is not less than a preset time threshold.

[0031] The input terminal of the first logic gate circuit is used to receive the first initial test signal and the second initial test signal, respectively;

[0032] The output of the first logic gate is connected to the clock terminal of the third D flip-flop, and is used to output a trigger signal to the third D flip-flop when the first initial test signal and the second initial test signal are detected to be in the target state.

[0033] Optionally, the edge detection circuit includes: a first buffer, a second buffer, and a first XOR gate;

[0034] The input terminal of the first buffer and the first input terminal of the first XOR gate are used to receive the first initial test signal;

[0035] The output of the first buffer is connected to the input of the second buffer, and the output of the second buffer is connected to the second input of the first XOR gate.

[0036] The output of the first XOR gate is connected to the clock terminal of the first D flip-flop.

[0037] Optionally, it may also include: a reset unit and an external reset control unit;

[0038] The input terminal of the reset unit is connected to the output unit and the external reset control unit. The reset unit is connected to the reset terminal of the loop control unit. It is used to receive and detect the output signal of the pulse unit output by the output unit, and receive the external reset pulse of the external reset control unit. When the falling edge of the pulse signal is detected or the external reset pulse of the external reset control unit is received, the reset unit outputs a reset signal to the loop control unit.

[0039] Optionally, the reset unit includes: a falling edge detector and a reset AND gate;

[0040] The input terminal of the falling edge detector is connected to the output unit, and the output terminal of the falling edge detector is connected to one input terminal of the reset AND gate;

[0041] The other input of the reset AND gate is connected to the external reset control unit, and the output of the reset AND gate is connected to the loop control unit.

[0042] Optionally, it also includes a timeout counter and logic gates;

[0043] The input terminal of the timeout counter is connected to the output terminal of the first loop unit, the output terminal of the second loop unit, and the output terminal of the output unit, respectively. The output terminal of the timeout counter is connected to an input terminal of a logic gate circuit. It is used to generate a counting clock based on the number of cycles of the first internal loop signal and the second internal loop signal when the pulse signal has no falling edge, and to output a falling edge signal to the logic gate circuit when the counting clock reaches a preset number threshold.

[0044] The other input terminal of the logic gate circuit is connected to the output terminal of the output unit, and the output terminal of the logic gate circuit is connected to the input terminal of the falling edge detector, for transmitting the falling edge signal and / or the pulse signal output by the timeout counter to the falling edge detector.

[0045] Optionally, the falling edge detector includes: a third buffer, a first NOT gate, and a first OR gate;

[0046] The input terminal of the third buffer is connected to one input terminal of the OR gate, serving as the input terminal of the falling edge detector;

[0047] The output of the third buffer is connected to the input of the first NOT gate, the output of the first NOT gate is connected to the other input of the OR gate, and the output of the OR gate is the output of the falling edge detector.

[0048] As can be seen from the above technical solutions, the present invention has the following advantages:

[0049] This invention provides a timing monitoring circuit, comprising: a first loop unit, a second loop unit, a loop control unit, a phase comparison unit, and an output unit; a first input terminal of the first loop unit is used to receive a first initial test signal; the output terminal of the first loop unit is connected to a second input terminal of the first loop unit and a first input terminal of the phase comparison unit, respectively, for outputting a first internal loop signal; a first input terminal of the second loop unit is used to receive a second initial test signal; the output terminal of the second loop unit is connected to a second input terminal of the second loop unit and a second input terminal of the phase comparison unit, respectively, for outputting a second internal loop signal; the input terminal of the loop control unit is used to receive the first initial test signal and the second initial test signal, respectively, and the output terminal of the loop control unit is connected to the first loop unit, a second loop unit, a loop control unit, a phase comparison unit, and an output unit. The controlled terminals of the first and second loop units are used to control the first loop unit to select the first internal loop signal when the rising or falling edge of the first initial test signal is detected; and to control the second loop unit to select the second internal loop signal when the rising edge of the second initial test signal is detected. The output terminal of the phase comparison unit is connected to the input terminal of the output unit and is used to detect and control the output unit to output a pulse signal according to the time difference between the first and second internal loop signals. A delay mismatch time interval is configured on the signal transmission path formed by the timing monitoring circuit. The delay mismatch time interval is used to cause the first and second initial test signals to have a transmission delay, and to cause the first and second internal loop signals to have a transmission delay.

[0050] Therefore, the timing monitoring circuit provided by this invention forms a closed feedback loop through a first loop unit, a second loop unit, and a loop control unit. By configuring a delay mismatch time interval on the signal transmission path, a transmission delay is generated between the first initial test signal and the second initial test signal. In each loop, a transmission delay is generated between the first internal loop signal corresponding to the first initial test signal and the second internal loop signal corresponding to the second initial test signal. This attenuates the time difference between the first and second initial test signals based on a fixed delay mismatch time interval. This achieves the monitoring of the time difference between the first and second initial test signals without the need for a large number of delay unit arrays and decision unit arrays, greatly simplifying the circuit structure and reducing the consumption of chip space and power resources. It avoids the situation of high chip resource consumption in existing timing monitoring circuits. Furthermore, this invention amplifies the time difference between the first and second initial test signals in the time dimension through a phase comparison unit and an output unit, improving the signal gain. The output pulse signal can be directly applied to scenarios requiring analog signals, avoiding the gain limitations and application scenario limitations of existing timing monitoring circuits. Therefore, the timing monitoring circuit provided by this invention solves the technical problems of existing timing monitoring circuits, such as high chip resource consumption, limited gain, and limited application scenarios. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A schematic diagram of the TDC structure of an existing vernier delay chain;

[0053] Figure 2 This is one of the structural schematic diagrams of a timing monitoring circuit provided in an embodiment of the present invention;

[0054] Figure 3 This is a second schematic diagram of a timing monitoring circuit provided in an embodiment of the present invention;

[0055] Figure 4 This is the third schematic diagram of a timing monitoring circuit provided in an embodiment of the present invention;

[0056] Figure 5 This is the fourth schematic diagram of a timing monitoring circuit provided in an embodiment of the present invention;

[0057] Figure 6This is a schematic diagram of the structure of the loop control unit provided in an embodiment of the present invention;

[0058] Figure 7 This is a schematic diagram of the structure of the timeout counter, reset unit, and logic gate circuit provided in the embodiments of the present invention;

[0059] Figure 8 This is a schematic diagram of the pulse shaping circuit provided in an embodiment of the present invention;

[0060] Figure 9 This is a timing diagram of each signal under normal operation provided in an embodiment of the present invention;

[0061] Figure 10 A schematic diagram of the simulation waveforms of the input and output of the timing monitoring circuit provided in an embodiment of the present invention;

[0062] Figure 11 This is a timing diagram for timeout reset provided in an embodiment of the present invention. Detailed Implementation

[0063] The technical terms involved in this invention will be explained below.

[0064] Timing margin: In digital circuits, the difference between the actual arrival time of a signal and the final arrival time required by the clock is a key indicator for measuring the timing robustness of a system.

[0065] TDC (Time-to-Digital Converter): A circuit that converts the time interval between two events into a digital value.

[0066] Setup Time: The minimum time period during which the data input signal must remain stable before the clock's effective edge (usually the rising edge) arrives to ensure that the data is properly latched.

[0067] SR Latch: A basic storage unit controlled by set and reset inputs, capable of latching states.

[0068] IR Drop: refers to the voltage drop that occurs when current flows through a power supply or ground network with a certain resistance. It is an important factor affecting chip performance and stability.

[0069] Parasitic parameters: These are additional capacitances, resistances, and inductances in integrated circuits that are not intentionally constructed by the designer but are inevitably generated due to the physical implementation of integrated circuits, such as interconnect capacitance and transistor input capacitance.

[0070] PVT (Process, Voltage, and Temperature): refers to the three major external factors that affect the performance of semiconductor chips: process, voltage, and temperature.

[0071] MUX (Multiplexer): A logic circuit that can select one of multiple input signals as its output.

[0072] Monostable circuit: A circuit that generates a pulse of fixed width when triggered by a signal.

[0073] Currently, one of the commonly used circuits for measuring minute time differences is the vernier delay line-based time-to-digital converter (TDC), whose core principle is similar to that of a vernier caliper. A typical vernier delay line-based time-to-digital converter (VDL-TDC) is as follows: Figure 1 As shown, it includes two parallel delay lines, each composed of multiple interconnected delay units (such as inverters). One of them is the "slow" delay line, with each unit having a delay of [value missing]. The other is a "fast" delay chain, where the delay of each unit is... ,and Slightly smaller (For example: ). This is the measurement resolution of TDC.

[0074] Two signals to be tested, such as data and cp, are simultaneously propagated as inputs to two delay chains. At each stage of the two delay chains, a decision unit (arbiter) is placed. The decision unit can be an SR latch or a D flip-flop. Taking a D flip-flop as an example, the output of the data signal's propagation path is connected to the data terminal D of the D flip-flop, and the output of the cp signal's propagation path is connected to the clock terminal CLK.

[0075] Initially, if the data signal leads the cp signal by a time difference of Tin, then at the beginning of the propagation phase, all D flip-flops will latch to a high level. As the cp signal propagates along the "fast" chain, it gradually catches up with the data signal. At each stage, cp catches up with the data signal a little further than the data signal. The time difference is calculated when the propagation reaches the Nth stage. At the Nth stage, the arrival time of the cp signal first surpasses that of the data signal, causing the output of the Nth D flip-flop to go low for the first time. By detecting the position N of this 0-1 toggle, the initial time difference can be calculated. .

[0076] However, the aforementioned time-to-digital converter has the following drawbacks:

[0077] 1. Large area and power consumption. To achieve high measurement range and accuracy, delay chains need to contain a large number of delay units and decision units, occupying a considerable area on the chip. At the same time, these units generate significant static and dynamic power consumption, thus consuming substantial space and power resources on the chip.

[0078] 2. A balance between resolution and stability is difficult to achieve. The resolution of a circuit is determined by the minute delay difference between two delay units. In advanced manufacturing processes, precisely controlling this minute difference is extremely difficult, as it is highly sensitive to changes in PVT (Progressive Voltage). To achieve stability, complex calibration circuits are often required, further increasing the complexity and cost of the circuit design.

[0079] 3. Gain Limitation. The gain of this time-to-digital converter is related to the inverter drive capability and the manufacturing process, depending on the mismatch between components (such as inverters and buffers), and is limited by the delay difference between the two inverters. However, under specific semiconductor processes, a minimum delay difference can be stably and reliably designed ( There is a physical and technological limit. This fundamental limitation results in a fundamental constraint on the intrinsic gain of VDL, making it difficult to achieve higher gains simply by reducing the design tolerance.

[0080] 4. Limited Application Scenarios. The output of the VDL-TDC is a "thermometer code," which needs to be further encoded into binary code before it can be used by digital systems. Essentially, it converts a time difference into a digital code rather than directly amplifying the time. This is not straightforward enough for some applications requiring analog signals or wide pulses, necessitating additional conversion circuitry. Therefore, this time-to-digital converter cannot directly support applications that require amplified time signals, resulting in limited application scenarios. Furthermore, using additional conversion circuitry further increases the circuit's construction cost and space requirements.

[0081] To address the shortcomings of the existing technology, this invention provides a timing monitoring circuit that can directly amplify tiny time differences at the picosecond (ps) or even femtosecond (fs) level into nanosecond (ns) level pulse widths, achieving a time gain of up to hundreds of times. Furthermore, it features a compact structure, low power consumption, and avoids the use of lengthy delay chains. It cleverly utilizes inherent parasitic parameters to achieve a stable time difference reduction mechanism, thereby simplifying design and improving robustness to process variations. It also includes a comprehensive timeout protection mechanism to ensure reliable operation and automatic reset under various input conditions.

[0082] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0083] Please see Figure 2 , Figure 2 A timing monitoring circuit provided in an embodiment of the present invention includes: a first loop unit 1, a second loop unit 2, a loop control unit 3, a phase comparison unit 4, and an output unit 5;

[0084] The first input terminal of the first loop unit 1 is used to receive the first initial test signal; the output terminal of the first loop unit 1 is connected to the second input terminal of the first loop unit 1 and the first input terminal of the phase comparison unit 4, respectively, and is used to output the first internal loop signal; the first input terminal of the second loop unit 2 is used to receive the second initial test signal; the output terminal of the second loop unit 2 is connected to the second input terminal of the second loop unit 2 and the second input terminal of the phase comparison unit 4, respectively, and is used to output the second internal loop signal; the input terminal of the loop control unit 3 is used to receive the first initial test signal and the second initial test signal, respectively, and the output terminal of the loop control unit 3 is connected to the first loop unit 1 and the second initial test signal, respectively. The controlled terminal of the second loop unit 2 is used to control the first loop unit 1 to select the first internal loop signal when the rising edge or falling edge of the first initial test signal is detected; and to control the second loop unit 2 to select the second internal loop signal when the rising edge of the second initial test signal is detected; the output terminal of the phase comparison unit 4 is connected to the input terminal of the output unit 5, and is used to detect and control the output unit 5 to output a pulse signal according to the time difference between the first internal loop signal and the second internal loop signal; a delay mismatch time interval is configured on the signal transmission path of the first initial test signal and / or the second initial test signal to cause a transmission delay between the first initial test signal and the second initial test signal.

[0085] It should be noted that in this invention, both the first loop unit 1 and the second loop unit 2 have signal selection functions, allowing them to select the signal input from one of their input terminals. Taking the first loop unit 1 as an example, the first loop unit 1 can select the first initial signal to be measured as the signal input, or select its own output first internal loop signal as the signal input. After determining the input signal, both the first loop unit 1 and the second loop unit 2 perform width normalization and amplitude normalization on the input signal, thereby outputting a pulse signal with fixed width and amplitude.

[0086] The signal selection function of the first loop unit 1 and the second loop unit 2 is triggered by the loop control unit 3. The loop control unit 3 detects the first initial test signal and the second initial test signal. When it detects the rising or falling edge of the first initial test signal, it outputs a first switching signal to the first loop unit 1, causing the first loop unit 1 to select the first internal loop signal as the signal input. When it detects the rising edge of the second initial test signal, it outputs a second switching signal to the second loop unit 2, causing the second loop unit 2 to select the second internal loop signal as the signal input. Therefore, when the first loop unit 1 does not receive the first switching signal, it selects the first initial test signal as the signal input; when the second loop unit 2 does not receive the second switching signal, it selects the second initial test signal as the signal input. Because there is a slight time difference between the first initial test signal and the second initial test signal, the rising or falling edge of the first initial test signal detected by the loop control unit 3 and the rising edge of the second initial test signal are detected in sequence. Therefore, the triggering times of the first loop unit 1 and the second loop unit 2 are also in sequence, so that the initial timing relationship between the first initial test signal and the second initial test signal is locked in the first loop unit 1 and the second loop unit 2, and a finite number of loops are performed based on this timing relationship.

[0087] The first loop unit 1 and the second loop unit 2 output normalized pulses with fixed width and amplitude according to the received signals (i.e., output the first internal loop signal and the second internal loop signal respectively), and the time difference between the rising edges of the first internal loop signal and the second internal loop signal is equal to the time difference between the first initial test signal and the second initial test signal.

[0088] In this embodiment, the loop control unit 3, the first loop unit 1, the phase comparison unit 4, and the output unit 5 constitute the transmission path of the first initial test signal. The loop control unit 3, the second loop unit 2, the phase comparison unit 4, and the output unit 5 constitute the transmission path of the second initial test signal. The first internal loop signal and the second internal loop signal output by the first loop unit 1 and the second loop unit 2 are transmitted in the transmission path. This application configures a delay mismatch time interval on the signal transmission path of the first initial test signal and / or the second initial test signal to cause a transmission delay between the first initial test signal and the second initial test signal. Therefore, in each iteration, the time difference between the first inner loop signal and the second inner loop signal is systematically and consistently reduced by a fixed amount (the delay mismatch time interval). ).For example:

[0089] Assuming the transmission delay of the first initial signal to be tested is greater than the transmission delay of the second initial signal to be tested, then the time difference of the k-th cycle... Wherein, Tin is the time difference between the first initial signal to be measured and the second initial signal to be measured.

[0090] In this embodiment, the delay mismatch time interval can be configured by utilizing and designing parasitic parameters of the layout, as shown in the following example.

[0091] Example 1: In this embodiment, during the layout design phase, the input transistors of the subsequent circuits (i.e., phase comparison units) driven by the first and second internal loop signals are configured asymmetrically. For example, the gate size of the input transistor connected to the first loop unit 1 can be set to be slightly larger than the gate size of the input transistor connected to the second loop unit 2. Since the gate capacitance of a transistor is positively correlated with its own size, the total load capacitance (i.e., the equivalent capacitance of the subsequent circuit) required to be driven during the transmission of the first initial test signal is slightly larger than the total load capacitance required to be driven by the transmission path of the second initial test signal. This causes the signal transmission path of the first initial test signal to require a longer charging and discharging time for the larger capacitor, thereby introducing a small delay difference (i.e., delay mismatch time interval) between the transmission of the first and second initial test signals. ).

[0092] Example 2: Configuration via IR Drop Mismatch. Specifically, during layout routing, a power supply network with a small resistance difference can be designed for the signal transmission paths of the first and second initial signals under test. For example, the effective voltage drop of the power supply network for the signal transmission path of the first initial signal under test is set to be less than that for the signal transmission path of the second initial signal under test. This causes the effective supply voltage of each logic gate in the signal transmission path of the first initial signal under test to be systematically lower due to the voltage drop (IR Drop), thereby increasing the overall propagation delay of the path and introducing a small delay difference (i.e., delay mismatch time interval) between the signal transmission paths of the first and second initial signals under test. ).

[0093] Example 3: In addition to the methods provided in Examples 1 and 2, the delay mismatch time interval can also be achieved by integrating a very small, fixed passive device (such as a miniature resistor or capacitive load) into the signal transmission path of the first initial signal under test or the second initial signal under test. The configuration is as follows: Specifically, assuming that a passive device is integrated on the signal transmission path of the first initial signal to be measured, the passive device is disposed in the path between the output terminal of the first loop unit 1 and the input terminal of the phase comparison unit 4, and is connected to the output terminal of the first loop unit 1 and the input terminal of the phase comparison unit 4 respectively, so as to turn on the first loop unit 1 and the phase comparison unit 4.

[0094] Alternatively, the signal transmission paths of the first initial signal under test and the second initial signal under test can use asymmetric driving gates (i.e., logic gates with different driving capabilities) to configure the delay mismatch time interval. It is understandable that logic gates with different driving capabilities require different driving times, thus affecting the output delay in order to complete the delay mismatch interval. Configuration.

[0095] The workflow of this embodiment is as follows: After the first initial test signal and the second initial test signal are input to the first loop unit 1, the second loop unit 2, and the loop control unit 3, the loop control unit 3 waits for the rising or falling edge of the first initial test signal and the rising edge of the second initial test signal. During the waiting period, the input signal of the first loop unit 1 is the first initial test signal, and the input signal of the second loop unit 2 is the second initial test signal. When the loop control unit 3 detects the rising or falling edge of the first initial test signal, it triggers the first loop unit 1 to select the first internal loop signal, and when it detects the rising edge of the second initial test signal, it triggers the second loop unit 2 to select the second internal loop signal. Based on this, the first loop unit 1 and the second loop unit 2 form a closed feedback loop, isolating the external first and second initial test signals, and looping in the first loop unit 1 and the second loop unit 2 with the first and second internal loop signals as references. Assuming the time between the first and second initial test signals is Tin, then in the first loop, the time difference between the rising edges of the fixed pulses output by the first loop unit 1 and the second loop unit 2 is approximately Tin. In each iteration, the time difference between the first inner loop signal and the second inner loop signal is systematically and consistently reduced by the delay mismatch interval. .

[0096] After the first loop unit 1 and the second loop unit 2 output the first internal loop signal and the second internal loop signal, both signals are input to the phase comparison unit 4. The phase comparison unit 4 detects the time difference between the two signals and outputs a corresponding control signal to the output unit 5 based on this time difference, causing the output unit 5 to output a corresponding pulse signal. Therefore, as long as the phase unit can detect a signal difference between the first and second internal loop signals, the output unit 5 will continuously output the corresponding pulse signal. In one example, for easier differentiation, the pulse signal output by the output unit 5 can be set to a high-level signal.

[0097] Taking the pulse signal output by output unit 5 as a high-level signal as an example, in this embodiment, "1" represents a high level and "0" represents a low level. As can be seen from the above, the width of the pulse signal output by output unit 5 starts from changing to "1" and ends at changing to "0," and its width is equal to the number of cycles multiplied by the time period of each cycle. The number of cycles N is proportional to the initial time difference Tin, i.e. Therefore, in this embodiment, the time difference between the first initial test signal and the second initial test signal is converted into a pulse signal width using the phase comparison unit 4 and the output unit 5. Furthermore, compared to the original first and second initial test signals, the pulse width of the pulse signal output by the output unit 5 is significantly amplified, with an amplification factor equal to the cycle period / In one application example, such as Figure 10 As shown, Figure 10 In the diagram, the horizontal axis represents the time difference between the rising edges of the two signal inputs (unit: ps), and the vertical axis represents the pulse width of the pulse signal output by output unit 5 (unit: ns). Figure 10 The slope in the equation represents the magnification factor, which is approximately 500 times.

[0098] As can be seen from the above, the timing monitoring circuit provided in this embodiment of the invention, by constructing a closed feedback loop circuit structure for amplifying time, accumulates minute delays based on a cyclic iteration method, thereby converting a tiny, fixed time at the input into a pulse signal with significantly amplified width at the output. Through the principle of cyclic amplification, this invention can easily achieve a time amplification factor of approximately 500 times, converting femtosecond-level time differences (~250fs) that are difficult to handle by traditional solutions into nanosecond-level pulse widths that are easy for subsequent digital circuits to measure, achieving extremely high gain and resolution. This solves the problems of limited gain and application scenarios existing in traditional VDL-TDC. Moreover, the closed-loop feedback loop provided in this embodiment of the invention has a compact structure, which greatly saves chip area compared to the large delay unit array and decision unit array required in traditional VDL-TDC. At the same time, since most of the timing circuit is in standby mode and only performs a limited number of cycles after triggering, its dynamic power consumption is also much lower than that of a continuously operating delay chain.

[0099] Furthermore, the present invention utilizes a mechanism for time difference reduction using parasitic parameters. By intentionally and asymmetrically designing the parasitic input capacitance and IR drop of the two signal paths during the layout design stage, a highly stable delay mismatch time interval is achieved at extremely low cost. This configuration, without relying on additional active delay units, can stably reduce the time difference between two signals under test in a loop. Furthermore, this invention utilizes inherent parasitic parameter mismatch to define the time reduction step size, avoiding the low control accuracy and high control cost caused by the difficult control of small delay differences between two independent delay units at different process angles in existing technologies. Moreover, the physical effect-based mismatch method provided in this embodiment exhibits better stability to PVT variations within a certain range.

[0100] In one embodiment, such as Figure 3 As shown, it also includes: a reset unit 6 and an external reset control unit 9;

[0101] The input terminal of the reset unit 6 is connected to the output unit 5 and the external reset control unit 9. The reset unit 6 is connected to the reset terminal of the loop control unit 3. It is used to receive and detect the output signal of the pulse unit output by the output unit 5, and receive the external reset pulse of the external reset control unit 9. When the falling edge of the pulse signal is detected or the external reset pulse of the external reset control unit 9 is received, the reset signal is output to the loop control unit 3.

[0102] It should be noted that the external reset pulse has two states: high level and low level. The reset signal is active low level. Therefore, when the reset unit 6 detects the falling edge of the pulse signal, it outputs a low level reset signal, or when the received external reset pulse is low level. In other cases, the high level reset signal output is invalid.

[0103] Specifically, as described in the foregoing embodiments, when the width of the pulse signal of the output unit 5 starts from changing to "1" and ends at changing to "0", it indicates that when the falling edge of the pulse signal is detected, it means that the detection result of the phase comparison unit 4 is that there is no time difference between the first initial test signal and the second initial test signal. Therefore, the iterative operation of the first loop unit 1 and the second loop unit 2 can be stopped. At this time, the reset unit 6 can output a low-level reset signal to the loop control unit 3 to reset the loop control unit 3 to the standby state; and / or, when a low-level external reset pulse is received, it outputs a low-level reset signal to the loop control unit 3. Therefore, by setting the reset unit 6, the present invention can stop the loop iteration process and can also respond to the reset request of the external reset control unit 9 to stop the loop iteration process of the circuit.

[0104] As a further improvement, considering a special case: when the time difference Tin between the first initial test signal and the second initial test signal is too small, the phase comparison unit 4 can no longer detect the time difference between the first internal loop signal and the second internal loop signal during the first loop, resulting in the output unit 5 continuously outputting a low-level signal "0". This prevents the pulse signal from generating a normal falling edge reset signal, causing the timing monitoring circuit to remain locked in the loop state, forming a "deadlock". To solve this technical problem, such as... Figure 4 As shown, the embodiments of the present invention also include: a timeout counter 7 and a logic gate circuit 8;

[0105] The input terminal of the timeout counter 7 is connected to the output terminal of the first loop unit 1, the output terminal of the second loop unit 2, and the output terminal of the output unit 5, respectively. The output terminal of the timeout counter 7 is connected to one input terminal of the logic gate circuit 8. It is used to generate a counting clock according to the number of cycles of the first internal loop signal and the second internal loop signal when the pulse signal has no falling edge, and output a falling edge signal to the logic gate circuit 8 when the counting clock reaches a preset number threshold.

[0106] Another input terminal of logic gate circuit 8 is connected to the output terminal of output unit 5, and the output terminal of logic gate circuit 8 is connected to the input terminal of falling edge detector, which is used to transmit the falling edge signal and / or pulse signal output by timeout counter 7 to falling edge detector.

[0107] It should be noted that in this embodiment, the timeout counter 7 is set to detect the falling edge of the pulse signal, and the first internal loop signal and the second internal loop signal are used to accumulate the number of times and generate the corresponding counting clock. When the counting clock reaches the preset number threshold and the pulse signal has no falling edge, the system is determined to be in a "deadlock" state, and the falling edge signal is output to the logic gate circuit 8. The logic gate circuit 8 will receive the falling edge signal and / or pulse signal.

[0108] Based on this, the reset unit 6 can output a corresponding reset signal by judging whether the pulse signal has a falling edge, or by judging the falling edge signal output by the timeout counter 7, or by responding to the external reset pulse of the external reset control unit 9. It integrates a normal reset path triggered by the falling edge of the output signal, and a timeout counter 7 reset path triggered by loop activity when the output is abnormal (always low). This prevents the circuit from deadlocking when the input time difference is extremely small, realizes a complete timeout protection and reset mechanism and the construction of a dual-mode reset system, ensures the reliable operation and automatic recovery capability of the circuit under various operating conditions, and improves the robustness of the system.

[0109] In one embodiment, the first loop unit includes: a first signal selector and a first pulse generator;

[0110] The first input terminal of the first signal selector is used to receive the first initial test signal;

[0111] The controlled terminal of the first signal selector is connected to the output terminal of the loop control unit;

[0112] The output of the first signal selector is connected to the input of the first pulse generator;

[0113] The output of the first pulse generator is connected to the second input of the first signal selector and the first input of the phase comparison unit, respectively.

[0114] In one embodiment, the second loop unit includes: a second signal selector and a second pulse signal generator;

[0115] The first input terminal of the second signal selector is used to receive the second initial test signal;

[0116] The controlled terminal of the second signal selector is connected to the output terminal of the loop control unit;

[0117] The output of the second signal selector is connected to the input of the second pulse generator.

[0118] The output of the second pulse generator is connected to the second input of the second signal selector and the second input of the phase comparison unit, respectively.

[0119] It should be noted that, as Figure 5 As shown, 11 is the first signal selector and 12 is the second signal selector.

[0120] In one embodiment, the loop control unit includes: a first D flip-flop, a second D flip-flop, and an edge detection circuit;

[0121] The input terminal of the edge detection circuit is used to receive the first initial test signal;

[0122] The output of the edge detection circuit is connected to the clock terminal of the first D flip-flop;

[0123] The output of the first D flip-flop is connected to the controlled terminal of the first signal selector.

[0124] The clock input of the second D flip-flop is used to receive the second initial test signal;

[0125] The output of the second D flip-flop is connected to the controlled terminal of the second signal selector.

[0126] The data terminals of the first and second D flip-flops are used to receive power supply voltage signals.

[0127] It should be noted that, as Figure 6 As shown, DFF1 and DFF2 are the first and second D flip-flops, respectively. VDD is the power supply voltage signal, data is the first initial test signal, and cp is the second initial test signal. D is the data terminal of the D flip-flop, Q is the output terminal of the D flip-flop, and CLK is the clock terminal of the D flip-flop.

[0128] In one embodiment, the edge detection circuit includes: a first buffer, a second buffer, and a first XOR gate;

[0129] The input terminal of the first buffer and the first input terminal of the first XOR gate are used to receive the first initial test signal;

[0130] The output of the first buffer is connected to the input of the second buffer, and the output of the second buffer is connected to the second input of the first XOR gate.

[0131] The output of the first XOR gate is connected to the clock terminal of the first D flip-flop.

[0132] It should be noted that, as Figure 6 As shown, 31 is the first buffer, 32 is the second buffer, and 33 is the first XOR gate.

[0133] In one embodiment, the phase comparison unit includes: a timing detection subunit and a first logic gate circuit; the output unit includes: a third D flip-flop;

[0134] The input terminal of the timing detection subunit is used to receive the first initial test signal and the second initial test signal, respectively;

[0135] The output of the timing detection subunit is connected to the data terminal of the third D flip-flop, and is used to output the target pulse signal to the third D flip-flop when the time difference between the first initial test signal and the second initial test signal is not less than a preset time threshold.

[0136] The input terminals of the first logic gate circuit are used to receive the first initial test signal and the second initial test signal, respectively.

[0137] The output of the first logic gate is connected to the clock terminal of the third D flip-flop, and is used to output a trigger signal to the third D flip-flop when the first initial test signal and the second initial test signal are detected to be in the target state.

[0138] It should be noted that, as Figure 5 As shown, DFF_out is the third D flip-flop. The timing detection subunit may include a latch and an inverter, and the first logic gate may be a NAND gate (such as...). Figure 5 As shown in Figure 41), this latch can be an SR latch. The timing monitoring subunit and the first logic gate circuit constitute a high-sensitivity phase comparator. It is understood that this phase comparator can also be replaced by other types of arbiter circuits, such as a fully dynamic latch or a current-mode logic comparator, as long as it meets the femtosecond resolution requirement. Figure 5 The phase comparator in the system includes a timing detection subunit.

[0139] In one embodiment, the reset unit includes: a falling edge detector and a reset AND gate;

[0140] The input terminal of the falling edge detector is connected to the output unit, and the output terminal of the falling edge detector is connected to one input terminal of the reset AND gate;

[0141] The other input of the reset AND gate is connected to an external reset control unit, and the output of the reset AND gate is connected to a loop control unit.

[0142] It should be noted that, as Figure 7 As shown, 61 is a reset AND gate.

[0143] In one embodiment, the falling edge detector includes: a third buffer, a first NOT gate, and a first OR gate;

[0144] The input of the third buffer is connected to one input of the OR gate, serving as the input of the falling edge detector;

[0145] The output of the third buffer is connected to the input of the first NOT gate, the output of the first NOT gate is connected to the other input of the OR gate, and the output of the OR gate is the output of the falling edge detector.

[0146] It should be noted that, as Figure 7 As shown, 62 is the third buffer, 63 is the first NOT gate, and 64 is the first OR gate.

[0147] In one embodiment, the timeout counter includes: a first NOR gate, a second NOR gate, a fourth D flip-flop, a fifth D flip-flop, a second NOT gate, and a second XOR gate; the logic gate circuit includes a second OR gate;

[0148] One input of the first NOR gate is connected to the output of the first loop unit, and the other output of the first NOR gate is connected to the output of the second loop unit; one input of the second NOR gate is connected to the output of the first NOR gate; the other input of the second NOR gate is connected to the output of the output unit; the output of the second NOR gate is connected to the clock terminals of the fourth D flip-flop and the fifth D flip-flop, respectively; the data terminal of the fourth D flip-flop is connected to the second NOT gate, and through the second NOT gate, is connected to the output of the fourth D flip-flop; the output of the fourth D flip-flop is connected to one input of the second XOR gate; the other input of the second XOR gate is connected to the output of the fifth D flip-flop; the output of the second XOR gate is connected to the data terminal of the fifth D flip-flop; the output of the fifth D flip-flop is connected to one input of the second OR gate; the other input of the second OR gate is connected to the output of the output unit; and the output of the second OR gate is connected to the input of the falling edge detector.

[0149] It should be noted that, as Figure 7 As shown, 71 is the first NOR gate, 72 is the second NOR gate, DFF4 is the fourth D flip-flop, DFF5 is the fifth D flip-flop, 73 is the second NOT gate, 74 is the second XOR gate, and 81 is the second OR gate.

[0150] Understandably, the clock for the timeout counter may not use a NOR gate, but rather be determined by the second internal loop signal c. <1> Or the first internal loop signal d <1> Any pulse in the circuit can be used to trigger the loop, as long as it can respond to the loop activity. The OR gate logic in the final logic gate circuit can also be implemented using other equivalent logic combinations (such as NAND gates and NOR gates).

[0151] In one embodiment, the first pulse generator and the second pulse generator can be any circuit capable of generating fixed-width pulses in each cycle, such as a pulse shaping circuit or a pulse generator composed of a delay line and logic gates.

[0152] In one example, the selected pulse shaping circuit structure includes: fourth to seventh buffers, third XOR gate, third NOT gate, and sixth D flip-flop;

[0153] One end of the fourth buffer is connected to the fifth buffer, and through the fifth buffer, it is connected to one input of the third XOR gate; the other end of the fourth buffer is connected to the other input of the third XOR gate as an input; the output of the third XOR gate is connected to the clock terminal of the sixth D flip-flop, and the data terminal of the sixth D flip-flop is used to receive the power supply voltage signal. The output of the sixth D flip-flop, the sixth buffer, the seventh buffer, the third NOT gate, and the CDN terminal of the sixth D flip-flop are connected in sequence.

[0154] It should be noted that, as Figure 8 As shown, 101 to 104 are the fourth to seventh buffers, 105 is the third XOR gate, 106 is the third NOT gate, and DFF6 is the sixth D flip-flop. VDD is the power supply voltage signal. D represents the input signal.

[0155] The following will combine Figures 5 to 11 The timing monitoring circuit provided by the present invention will be described as follows.

[0156] Figures 5 to 11 The first initial signal to be measured is data; the second initial signal to be measured is cp, and there is a small initial time difference between the two, Tin. <0> The pulse signal output by the output unit has a width proportional to the initial time difference of the input. <1> d <1> These are two pulse signals that circulate in the feedback loop and have been normalized by the pulse shaping circuit. Where d <1> c is the first internal loop signal output by the first loop unit; <1> This is the second internal loop signal output by the second loop unit. D_Lead: In the high-sensitivity phase comparator, the intermediate signal generated by the SR latch, its level is used to characterize c. <1> and d <1> The order of arrival. Sample_Clk: In a high-sensitivity phase comparator, c... <1> and d <1> The sampling clock signal generated by the NAND gate is used to latch the state of D_Lead at a specific time. The first signal selector is a 2-to-1 multiplexer MUX1, the second signal selector is a 2-to-1 multiplexer MUX2, the first D flip-flop is DFF1, and the second D flip-flop is DFF2. The latching controller, composed of the two D flip-flops (DFF1, DFF2), directly controls the multiplexer. The third D flip-flop is DFF_out. Figure 5 The control logic module includes a timeout counter, logic gates, a reset unit, and an external reset control unit.

[0157] The timing monitoring circuit process can be divided into the following stages.

[0158] Phase 1: Standby and Trigger Lock.

[0159] (1) Standby state. Initially, the MUX<0:1> signal output by the lock controller is '0'. Both MUX1 and MUX2 select their external input ports and connect them to the external signals to be measured, data and cp, respectively. At this time, the circuit is in standby state, waiting for the rising edge of the input signal.

[0160] (2) Triggering and Locking. When data and cp have rising edges one after the other, these two rising edges trigger DFF1 and DFF2 respectively, causing the MUX<0:1> signal output by the lock controller to become '1', thereby causing MUX1 and MUX2 to immediately switch to their feedback input ports. In this way, the external data and cp signals are isolated, the system forms a closed feedback loop, and the initial timing relationship is "locked" into the loop. It can be understood that since there is an edge detection circuit before the clock of DFF1, both the rising and falling edges of data can trigger DFF1, while the clock of DFF2 is directly connected to the cp signal, so DFF2 can only be triggered by the rising edge of cp.

[0161] Second stage: Loop amplification.

[0162] After the lock controller locks, the signals output from MUX1 and MUX2 are fed into the pulse shaping circuit. The pulse shaping circuit generates a pair of pulse signals d with normalized width and amplitude in each cycle. <1> and c <1> This ensures that the benchmark for comparison is consistent in each loop. In the first loop, d <1> and c <1> The time difference between the rising edges is approximately Tin.

[0163] The output d of the pulse shaping circuit <1> and c <1> It propagates in the loop and eventually feeds back to the inputs of MUX1 and MUX2. Because d <1> and c <1> The two signal paths are physically designed to have a small, fixed delay mismatch. In each cycle, the time difference between the two pulse signals is systematically and steadily reduced by a fixed amount (the delay mismatch time interval). For example, if d <1> If the path delay is greater, then the time difference of the kth iteration... ,like Figure 9 As shown.

[0164] Phase 3: High-sensitivity comparison and output.

[0165] In each loop, d <1> and c <1> The pulse is fed into the SR latch of the phase comparator. The SR latch receives d. <1> and c <1> Depending on which signal arrives first, its inverter output D_Lead is set to '1' or '0'. For example, d <1> First arrives, D_Lead is '1'; c <1> First, D_Lead is '0'. Since it is a latch, this state will be maintained.

[0166] At the same time, d <1> and c <1> The signal is also fed into a NAND gate. When both pulses are high, the NAND gate outputs Sample_Clk as '0'; when both pulses end and return to low, the NAND gate outputs a rising edge from '0' to '1'. This rising edge serves as the clock signal for the third D flip-flop, DFF_out, and the SR latch is input to the data terminal of DFF_out via the output D_Lead of the inverter. Therefore, as long as d <1> and c <1> If the time difference is greater than the comparator's setup time, the SR latch can correctly determine the order, ensuring that the output q of DFF_out is correct. <0> It is '1'. As the loop continues, when d <1> and c <1> When the time difference is reduced to less than the comparator's setup time, the SR latch outputs '0', ultimately causing DFF_out to latch as '0'. Therefore, the q output by DFF_out... <0> It is a pulse whose width (from q) <0> The cycle starts at '1' and ends at '0', and is equal to the number of iterations multiplied by the period of each iteration. Since the number of iterations N is proportional to the initial time difference Tin (i.e., ... ), finally q <0> Pulse width T out It has been greatly magnified, with a magnification factor of the cycle period / , Figure 10 The simulation results shown in the image, specifically the slope, are magnified by approximately 500 times.

[0167] Phase 4: Reset and Timeout Control

[0168] (1) Normal reset. The falling edge detector continuously monitors q. <0> The output of q. Once q <0> The transition from '1' to '0' indicates the end of the amplification process. The detector immediately generates a reset pulse, which resets the lock controllers (DFF1, DFF2), causing the MUX<0:1> signal to return to '0', breaking the loop, and the system returns to standby mode.

[0169] (2) Timeout protection: Considering a special case: Tin is too small, so that d will be too small in the first loop. <1> and c <1> The time difference is less than the comparator setup time, causing q <0> The value remains '0', preventing the generation of a normal falling-edge reset signal. Meanwhile, the system is locked in a loop, resulting in a "deadlock." To address this issue, a timeout counter was designed.

[0170] The clock of the timeout counter is determined by c <1> and d <1> The pulse passes through a NOR gate and is then compared with q. <0> Generates through an OR gate ( This means that a counting clock is generated after the pulse of each cycle ends. Based on Figure 7 It can be seen that the timeout counter only operates when the "MUX<0:1> signal is '1' and q <0> It is enabled when the value is '0', and otherwise in standby mode. When the counter reaches a preset value (e.g., 4), it indicates that the system has entered a "deadlock", at which point the timeout counter will force a reset pulse.

[0171] (3) Final Reset. Since the output reset signal RESET is active low, the external reset pulse rst_n (forced reset) and the internal reset pulse clr (normal reset and timeout protection) are combined through an AND gate to ensure reliable system reset in either case. The timeout reset timing diagram is shown below. Figure 11 As shown.

[0172] In the embodiments provided in this application, it should be understood that the disclosed units are merely illustrative and can be implemented in other ways. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0173] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0174] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each functional unit can be a separate physical entity, or two or more functional units can be integrated into one processing unit.

[0175] The terms "first," "second," "third," "fourth," etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. It should also be noted that in the description of this invention, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0176] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A timing monitoring circuit, characterized in that, include: First loop unit, second loop unit, loop control unit, phase comparison unit, output unit; The first input terminal of the first loop unit is used to receive the first initial test signal; The output terminal of the first loop unit is connected to the second input terminal of the first loop unit and the first input terminal of the phase comparison unit, respectively, for outputting a first internal loop signal; The first input terminal of the second loop unit is used to receive the second initial test signal; the output terminal of the second loop unit is connected to the second input terminal of the second loop unit and the second input terminal of the phase comparison unit respectively, and is used to output the second internal loop signal. The input terminal of the loop control unit is used to receive the first initial test signal and the second initial test signal respectively. The output terminal of the loop control unit is connected to the controlled terminals of the first loop unit and the second loop unit respectively. When the rising edge or falling edge of the first initial test signal is detected, the first loop unit is controlled to select the first internal loop signal; and when the rising edge of the second initial test signal is detected, the second loop unit is controlled to select the second internal loop signal. The output terminal of the phase comparison unit is connected to the input terminal of the output unit, and is used to detect and control the output unit to output a pulse signal based on the time difference between the first internal loop signal and the second internal loop signal. The signal transmission path formed by the timing monitoring circuit is configured with a delay mismatch time interval, which is used to cause the first initial test signal and the second initial test signal to have a transmission delay, and to cause the first internal loop signal and the second internal loop signal to have a transmission delay.

2. The circuit according to claim 1, characterized in that, The first loop unit includes: a first signal selector and a first pulse generator; The first input terminal of the first signal selector is used to receive the first initial test signal; The controlled terminal of the first signal selector is connected to the output terminal of the loop control unit; The output of the first signal selector is connected to the input of the first pulse generator; The output terminal of the first pulse generator is connected to the second input terminal of the first signal selector and the first input terminal of the phase comparison unit, respectively.

3. The circuit according to claim 2, characterized in that, The second loop unit includes: a second signal selector and a second pulse signal generator; The first input terminal of the second signal selector is used to receive the second initial test signal; The controlled terminal of the second signal selector is connected to the output terminal of the loop control unit; The output of the second signal selector is connected to the input of the second pulse signal generator; The output terminal of the second pulse generator is connected to the second input terminal of the second signal selector and the second input terminal of the phase comparison unit, respectively.

4. The circuit according to claim 3, characterized in that, The loop control unit includes: a first D flip-flop, a second D flip-flop, and an edge detection circuit; The input terminal of the edge detection circuit is used to receive the first initial test signal; The output of the edge detection circuit is connected to the clock terminal of the first D flip-flop; The output terminal of the first D flip-flop is connected to the controlled terminal of the first signal selector; The clock input of the second D flip-flop is used to receive the second initial test signal; The output of the second D flip-flop is connected to the controlled terminal of the second signal selector; The data terminals of the first and second D flip-flops are used to receive power supply voltage signals.

5. The circuit according to claim 4, characterized in that, The phase comparison unit includes: a timing detection subunit and a first logic gate circuit; the output unit includes: a third D flip-flop; The input terminal of the timing detection subunit is used to receive the first internal loop signal and the second internal loop signal, respectively. The output terminal of the timing detection subunit is connected to the data terminal of the third D flip-flop, and is used to output a target pulse signal to the third D flip-flop when the time difference between the first initial test signal and the second initial test signal is not less than a preset time threshold. The input terminal of the first logic gate circuit is used to receive the first initial test signal and the second initial test signal, respectively; The output of the first logic gate is connected to the clock terminal of the third D flip-flop, and is used to output a trigger signal to the third D flip-flop when the first initial test signal and the second initial test signal are detected to be in the target state.

6. The circuit according to claim 4, characterized in that, The edge detection circuit includes: a first buffer, a second buffer, and a first XOR gate; The input terminal of the first buffer and the first input terminal of the first XOR gate are used to receive the first initial test signal; The output of the first buffer is connected to the input of the second buffer, and the output of the second buffer is connected to the second input of the first XOR gate. The output of the first XOR gate is connected to the clock terminal of the first D flip-flop.

7. The circuit according to any one of claims 1-6, characterized in that, Also includes: Reset unit and external reset control unit; The input terminal of the reset unit is connected to the output unit and the external reset control unit. The reset unit is connected to the reset terminal of the loop control unit. It is used to receive and detect the output signal of the pulse unit output by the output unit, and receive the external reset pulse of the external reset control unit. When the falling edge of the pulse signal is detected or the external reset pulse of the external reset control unit is received, the reset unit outputs a reset signal to the loop control unit.

8. The circuit according to claim 7, characterized in that, The reset unit includes: a falling edge detector and a reset AND gate; The input terminal of the falling edge detector is connected to the output unit, and the output terminal of the falling edge detector is connected to one input terminal of the reset AND gate; The other input of the reset AND gate is connected to the external reset control unit, and the output of the reset AND gate is connected to the loop control unit.

9. The circuit according to claim 8, characterized in that, It also includes timeout counters and logic gates; The input terminal of the timeout counter is connected to the output terminal of the first loop unit, the output terminal of the second loop unit, and the output terminal of the output unit, respectively. The output terminal of the timeout counter is connected to an input terminal of a logic gate circuit. It is used to generate a counting clock based on the number of cycles of the first internal loop signal and the second internal loop signal when the pulse signal has no falling edge, and to output a falling edge signal to the logic gate circuit when the counting clock reaches a preset number threshold. The other input terminal of the logic gate circuit is connected to the output terminal of the output unit, and the output terminal of the logic gate circuit is connected to the input terminal of the falling edge detector, for transmitting the falling edge signal and / or the pulse signal output by the timeout counter to the falling edge detector.

10. The circuit according to claim 9, characterized in that, The falling edge detector includes: a third buffer, a first NOT gate, and a first OR gate; The input terminal of the third buffer is connected to one input terminal of the OR gate, serving as the input terminal of the falling edge detector; The output of the third buffer is connected to the input of the first NOT gate, the output of the first NOT gate is connected to the other input of the OR gate, and the output of the OR gate is the output of the falling edge detector.

Images