Display panel and display device
By designing the multiplexing circuit as electrically connected first and second switch groups, and setting the first switch group with a smaller layout area in the non-display portion, the problem that the bottom bezel of the display panel could not be reduced to its limit in the prior art is solved, achieving a smaller bezel size and a higher display effect.
Patent Information
- Application Number
- CN202511366416.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-23
- Publication Date
- 2025-11-18
AI Technical Summary
The bottom bezel size of existing display panels has not been reduced to its limit, especially for panels using ramless display driver chips, where multiplexing circuits occupy a large space, making it difficult to further reduce the bezel size.
The multiplexing circuit is configured as a first switch group and a second switch group that are electrically connected. The first switch group is located in the non-display area and has a smaller layout area than the second switch group. Only the first switch group is located in the non-display area. The area occupied by the second switch group is reduced by lowering the channel aspect ratio.
It effectively reduces the size of the bottom bezel of the display panel, increases the screen-to-body ratio and improves the display effect, and reduces the power consumption of the multiplexing circuit.
Smart Images
Figure CN120977202A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and more specifically to a display panel and a display device. Background Technology
[0002] With the development of display technology, people are increasingly pursuing displays with high screen-to-body ratios. Flexible panels, due to their bendability and smaller bezels, have captured a significant share of the display panel market. For example... Figure 1 As shown, in the prior art, the driving chip 50' is bent along with the wiring area 30' of the display panel 100' to the backlight side of the display panel 100' to reduce the bottom bezel size d' of the display panel. However, the bottom bezel size of the display panel 100' has not yet been reduced to its limit, and further improvements are needed. Summary of the Invention
[0003] In view of the problems in the prior art, the purpose of the present invention is to provide a display panel and display device to reduce the size of the bottom bezel of the display panel and improve the display effect of the display panel.
[0004] In a first aspect, embodiments of the present invention provide a display panel, including a display area, a bending area, and a wiring area. The display area is connected to the wiring area via the bending area. The display area includes a display portion and a non-display portion disposed on the side of the display portion near the bending area. The display portion has periodically arranged pixel columns, and the non-display portion has multiple multiplexing circuits for providing data signals to corresponding pixel columns.
[0005] The multiplexing circuit includes a first switch group and a second switch group that are electrically connected. The first switch group is located in the non-display area, and the second switch group extends from the bending area and is located in the wiring area. The layout area of the first switch group is smaller than the layout area of the second switch group.
[0006] Secondly, embodiments of the present invention provide a display device, including the display panel described in the first aspect.
[0007] The display panel and display device provided by the present invention have the following advantages:
[0008] By setting the multiplexing circuit as an electrically connected first switch group and second switch group, and only the first switch group is located in the non-display section, the layout area of the first switch group is smaller than that of the second switch group. This reduces the area occupied by the multiplexing circuit in the non-display section, thereby reducing the size of the non-display section, i.e., reducing the size of the bottom bezel of the display panel, and improving the display effect of the display panel. Attached Figure Description
[0009] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.
[0010] Figure 1 This is a schematic diagram of the display panel after bending, provided by the relevant technology.
[0011] Figure 2 This is a schematic diagram of the display panel before bending, provided by the relevant technology.
[0012] Figure 3 This is a schematic diagram of the specific structure of a multiplexed circuit in the prior art;
[0013] Figure 4 This is a schematic diagram of a display panel provided in an embodiment of the present invention;
[0014] Figure 5 This is a schematic diagram of the structure of a multiplexing circuit provided in an embodiment of the present invention;
[0015] Figure 6 This is a schematic diagram of the specific structure of a multiplexing circuit provided in an embodiment of the present invention;
[0016] Figure 7 This is a schematic diagram of the specific structure of a multiplexing circuit provided in another embodiment of the present invention;
[0017] Figure 8 This is a schematic diagram of a display device provided in an embodiment of the present invention.
[0018] Figure label:
[0019] 100' Display Panel 30 Wiring Area
[0020] 40' Multiplexing Circuit
[0021] 50' Driver chip 41 First switch group
[0022] a' Input terminal 42 Second switch group
[0023] b1'~b4' First output terminal~Fourth output terminal a Input terminal
[0024] c1'~c4' First control terminal~Fourth control terminal b Output terminal
[0025] SW1'~SW4' First control line~Fourth control line c Control terminal
[0026] M1'~M4' First transistor~Fourth transistor SW control lines
[0027] 100 Display panel M11, M12 First switching transistor
[0028] 10 Display Area SW11, SW12 First Control Line
[0029] 11 Display section SW21, SW22 second control lines
[0030] 12 Non-display section b1~b4 output terminals
[0031] 20 Bending area D Data cable
[0032] M21, M22, M23, M24 Second switching transistors
[0033] C11, C12, C21, C22, C23, C24 control terminals
[0034] D1, D2, D3, D4 (First Data Line to Fourth Data Line) Detailed Implementation
[0035] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.
[0036] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.
[0037] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0038] It should be further understood that the terms "comprising" or "including" indicate the presence of a feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C." Exceptions to this definition only arise when a combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.
[0039] The driver chip includes the Display Driver Integrated Circuit (DDIC). The DDIC receives processed digital image signals from the image processor, converts them into analog signals, processes them according to the display's resolution and refresh rate, and finally outputs the converted signals to each pixel of the display through pins to control their brightness and color changes. In existing technology, the display driver chips that drive OLED display panels include RAM-less display driver chips and RAM display driver chips. Compared to RAM display driver chips, RAM-less display driver chips are increasingly being used in the display industry due to their superior display performance and cost advantages.
[0040] However, the bottom bezel of display panels using ramless display driver chips can currently only be reduced to about 1.2mm, while the bottom bezel of display panels using ram-based display driver chips can already reach about 1.0mm. Therefore, the bottom bezel size of display panels using ramless display driver chips has not reached its limit and needs to be further reduced.
[0041] In practical design, ramless display driver chips are paired with multiplexer circuits (mux circuits) to distribute the data signals output by the display driver chip to the corresponding data lines in a time-division manner. This allows more pixels to be controlled with fewer signal lines, reducing the number of pins on the display driver chip and lowering the complexity and cost of the system. Figure 2 A schematic diagram of a display panel in the prior art before bending is shown. (Example) Figure 2 As shown, the multiplexing circuit 40' is usually located in the lower bezel area of the display panel 100'. Therefore, to reduce the size of the lower bezel of the display panel 100', the space occupied by the multiplexing circuit 40' in this area needs to be reduced.
[0042] Figure 3 A schematic diagram of a specific structure of a multiplexing circuit in the prior art is shown. For example... Figure 3 As shown, the multiplexing circuit 40' includes one input terminal a', four output terminals (first output terminal b1' to fourth output terminal b4') and four control terminals (first control terminal c1' to fourth control terminal c4'). Furthermore, the multiplexing circuit 40' also includes a first transistor M1', a second transistor M2', a third transistor M3' and a fourth transistor M4', and a first control line SW1', a second control line SW2', a third control line SW3' and a fourth control line SW4'.
[0043] Specifically, the input terminals of the first transistor M1', the second transistor M2', the third transistor M3', and the fourth transistor M4' are electrically connected to the input terminal a' of the multiplexing circuit 40'; the control terminal of the first transistor M1' is electrically connected to the first control line SW1' via the first control terminal c1', and the output terminal of the first transistor M1' is electrically connected to the first output terminal b1'; the control terminal of the second transistor M2' is electrically connected to the second control line SW2' via the second control terminal c2', and the output terminal of the second transistor M2' is electrically connected to the second output terminal b2'; the control terminal of the third transistor M3' is electrically connected to the third control line SW3' via the third control terminal c3', and the output terminal of the third transistor M3' is electrically connected to the third output terminal b3'; the control terminal of the fourth transistor M4' is electrically connected to the fourth control line SW4' via the fourth control terminal c4', and the output terminal of the fourth transistor M4' is electrically connected to the fourth output terminal b4'.
[0044] When the first control line SW1' provides an on level, the first transistor M1' is turned on. This means the data signal transmitted to input terminal a' is transmitted through the first transistor M1' to the first output terminal b1', thus providing a data signal for the corresponding data line connected to the first output terminal b1'. When the second control line SW2' provides an on level, the second transistor M2' is turned on. This means the data signal transmitted to input terminal a' is transmitted through the second transistor M2' to the second output terminal b2', thus providing a data signal for the corresponding data line connected to the second output terminal b2'. When the third control line SW3' provides an on level, the third transistor M3' is turned on. This means the data signal transmitted to input terminal a' is transmitted through the third transistor M3' to the third output terminal b3', thus providing a data signal for the corresponding data line connected to the third output terminal b3'. When the fourth control line SW4' provides a conduction level, the fourth transistor M4' conducts. This means the data signal transmitted to input terminal a' will be transmitted through the fourth transistor M4' to the fourth output terminal b4', thus providing a data signal to the corresponding data line connected to the fourth output terminal b4'. Figure 3The multiplexing circuit 40' shown takes the data signal output from one pin of the driver chip 50' and distributes it to four data lines in a time-division manner through timing control logic.
[0045] Currently, the channel aspect ratios of the transistors in the multiplexing circuit 40' are generally 96:3, 128:3, 144:3, etc. The large channel aspect ratios of the transistors result in larger transistor sizes, which in turn causes the multiplexing circuit 40' to occupy more layout space on the lower bezel of the display panel 100'. Consequently, it is difficult to further reduce the size of the lower bezel of the display panel 100' using the existing transistor sizes.
[0046] To address the aforementioned problems with display panels, this invention provides a display panel including a display area, a bending area, and a wiring area. The display area is connected to the wiring area via the bending area. The display area includes a display portion and a non-display portion located on the display portion near the bending area. The display portion has periodically arranged pixel columns, and the non-display portion has multiple multiplexing circuits. These multiplexing circuits provide data signals to corresponding pixel columns.
[0047] The multiplexing circuit includes a first switch group and a second switch group that are electrically connected. The first switch group is located in the non-display area, and the second switch group extends from the bending area and is located in the wiring area. The layout area of the first switch group is smaller than the layout area of the second switch group.
[0048] The technical solution provided by this invention sets the multiplexing circuit as an electrically connected first switch group and second switch group, and only the first switch group is located in the non-display part. Since the layout area of the first switch group is smaller than that of the second switch group, the area occupied by the multiplexing circuit in the non-display section can be reduced, and the size of the non-display section can be further reduced, that is, the size of the bottom bezel of the display panel can be reduced. The size of the non-display part of the display panel is reduced, the screen ratio of the display panel is increased, and thus the display effect of the display panel can be improved.
[0049] The display panel provided by the present invention will be explained in detail below with reference to specific embodiments.
[0050] Figure 4 A schematic diagram of a display panel according to an embodiment of the present invention is shown. Figure 4As shown, the display panel 100 includes a display area 10, a bending area 20, and a wiring area 30. The display area 10 is connected to the wiring area 30 through the bending area 20. The display area 10 includes a display portion 11 and a non-display portion 12 located on the side of the display portion 11 near the bending area 20. The display portion 11 has periodically arranged pixel columns, and the non-display portion 12 has multiple multiplexing circuits 40. The multiplexing circuits 40 are used to provide data signals to the corresponding multiple pixel columns.
[0051] The multiplexing circuit 40 includes a first switch group 41 and a second switch group 42 that are electrically connected. The first switch group 41 is located in the non-display portion 12, and the second switch group 42 extends from the bending area 20 and is located in the wiring area 30. The layout area of the first switch group 41 is smaller than the layout area of the second switch group 42.
[0052] By configuring the multiplexing circuit 40 as an electrically connected first switch group 41 and second switch group 42, the layout area of the first switch group 41 on the display panel is smaller than the layout area of the second switch group 42 on the display panel 100. Since only the first switch group 41 is located in the non-display portion 12, the area occupied by the multiplexing circuit 40 on the non-display portion 12 of the display panel 100 will be reduced accordingly. When the area occupied by the multiplexing circuit 40 on the non-display portion 12 is reduced, but the other arrangements of the non-display portion 12 remain unchanged, the size of the non-display portion 12 can be reduced accordingly, that is, the size of the lower bezel of the display panel 100 can be reduced.
[0053] Furthermore, in the display panel 100 provided in this embodiment of the invention, the width d of the non-display portion 12 is less than or equal to 1.1 mm. That is, the bottom bezel of the display panel provided in this embodiment of the invention is less than or equal to 1.1 mm. For example, the width d of the non-display portion 12 can be 1 mm, 0.9 mm, or 0.8 mm.
[0054] Figure 5 A schematic diagram of a multiplexing circuit according to an embodiment of the present invention is shown. (In conjunction with...) Figure 4 and Figure 5As shown, the display panel 100 also includes a driver chip 50, located in the wiring area 30; the multiplexing circuit 40 includes an input terminal a, a control terminal c, and an output terminal b. The input terminal a is electrically connected to the driver chip 50, the control terminal c is electrically connected to the control signal line SW, and the output terminal b is electrically connected to the data line of the corresponding pixel column. The input terminal a is electrically connected to the driver chip 50 to receive the data signal transmitted by the driver chip 50; the control terminal c is electrically connected to the control signal line SW to enable a portion of the circuit of the multiplexing circuit 40; the output terminal b is electrically connected to the data line of the corresponding pixel column to transmit the data signal received by the input terminal a to the corresponding data line through the conduction circuit of the multiplexing circuit 40, providing the necessary data signal for the display panel to display.
[0055] It should be noted that on the display panel, pixels in the same pixel column receive data signals through the same data line. Therefore... Figure 4 The output terminal b of the multiplexing circuit 40 is electrically connected to the corresponding data line D on the display panel 100.
[0056] Figure 6 A schematic diagram of the specific structure of a multiplexing circuit provided in an embodiment of the present invention is shown. For example... Figure 6 As shown, the first switch group 41 includes at least one first switch transistor and at least one first control line. The number of first switch transistors is the same as the number of first control lines. The control terminal of the first switch transistor is electrically connected to the corresponding first control line, the input terminal of the first switch transistor is electrically connected to the driver chip 50, and the output terminal of the first switch transistor is electrically connected to the input terminal of the corresponding second switch group 42.
[0057] The second switch group 42 includes multiple second switch transistors and multiple second control lines; the control terminal of the second switch transistor is electrically connected to the corresponding second control line, the input terminal of the second switch transistor is electrically connected to the output terminal of the corresponding first switch transistor, and the output terminal of the second switch transistor is electrically connected to the corresponding data line.
[0058] For example, Figure 6 The first switch group 41 shown includes two first switch transistors and two first control lines, namely first switch transistor M11, first switch transistor M12, first control line SW11 and first control line SW12.
[0059] Specifically, the control terminal c11 of the first switching transistor M11 is electrically connected to the first control line SW11; the control terminal c12 of the first switching transistor M12 is electrically connected to the first control line SW12; and the input terminals of both the first switching transistors M11 and M12 are electrically connected to the driver chip 50. It should be noted that the input terminals of the first switching transistors M11 and M12 are electrically connected, meaning they are both electrically connected to the same pin on the driver chip 50. This pin on the driver chip 50 can provide different data signals to the input terminals of the first switching transistors M11 and M12 in a time-division multiplexing manner.
[0060] Figure 6 The second switch group 42 shown includes four second switch transistors and two second control lines, namely second switch transistor M21, second switch transistor M22, second switch transistor M23, second switch transistor M24, second control line SW21, and second control line SW22.
[0061] Specifically, the control terminal c21 of the second switch M21 is electrically connected to the second control line SW22, the input terminal of the second switch M21 is electrically connected to the output terminal of the first switch M11, and the output terminal b1 of the second switch M21 is electrically connected to the first data line D1. The control terminal c22 of the second switch M22 is electrically connected to the second control line SW21, the input terminal of the second switch M22 is electrically connected to the output terminal of the first switch M11, and the output terminal b2 of the second switch M22 is electrically connected to the second data line D2. The control terminal c23 of the second switch M23 is electrically connected to the second control line SW22, the input terminal of the second switch M23 is electrically connected to the output terminal of the first switch M12, and the output terminal b3 of the second switch M23 is electrically connected to the third data line D3. The control terminal c24 of the second switch M24 is electrically connected to the second control line SW21, the input terminal of the second switch M24 is electrically connected to the output terminal of the first switch M12, and the output terminal b4 of the second switch M24 is electrically connected to the fourth data line D4.
[0062] The working principle of the multiplexing circuit 40 is as follows: when the first control line SW11 and the second control line SW22 provide a conduction level at the same time, the first switch M11 and the second switch M21 are turned on, and the driver chip 50 provides the required data signal to the first data line D1.
[0063] When the first control line SW11 and the second control line SW21 simultaneously provide a conduction level, the first switch M11 and the second switch M22 are turned on, and the driver chip 50 provides the required data signal to the second data line D2.
[0064] When the first control line SW12 and the second control line SW22 simultaneously provide a conduction level, the first switch M12 and the second switch M23 are simultaneously turned on, and the driver chip 50 provides the required data signal to the third data line D3.
[0065] When the first control line SW12 and the second control line SW21 simultaneously provide a conduction level, the first switch M12 and the second switch M24 are simultaneously turned on, and the driver chip 50 provides the required data signal to the fourth data line D4.
[0066] therefore, Figure 6 The multiplexing circuit 40 shown can distribute a one-channel data signal output from one pin of the driver chip to four data lines in a time-division manner through timing control logic. It should be noted that the specific structure of the multiplexing circuit 40 is not limited to this; those skilled in the art can configure the number of output signals of the multiplexing circuit 40 according to actual needs.
[0067] For further information, please refer to [link / reference]. Figure 6 When there are multiple first and second switching transistors, the first and second switching transistors are arranged in a direction perpendicular to the direction from the display area 10 to the bending area 20; the data lines are evenly arranged in a direction parallel to the direction from the display area 10 to the bending area 20. Multiple first and second switching transistors are arranged in a direction perpendicular to the direction from the display area 10 to the bending area 20, meaning that multiple first switching transistors are only located within the non-display portion 12, and multiple second switching transistors are only located in the area extending from the bending area 20 to the wiring area 30. Further, in this embodiment, the layout area of the first switching transistors is smaller than the layout area of the second switching transistors. When the layout area of the first switching transistors is smaller than the layout area of the second switching transistors, the layout area of the first switch group 41 can be correspondingly smaller than the layout area of the second switch group 42. Since the first switch group 41 is located in the non-display portion 12 of the display area 10, it occupies a smaller area in the non-display portion 12, thus reducing the area of the non-display portion 12, i.e., reducing the distance of the lower bezel of the display panel after bending.
[0068] Figure 7 A detailed structural diagram of a multiplexing circuit according to an embodiment of the present invention is shown. For example... Figure 7As shown, in this embodiment of the invention, both the first and second switching transistors are thin-film transistors (TFTs). A TFT includes a gate, a source, and a drain. In this embodiment, the control terminal of the switching transistor is the gate of the TFT, the input terminal is one of the source and drain of the TFT, and the output terminal is the other of the source and drain of the TFT. Based on their characteristics, TFTs can be classified into N-type and P-type transistors. A P-type TFT conducts when the control terminal is low and is cut off when it is high; while an N-type TFT conducts when the control terminal is high and is cut off when it is low. Those skilled in the art can specify the type of TFT according to actual needs; no specific limitations are made here.
[0069] Furthermore, when the first switching transistor is a thin-film transistor, the channel width-to-length ratio of the first switching transistor is one of 144:3, 128:3, or 196:3. When the first switching transistor is a thin-film transistor, the size of the thin-film transistor is the same as the size of the transistor in the prior art multiplexing circuit 40'.
[0070] When the second switching transistor is a thin-film transistor (TFT), its channel aspect ratio is 3:2 or 5:3. When the second switching transistor is a TFT, its size is smaller than that of the first switching transistor. By reducing the channel aspect ratio of the second switching transistor, the area occupied by its channel can be reduced, further reducing the layout area occupied by the second switching transistor on the display panel 100. This reduces the area of the non-display portion 12 on the display panel 100 occupied by the multiplexing circuit 40, thus reducing the size of the lower bezel of the display panel 100.
[0071] Furthermore, it should be noted that the first switching transistor has a relatively large channel length-to-width ratio. When the display panel is lit, the conduction current of the first switching transistor can be designed to be in the saturation region, while the second switching transistor is in the linear region. When the display panel is lit, the first switching transistor being in the saturation region enhances the driving capability, ensures current stability, and improves signal transmission stability. The second switching transistor being in the linear region saves power consumption in the multiplexing circuit, thereby reducing the power consumption of the display panel 100 and improving the energy efficiency of the display panel.
[0072] This invention also provides a display device, including the display panel described above. The display device 1000 includes the display panel described above, and therefore can achieve all the technical effects of the aforementioned display panel, which will not be repeated here. Figure 8 A schematic diagram of a display device according to an embodiment of the present invention is shown. Figure 8As shown, the display device 1000 includes the display panel described above. Specifically, the display device 1000 can be a mobile phone, wireless device, personal data assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, TV monitor, flat panel display, computer monitor, car display, electronic photograph, electronic billboard or sign, projector, building structure, packaging and aesthetic structure, etc.
[0073] In summary, the display panel and display device provided by the present invention have the following advantages:
[0074] By setting the multiplexing circuit as an electrically connected first switch group and second switch group, and only the first switch group is located in the non-display section, the area occupied by the multiplexing circuit in the non-display section can be reduced because the layout area of the first switch group is smaller than that of the second switch group. Therefore, the size of the non-display section can be reduced, i.e., the size of the bottom bezel of the display panel can be reduced.
[0075] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A display panel, characterized in that, The system includes a display area, a bending area, and a wiring area. The display area is connected to the wiring area via the bending area. The display area includes a display portion and a non-display portion located on the display portion near the bending area. The display portion has periodically arranged pixel columns, and the non-display portion has multiple multiplexing circuits. These multiplexing circuits provide data signals to corresponding pixel columns. The multiplexing circuit includes a first switch group and a second switch group that are electrically connected. The first switch group is located in the non-display area, and the second switch group extends from the bending area and is located in the wiring area. The layout area of the first switch group is smaller than the layout area of the second switch group.
2. The display panel according to claim 1, characterized in that, The width of the non-display portion is less than or equal to 1.1 mm.
3. The display panel according to claim 1, characterized in that, It also includes a driver chip located in the wiring area; the multiplexing circuit includes an input terminal, a control terminal, and an output terminal, the input terminal being electrically connected to the driver chip, the control terminal being electrically connected to the control signal line, and the output terminal being electrically connected to the data line corresponding to the pixel column.
4. The display panel according to claim 3, characterized in that, The first switch group includes at least one first switch transistor and at least one first control line, the number of first switch transistors being the same as the number of first control lines; the control terminal of the first switch transistor is electrically connected to the corresponding first control line, the input terminal of the first switch transistor is electrically connected to the driver chip, and the output terminal of the first switch transistor is electrically connected to the input terminal of the corresponding second switch group.
5. The display panel according to claim 4, characterized in that, The second switch group includes multiple second switch transistors and multiple second control lines; the control terminal of the second switch transistor is electrically connected to the corresponding second control line, the input terminal of the second switch transistor is electrically connected to the output terminal of the corresponding first switch transistor, and the output terminal of the second switch transistor is electrically connected to the corresponding data line.
6. The display panel according to claim 5, characterized in that, When there are multiple first switching transistors and multiple second switching transistors, the first switching transistors and the second switching transistors are arranged in a direction perpendicular to the direction from the display area to the bending area; the data lines are evenly arranged in a direction parallel to the direction from the display area to the bending area.
7. The display panel according to claim 5, characterized in that, The layout area of the first switching transistor is smaller than that of the second switching transistor.
8. The display panel according to claim 7, characterized in that, The first switching transistor is a thin-film transistor, and the channel width-to-length ratio of the first switching transistor is one of 144:3, 128:3 or 196:
3.
9. The display panel according to claim 7, characterized in that, The second switching transistor is a thin-film transistor, and the aspect ratio of the channel of the second switching transistor is 3:2 or 5:
3.
10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.