Shift register, gate drive circuit and display panel

Abstract

The invention provides a shift register, a gate drive circuit and a display panel, and the shift register comprises a pull-up module, a signal storage module and an output module, and enables a signal of a first node of the shift register to have an effective level in a first time period. And storing the level information of the signal of the first node to a second node of the shift register in a second time period, enabling the signal of the first node to have an invalid level in a third time period, and enabling the signal of the first node to have an effective level again in a fourth time period, therefore, the signal of the first node can have the ineffective level in the third time period between the first time period with the effective level and the fourth time period, the duration of bias stress borne by an output transistor in the output module is shortened, and the influence of the bias stress borne by the output transistor for a long time is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to shift registers, gate drive circuits, and display panels. Background Technology

[0002] In a shift register, if the output transistor remains on for an extended period of time, it will be continuously subjected to bias stress, causing a drift in the threshold voltage and affecting the quality of the gate control signal output by the shift register. Summary of the Invention

[0003] This application provides a shift register, a gate drive circuit, and a display panel, which can improve the effect of bias stress on the output transistor over a long period of time.

[0004] This application provides a shift register, including a pull-up module, a signal storage module, and an output module. The pull-up module is electrically connected to a first node and is configured to control the signal of the first node to have a corresponding valid level in a first time period according to a pull-up control signal. The signal storage module is electrically connected to a first node and a second node and is configured to store the level information of the first node in a second time period following the first time period according to the signal of the first node and a first control signal, control the signal of the first node to have a corresponding invalid level in a third time period following the second time period according to a second control signal, and control the signal of the first node to have a corresponding valid level in a fourth time period following the third time period according to the first control signal and the signals of the second node. The output module is electrically connected to the first node and includes an output transistor configured to transmit a clock signal to the signal output terminal of the shift register according to the valid level corresponding to the signal of the first node.

[0005] This application also provides a gate driving circuit, including any of the aforementioned shift registers. The pull-up control signals corresponding to the first m shift registers are start signals, and the pull-up control signal corresponding to the nth shift register is the gate control signal output by the nmth stage shift register, where 1 ≤ m. <n,n-m≥1。

[0006] This application also provides a display panel including any of the aforementioned gate driving circuits; and a plurality of sub-pixels. The plurality of sub-pixels are electrically connected to the gate driving circuits and are configured to receive a plurality of gate control signals output by the gate driving circuits. The display panel includes a display period and a touch period in a display cycle. The display period includes a first period, the touch period includes a third period, a second period is located before the touch period and between the touch period and the display period, and a fourth period is located after the touch period and between the touch period and the display period.

[0007] The above technical solution includes a shift register comprising a pull-up module electrically connected to the first node, a signal storage module electrically connected to the first node and the second node, and an output module electrically connected to the first node. It ensures that the signal of the first node has an effective level during a first time period, stores the signal level information of the first node in the second node during a second time period, invalidates the signal of the first node during a third time period, and makes the signal of the first node effective again during a fourth time period. This allows the signal of the first node to have an invalid level during the third time period between the first and fourth time periods, thereby shortening the duration of bias stress on the output transistor in the output module and mitigating the impact of long-term bias stress on the output transistor. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0009] Figure 1 This is a block diagram illustrating the principle of a shift register according to an embodiment of this application;

[0010] Figure 2 This is a circuit diagram of the shift register according to an embodiment of this application;

[0011] Figure 3 This is a timing diagram of the signals corresponding to the shift register in an embodiment of this application;

[0012] Figure 4 This is a schematic diagram of the gate drive circuit according to an embodiment of this application;

[0013] Figure 5 This is a timing diagram of the signals corresponding to the gate drive circuit in an embodiment of this application;

[0014] Figure 6 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0015] Figure 7 The timing diagram is provided for a comparative shift register in an embodiment of this application.

[0016] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0018] Furthermore, descriptions involving "first," "second," etc., in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0019] Figure 1 This is a block diagram illustrating the principle of a shift register according to an embodiment of this application. This application provides a shift register GA, which is configured to output a gate control signal Scan through its signal output terminal Sout. The shift register GA may include a pull-up module 100, a signal storage module 200, and an output module 300.

[0020] Pull-up module 100 is electrically connected to the first node No1. Pull-up module 100 is configured to control the signal of the first node No1 in the first time period tA (as described below) according to the pull-up control signal STV. Figure 3 (As shown) has a corresponding effective level.

[0021] Optionally, the pull-up module 100 is configured to transmit the pull-up control signal STV to the first node No1 during a first time period tA, so that the signal of the first node No1 has a corresponding valid level during the first time period tA. Alternatively, the pull-up module 100 is configured to transmit the pull-up control signal STV to the first node No1 based on the valid level of the pull-up control signal STV, so that the signal of the first node No1 has a valid level.

[0022] Optionally, the pull-up module 100 can also be electrically connected to the constant voltage terminal. The pull-up module 100 is configured to control the electrical connection between the first node No1 and the constant voltage terminal according to the pull-up control signal STV. For example, the pull-up module 100 can be configured to connect the electrical connection between the first node No1 and the constant voltage terminal according to the effective level of the pull-up control signal STV, and the pull-up module 100 can be configured to disconnect the electrical connection between the first node No1 and the constant voltage terminal according to the ineffective level of the pull-up control signal STV. The constant voltage terminal can be a high-voltage terminal or a low-voltage terminal.

[0023] Please continue reading. Figure 1 The signal storage module 200 is electrically connected to the first node No1 and the second node No2. The signal storage module 200 is configured to store the level information of the signal of the first node No1 to the second node No2 in the second time period tB after the first time period tA according to the signal of the first node No1 and the first control signal Scs, control the signal of the first node No1 to have a corresponding invalid level in the third time period tC after the second time period tB according to the second control signal Res, and control the signal of the first node No1 to have a corresponding valid level in the fourth time period tD after the third time period tC according to the first control signal Scs and the signal of the second node No2.

[0024] Output module 300 is electrically connected to the first node No1. Output module 300 includes output transistor To. Output transistor To is configured to transmit clock signal CK to the signal output terminal Sout of shift register GA according to the effective level corresponding to the signal of the first node No1.

[0025] By including a pull-up module 100, a signal storage module 200, and an output module 300 in the shift register GA, the signal of the first node No1 can have a transition from an effective level to an ineffective level and a transition from an ineffective level to an effective level during the first time period tA to the fourth time period tD. This allows the output transistor To to switch between the on and off states according to the signal of the first node No1, thereby shortening the on-time of the output transistor To and improving the bias stress effect on the output transistor To over a long period of time.

[0026] It should be noted that the effective level of a signal can refer to the level state that turns on the transistor controlled by the signal, while the ineffective level of a signal can refer to the level state that turns off the transistor controlled by the signal. Optionally, the effective level can refer to either a high level or a low level of the signal, and the ineffective level can refer to the other of a high level or a low level of the signal.

[0027] Please continue reading. Figure 1The signal storage module 200 may include a first control unit 201. The first control unit 201 is electrically connected to a first node No1 and a second node No2. The first control unit 201 is configured to store the signal level information of the first node No1 to the second node No2 during a second time period tB based on the signal of the first node No1 and a first control signal Scs, and to control the signal of the first node No1 to have a corresponding effective level during a fourth time period tD based on the first control signal Scs. By configuring the first control unit 201, the storage of the signal level information of the first node No1 and the recovery of the effective level of the signal of the first node No1 can be realized.

[0028] In some embodiments, the first control signal Scs may include a first sub-control signal SQ1, and the first control unit 201 may include a first sub-control unit 2011. The first sub-control unit 2011 is electrically connected to a first node No1 and a second node No2, and is configured to transmit the first sub-control signal SQ1 to the second node No2 during a second time period tB based on the signal from the first node No1, so that the signal from the second node No2 has a corresponding effective level.

[0029] By setting the first sub-control unit 2011 and transmitting the first sub-control signal SQ1 to the second node No2 during the second time period tB, the signal of the second node No2 is made to have an effective level, so that the level information of the signal of the first node No1 can be stored in the second node No2 through the action of the first sub-control signal SQ1 and the first sub-control unit 2011, thereby realizing the storage control of the level information of the signal of the first node No1.

[0030] In some embodiments, the first control signal Scs may include a second sub-control signal Sc, and the first control unit 201 may include a second sub-control unit 2012. The second sub-control unit 2012 is electrically connected to the second node No2 and the first power supply terminal, and the second sub-control unit 2012 is configured to disconnect the electrical connection between the first power supply terminal and the second node No2 at a second time period tB according to the second sub-control signal Sc.

[0031] Optionally, the first power supply terminal may be a constant power supply terminal. In some embodiments, the first power supply terminal may be a high-voltage terminal. In other embodiments, the first power supply terminal may be a low-voltage terminal.

[0032] To facilitate understanding of this application, the first power supply terminal is described as a low-voltage terminal. Here, the first power supply terminal is denoted as VGL, as... Figure 1 As shown.

[0033] In some embodiments, the first electrical signal supplied by the first power supply terminal VGL can be used to make the signal of the second node No2 have an invalid level. Accordingly, since the second node No2 stores the level information of the signal of the first node No1 in the second time period tB, the second node No2 has an valid level in the second time period tB. The second sub-control unit 2012 can reduce the influence of the first electrical signal on the signal of the second node No2 in the second time period tB, thereby improving the accuracy of the level information stored in the second node No2.

[0034] Optionally, the second sub-control unit 2012 is configured to connect the electrical connection between the first power supply terminal VGL and the second node No2 according to the effective level of the second sub-control signal Sc, and disconnect the electrical connection between the first power supply terminal VGL and the second node No2 during the second time period tB according to the ineffective level of the second sub-control signal Sc.

[0035] In some embodiments, the first control signal Scs may include a third sub-control signal SQ2, and the first control unit 201 may include a third sub-control unit 2013. The third sub-control unit 2013 is electrically connected to the first node No1 and the second node No2. The third sub-control unit 2013 is configured to transmit the third sub-control signal SQ2 to the first node No1 in the second time period tB and the third time period tC according to the signal of the second node No2, so as to maintain the potential of the first node No1 in the second time period tB and the third time period tC; and is configured to transmit the third sub-control signal SQ2 to the first node No1 in the fourth time period tD according to the signal of the second node No2, so that the signal of the first node No1 has a corresponding effective level in the fourth time period tD.

[0036] By setting the third sub-control unit 2013, the potential of the first node No1 is maintained by the third sub-control unit 2013 and the third sub-control signal SQ2, and the signal of the first node No1 is controlled to switch from an invalid level to an effective level in the fourth time period tD.

[0037] Please continue reading. Figure 1 The signal storage module 200 may include a second control unit 202. The second control unit 202 is electrically connected to the first node No1 and the first power supply terminal VGL. The second control unit 202 is configured to transmit the first electrical signal transmitted from the first power supply terminal VGL to the first node No1 during a third time period tC, according to a second control signal Res, so that the signal of the first node No1 has an invalid level during the third time period tC. By configuring the second control unit 202, the switching control of the signal of the first node No1 from an valid level to an invalid level can be realized.

[0038] Optionally, the second control unit 202 may also be electrically connected to the signal output terminal Sout of the shift register GA. The second control unit 202 is configured to transmit the first electrical signal to the signal output terminal Sout in the third time period tC according to the second control signal Res.

[0039] Please continue reading. Figure 1 The shift register GA also includes an inverting module 400 and a pull-down sustaining module 500.

[0040] The inverting module 400 is electrically connected to the first node No1, the third node No3, the first power supply terminal VGL, and the second power supply terminal. The inverting module 400 is configured to control the first power supply terminal VGL and the second power supply terminal to be electrically connected to the third node No3 in a time-division manner according to the signal of the first node No1.

[0041] The pull-down sustaining module 500 is electrically connected to the first node No1 and the third node No3, and is electrically connected to at least one of the first power supply terminal VGL and the signal output terminal Sout. The pull-down sustaining module 500 is configured to control the on / off of the electrical connection between at least one of the first node No1 and the signal output terminal Sout and the first power supply terminal VGL according to the signal of the third node No3.

[0042] Optionally, the second power supply terminal can be a constant voltage terminal, one of the first and second power supply terminals can be a low voltage terminal, and the other of the first and second power supply terminals can be a high voltage terminal. The constant voltage terminal supplies a DC voltage, and the high voltage terminal supplies a voltage greater than the low voltage terminal supplies.

[0043] To facilitate understanding of this application, the second power supply terminal is described as a high-voltage terminal. The second power supply terminal can be denoted as VGH, as follows: Figure 1 As shown.

[0044] Optionally, the inverting module 400 is configured to connect the electrical connection between the first power supply terminal VGL and the third node No3 based on the valid level of the signal of the first node No1, so that the signal of the third node No3 has an invalid level. The inverting module 400 is also configured to disconnect the electrical connection between the first power supply terminal VGL and the third node No3 when the signal of the first node No1 has an invalid level, so that the signal of the third node No3 has a valid level. The first pull-down sustaining module 500 is configured to disconnect the electrical connection between at least one of the first node No1 and the signal output terminal Sout and the first power supply terminal VGL based on the invalid level of the signal of the third node No3. The first pull-down sustaining module 500 is also configured to connect the electrical connection between at least one of the first node No1 and the signal output terminal Sout and the first power supply terminal VGL based on the valid level of the signal of the third node No3, so that the signal of the first node No1 has an invalid level.

[0045] Optionally, the first pull-down sustaining module 500 is configured to disconnect the electrical connection between the first node No1 and the first power supply terminal VGL based on the invalid level of the signal of the third node No3, so as to reduce the influence of the first electrical signal on the signal of the first node No1 during the period when the signal of the first node No1 has an effective level.

[0046] It should be noted that the shift register GA may include at least one inverting module 400 and at least one pull-down sustaining module 500. In some embodiments, the shift register GA may include two inverting modules 400 and two pull-down sustaining modules 500, with the two inverting modules 400 and the two pull-down sustaining modules 500 operating in a time-sharing manner to improve the problem that the output of the shift register GA is affected when one inverting module 400 and one pull-down sustaining module 500 are in a working state for a long time.

[0047] Optionally, the first control unit 201 may further include a fourth sub-control unit 2014, such as... Figure 1 As shown. The fourth sub-control unit 2014 is electrically connected to the second node No2, the third node No3 and the first power supply terminal VGL. The fourth sub-control unit 2014 is configured to control the on / off connection between the first power supply terminal VGL and the third node No3 according to the signal of the second node No2.

[0048] By setting the fourth sub-control unit 2014, the electrical connection between the first node No1 and the first power supply terminal VGL can be disconnected in the fourth time period tD, so as to reduce the leakage current from the first node No1 to the first power supply terminal VGL in the fourth time period tD.

[0049] Optionally, in order to ensure that the effective pulse of the gate control signal Scan can be output completely, the output module 300 of the shift register GA may further include a storage unit. The storage unit is electrically connected to the first node No1 and the signal output terminal Sout of the shift register GA. The storage unit is used to maintain the potential of the first node No1.

[0050] In some embodiments, the storage unit may include a capacitor Cbt, which is electrically connected between the first node No1 and the signal output terminal Sout.

[0051] Optionally, the shift register GA may also include a pull-down module 600, which is electrically connected to the first node No1 and the first power supply terminal VGL. The pull-down module 600 is configured to control the electrical connection between the first node No1 and the first power supply terminal VGL according to the pull-down control signal PD.

[0052] In some embodiments, the pull-down module 600 is configured to connect the electrical connection between the first node No1 and the first power supply terminal VGL according to the effective level of the pull-down control signal PD, and the pull-down module 600 is configured to control the electrical connection between the first node No1 and the first power supply terminal VGL according to the pull-down control signal PD.

[0053] The time periods during which the pull-up control signal STV has a valid pulse and the time periods during which the pull-down control signal PD has a valid pulse do not overlap, so that the signal of the first node No1 has a time-division valid level and an invalid level.

[0054] Optionally, the shift register GA may also include a stage transmission module, which is electrically connected to the first node No1 and the stage transmission output terminal of the shift register GA. The stage transmission module is configured to transmit the corresponding clock signal to the stage transmission output terminal according to the signal of the first node No1.

[0055] In some embodiments, the clock signal received by the cascading module is the same as the clock signal CK received by the output module 300, so as to reduce the number of signals used by the shift register GA and reduce the power consumption of the shift register GA.

[0056] Optionally, the operating state of the cascading module and the operating state of the output module 300 can be synchronized so that when the shift register GA is used to implement the design of the gate drive circuit, the cascading module can be used to realize the cascade design of the gate drive circuit, and the load corresponding to the signal output terminal Sout of the shift register GA can be reduced, thereby improving the quality of the gate control signal Scan output by the shift register GA.

[0057] In some embodiments, the pull-down sustaining module 500 may also be electrically connected to the stage output terminal, and the pull-down sustaining module 500 may also be configured to control the electrical connection between the first power supply terminal VGL and the stage output terminal according to the signal of the third node No3.

[0058] like Figure 2 This is a circuit diagram of a shift register according to an embodiment of this application. For ease of understanding the shift register GA of this application, [the diagram is shown]. Figure 2 The structure of the shift register GA shown is used as an example for explanation.

[0059] The pull-up module 100 includes a pull-up transistor Tu. The control terminal of the pull-up transistor Tu is configured to receive a pull-up control signal STV. The first source-drain terminal of the pull-up transistor Tu is configured to receive the pull-up control signal STV or be electrically connected to the second power supply terminal VGH. The second source-drain terminal of the pull-up transistor Tu is electrically connected to the first node No1.

[0060] In the output module 300, the control terminal of the output transistor To is electrically connected to the first node No1, the first source-drain terminal of the output transistor To is configured to receive the corresponding clock signal CK, and the second source-drain terminal of the output transistor To is electrically connected to the signal output terminal Sout.

[0061] The first sub-control unit 2011 of the signal storage module 200 may include a first transistor T1, the control terminal of the first transistor T1 is electrically connected to the first node No1, the first source-drain terminal of the first transistor T1 is configured to receive the first sub-control signal SQ1, and the second source-drain terminal of the first transistor T1 is electrically connected to the second node No2.

[0062] The second sub-control unit 2012 of the signal storage module 200 may include a second transistor T2. The control terminal of the second transistor T2 is configured to receive a second sub-control signal Sc. The first source-drain terminal of the second transistor T2 is electrically connected to the first power supply terminal VGL, and the second source-drain terminal of the second transistor T2 is electrically connected to the second node No2.

[0063] The third sub-control unit 2013 of the signal storage module 200 may include a third transistor T3. The control terminal of the third transistor T3 is electrically connected to the second node No2. The first source-drain terminal of the third transistor T3 is configured to receive the third sub-control signal SQ2. The second source-drain terminal of the third transistor T3 is electrically connected to the first node No1.

[0064] Optionally, the first control unit 201 of the signal storage module 200 may further include a fourth sub-control unit 2014. The fourth sub-control unit 2014 may include a fourth transistor T4. The control terminal of the fourth transistor T4 is electrically connected to the second node No2. The first source-drain terminal of the fourth transistor T4 is electrically connected to the first power supply terminal VGL. The second source-drain terminal of the fourth transistor T4 is electrically connected to the third node No3.

[0065] The second control unit 202 of the signal storage module 200 may include a first switching transistor TrQ. The control terminal of the first switching transistor TrQ is configured to receive a second control signal Res. The first source-drain terminal of the first switching transistor TrQ is electrically connected to the first power supply terminal VGL, and the second source-drain terminal of the first switching transistor TrQ is electrically connected to the first node No1.

[0066] Optionally, the second control unit 202 may further include a second switching transistor TrG, the control terminal of the second switching transistor TrG being configured to receive a second control signal Res, the first source-drain terminal of the second switching transistor TrG being electrically connected to the first power supply terminal VGL, and the second source-drain terminal of the second switching transistor TrG being electrically connected to the signal output terminal Sout.

[0067] The inverter module 400 may include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The control terminal and the first source-drain terminal of the fifth transistor T5 are electrically connected to the second power supply terminal VGH. The second source-drain terminal of the fifth transistor T5 is electrically connected to the control terminal of the sixth transistor T6. The first source-drain terminal of the sixth transistor T6 is electrically connected to the second power supply terminal VGH. The second source-drain terminal of the sixth transistor T6 is also electrically connected to the third node No3. The control terminals of the seventh transistor T7 and the eighth transistor T8 are electrically connected to the first node No1. The first source-drain terminals of the seventh transistor T7 and the eighth transistor T8 are electrically connected to the first power supply terminal VGL. The second source-drain terminal of the seventh transistor T7 is electrically connected to the control terminal of the sixth transistor T6. The second source-drain terminal of the eighth transistor T8 is also electrically connected to the third node No3.

[0068] Optionally, the first pull-down sustaining module 500 may include a ninth transistor T9, the control terminal of the ninth transistor T9 being electrically connected to the third node No3, the first source-drain terminal of the ninth transistor T9 being electrically connected to the first power supply terminal VGL, and the second source-drain terminal of the ninth transistor T9 being electrically connected to the first node No1.

[0069] Optionally, the first pull-down sustaining module 500 may include a tenth transistor T10, the control terminal of the tenth transistor T10 being electrically connected to the third node No3, the first source-drain terminal of the tenth transistor T10 being electrically connected to the first power supply terminal VGL, and the second source-drain terminal of the tenth transistor T10 being electrically connected to the signal output terminal Sout.

[0070] Optionally, the shift register GA may also include a cascade module, which includes a cascade transistor. The control terminal of the cascade transistor is electrically connected to the first node No.1. The first source-drain terminal of the cascade transistor is configured to receive the corresponding clock signal, and the second source-drain terminal of the cascade transistor is electrically connected to the cascade output terminal.

[0071] Optionally, the first pull-down sustaining module 500 may further include an eleventh transistor, the control terminal of the eleventh transistor being electrically connected to the third node No3, the first source-drain terminal of the eleventh transistor being electrically connected to the first power supply terminal VGL, and the second source-drain terminal of the eleventh transistor being electrically connected to the stage output terminal.

[0072] It should be noted that when the shift register GA includes two inverting modules 400 and two pull-down sustaining modules 500, the two inverting modules 400 may each include a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8, and the two first pull-down sustaining modules 500 may each include at least one of a ninth transistor T9, a tenth transistor T10, and an eleventh transistor. The shift register GA may include two third nodes No3, with each of the two inverting modules 400 connected to one third node No3 and each of the two first pull-down sustaining modules 500 connected to one third node No3.

[0073] Please continue reading. Figure 2 The pull-down module 600 of the shift register GA may include a pull-down transistor Td. The control terminal of the pull-down transistor Td is configured to receive a pull-down control signal PD. The first source-drain terminal of the pull-down transistor Td is electrically connected to the first power supply terminal VGL, and the second source-drain terminal of the pull-down transistor Td is electrically connected to the first node No1.

[0074] It is understandable that at least one of the following transistors can be an N-type transistor or a P-type transistor: the first transistor T1 to the eleventh transistor, the pull-up transistor Tu, the pull-down transistor Td, the output transistor To, the stage transistor, the first switching transistor TrQ, and the second switching transistor TrG.

[0075] It should be noted that the control terminal of a transistor can be the gate of the transistor, the first source-drain terminal of the transistor can be one of the source and drain terminals of the transistor, and the second source-drain terminal of the transistor can be the other of the source and drain terminals of the transistor.

[0076] It should be understood that, Figure 2 This example only illustrates the design using a combination of transistors and capacitors. However, in some embodiments, the modules can be implemented with more complex connections or a greater number or type of components. These components can be at least one of transistors and capacitors.

[0077] like Figure 3 This is a timing diagram corresponding to the shift register provided in an embodiment of the present invention. Wherein, Figure 3 In this context, Nos1 represents the signal of the first node No1, abbreviated as First Node Signal Nos1. Nos2 represents the signal of the second node No2, abbreviated as Second Node Signal Nos2. Taking the shift register GA as an example where all transistors are N-type transistors, the first power supply terminal VGL corresponds to the low-voltage terminal, and the second power supply terminal VGH corresponds to the high-voltage terminal, combined with... Figure 2 The circuit topology of the shift register GA shown is used to explain the working principle of the shift register GA of the present invention.

[0078] In the first time period tA: the second sub-control signal Sc and the pull-up control signal STV are high, while the second control signal Res, the first sub-control signal SQ1, the third sub-control signal SQ2, the clock signal CK, and the pull-down control signal PD are low. Pull-up transistor Tu, output transistor To, first transistor T1, second transistor T2, seventh transistor T7, and eighth transistor T8 are turned on. First switching transistor TrQ, second switching transistor TrG, pull-down transistor Td, ninth transistor T9, tenth transistor T10, third transistor T3, and fourth transistor T4 are turned off. The pull-up control signal STV is transmitted to the first node No1, and the first node signal Nos1 is high. The first power supply terminal VGL is electrically connected to the second node No2 and the third node No3, and the first sub-control signal SQ1 is transmitted to the second node No2. The gate control signal Scan output by the shift register GA is low.

[0079] In the second time period tB: the pull-down control signal PD, pull-up control signal STV, second sub-control signal Sc, second control signal Res, and clock signal CK are at low levels, while the first sub-control signal SQ1 and the third sub-control signal SQ2 are at high levels. The second transistor T2, the first switching transistor TrQ, and the second switching transistor TrG are off. Because the first node signal Nos1 is at a high level, the first transistor T1 is turned on, and the first sub-control signal SQ1 is transmitted to the second node No2 to charge it. The potential of the second node No2 rises to a high level, causing the third transistor T3 and the fourth transistor T4 to turn on. The third sub-control signal SQ2 is transmitted to the first node No1 to maintain the first node signal Nos1 at a high level. The gate control signal Scan is at a low level.

[0080] In the third time period tC: the pull-down control signal PD, pull-up control signal STV, clock signal CK, second sub-control signal Sc, and third sub-control signal SQ2 are all low. The first sub-control signal SQ1 transitions from high to low. The second control signal Res transitions from high to low. The first switching transistor TrQ and the second switching transistor TrG are turned on, making the first node signal Nos1 low. The first transistor T1 and the second transistor T2 are turned off. Because the second node signal Nos2 is high, the third transistor T3 is turned on, causing the third sub-control signal SQ2 to transmit the first node No1 to maintain the first node signal Nos1 at a low level. The gate control signal Scan is low.

[0081] In the fourth time period tD: the pull-down control signal PD, pull-up control signal STV, clock signal CK, second sub-control signal Sc, and second control signal Res are at low levels, while the first sub-control signal SQ1 and third sub-control signal SQ2 are at high levels. The second transistor T2, the first switching transistor TrQ, and the second switching transistor TrG are off. Because the second node signal Nos2 is at a high level, the third transistor T3 and the fourth transistor T4 remain on. The third sub-control signal SQ2 is transmitted to the first node No1 to charge it. The potential of the first node No1 rises to a high level, causing the first transistor T1, the output transistor To, the seventh transistor T7, and the eighth transistor T8 to conduct. The first power supply terminal VGL is electrically connected to the third node No3, causing the ninth transistor T9 and the tenth transistor T10 to be off, thereby reducing leakage current between the first node No1 and the first power supply terminal VGL during charging. The first sub-control signal SQ1 is transmitted to the first node No1 to maintain the potential of the second node No2 at a high level. The gate control signal Scan is at a low level.

[0082] In the fifth time period tE: the pull-down control signal PD, pull-up control signal STV, clock signal CK, first sub-control signal SQ1, and second control signal Res are low; the second sub-control signal Sc and third sub-control signal SQ2 are high. The second transistor T2 is turned on, and the first power supply terminal VGL is electrically connected to the second node No2 to maintain the second node signal Nos2 at a low level. The third transistor T3 and the fourth transistor T4 are turned off. The gate control signal Scan is low.

[0083] In the sixth time period tF: the clock signal CK and the second sub-control signal Sc are at high level, the pull-down control signal PD, the pull-up control signal STV, the second control signal Res, the first sub-control signal SQ1, and the third sub-control signal SQ2 are at low level, the clock signal CK is transmitted to the signal output terminal Sout, and the gate control signal Scan is at high level.

[0084] In the seventh time period tG: the pull-down control signal PD and the second sub-control signal Sc are high, while the pull-up control signal STV, the clock signal CK, the second control signal Res, the first sub-control signal SQ1, and the third sub-control signal SQ2 are low. Pull-down transistor Td, ninth transistor T9, tenth transistor T10, and second transistor T2 are turned on; first switching transistor TrQ, second switching transistor TrG, pull-up transistor Tu, output transistor To, seventh transistor T7, eighth transistor T8, first transistor T1, third transistor T3, and fourth transistor T4 are turned off; and the gate control signal Scan is low.

[0085] It should be understood that this application only uses the example of a shift register GA output driving the gate control signal Scan of an N-type transistor. However, those skilled in the art can adjust the type of transistors included in the shift register GA, the settings of the first power supply terminal and the second power supply terminal according to actual needs, so that the shift register GA output drives the gate control signal Scan of a P-type transistor, which is also permitted and included in this application.

[0086] like Figure 4 This is a schematic diagram of the gate drive circuit in an embodiment of this application. This application also provides a gate drive circuit GDC, which includes any of the above-mentioned shift registers GA. Multiple shift registers GA are cascaded so that multiple gate control signals Scan output by the gate drive circuit GDC have valid pulses in sequence.

[0087] Optionally, the pull-up control signal STV corresponding to the first m shift registers GA in the plurality of shift registers GA is the start signal, and the pull-up control signal STV corresponding to the nth shift register GA in the plurality of shift registers GA is the gate control signal Scan(nm) output by the nm-th stage shift register GA(nm). Wherein, 1≤m <n,n-m≥1。

[0088] In some embodiments, the first-stage shift registers GA(1) to the fourth-stage shift registers GA(4) of the multiple shift registers GA receive corresponding start signals as pull-up control signals STV. The pull-up control signal STV corresponding to the nth shift register GA(n) of the multiple shift registers GA is the gate control signal Scan(n-4) output by the (n-4)th stage shift register GA(n-4). Among them, the first-stage shift registers GA(1) to the fourth-stage shift registers GA(4) may share the same start signal or may not share the same start signal. Instead, four start signals are set for the first-stage shift registers GA(1) to the fourth-stage shift registers GA(4).

[0089] In some embodiments, the pull-up control signal STV corresponding to the first-stage shift register GA(1) in the plurality of shift registers GA is the start signal, and the pull-up control signal STV corresponding to the nth shift register GA(n) in the plurality of shift registers GA is the gate control signal Scan(n-1) output by the (n-1)th-stage shift register GA(n-1).

[0090] Optionally, the pull-down control signal PD corresponding to the q-th shift register GA(q) among the multiple shift registers GA is the gate control signal Scan(q+p) output by the (q+p)-th shift register GA(q+p). Where p≥1, q≥1.

[0091] In some embodiments, the pull-down control signal PD corresponding to the q-th shift register GA(q) is the gate control signal Scan(q+4) output by the (q+4)-th shift register GA(q+4). In other embodiments, the pull-down control signal PD corresponding to the q-th shift register GA(q) is the gate control signal Scan(q+1) output by the (q+1)-th shift register GA(q+1).

[0092] Optionally, multiple shift registers GA can multiplex multiple clock signals CK to save the number of clock signals CK used by the gate drive circuit GDC and reduce the power consumption of the gate drive circuit GDC.

[0093] In some embodiments, the gate drive circuit GDC includes Z clock lines CL, which are electrically connected to multiple shift registers GA to provide corresponding clock signals CK to the multiple shift registers GA. Where Z ≥ 2. The Z clock signals CK transmitted by the Z clock lines CL have the same frequency, and the Z clock signals CK have the same phase difference sequentially among themselves.

[0094] Optionally, the ZK+M-th stage shift register GA (ZK+M) is electrically connected to the M-th clock line of the Z clock lines CL, so as to enable the multi-stage shift register GA to multiplex the clock signal CK transmitted by the multiple clock lines CL. K≥0, and K is a positive integer; 1≤M≤Z.

[0095] Please continue reading. Figure 4 Taking Z=8 as an example, the 8 clock lines CL include the first clock line CL1, the second clock line CL2, the third clock line CL3, the fourth clock line CL4, the fifth clock line CL5, the sixth clock line CL6, the seventh clock line CL7, and the eighth clock line CL8. Specifically, the 8K+1 stage shift register GA (8K+1) is electrically connected to the first clock line CL1; the 8K+2 stage shift register GA (8K+2) is electrically connected to the second clock line CL2; the 8K+3 stage shift register GA (8K+3) is electrically connected to the third clock line CL3; the 8K+4 stage shift register GA (8K+4) is electrically connected to the fourth clock line CL4; the 8K+5 stage shift register GA (8K+5) is electrically connected to the fifth clock line CL5; the 8K+6 stage shift register GA (8K+6) is electrically connected to the sixth clock line CL6; the 8K+7 stage shift register GA (8K+7) is electrically connected to the seventh clock line CL7; and the 8K+8 stage shift register GA (8K+8) is electrically connected to the eighth clock line CL8.

[0096] It should be understood that, Figure 4The structure of the gate drive circuit GDC is illustrated only with Z=8, m=4 and p=4 as examples. Those skilled in the art are permitted to adjust the values ​​of Z, m and p according to actual needs and this application includes such adjustments.

[0097] Optionally, the multi-stage shift registers (GAs) can share the first control signal Scs and the second control signal Res to reduce the number of control signals applied to multiple shift registers (GAs) and reduce the cost and power consumption of the gate drive circuit (GDC).

[0098] Please continue reading. Figure 4 The first control signal Scs includes a first sub-control signal SQ1, a second sub-control signal Sc, and a third sub-control signal SQ2. The signal storage module 200 of at least one shift register GA is configured to transmit the first sub-control signal SQ1 to the second node No2 in a second time period tB according to the signal of the first node No1, disconnect the electrical connection between the first power supply terminal VGL and the second node No2 in the second time period tB according to the second sub-control signal Sc, and transmit the third sub-control signal SQ2 to the first node No1 in the second time period tB, the third time period tC, and the fourth time period tD according to the signal of the second node No2.

[0099] The gate drive circuit GDC also includes a first control line Sl1, a second control line Sl2, a third control line Sl3, and a fourth control line Sl4 electrically connected to multiple shift registers GA. Specifically, the first control line Sl1 is configured to transmit a first sub-control signal SQ1 to the multiple shift registers GA; the second control line Sl2 is configured to transmit a second sub-control signal Sc to the multiple shift registers GA; the third control line Sl3 is configured to transmit a third sub-control signal SQ2 to the multiple shift registers GA; and the fourth control line Sl4 is configured to transmit a second control signal Res to the multiple shift registers GA, so that the multiple shift registers GA can share the first control signal Scs and the second control signal Res.

[0100] In some embodiments, the clock signals CK transmitted through multiple clock lines CL can be made to have invalid levels corresponding to the second time period tB, the third time period tC, and the fourth time period tD. This allows for level control of the signal at the first node No1 in the shift register GA, while ensuring that the gate control signals Scan output by the multiple shift registers GA included in the gate drive circuit GDC have no valid pulses corresponding to the second time period tB and the fourth time period tD. Furthermore, having the clock signals CK transmitted through multiple clock lines CL have invalid levels corresponding to the second time period tB, the third time period tC, and the fourth time period tD can also reduce the power consumption of the gate drive circuit GDC.

[0101] like Figure 5This is a timing diagram of the signals corresponding to the gate drive circuit in an embodiment of this application. Taking the (n-4)th stage shift register GA(n-4) to the (n+4)th stage shift register GA(n+4) as an example, combined with the following... Figure 2 The circuit topology of the shift register GA is shown, and the transistors included in the shift register GA are all N-type transistors. The working principle of the gate control signal Scan output by the multiple shift registers GA included in the gate drive circuit GDC, where there are no valid pulses in the second time period tB and the fourth time period tD, is explained. Where Z = 8, m = 4, p = 4, the clock signal CK corresponding to the (n-4)th stage shift register GA(n-4) and the (n+4)th stage shift register GA(n+4) is the first clock signal CK1 transmitted by the first clock line CL1, the clock signal CK corresponding to the (n-3)th stage shift register GA(n-3) is the second clock signal CK2 transmitted by the second clock line CL2, the clock signal CK corresponding to the (n-2)th stage shift register GA(n-2) is the third clock signal CK3 transmitted by the third clock line CL3, and the clock signal CK corresponding to the (n-1)th stage shift register GA(n-1) is the fourth clock signal CK3 transmitted by the fourth clock line CL2. The fourth clock signal CK4 is transmitted by clock line CL4. The clock signal CK corresponding to the nth stage shift register GA(n) is the fifth clock signal CK5 transmitted by the fifth clock line CL5. The clock signal CK corresponding to the (n+1)th stage shift register GA(n+1) is the sixth clock signal CK6 transmitted by the sixth clock line CL6. The clock signal CK corresponding to the (n+2)th stage shift register GA(n+2) is the seventh clock signal CK7 transmitted by the seventh clock line CL7. The clock signal CK corresponding to the (n+3)th stage shift register GA(n+3) is the eighth clock signal CK8 transmitted by the eighth clock line CL8.

[0102] In the first stage t1: the second sub-control signal Sc and the gate control signal Scan(n-5) output from the (n-5)th stage shift register GA(n-5) are high; the sixth clock signal CK6 to the eighth clock signal CK8 are high; the first clock signal CK1 to the fifth clock signal CK5 are low; and the first sub-control signal SQ1, the third sub-control signal SQ2, and the second control signal Res are low. In the (n-1)th stage shift register GA(n-1), the first node signal Nos1(n-1) is high, the second node signal Nos2(n-1) is low, and the pull-up transistor Tu, the output transistor To, the seventh transistor T7, the eighth transistor T8, the first transistor T1, and the second transistor T2 are turned on. The first switching transistor TrQ, the second switching transistor TrG, the pull-down transistor Td, the ninth transistor T9, the tenth transistor T10, the third transistor T3, and the fourth transistor T4 are turned off. The (n-1)th stage gate control signal Scan(n-1) output by the (n-1)th stage shift register GA(n-1) is low.

[0103] In the second stage t2: the gate control signal Scan(n-5), the first clock signal CK1, and the fifth to eighth clock signals CK5 and CK8 of the (n-5)th stage are low; the second to fourth clock signals CK4 are high; the second sub-control signal Sc is high; and the first sub-control signal SQ1, the third sub-control signal SQ2, and the second control signal Res are low. In the (n-1)th stage shift register GA(n-1), the first node signal Nos1(n-1) is high, and the second node signal Nos2(n-1) is low; the output transistors To, T7, T8, T1, and T2 are turned on. The first switching transistor TrQ, the second switching transistor TrG, the pull-up transistor Tu, the pull-down transistor Td, T9, T10, T3, and T4 are turned off. The gate control signal Scan(n-1) of the (n-1)th stage is high.

[0104] In the third stage t3: the third clock signal CK3 to the fourth clock signal CK4 are high, the first clock signal CK1, the second clock signal CK2, the fifth clock signal CK5 to the eighth clock signal CK8 are low, the second sub-control signal Sc is high, and the first sub-control signal SQ1, the third sub-control signal SQ2, and the second control signal Res are low. In the (n-1)th stage shift register GA(n-1), the first node signal Nos1(n-1) is high, and the second node signal Nos2(n-1) is low; the output transistors To, T7, T8, T1, and T2 are turned on. The first switching transistor TrQ, the second switching transistor TrG, the pull-up transistor Tu, the pull-down transistor Td, T9, T10, T3, and T4 are turned off. The (n-1)th stage gate control signal Scan(n-1) is high.

[0105] In stage t4: the fourth clock signal CK4 is high, the first clock signals CK1 to CK3, the fifth clock signals CK5 to CK8 are low, the second sub-control signal Sc is high, and the first sub-control signal SQ1, the third sub-control signal SQ2, and the second control signal Res are low. In the (n-1)th stage shift register GA(n-1), the first node signal Nos1(n-1) is high, and the second node signal Nos2(n-1) is low; output transistors To, T7, T8, T1, and T2 are turned on. The first switching transistor TrQ, the second switching transistor TrG, the pull-up transistor Tu, the pull-down transistor Td, T9, T10, T3, and T4 are turned off. The (n-1)th stage gate control signal Scan(n-1) is high.

[0106] Phase 5 (t5): The first clock signal CK1 to the eighth clock signal CK8 are low; the second sub-control signal Sc is high; and the first sub-control signal SQ1, the third sub-control signal SQ2, and the second control signal Res are low. In the (n-1)th stage shift register GA(n-1), the first node signal Nos1(n-1) is high, and the second node signal Nos2(n-1) is low; output transistors To, T7, T8, T1, and T2 are turned on. The first switching transistor TrQ, the second switching transistor TrG, the pull-up transistor Tu, the pull-down transistor Td, T9, T10, T3, and T4 are turned off. The (n-1)th stage gate control signal Scan(n-1) is low.

[0107] In stage 6 (t6), the first clock signal CK1 to the eighth clock signal CK8, the second sub-control signal Sc, the first sub-control signal SQ1, the third sub-control signal SQ2, and the second control signal Res are all low. The second transistor T2 of the multiple shift registers GA included in the gate drive circuit GDC is turned off. The signals of the first node No1 and the second node No2 in each stage of the shift register GA maintain the state of stage 5 (t5), causing the gate control signal Scan output by each stage of the shift register GA to also maintain the state of stage 5 (t5).

[0108] In stage 7 (t7), the first clock signal CK1 to the eighth clock signal CK8, the second sub-control signal Sc, and the second control signal Res are at low levels, while the first sub-control signal SQ1 and the third sub-control signal SQ2 are at high levels. The second transistor T2, the first switching transistor TrQ, and the second switching transistor TrG of the multiple shift registers GA included in the gate drive circuit GDC are turned off. Because the first node signal Nos1(n-4) of the G(n-4) stage shift register GA(n-4) to the first node signal Nos1(n+3) of the G(n+3) stage shift register GA(n+3) are at high levels, the first transistor T1 in the G(n-4) stage shift register GA(n-4) to the G(n+3) stage shift register GA(n+3) is turned on. The first sub-control signal SQ1 is transmitted to the second node No2, causing the third transistor T3 and the fourth transistor T4 to turn on. Because the first node signal Nos1 is low in the other shift registers GA, the first transistor T1 in the other shift registers GA is turned off.

[0109] Stage 8 (t8): The first clock signal CK1 to the eighth clock signal CK8 are low, the second sub-control signal Sc and the third sub-control signal SQ2 are low, and the first sub-control signal SQ1 and the second control signal Res are high. The first switching transistor TrQ and the second switching transistor TrG of the multiple shift registers GA included in the gate drive circuit GDC are turned on, causing the first node signal Nos1 of the multiple shift registers GA included in the gate drive circuit GDC to be low. The first transistor T1 and the second transistor T2 of the multiple shift registers GA included in the gate drive circuit GDC are turned off. Because the second node signal Nos2(n-4) of the G(n-4) stage shift register GA(n-4) to the G(n+3) stage shift register GA(n-3) are low... When the second node signal Nos2(n+3) of (n+3) is high, the third transistor T3 of the shift registers GA(n-4) to GA(n+3) of the G(n-4) stage is turned on, so that the third sub-control signal SQ2 is transmitted to the first node No1 of the shift registers GA(n-4) to GA(n+3) of the G(n-4) stage and the gate control signal Scan output by the multiple shift registers GA included in the gate drive circuit GDC is also low.

[0110] In stage 9 (t9): the first clock signal CK1 to the eighth clock signal CK8, the second sub-control signal Sc, the first sub-control signal SQ1, and the third sub-control signal SQ2 are low, the second control signal Res is high, and the first switching transistor TrQ and the second switching transistor TrG of the multiple shift registers GA included in the gate drive circuit GDC are turned on, making the first node signal Nos1 of the multiple shift registers GA included in the gate drive circuit GDC low, and the gate control signal Scan output by the multiple shift registers GA included in the gate drive circuit GDC is also low. The second node signal Nos2(n-4) of the G(n-4) stage shift register GA(n-4) to the second node signal Nos2(n+3) of the G(n+3) stage shift register GA(n+3) are high.

[0111] Stage 10 (t10): The first clock signal CK1 to the eighth clock signal CK8, the second sub-control signal Sc, the first sub-control signal SQ1, the third sub-control signal SQ2, and the second control signal Res are all low. The signals of the first node No1 and the second node No2 in each stage of the shift register GA maintain the state of stage 9 (t9), making the gate control signal Scan output by each stage of the shift register GA low.

[0112] Stage 11 (t11): The first clock signal CK1 to the eighth clock signal CK8 are at low level, the second sub-control signal Sc and the second control signal Res are at low level, and the first sub-control signal SQ1 and the third sub-control signal SQ2 are at high level. The second transistor T2, the first switching transistor TrQ, and the second switching transistor TrG of the multiple shift registers GA included in the gate drive circuit GDC are turned off. Since the second node signal Nos2(n-4) of the G(n-4) stage shift register GA(n-4) to the second node signal Nos2(n+3) of the G(n+3) stage shift register GA(n+3) are at a high level, the third transistor T3 and the fourth transistor T4 of the G(n-4) stage shift register GA(n-4) to the G(n+3) stage shift register GA(n+3) remain on. The third sub-control signal SQ2 is transmitted to the first node No1, which turns on the first transistor T1, the output transistor To, the eighth transistor T8, and the seventh transistor T7, while the ninth transistor T9 and the tenth transistor T10 are turned off.

[0113] Stage 12 (t12): The first clock signal CK1 to the eighth clock signal CK8 are low; the first sub-control signal SQ1 and the second control signal Res are low; and the second sub-control signal Sc and the third sub-control signal SQ2 are high. The second transistor T2 of the multiple shift registers GA included in the gate drive circuit GDC is turned on, QS of the multiple shift registers GA included in the gate drive circuit GDC is low, and the third transistor T3 and the fourth transistor T4 are turned off.

[0114] In the thirteenth stage t13: the fifth clock signal CK5 is high, the nth level scan signal Scan(N) output by the G(n) level shift register is high, and the first node signal Nos1(n-4) of the G(n-4) level shift register is low.

[0115] Stage 14 t14: The gate control signal Scan(n+4) of the N+4th stage is high, and the first node signal Nos1(n) of the shift register of the G(n)th stage is low.

[0116] Reference Figure 4 and Figure 5 As can be seen from the principle analysis, each shift register GA has its own corresponding first time period tA, such as Figure 5 The first time period tA shown is the first time period corresponding to the (n-1)th stage shift register GA(n-1), and the first time period tA corresponds to the time periods corresponding to the second stage t2 to the fourth stage t4.

[0117] Each shift register corresponds to the same second time period tB, third time period tC, and fourth time period tD. For example... Figure 5 As shown, the second time period tB corresponds to the time period corresponding to the seventh stage t7, the third time period tC corresponds to the time period corresponding to the eighth stage t8 to the tenth stage t10, and the fourth time period tD corresponds to the time period corresponding to the eleventh stage t11. Corresponding to the second time period tB to the fourth time period tD, the gate control signals Scan output by the multiple shift registers GA included in the gate drive circuit GDC have no valid pulses.

[0118] Understandably, the working principle of the shift registers (GA) in the remaining stages of the gate drive circuit (GDC) can be found in [reference needed]. Figure 5 The relevant explanations shown are provided and will not be repeated here.

[0119] like Figure 6 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. This application also provides a display panel, which includes any of the aforementioned gate drive circuits (GDC).

[0120] Optionally, the display panel can be a passive light-emitting display panel or a self-emissive display panel. Passive light-emitting display panels include liquid crystal display panels, while self-emissive display panels include display panels that use light-emitting devices as sub-pixels. The light-emitting devices can include at least one of organic light-emitting diodes (OLEDs), sub-millimeter light-emitting diodes (PMLEDs), and micro LEDs.

[0121] Please continue reading. Figure 6 The display panel includes multiple sub-pixels SPX, which are electrically connected to a gate drive circuit GDC. The gate drive circuit GDC is configured to transmit gate control signals Scan to the multiple sub-pixels SPX, and the multiple sub-pixels SPX are configured to receive multiple gate control signals Scan output by the gate drive circuit GDC, so as to realize the display function of the display panel according to the received gate control signals Scan and data signals.

[0122] The display panel may also include source drivers and timing controllers (not shown). The timing controller is electrically connected to the gate drive circuit GDC and the source drivers. The timing controller can provide the required clock signal CK to the gate drive circuit GDC. The source drivers can generate data signals based on the control signals output by the timing controller, and output them to multiple sub-pixels SPX, thereby controlling the display content of the multiple sub-pixels SPX.

[0123] Optionally, the multiple shift registers GA of the gate drive circuit GDC are electrically connected to multiple clock lines CL, which are configured to transmit corresponding clock signals CK to the multiple shift registers GA. Specifically, the clock signals CK transmitted by the multiple clock lines CL have an invalid level corresponding to the second time period tB, the third time period tC, and the fourth time period tD. This ensures that, while controlling the level of the signal at the first node No1 in the shift register GA, the gate control signals Scan output by the multiple shift registers GA included in the gate drive circuit GDC have no valid pulses corresponding to the second time period tB to the fourth time period tD. Furthermore, the fact that the clock signals CK transmitted by the multiple clock lines CL have invalid levels corresponding to the second time period tB, the third time period tC, and the fourth time period tD can also reduce the power consumption of the display panel.

[0124] Optionally, the display panel may include a display period t_ds and a touch period t_tc in a display cycle, such as Figure 5 As shown, a touch period t_tc is inserted into the display period t_ds, so that the display panel can perform both display and touch functions.

[0125] During the touch period t_tc, to reduce the impact of the gate control signal Scan on the touch function, the gate control signal Scan output by the gate drive circuit GDC, which supports the display function, cannot have valid pulses. Furthermore, to ensure that the display period t_ds continues after the touch phase ends, the valid pulses of the multiple gate drive signals output by the gate drive circuit GDC need to be consecutively set before and after the touch period t_tc. Therefore, the display period t_ds can include a first period tA, the touch period t_tc and the third period tC at least partially overlapping, a second period tB located before the touch period t_tc and between the touch period t_tc and the display period t_ds, and a fourth period tD located after the touch period t_tc and between the touch period t_tc and the display period t_ds. During the display period t_ds, the potential of the first node No1 of the shift register GA in the gate drive circuit GDC controls the corresponding output transistor To to turn on, so that the gate control signal Scan output by the gate drive circuit GDC sequentially has valid pulses, thereby realizing the display function of the display panel. During the touch period t_tc, the potential of the first node No1 of all shift registers GA in the gate drive circuit GDC can be used to control the corresponding output transistor To to be turned off, so that the multiple gate control signals Scan output by the gate drive circuit GDC are all kept at an invalid level, thereby reducing the impact of the gate control signal Scan on the touch function.

[0126] In some embodiments, the shift register GA in the gate drive circuit GDC used in the display panel does not include the signal storage module 200. When the shift register GA does not include the signal storage module 200, during the touch period t_tc, the signal of the first node No1 of a portion of the shift register GA in the gate drive circuit GDC remains at an active level, such as... Figure 7As shown by the first node signal Nos1, the corresponding output transistor To remains continuously on, allowing the gate drive circuit GDC to continue its cascading function after the touch period t_tc ends. This enables the display panel to control the continuity of its display content before and after the touch period t_tc based on the multiple gate control signals Scan output by the gate drive circuit GDC. However, during the touch period t_tc, the output transistors To in some shift registers GA of the gate drive circuit GDC remain on, while the output transistors To in other shift registers GA remain off. Therefore, the output transistor To, which is turned on during the touch period t_tc, will be continuously affected by bias stress, resulting in a threshold voltage drift. This causes a threshold voltage bias difference between the output transistor To, which is turned on during the touch period t_tc, and the output transistor To, which is turned off during the touch period t_tc. Consequently, the gate control signal Scan output by the shift register GA, which keeps the output transistor To on during the touch period t_tc, will be different from the gate control signal Scan output by the shift register GA, which keeps the output transistor To off during the touch period t_tc, thus causing display differences (such as horizontal lines).

[0127] In this application, by setting a signal storage module 200 in the shift register GA, the signal level of the first node No1 in the shift register GA can switch between an active level and an inactive level under the control of the first control signal Scs and the second control signal Res. This allows the signal of the first node No1 in the shift register GA to have an inactive level during the touch period t_tc. Figure 5 As shown, the output transistor To of the shift register GA is then controlled to be turned off during the touch period t_tc, which helps to improve the display difference caused by the continuous conduction of the output transistor To of part of the shift register GA during the touch period t_tc.

[0128] Furthermore, in this application, by making the multiple shift registers GA in the gate drive circuit GDC share the first control signal Scs and the second control signal Res, and by making the multiple clock signals CK shared by the multiple shift registers GA included in the gate drive circuit GDC have invalid levels in the second time period tB, the third time period tC, and the fourth time period tD, the multiple gate control signals Scan output by the gate drive circuit GDC can be made to have no valid level in the touch period t_tc. This simplifies the control logic of the multiple shift registers GA, reduces the power consumption of the display panel, and can improve the display difference (such as horizontal lines) problem that exists when the display function and touch function of the display panel coexist.

[0129] It should be noted that when the multiple shift registers GA included in the gate drive circuit GDC have invalid levels in the corresponding second time period tB, third time period tC and fourth time period tD, the second time period tB can be called the sinking stage, the touch period t_tc can be called the sinking stage, and the fourth time period tD can be called the sinking stage.

[0130] This application also provides a display device, which includes any of the above-mentioned gate drive circuits GA, shift registers GDC, or display panels.

[0131] Display devices can be mobile phones, computers, virtual reality displays, augmented reality displays, and other similar devices. They can be used in fields such as education, entertainment, transportation, healthcare, and defense to achieve display functions.

[0132] The above description is merely an optional embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A shift register, characterized in that, include: The pull-up module, electrically connected to the first node, is configured to control the signal of the first node to have a corresponding effective level in a first time period according to the pull-up control signal; The signal storage module, electrically connected to the first node and the second node, is configured to store the level information of the first node's signal to the second node in a second period after the first period based on the signal of the first node and a first control signal, control the first node's signal to have a corresponding invalid level in a third period after the second period based on a second control signal, and control the first node's signal to have a corresponding valid level in a fourth period after the third period based on the first control signal and the signal of the second node. as well as An output module, electrically connected to the first node, includes an output transistor configured to transmit a clock signal to the signal output terminal of the shift register according to the effective level corresponding to the signal of the first node.

2. The shift register according to claim 1, characterized in that, The signal storage module includes: A first control unit, electrically connected to the first node and the second node, is configured to store the signal level information of the first node in the second time period to the second node according to the signal of the first node and the first control signal, and to control the signal of the first node to have a corresponding effective level in the fourth time period according to the first control signal; and The second control unit, electrically connected to the first node and the first power supply terminal, is configured to transmit the first electrical signal transmitted from the first power supply terminal to the first node during the third time period according to the second control signal, so that the signal of the first node has an invalid level during the third time period.

3. The shift register according to claim 2, characterized in that, The first control signal includes a first sub-control signal, a second sub-control signal, and a third sub-control signal; the first control unit includes: The first sub-control unit, electrically connected to the first node and the second node, is configured to transmit the first sub-control signal to the second node during the second time period based on the signal of the first node, so that the signal of the second node has a corresponding effective level; The second sub-control unit, electrically connected to the second node and the first power supply terminal, is configured to disconnect the electrical connection between the first power supply terminal and the second node during the second time period according to the second sub-control signal. A third sub-control unit, electrically connected to the first node and the second node, is configured to transmit the third sub-control signal to the first node during the second and third time periods based on the signal from the second node, so as to maintain the potential of the first node during the second and third time periods; and is configured to transmit the third sub-control signal to the first node during the fourth time period based on the signal from the second node, so that the signal of the first node has a corresponding effective level during the fourth time period.

4. The shift register according to claim 3, characterized in that, The first sub-control unit includes a first transistor, the control terminal of the first transistor is electrically connected to the first node, the first source-drain terminal of the first transistor is configured to receive the first sub-control signal, and the second source-drain terminal of the first transistor is electrically connected to the second node. The second sub-control unit includes a second transistor, the control terminal of the second transistor is configured to receive the second sub-control signal, the first source-drain terminal of the second transistor is electrically connected to the first power supply terminal, and the second source-drain terminal of the second transistor is electrically connected to the second node; The third sub-control unit includes a third transistor, the control terminal of which is electrically connected to the second node, the first source-drain terminal of which is configured to receive the third sub-control signal, and the second source-drain terminal of which is electrically connected to the first node.

5. The shift register according to claim 3, characterized in that, The second control unit includes: A first switching transistor, wherein the control terminal of the first switching transistor is configured to receive the second control signal, the first source-drain terminal of the first switching transistor is electrically connected to the first power supply terminal, and the second source-drain terminal of the first switching transistor is electrically connected to the first node.

6. The shift register according to claim 2, characterized in that, The second control unit is electrically connected to the signal output terminal, and the second control unit is configured to transmit the first electrical signal to the signal output terminal during the third time period according to the second control signal.

7. The shift register according to claim 6, characterized in that, The second control unit includes: The second switching transistor has a control terminal configured to receive the second control signal, a first source-drain terminal electrically connected to the first power supply terminal, and a second source-drain terminal electrically connected to the signal output terminal.

8. The shift register according to any one of claims 2 to 7, characterized in that, Also includes: An inverting module is electrically connected to the first node, the third node, the first power supply terminal, and the second power supply terminal, and is configured to control the first power supply terminal and the second power supply terminal to be electrically connected to the third node in a time-division manner according to the signal of the first node. as well as The pull-down sustaining module is electrically connected to the first node, the third node, the first power supply terminal, and the signal output terminal, and is configured to control the on / off connection between the first power supply terminal and the first node and the signal output terminal based on the signal from the third node.

9. The shift register according to claim 8, characterized in that, The first control unit also includes: The fourth sub-control unit, electrically connected to the second node, the third node and the first power supply terminal, is configured to control the on / off connection between the first power supply terminal and the third node based on the signal from the second node.

10. The shift register according to claim 9, characterized in that, The fourth sub-control unit includes: The fourth transistor has its control terminal electrically connected to the second node, its first source-drain terminal electrically connected to the first power supply terminal, and its second source-drain terminal electrically connected to the third node.

11. A gate driving circuit, characterized in that, Includes multiple shift registers as described in any one of claims 1 to 10; Among them, the pull-up control signals corresponding to the first m shift registers are the start signals, and the pull-up control signal corresponding to the nth shift register is the gate control signal output by the nmth stage shift register, where 1 ≤ m <n,n-m≥1。 12. The gate driving circuit according to claim 11, characterized in that, The first control signal includes a first sub-control signal, a second sub-control signal, and a third sub-control signal; the signal storage module is configured to transmit the first sub-control signal to the second node in the second time period according to the signal of the first node, disconnect the electrical connection between the first power supply terminal and the second node in the second time period according to the second sub-control signal, and transmit the third sub-control signal to the first node in the second time period, the third time period, and the fourth time period according to the signal of the second node; The gate drive circuit further includes a first control line, a second control line, a third control line, and a fourth control line electrically connected to the plurality of shift registers; Wherein, the first control line is configured to transmit the first sub-control signal to the plurality of shift registers, the second control line is configured to transmit the second sub-control signal to the plurality of shift registers, the third control line is configured to transmit the third sub-control signal to the plurality of shift registers, and the fourth control line is configured to transmit the second control signal to the plurality of shift registers.

13. A display panel, characterized in that, include: The gate drive circuit as described in claim 11 or 12; as well as Multiple sub-pixels, electrically connected to the gate driving circuit, are configured to receive multiple gate control signals output by the gate driving circuit; The display panel includes a display period and a touch period in a display cycle. The display period includes the first period. The touch period at least partially overlaps with the third period. The second period is located before the touch period and between the touch period and the display period. The fourth period is located after the touch period and between the touch period and the display period.

14. The display panel according to claim 13, characterized in that, include: Multiple clock lines are electrically connected to multiple shift registers of the gate drive circuit and are configured to transmit corresponding clock signals to the multiple shift registers; Specifically, corresponding to the second time period, the third time period, and the fourth time period, the clock signals transmitted by the multiple clock lines have invalid levels.

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