Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a first gate drive circuit, a pixel circuit and a light-emitting element, the first gate drive circuit comprises a plurality of cascaded shift registers, each shift register comprises a cascade transmission module and a gating module, and the cascade transmission modules are electrically connected with the gating modules. The output end of the stage transmission module in the wth-stage shifting register is electrically connected with the trigger signal end of the (w + 1) th-stage shifting register, the gating module comprises a first transistor, the first electrode of the first transistor is electrically connected with a first voltage signal line, and the second electrode of the first transistor is electrically connected with the grid electrode of the compensation transistor; the display panel comprises at least two first voltage signal lines, the ith-level shifting register and the (i + 1) th-level shifting register are electrically connected with different first voltage signal lines, i is larger than or equal to 1, and effective voltage output by the shifting registers comprises voltage on the first voltage signal lines. According to the embodiment of the invention, the problem of obvious boundary of different refresh areas of the display panel can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the continuous development of display technology, the functions of display products are more and more diversified. For example, a display panel supports partition refresh display, that is, the display area of the display panel is divided into multiple display regions, and the refresh rate of each display region can be independently set to achieve the effect of reducing the driving power consumption of the display panel.

[0003] For example, the display panel includes a high refresh rate area and a low refresh rate area, and the refresh rate of the high refresh rate area is greater than that of the low refresh rate area. In the related art, an obvious boundary line is prone to appear at the boundary between the high refresh rate area and the low refresh rate area. SUMMARY

[0004] Embodiments of the present application provide a display panel and a display device, which can improve the obvious boundary problem of different refresh areas of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel, which includes a first gate drive circuit, a pixel circuit and a light emitting element, the pixel circuit is electrically connected with the light emitting element, the pixel circuit includes a driving transistor, a data writing transistor and a compensation transistor, the data writing transistor is electrically connected with a data signal end and a first electrode of the driving transistor, and the compensation transistor is electrically connected with a second electrode and a gate electrode of the driving transistor; the first gate drive circuit includes a plurality of shift registers connected in cascade, the shift register includes a stage transmission module and a gating module, the stage transmission module is electrically connected with the gating module, and an output end of the stage transmission module in a wth shift register is electrically connected with a trigger signal end of a (w+1)th shift register, the gating module includes a first transistor, a first electrode of the first transistor is electrically connected with a first voltage signal line, and a second electrode of the first transistor is electrically connected with a gate electrode of the compensation transistor; the display panel includes at least two first voltage signal lines, an i th shift register and an (i+1)th shift register are electrically connected with different first voltage signal lines, i≥1, and an effective voltage output by the shift register includes a voltage on the first voltage signal line.

[0006] In a second aspect, an embodiment of the present application provides a display device, which includes the display panel as described in the first aspect.

[0007] According to the display panel and the display device provided in the embodiments of the present application, the i-th stage shift register VSR(i) and the i+1-th stage shift register VSR(i+1) in the first gate drive circuit are electrically connected to two different first voltage signal lines, and the same first voltage signal line is electrically connected to the shift registers in the first gate drive circuit, so that the period of the ripple in the effective level of the first scanning signal can be increased, and even the ripple in the effective level of the first scanning signal can be eliminated, so that the second scanning signal SP is more likely to avoid the area corresponding to the ripple, and the influence of the ripple on the writing of the data signal can be avoided or even eliminated, so that the problem of bright boundary between the high brush area and the low brush area is improved. BRIEF DESCRIPTION OF DRAWINGS

[0008] Other characteristics, objects and advantages of the present application will become more apparent from the following detailed description of non-restrictive embodiments, with reference to the attached drawings, wherein the same or similar reference signs refer to the same or similar features, and the drawings are not drawn to scale.

[0009] Figure 1 A display scene schematic diagram of a display panel is shown;

[0010] Figure 2 A timing schematic diagram of a display panel in the related art is shown;

[0011] Figure 3 A structure schematic diagram of a display panel provided in the embodiments of the present application is shown;

[0012] Figure 4a A structure schematic diagram of a pixel circuit in the display panel provided in the embodiments of the present application is shown;

[0013] Figure 4b A timing schematic diagram of Figure 4a is shown;

[0014] Figure 5 A structure schematic diagram of a first gate drive circuit in the display panel provided in the embodiments of the present application is shown;

[0015] Figure 6 A timing schematic diagram of a display panel provided in the embodiments of the present application is shown;

[0016] Figure 7 Another structure schematic diagram of a first gate drive circuit in the display panel provided in the embodiments of the present application is shown;

[0017] Figure 8 Another timing schematic diagram of a display panel provided in the embodiments of the present application is shown;

[0018] Figure 9 Still another timing schematic diagram of a display panel provided in the embodiments of the present application is shown;

[0019] Figure 10 Another timing diagram of the display panel is shown;

[0020] Figure 11 Another structure diagram of the first gate drive circuit in the display panel is shown;

[0021] Figure 12 Another structure diagram of the first gate drive circuit in the display panel is shown;

[0022] Figure 13 Another structure diagram of the first gate drive circuit in the display panel is shown;

[0023] Figure 14 A structure diagram of the shift register in the display panel is shown;

[0024] Figure 15 A timing diagram of Figure 14 is shown;

[0025] Figure 16 Another timing diagram of Figure 14 is shown;

[0026] Figure 17 A structure diagram of the display device is shown. DETAILED DESCRIPTION

[0027] The features and exemplary embodiments of various aspects of the present application will be described in detail below with reference to the drawings. To make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are configured only to explain the present application and are not configured to limit the present application. The present application can be implemented without some of these specific details for those skilled in the art. The following description of the embodiments is merely to provide a better understanding of the present application by showing examples of the present application.

[0028] It should be noted that, in the present document, relational terms such as first and second and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0029] It should be understood that when a layer, region or element is referred to as being "on" or "above" another layer, region, or element, it can be directly on or above the other layer, region, or element or intervening layers or regions can also be present. In addition, when an element is referred to as being "below" or "under" another element, it can be directly below or under the other element, or intervening layers or regions can also be present.

[0030] It should be understood that the term "and / or" as used herein merely indicates that there can be three conditions, for example, A and / or B can indicate that there are the following three cases: A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in the present document generally indicates that the front and rear associated objects have an "or" relationship.

[0031] In the embodiments of the present application, the term "electrically connected" can mean that two components are directly electrically connected, or can mean that two components are electrically connected via one or more other components. The term "end" can mean "end section" or "end edge". The display panel can be a display device or a module / part of a display device.

[0032] Various modifications and changes can be made to the present application in matters of form and details without departing from the spirit and scope of the present application, which will be apparent to one skilled in the art from the foregoing description. Accordingly, the application intends to embrace all such changes and modifications as fall within the scope of the appended claims (claimed technical solutions) and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other as long as they are not contradictory.

[0033] Before the technical solutions provided by the embodiments of the present application are described, the problems existing in the related art will be specifically described in order to facilitate the understanding of the embodiments of the present application:

[0034] As Figure 1As shown, the display panel supports partition refresh display. The display panel includes a high refresh area and a low refresh area. The high refresh area has a higher data refresh frequency and can be used to play movie, game and other pictures to ensure fast picture refresh and improve user experience. The low refresh area can be used to display text, time information and the like. The low refresh area does not need to have a high data refresh frequency to reduce power consumption.

[0035] However, at the junction of the high refresh area and the low refresh area, an abnormal bright line is prone to occur.

[0036] The inventors have conducted in-depth research on the causes of this problem, as follows:

[0037] In the case that the scan signal S2N is at an active level (for example, high level) and the scan signal SP is at an active level (for example, low level), the data signal can be written into the gate of the driving transistor of the pixel circuit. As shown, Figure 2 As shown, the active level (for example, high level) of the scan signal S2N accessed by the high refresh area is transmitted step by step, and the scan signal S2N accessed by the low refresh area maintains an inactive level (for example, low level).

[0038] The gate driving circuit for outputting the scan signal S2N includes a plurality of cascaded shift registers. The scan signal S2N output by the shift register is used as a driving signal of the pixel circuit, and the scan signal S2N output by the previous stage shift register is used as the input signal of the next stage shift register. Taking the case that the active level of the scan signal S2N is high level as an example, the active level of the scan signal S2N output by each shift register comes from the same VGH signal line. In the case that the scan signal S2N output by the next stage shift register includes an active level, the next stage shift register constitutes a load of the VGH signal line. If the scan signal S2N output by the next stage shift register does not include an active level, the next stage shift register is equivalent to not constituting a load of the VGH signal line.

[0039] If the scan signal S2N output by the next stage shift register includes an active level, when the scan signal S2N output by the next stage shift register jumps from an inactive level to an active level, the high level output by the VGH signal line generates a downward ripple, so that the high level of the scan signal S2N output by the previous stage shift register has a downward ripple. If the scan signal S2N output by the next stage shift register does not include an active level, the load of the VGH signal line will not be increased, so that the high level of the scan signal S2N output by the previous stage shift register will not have a downward ripple.

[0040] For example, the scan signals S2N(n-5) to S2N(n) in the high brush area have valid levels, and the scan signals S2N(n+1) to S2N(n+6) in the low brush area do not have valid levels. Since the previous stage scan signal S2N is affected by the next stage scan signal S2N when the next stage scan signal S2N has a valid level, the valid level of the previous stage scan signal S2N has a ripple (for example, a downward ripple). The scan signals S2N in the high brush area and at the junction with the low brush area have abnormal ripples because the scan signals S2N in the low brush area do not have valid levels.

[0041] For example, each of the scan signals S2N(n-5) to S2N(n+6) drives two rows of pixel circuits, the valid level of the scan signal S2N progresses by 2H, and the downward ripple of the valid level of the scan signal S2N occurs with a period of 2H. The ripples of the last few stage scan signals S2N in the high brush area are abnormal, for example, Figure 2 The scan signal SP at the middle position 1 has a valid level, but the scan signals S2N(n-5), S2N(n-4), and S2N(n-3) have downward ripples at this position; Figure 2 The scan signal SP at the middle position 2 has a valid level, but the scan signals S2N(n-2), S2N(n-1), and S2N(n) do not have ripples at this position; this causes abnormal writing of the data signal and is prone to display brightening, resulting in a bright line at the junction of the high brush area and the low brush area.

[0042] To improve the above technical problems, embodiments of the present application provide a display panel and a display device, which will be described below with reference to the accompanying drawings.

[0043] Please refer to Figures 3 to 5 The display panel 100 provided by the embodiments of the present application includes a first gate drive circuit 1, a pixel circuit 2, and a light emitting element 3.

[0044] The pixel circuit 2 is electrically connected to the light emitting element 3. The pixel circuit 2 is configured to drive the light emitting element 3 to emit light.

[0045] A plurality of pixel circuits 2 are arranged in an intersecting first direction X and a second direction Y. For example, the first direction X is a row direction, and the second direction Y is a column direction.

[0046] The pixel circuit 2 includes a driving transistor M3, a data writing transistor M2, and a compensation transistor M5. The data writing transistor M2 is electrically connected between a data signal end Vdata and a first electrode of the driving transistor M3. The compensation transistor M5 is electrically connected between a second electrode of the driving transistor M3 and a gate electrode of the driving transistor M3.

[0047] The gate of compensation transistor M5 is connected to the first scan signal S2N, and the gate of data writing transistor M2 is connected to the second scan signal SP. When the first scan signal S2N is active and the second scan signal SP is active, data writing transistor M2 is turned on, compensation transistor M5 is turned on, the signal at the data signal terminal Vdata is written to the gate of driving transistor M3, and compensation transistor M5 compensates for the threshold voltage of driving transistor M3.

[0048] In this application, the effective level of the first scan signal S2N is high and the effective level of the second scan signal SP is low, but this is not intended to limit this application.

[0049] For example, the pixel circuit also includes light-emitting control transistors M1 and M6, a first reset transistor M4, a second reset transistor M7, and a bias adjustment transistor M8.

[0050] The light-emitting control transistors M1 and M6 are used to control whether the light-emitting element emits light under the control of the light-emitting control signal Emit.

[0051] The first reset transistor M4 is used to reset the gate of the drive transistor M3 based on the signal of the first reset signal terminal Vref1 under the control of the scan signal S1N.

[0052] The second reset transistor M7 is used to reset the scan signal SP. * Under the control of [the system], the first electrode of the light-emitting element 2 is reset based on the signal of the second reset signal terminal Vref2.

[0053] Bias adjustment transistor M8 is used for scanning signal SP * Under the control of the bias adjustment signal terminal DVH, the bias state of the driving transistor M3 is adjusted.

[0054] It should be noted that, Figure 4a The structure shown is merely an example and is not intended to limit this application. The technical concept of this application also applies to... Figure 4a Pixel circuits with other structures besides those mentioned above.

[0055] The first gate drive circuit 1 includes multiple cascaded shift registers (VSRs). Each VSR includes a cascading module 11 and a gating module 12. The cascading module 11 and the gating module 12 are electrically connected, and the output terminal next of the cascading module 11 in the w-th stage shift register VSR(w) is electrically connected to the input signal terminal IN of the (w+1)-th stage shift register VSR(w+1). The signal output from the output terminal next of the cascading module 11 in the w-th stage shift register VSR(w) serves as the trigger signal for the (w+1)-th stage shift register VSR(w+1) to perform signal cascading. w is an integer greater than 0.

[0056] The gate of the first transistor 121 is electrically connected to the first voltage signal line VGH1, the source of the first transistor 121 is electrically connected to the output terminal out of the gate-on module 12, and the output terminal out of the gate-on module 12 is electrically connected to the gate of the compensation transistor M5. The output terminal out of the gate-on module 12 outputs the first scan signal S2N. The effective voltage of the first scan signal S2N is from the voltage on the first voltage signal line VGH1. The voltage on the first voltage signal line VGH1 is a constant voltage. The effective voltage of the first scan signal S2N is a voltage for controlling the compensation transistor M5 to be turned on. For example, the compensation transistor M5 is an N-type transistor, and the effective voltage of the first scan signal S2N and the voltage on the first voltage signal line VGH1 are high voltages.

[0057] For example, the first-stage shift register VSR can be used to drive two rows of pixel circuits 2. That is, the output terminal out of the gate-on module 12 in the first-stage shift register VSR is electrically connected to the gates of the compensation transistors M5 in the two rows of pixel circuits 2.

[0058] Of course, in other embodiments, the first-stage shift register VSR can also be used to drive one row of pixel circuits 2, or the first-stage shift register VSR can also be used to drive three or even more rows of pixel circuits 2.

[0059] The gate-on module 12 is also connected to the gate-on signal S2N_Ctrl, which is used to control whether the first scan signal S2N output by the gate-on module 12 includes an effective voltage. For example, when the gate-on signal S2N_Ctrl is at a low level, the first scan signal S2N output by the gate-on module 12 includes an effective voltage; when the gate-on signal S2N_Ctrl is at a high level, the first scan signal S2N output by the gate-on module 12 maintains an ineffective voltage. The ineffective voltage of the first scan signal S2N cannot control the compensation transistor M5 to be turned on.

[0060] By controlling the level of the gate-on signal S2N_Ctrl, the display panel can be partitioned for frequency division display. For example, for the first display area A1 in the first display area A1, the gate-on signal S2N_Ctrl connected to the shift register VSR is at a low level, and the display area A1 is refreshed at a high refresh frequency. For the second display area A2 in the second display area A2, the gate-on signal S2N_Ctrl connected to the shift register VSR is at a high level, and the display area A1 is refreshed at a low refresh frequency. Figure 3 Figure 3 For the second display area A2 in the second display area A2, the gate-on signal S2N_Ctrl connected to the shift register VSR is at a high level, and the display area A1 is refreshed at a low refresh frequency.

[0061] ​The display panel comprises at least two first voltage signal lines VGH1, the first transistor 121 in the i-th stage shift register VSR(i) is electrically connected to the first first voltage signal line VGHA, the first transistor 121 in the i+1-th stage shift register VSR(i+1) is electrically connected to the second first voltage signal line VGHB, and the first voltage signal line VGHA and the first voltage signal line VGHB are two different first voltage signal lines. Wherein, i≥1, and i is an integer.

[0062] The i-th stage shift register VSR(i) and the i+1-th stage shift register VSR(i+1) are two adjacent stage shift registers. The stage transmission output end next of the stage transmission module 11 in the i-th stage shift register VSR(i) is electrically connected to the input signal end IN of the i+1-th stage shift register VSR(i+1).

[0063] The i-th stage shift register VSR(i) and the i+1-th stage shift register VSR(i+1) can be any two adjacent stage shift registers in the first gate drive circuit. In this way, the first transistor in any two adjacent stage shift registers is electrically connected to different first voltage signal lines.

[0064] For example, as shown in FIG. 2, the first voltage signal line VGHA is electrically connected to the first transistor 121 in the i-th stage shift register VSR(i), and the first voltage signal line VGHB is electrically connected to the first transistor 121 in the i+1-th stage shift register VSR(i+1). Figure 6 As shown in FIG. 2, the first scan signal S2N(n-5) to the first scan signal S2N(n+3) are respectively signals output by the continuous n-5-th stage shift register to the n+3-th stage shift register. For example, the n-5-th stage shift register, the n-3-th stage shift register, the n-1-th stage shift register, the n+1-th stage shift register, and the n+3-th stage shift register are electrically connected to the first voltage signal line VGHA, and the n-4-th stage shift register, the n-2-th stage shift register, the n-th stage shift register, and the n+2-th stage shift register are electrically connected to the first voltage signal line VGHB. Taking the n-5-th stage shift register and the n-4-th stage shift register as an example, since the n-5-th stage shift register is electrically connected to the first voltage signal line VGHA and the n-4-th stage shift register is electrically connected to the first voltage signal line VGHB, the n-4-th stage shift register does not constitute a load of the first voltage signal line VGHA, so when the first scan signal S2N(n-4) output by the n-4-th stage shift register jumps from a low level to a high level, it will not cause a downward ripple of the high level output by the first voltage signal line VGHA, thereby not causing a downward ripple of the first scan signal S2N(n-5) output by the n-5-th stage shift register at this time. With respect to Figure 2The illustrated ripple period, will be passed on to the step-by-step transfer caused by the ripple into the interlaced ripple, for example, the interval period of the ripple from 2H increased to 4H. In this way, the effective level of the second scanning signal SP is more easily avoided in the region corresponding to the ripple, and is beneficial to avoid the influence of the ripple on the data signal writing, thereby improving the problem of brightening at the boundary between the high brush area and the low brush area.

[0065] Figure 4b A timing diagram of the pixel circuit is shown, please refer to Figure 4a and Figure 4b In stage d1, the scanning signal S1N is at an effective level (high level), the first reset transistor M4 is turned on, and the signal at the first reset signal end Vref1 resets the gate of the driving transistor M3. In stage d2, the scanning signal S2N is at an effective level (high level), the scanning signal SP is at an effective level (low level), the data writing transistor M2 and the compensation transistor M5 are turned on, the data signal at the data signal end data is written to the gate of the driving transistor M3, and the compensation transistor M5 compensates the threshold voltage of the driving transistor M3. In stage d3, the scanning signal SP* is at an effective level (low level), the bias adjustment transistor M8 is turned on, and the signal at the bias adjustment signal end DVH adjusts the bias state of the driving transistor M3. In stage d4, the light emitting control signal Emit is at an effective level (low level), the light emitting control transistors M1 and M6 are turned on, and the light emitting element 3 emits light.

[0066] If the effective level of the scanning signal S2N includes a ripple, and the scanning signal SP is at an effective level and overlaps with the ripple of the effective level of the scanning signal S2N, the writing effect of the data signal will be affected. According to the display panel provided in the embodiments of the present application, the i-th shift register VSR(i) and the i+1-th shift register VSR(i+1) in the first gate drive circuit are electrically connected to two different first voltage signal lines, and are electrically connected to the same first voltage signal line with respect to the shift registers in the first gate drive circuit. In this way, when the scanning signal output by the i+1-th shift register VSR(i+1) includes an effective level, it will not form a load for the first voltage signal line electrically connected to the i-th shift register VSR(i), so that when the scanning signal output by the i+1-th shift register VSR(i+1) jumps to an effective level, the voltage of the first voltage signal line electrically connected to the i-th shift register VSR(i) will not produce a ripple, thereby increasing the period of the ripple in the effective level of the first scanning signal output by the shift register, and even eliminating the ripple in the effective level of the first scanning signal, so that the second scanning signal SP is more easily avoided in the region corresponding to the ripple, and is beneficial to avoid the influence of the ripple on the data signal writing, thereby improving the problem of brightening at the boundary between the high brush area and the low brush area.

[0067] In some embodiments, such as Figure 7 As shown, the number of first voltage signal lines VGH1 is j, j≥2, and j is an integer. The first gate drive circuit includes multiple shift circuit groups 10. Each shift circuit group 10 includes j cascaded shift registers VSR. The j shift registers VSR in the shift circuit group 10 and the j first voltage signal lines VGH1(1) to VGH1(j) are electrically connected in a one-to-one correspondence.

[0068] For example, in the same shift circuit group 10, the first shift register VSR(1) is electrically connected to the first first voltage signal line VGH1(1), the second shift register VSR(2) is electrically connected to the second first voltage signal line VGH1(2), and so on, the j-th shift register VSR(j) is electrically connected to the j-th first voltage signal line VGH1(j).

[0069] In the same shift circuit group 10, the j shift registers VSR are cascaded, and any two shift registers VSR are electrically connected to different first voltage signal lines VGH1. Therefore, in the same shift circuit group 10, when the first scan signal S2N output by any shift register VSR changes from low to high, it will not cause ripple in the effective level of the first scan signal S2N output by its previous shift register VSR.

[0070] For example, when j=2, the two shift registers VSR and the two first voltage signal lines VGH1 within shift circuit group 10 are electrically connected in a one-to-one correspondence. As another example, when j=3, the three shift registers VSR and the three first voltage signal lines VGH1 within shift circuit group 10 are electrically connected in a one-to-one correspondence. Examples will not be provided further here.

[0071] Each of the j first voltage signal lines VGH1(1) to VGH1(J) is electrically connected to one of the j shift registers VSR in any shift circuit group 10. For example, each of the j first voltage signal lines VGH1(1) to VGH1(j) is electrically connected to one of the j shift registers VSR in the first shift circuit group 10, and so on, until the j first voltage signal lines VGH1(1) to VGH1(j) are electrically connected to one of the j shift registers VSR in the last shift circuit group 10. In other words, multiple shift circuit groups 10 share the same j first voltage signal lines VGH1.

[0072] In some embodiments, such as Figure 7As shown, the shift registers VSR with the same order in different shift circuit groups 10 are electrically connected to the same first voltage signal line VGH1.

[0073] For example, the first shift register VSR(1) in the first shift circuit group 101 and the first shift register VSR(1) in the second shift circuit group 102 are electrically connected to the first first voltage signal line VGH1(1); the second shift register VSR(2) in the first shift circuit group 101 and the second shift register VSR(2) in the second shift circuit group 102 are electrically connected to the second first voltage signal line VGH1(2); and so on, the jth shift register VSR(j) in the first shift circuit group 101 and the jth shift register VSR(j) in the second shift circuit group 102 are electrically connected to the jth first voltage signal line VGH1(j).

[0074] In this embodiment, the shift registers VSR with the same order in different shift circuit groups 10 are electrically connected to the same first voltage signal line VGH1, so that the connection rule of the plurality of shift registers and the plurality of first voltage signal lines in different shift circuit groups is the same, which can improve the display uniformity.

[0075] The more the number of the first voltage signal lines VGH1 electrically connected to the first gate drive circuit, the more the period of the ripple of the effective level of the first scan signal S2N can be increased, and even the ripple of the effective level of the first scan signal S2N can be eliminated. However, the more the number of the first voltage signal lines VGH1, the more difficult it is to realize a narrow frame.

[0076] In some embodiments, in the case that the shift registers VSR with the same order in different shift circuit groups 10 are electrically connected to the same first voltage signal line VGH1, as shown in FIG. 2, the output end out of the plurality of shift registers VSR outputs the first scan signal S2N with an effective level that progresses by k*H. Figure 8 As shown, the effective level of the first scan signal S2N output by the output end out of the plurality of shift registers VSR progresses by k*H. That is, the starting time of the effective level of the first scan signal S2N output by the output end out of the previous shift register VSR is earlier than the starting time of the effective level of the first scan signal S2N output by the output end out of the next shift register VSR by a time length of k*H. H is the scanning time length of one row of pixel circuits. Exemplarily, k is an integer.

[0077] The time length of the effective level of the first scan signal S2N is m*H, and 2≤j≤m / k. m / k is an integer. Exemplarily, m and k are integers.

[0078] The minimum value of j is 2, and the maximum value of j is m / k.

[0079] In some embodiments, j=m / k.

[0080] For the first scanning signal S2N outputted by any stage of the shift register, the starting time of the effective level of the first scanning signal S2N has overlap with the first scanning signal S2N outputted by the (m / k)-1 stage of the shift register. In the case of j=m / k, the ripple of the effective level of the first scanning signal S2N outputted by any stage of the shift register is eliminated.

[0081] For example, the shift registers VSR with the same order in different shift circuit groups 10 are connected to the same first voltage signal line VGH1, and as shown in FIG. 2, j=m / k, k=2, m=10, and j=5. The effective level of the first scanning signal S2N is advanced by 2*H, and the time length of the effective level of the first scanning signal S2N is 10*H. Figure 8

[0082] In the case of j=5, every five shift registers VSR form a shift circuit group.

[0083] For example, the five shift registers outputting the first scanning signal S2N(n-5) to the first scanning signal S2N(n-1) form a shift circuit group. The five shift registers outputting the first scanning signal S2N(n-5) to the first scanning signal S2N(n-1) are connected to the five first voltage signal lines VGH1 in one-to-one correspondence. When any one of the first scanning signal S2N(n-4) to the first scanning signal S2N(n-1) jumps from low level to high level, the high level (the effective level has ripple) of the first scanning signal S2N(n-5) is not caused. The first scanning signals S2N outputted by other stages of the shift registers are the same, and thus are not described one by one here.

[0084] That is, in the case of j=m / k, the ripple of the effective level of the first scanning signal S2N outputted by any stage of the shift register is avoided. In the embodiments of the present application, the value range of j is designed as 2≤j≤m / k. The ripple of the effective level of the first scanning signal S2N outputted by any stage of the shift register is improved or even eliminated, and the problem of too many first voltage signal lines VGH1 causing a large frame is not caused.

[0085] In addition, in the case of j=m / k, the effective level of the first scanning signal S2N outputted by any stage of the shift register has no ripple, and the position of the effective level of the second scanning signal SP in time is not limited by the ripple. The position of the effective level of the second scanning signal SP in time can be more flexibly designed to flexibly meet more requirements.

[0086] In some embodiments, the time length of the effective level of the first scanning signal S2N is m*H, and m=(2+4*N)*H, N≥1.

[0087] ​Here, N can be an integer. N has a minimum value of 1, and a maximum value of N can be designed according to actual requirements. The greater N is, the greater the pulse width of the effective level of the first scanning signal S2N is.

[0088] In this embodiment, m is limited to (2+4*N)*H, and the duration of the effective level of the first scanning signal S2N is greater than 2H, which ensures that the effective level of the first scanning signal S2N has sufficient width, so that the effective level of the first scanning signal S2N can cover at least the effective level of the second scanning signal SP accessed by the adjacent two rows of pixel circuits, thereby ensuring that the first scanning signal S2N output by the primary shift register can drive at least two rows of pixel circuits, realizing the function of one driving multiple, reducing the number of shift registers, and realizing narrow frame.

[0089] In some embodiments, k≥2. In the case of k=2, the primary shift register VSR can be used to drive two rows of pixel circuits. The greater k is, the greater the number of rows of pixel circuits that can be driven by the primary shift register VSR. In this embodiment, it is further ensured that the first scanning signal S2N output by the primary shift register can drive at least two rows of pixel circuits, realizing the function of one driving multiple, reducing the number of shift registers, and realizing narrow frame.

[0090] In the case of k=m / k, the effective level of the first scanning signal S2N can be free of ripple.

[0091] In other embodiments, j can be in the range of 2

[0092] In different shift circuit groups 10, in the case that the shift registers VSR of the same order are electrically connected to the same first voltage signal line VGH1, the effective level of the first scanning signal S2N output by the output end out of the plurality of shift registers VSR is taken as an example, and H is the scanning duration of a row of pixel circuits. Exemplarily, k is an integer.

[0093] As shown in Figure 3 and Figure 4a , the display panel includes a plurality of rows of pixel circuits 2 arranged in the second direction Y. In the case that the first scanning signal S2N is at the effective level (high level) and the second scanning signal SP is at the effective level (low level), the data signal of the data signal end Vdata can be written to the gate of the driving transistor M3.

[0094] AsFigure 9 As shown, the gate of the compensation transistor in the 2a-1th row pixel circuit is connected to the first scanning signal S2N(a), and the gate of the data writing transistor in the 2a-1th row pixel circuit is connected to the second scanning signal SP(2a-1); the gate of the data writing transistor in the 2a row pixel circuit is connected to the second scanning signal SP(2a). In other words, the 2a-1th row pixel circuit and the 2a row pixel circuit are driven by the same first scanning signal S2N(a) and different second scanning signals SP.

[0095] The start time of the active level of the second scanning signal SP(2a-1) is separated from the start time of the active level of the first scanning signal S2N(a) by a time length L, L≥[2*j*(b-1)+1]*H, and b is greater than or equal to 1. For example, b is an integer greater than or equal to 1.

[0096] The j shift registers in the same shift circuit group 10 and the j first voltage signal lines VGH1 are connected one by one, and in the case of 2

[0097] For example, b=1, the active level of the second scanning signal SP(2a-1) and SP(2a) is located in the first ripple period, L≥1H, and D≥0. D represents the separation time length between the end time of the active level of the second scanning signal SP(2a) and the first ripple after it.

[0098] For example, b=2, the active level of the second scanning signal SP(2a-1) and SP(2a) is located in the second ripple period Figure 9 The active level of the second scanning signal SP(2a-1) and SP(2a) in the second ripple period is shown by a dashed line), L≥(2*j+1)*H, and D≥0.

[0099] That is, taking the start time of the active level of the first scanning signal S2N(2a-1) as the reference point, the active level of the second scanning signal SP(2a-1) and SP(2a) is located in [2*j*(b-1)+2]*H to [2*j*b]*H, in which case, the active level of the second scanning signal SP(2a-1) can avoid the ripple of the first scanning signal S2N(2a-1), thereby avoiding the influence of the ripple on the writing of the data signal.

[0100] The greater the value of j is, the more the number of the first voltage signal lines VGH1 required is, and the more unfavorable narrow frame is achieved. In some other embodiments, j = 2. In this embodiment, only two first voltage signal lines are provided, which can both increase the period of the ripple in the effective level of the first scanning signal and better achieve narrow frame.

[0101] In some embodiments, as shown in FIG. 2, in the case of j = 2, the odd-numbered stage shift registers VSR are connected to the first first voltage signal line VGHA, and the even-numbered stage shift registers VSR are connected to the second first voltage signal line VGHB. Figure 5

[0102] Each shift register VSR includes a first transistor 121, one end of the first transistor 121 being connected to an output end out, the output end out being electrically connected to the gate of the compensation transistor in the pixel circuit. The first transistor 121 in the odd-numbered stage shift register VSR is connected to the first first voltage signal line VGHA, and the first transistor 121 in the even-numbered stage shift register VSR is connected to the second first voltage signal line VGHB.

[0103] In this embodiment, it can be ensured that any two adjacent stage shift registers are electrically connected to different first voltage signal lines VGH1, which can both increase the period of the ripple in the effective level of the first scanning signal and make the period of the ripple in the effective level of the first scanning signal more regular, so as to facilitate the effective level of the second scanning signal SP to avoid the ripple of the first scanning signal.

[0104] It can be understood that in the case of j = 2, the effective level of at least one first scanning signal S2N still has a ripple, and the relative positions of the first scanning signal S2N and the second scanning signal SP can be designed in the following manner to make the effective level of the second scanning signal SP avoid the ripple of the first scanning signal S2N, thereby avoiding the influence of the ripple on the writing of the data signal.

[0105] In the case of j = 2, the odd-numbered stage shift registers VSR being connected to the first first voltage signal line VGHA, and the even-numbered stage shift registers VSR being connected to the second first voltage signal line VGHB, the effective level of the first scanning signal S2N output by the output end out of the plurality of shift registers VSR is taken as an example, and the effective level is taken as an example of k*H progression, H being the scanning time length of one row of pixel circuits. Exemplarily, k is an integer.

[0106] As shown in FIG. 2, in the case of j = 2, the odd-numbered stage shift registers VSR are connected to the first first voltage signal line VGHA, and the even-numbered stage shift registers VSR are connected to the second first voltage signal line VGHB. Figure 10 ​As shown, the gate of the compensation transistor in the 2a-1th row pixel circuit is connected to the first scanning signal S2N(a), and the gate of the data writing transistor in the 2a-1th row pixel circuit is connected to the second scanning signal SP(2a-1); the gate of the compensation transistor in the 2a row pixel circuit is connected to the first scanning signal S2N(a), and the gate of the data writing transistor in the 2a row pixel circuit is connected to the second scanning signal SP(2a). In other words, the 2a-1th row pixel circuit and the 2a row pixel circuit are driven by the same first scanning signal S2N(a) and different second scanning signals SP.

[0107] The start time of the active level of the second scanning signal SP(2a-1) is separated from the start time of the active level of the first scanning signal S2N(a) by a time interval t1, t1≥(4*N+0.5)*H, or t1≥4*N*H+0.5us, N≥0, and N is an integer. Us represents microsecond, 1us=10 -6 s.

[0108] The end time of the active level of the second scanning signal SP(2a) is separated from the start time of the active level of the first scanning signal S2N(a) by a time interval t2, t2<(4*N+4)*H.

[0109] Here, N can be an integer. The minimum value of N is 1, and the maximum value of N can be designed according to actual requirements. The larger N is, the larger t1 is.

[0110] For example, the width of the active level of the first scanning signal S2N is 10H, and the rising edge of the first scanning signal S2N is taken as the reference position. The ripple periodically appears within (4N+1)*H from the rising edge of the first scanning signal S2N, that is, at 5H and 9H. The influence time of the ripple is less than 0.5H, that is, the time length of the ripple is less than 0.5H, and therefore the corresponding second scanning signal SP needs to be located between 5.5H and 8H from the rising edge of the first scanning signal S2N. Figure 10 Here, t2>0.5H, and t4>0.

[0111] If the width of the active level of the first scanning signal S2N is other values, the ripple still periodically appears within (4N+0.5)*H from the rising edge of the first scanning signal S2N. For the second scanning signal SP, the falling edge of the second scanning signal SP(2a-1) is separated from the rising edge of the first scanning signal S2N(2a-1) by a time interval t1, t1≥(4N+0.5)H, and the rising edge of the second scanning signal SP(2a) is separated from the rising edge of the first scanning signal S2N(2a-1) by a time interval t4, t4<(4N+4)H.

[0112] In this way, the effective levels of the second scan signal SP(2a-1) and the second scan signal SP(2a) can avoid the ripple of the first scan signal S2N(2a-1), thereby avoiding the influence of ripple on the data signal writing.

[0113] In some embodiments, the time interval between the end of the effective level of the second scan signal SP(2a-1) and the start of the effective level of the second scan signal SP(2a) is greater than 0.

[0114] For example, the effective level of the second scan signal SP is low, and the time interval between the falling edge of the second scan signal SP(2a-1) and the rising edge of the second scan signal SP(2a) is greater than 0.

[0115] In other words, the effective level of the second scan signal SP(2a-1) and the effective level of the second scan signal SP(2a) do not overlap.

[0116] When the second scan signal SP(2a-1) is active, the pixel circuit of row 2a-1 writes data signals; when the second scan signal SP(2a) is active, the pixel circuit of row 2a writes data signals; when the active levels of the second scan signal SP(2a-1) and the second scan signal SP(2a) do not overlap, data signals can be written to the pixel circuit row by row, avoiding data signal writing errors.

[0117] Understandably, the number of first voltage signal lines j electrically connected to the first gate drive circuit and the number of pixel circuit rows driven by the first-level shift register may differ in different display products. For example, the period of the ripple in the effective level of the first scan signal is defined as E*H, where E=j*p, and p represents the number of pixel circuit rows driven by the first-level shift register; for any case, the time interval t' between the start time of the effective level of the second scan signal SP(2a-1) and the start time of the effective level of the first scan signal S2N(a) can satisfy the following conditions: t'≥(E*N+0.5)*H, or t'≥(E*N)*H+0.5us.

[0118] For example, when j=2 and p=2, E=4 and t'=t1.

[0119] In some embodiments, such as Figure 11 As shown, the shift register also includes a second transistor 122, and both the second transistor 122 and the first transistor 121 need to be connected to a high voltage. The second transistor and the first transistor in the same shift register VSR are electrically connected to the same first voltage signal line VGH1.

[0120] For example, Figure 11In the first stage shift register VSR(i), the first transistor 121 is connected to the first voltage signal line VGHA, and the second transistor 122 in the first stage shift register VSR(i) is also electrically connected to the first voltage signal line VGHA.

[0121] The first transistor 121 in the (i+1)th stage shift register VSR(i+1) is electrically connected to the second first voltage signal line VGHB.

[0122] In this embodiment, in the same level shift register, the first transistor and the second transistor that need to be connected to a high level are electrically connected to the same first voltage signal line. This reduces the number of first voltage signal lines required and is more conducive to achieving a narrow bezel.

[0123] In other embodiments, such as Figure 12 As shown, the shift register also includes a second transistor 122, which is electrically connected to the second voltage signal line VGH2.

[0124] The second voltage signal line VGH2 and the first voltage signal line VGH1 are different voltage signal lines. Both the second voltage signal line VGH2 and the first voltage signal line VGH1 are used to transmit high voltage. For example, the voltages of the second voltage signal line VGH2 and the first voltage signal line VGH1 may be the same or different.

[0125] In this embodiment, the first transistor and the second transistor in the same stage shift register are connected to different voltage signal lines, which allows for flexible adjustment of the voltage levels connected to the first transistor and the second transistor respectively.

[0126] In some embodiments, such as Figure 12 As shown, when the second transistor 122 and the second voltage signal line VGH2 are electrically connected, the second transistor 122 in the i-th stage shift register VSR(i) and the second transistor 122 in the (i+1)-th stage shift register VSR(i+1) are electrically connected to the same second voltage signal line VGH2.

[0127] For example, the first transistor 121 in the i-th stage shift register VSR(i) is electrically connected to the first first voltage signal line VGHA, the first transistor 121 in the (i+1)-th stage shift register VSR(i+1) is electrically connected to the second first voltage signal line VGHB, and the second voltage signal line electrically connected to the second transistor 122 in the i-th stage shift register VSR(i) and the second transistor 122 in the (i+1)-th stage shift register VSR(i+1) is marked as VGHC.

[0128] In the embodiment, the second transistor in different stages of the shift register is electrically connected to the same second voltage signal line, which is beneficial to realize narrow frame.

[0129] In some embodiments, as shown in FIG. 1, the first transistor 121 in the i-th stage of the shift register VSR(i) is electrically connected to the first voltage signal line VGH1, and the first transistor 121 in the i+1-th stage of the shift register VSR(i+1) is electrically connected to the second voltage signal line VGH2. Figure 13

[0130] For example, the first transistor 121 in the i-th stage of the shift register VSR(i) is electrically connected to the first voltage signal line VGH1, the first transistor 121 in the i+1-th stage of the shift register VSR(i+1) is electrically connected to the second voltage signal line VGH2, the second transistor 122 in the i-th stage of the shift register VSR(i) is electrically connected to the second voltage signal line VGH2, and the second transistor 122 in the i+1-th stage of the shift register VSR(i+1) is electrically connected to the second voltage signal line VGH1.

[0131] In the embodiment, the first transistor in different stages of the shift register is electrically connected to different first voltage signal lines, and the second transistor in different stages of the shift register is electrically connected to different second voltage signal lines, which can more flexibly adjust the voltage to which the first transistor and the second transistor are connected.

[0132] In some embodiments, different first voltage signal lines VGH1 are electrically connected to different signal terminals. The voltages of the different signal terminals electrically connected by the different first voltage signal lines VGH1 are the same.

[0133] For example, the first voltage signal line VGH1 and the second voltage signal line VGH2 are electrically connected to different signal terminals. The voltages of the signal terminals electrically connected by the first voltage signal line VGH1 and the second voltage signal line VGH2 are the same.

[0134] Of course, in other embodiments, the voltages of the different signal terminals electrically connected by the different first voltage signal lines VGH1 can also be the same.

[0135] For example, the first voltage signal line VGH1 and the second voltage signal line VGH2 are electrically connected to different signal terminals. The voltages of the signal terminals electrically connected by the first voltage signal line VGH1 and the second voltage signal line VGH2 are the same.

[0136] ​Of course, in other embodiments, the voltages of the signal terminals to which the first voltage signal line VGH1 and the second voltage signal line VGH2 are electrically connected can also be different.

[0137] As an example, the different second voltage signal lines VGH2 are electrically connected to different signal terminals. The voltages of the different signal terminals to which the different second voltage signal lines VGH2 are electrically connected are the same. Alternatively, the voltages of the different signal terminals to which the different second voltage signal lines VGH2 are electrically connected can also be different.

[0138] As an example, the circuit structure of the shift register can be as shown in Figure 14 The first transistor 121 in the above example includes the transistor T20 in Figure 14 The second transistor 122 in the above example includes the transistors T6, T9, T13, T12, T19 in Figure 14

[0139] The transistor T20 is configured to transmit the voltage on the first voltage signal line VGH1 to the output terminal out, i.e., the voltage on the first voltage signal line VGH1 output by the transistor T20 to the pixel circuit.

[0140] The transistor T9 is configured to transmit the voltage on the signal line VGH to the next stage terminal next. The signal line VGH to which the transistor T9 is electrically connected can be the same signal line as the first voltage signal line VGH1, or can be a different signal line.

[0141] The transistor T19 is configured to transmit the voltage on the signal line VGH to the gate of the transistor T20. The signal line VGH to which the transistor T19 is electrically connected can be the same signal line as the first voltage signal line VGH1, or can be a different signal line.

[0142] The transistor T6 is configured to transmit the voltage on the signal line VGH to the node N12. The signal line VGH to which the transistor T6 is electrically connected can be the same signal line as the first voltage signal line VGH1, or can be a different signal line.

[0143] The transistor T12 is configured to transmit the voltage on the signal line VGH to the node N11_2. The signal line VGH to which the transistor T12 is electrically connected can be the same signal line as the first voltage signal line VGH1, or can be a different signal line.

[0144] The transistor T13 is configured to transmit the voltage on the signal line VGH to the node N11_1. The signal line VGH to which the transistor T13 is electrically connected can be the same signal line as the first voltage signal line VGH1, or can be a different signal line.

[0145] Of course, Figure 14 ​The technical concept of the present application can also be applied to shift registers of other structures.

[0146] For example, referring to Figure 14 and Figure 15 , the display area of the display panel can include a high-refresh area and a low-refresh area, the working timing of the shift register electrically connected to the high-refresh area corresponds to the high-refresh area timing, and the working timing of the shift register electrically connected to the low-refresh area corresponds to the low-refresh area maintenance timing.

[0147] In the high-refresh area timing, the signals output by the output end out all include a valid level (high level); in the low-refresh area maintenance timing, the signals output by the output end out maintain an invalid level (low level). In the high-refresh area timing and the low-refresh area maintenance timing, the signals output by the stage transfer output end next all include a valid level, thereby ensuring normal signal stage transfer in the case of realizing partition frequency division refresh.

[0148] Next, referring to Figure 14 and Figure 15 , the high-refresh area timing is introduced, where the selection signal S2N_Ctrl maintains a low level, and the transistor T18 remains in an on state.

[0149] In stage c11, the high level of the input signal end IN is written to node N1, at this time, the transistor T10 and the transistor T21 are closed, node N2 maintains a high level, the transistor T9 and the transistor T20 are closed, and the stage transfer end Next and the output end out maintain a low level output.

[0150] In stage c12, the clock signal XCK jumps from a high level to a low level, at this time, node N2 and node N9 are written to a low level, the transistor T9 and the transistor T20 are turned on, and the stage transfer end Next and the output end out output a high level.

[0151] In stage c13, the low level of the input signal end IN is written to node N1, node N2 and node N9 are written to a high level, at this time, the transistor T10 and the transistor T21 are turned on, and the stage transfer end Next and the output end out output a low level.

[0152] Next, referring to Figure 14 and Figure 15 , the low-refresh area maintenance timing is introduced, where the selection signal S2N_Ctrl maintains a low level, and the transistor T18 remains in a closed state.

[0153] Among them, the timing of stage c21 is the same as that of stage c11, and the timing of stage c23 is the same as that of stage c13.

[0154] In stage c12, node N9 cannot be written to low level because transistor T18 is off, at this time output end out maintains output low level. But level transfer end next can output high level, so as not to affect normal level transfer of signals.

[0155] In some embodiments, as shown in Figure 7 The display panel at least includes a first connection line 41 and a second connection line 42, the first connection line 41 is electrically connected to the j_1th first voltage signal line VGH1(1) and the shift register VSR, the second connection line 42 is electrically connected to the j_2th first voltage signal line VGH1(2) and the shift register VSR, and the first connection line 41 and the second connection line 42 are electrically connected to different shift registers VSR.

[0156] The length of the first connection line 41 is less than the length of the second connection line 42, and the impedance of the j_1th first voltage signal line VGH1(1) per unit length is greater than the impedance of the j_2th first voltage signal line VGH1(2) per unit length.

[0157] In the case that the impedance of the first connection line 41 per unit length is equal to the impedance of the second connection line 42 per unit length, the impedance of the first connection line 41 is less than the impedance of the second connection line 42.

[0158] The length of the j_1th first voltage signal line VGH1(1) can be equal to the length of the j_2th first voltage signal line VGH1(2), and in the case that the impedance of the j_1th first voltage signal line VGH1(1) per unit length is greater than the impedance of the j_2th first voltage signal line VGH1(2) per unit length, the impedance of the j_1th first voltage signal line VGH1(1) is greater than the impedance of the j_2th first voltage signal line VGH1(2). In this way, the overall impedance of the first connection line 41 and the j_1th first voltage signal line VGH1(1) is close to the overall impedance of the second connection line 42 and the j_2th first voltage signal line VGH1(2), so that the voltage drop corresponding to the access of different shift registers to the first voltage is comparable, and the display uniformity can be improved.

[0159] In some embodiments, the line width of the j_1th first voltage signal line VGH1(1) is less than the line width of the j_2th first voltage signal line VGH1(2). For example, the j_1th first voltage signal line VGH1(1) and the j_2th first voltage signal line VGH1(2) are located in the same film layer, so that the materials of the two are the same, and the line width is smaller, so that the impedance per unit length is larger, so that the impedance of the j_1th first voltage signal line VGH1(1) per unit length is greater than the impedance of the j_2th first voltage signal line VGH1(2) per unit length.

[0160] Of course, the impedance of the j_1th first voltage signal line VGH1(1) per unit length can be greater than the impedance of the j_2th first voltage signal line VGH1(2) per unit length by other means, such as changing the thickness of the wire, changing the film layer of the wire, changing the length of the wire, etc., which are not limited in the present application.

[0161] In some embodiments, as shown in Figure 16 , the shift register accesses the clock signal CK, XCK, and the scan signal accessed by the gate of the data writing transistor of the pixel circuit is denoted as the second scan signal SP, wherein, Figure 16 , the second scan signal SP(2a-1) represents the scan signal accessed by the gate of the data writing transistor of the 2a-1th row of pixel circuits, and the second scan signal SP(2a) represents the scan signal accessed by the gate of the data writing transistor of the 2ath row of pixel circuits.

[0162] The transition time of the clock signal CK, XCK accessed by the shift register does not overlap with the period when the second scan signal SP is at an active level (for example, low level).

[0163] Figure 16 , CK', XCK', OUT' represent the signals before modification, and the transition time of the clock signal XCK' before modification overlaps with the period when the second scan signal SP(2a) is at an active level (low level), affecting the writing time of the data signal controlled by the second scan signal SP(2a).

[0164] In the present embodiment, the transition of the clock signal CK, XCK will not affect the writing time of the data signal, and the boundary line in the display picture can be reduced.

[0165] In some embodiments, the time interval between the start time of the active level of the second scan signal and the target transition time of the clock signal is greater than or equal to 1.2us, the target transition time is before the start time of the active level of the second scan signal, and among the multiple transition times of the clock signal, the target transition time is closest to the start time of the active level of the second scan signal.

[0166] Please refer to Figure 14 and Figure 16 , the input signal end IN of the shift register is at a high level, and the clock signal CK or XCK jumps from a high level to a low level, and the level transmission end Next and the output end out output a high level.

[0167] For example, when the input signal end IN of the first stage shift register is high and the clock signal XCK jumps from high to low, the stage transmission end Next and the output end out of the first stage shift register output high; when the input signal end IN of the second stage shift register is high and the clock signal CK jumps from high to low, the stage transmission end Next and the output end out of the second stage shift register output high; when the input signal end IN of the third stage shift register is high and the clock signal XCK jumps from high to low, the stage transmission end Next and the output end out of the third stage shift register output high. The jump of the clock signal CK and the clock signal XCK from high to low will cause a certain disturbance to the output signal of the shift register.

[0168] For example, taking the second scan signal SP(2a-1) as an example, the target jump time of the clock signal is one of the jump times of the clock signal XCK jumping from high to low, which is closest to the start time of the active level of the second scan signal SP(2a-1). The time interval between the jump time and the start time of the active level of the second scan signal SP(2a-1) is t3. The inventors have found through a large number of experimental studies that, in the case of t3≥1.2us, the influence of the jump of the clock signal on the data signal write time can be better avoided.

[0169] For example, the phase of the clock signal and the low level time length of the clock signal can be adjusted. For example, the modified clock signal CK and the modified clock signal XCK are advanced relative to the modified clock signal CK' and the modified clock signal XCK'. The low level width of the modified clock signal CK and the modified clock signal XCK is reduced relative to the low level width of the modified clock signal CK' and the modified clock signal XCK', so as to reduce or even avoid the influence of the jump of the clock signal on the write of the data signal.

[0170] The application also provides a display device comprising the display panel provided by the application. Please refer to Figure 17 , Figure 17 is a structural schematic diagram of a display device provided by an embodiment of the application. Figure 17 The display device 1000 provided by the application comprises the display panel 100 provided by any of the embodiments of the application. Figure 17 The embodiments are only described by taking a mobile phone as an example, and the display device 1000 can be a wearable product, a computer, a television, a vehicle-mounted display device or other display devices with a display function. The application does not specifically limit this. The display device provided by the embodiments of the application has the beneficial effects of the display panel provided by the embodiments of the application. For specific descriptions of the display panel, please refer to the specific descriptions of the display panel in the above embodiments, which will not be described herein.

[0171] In accordance with the embodiments of the application described above, these embodiments are not meant to be all-inclusive or limiting of the scope of the application. It will be apparent to those having skill in the art that many more modifications than those already described are possible. The present specification has been put forth with a full description for the purpose of enabling others skilled in the art to employ this application and modifications made by others skilled in the art based on the teachings herein. The application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized by, The display panel comprises a first gate drive circuit, a pixel circuit and a light emitting element, the pixel circuit is electrically connected with the light emitting element, the pixel circuit comprises a drive transistor, a data writing transistor and a compensation transistor, the data writing transistor is electrically connected with a data signal end and a first pole of the drive transistor, and the compensation transistor is electrically connected with a second pole and a gate pole of the drive transistor. The first gate drive circuit comprises a plurality of shift registers connected in cascade, the shift register comprises a stage transmission module and a gating module, the stage transmission module is electrically connected with the gating module, and an output end of the stage transmission module in the shift register of the wth stage is electrically connected with a trigger signal end of the shift register of the w+1th stage, the gating module comprises a first transistor, a first pole of the first transistor is electrically connected with a first voltage signal line, and a second pole of the first transistor is electrically connected with a gate pole of the compensation transistor. The display panel comprises at least two first voltage signal lines, the shift register of the ith stage and the shift register of the i+1th stage are electrically connected with different first voltage signal lines, i >= 1, and the effective voltage output by the shift register comprises the voltage on the first voltage signal line.

2. The display panel of claim 1, wherein, The number of the first voltage signal lines is j, j >= 2. The first gate drive circuit comprises a plurality of shift circuit groups, the shift circuit group comprises j shift registers connected in cascade, and the j shift registers in the shift circuit group are electrically connected with j first voltage signal lines in a one-to-one manner.

3. The display panel of claim 2, wherein, The shift registers with the same order in different shift circuit groups are electrically connected with the same first voltage signal line.

4. The display panel of claim 3, wherein, The effective level of the first scanning signal output by the output end of the plurality of shift registers progresses by k*H, and the time length of the effective level of the first scanning signal is m*H, j <= m / k; wherein H is the scanning time length of a row of pixel circuits.

5. The display panel of claim 4, wherein, j = m / k.

6. The display panel of claim 4, wherein, m = (2+4*N)*H, N >= 1.

7. The display panel of claim 4, wherein, k≥2。 8. The display panel of claim 4, wherein, 2 < j < m / k, the effective level of the first scanning signal output by the output end of the plurality of shift registers progresses by k*H, and H is the scanning time length of a row of pixel circuits. The first scanning signal input by the gate pole of the compensation transistor in the pixel circuit of the 2a-1th row is S2N(a), and the second scanning signal input by the gate pole of the data writing transistor in the pixel circuit of the 2a-1th row is SP(2a-1). The starting time of the effective level of the second scanning signal SP(2a-1) is separated from the starting time of the effective level of the first scanning signal S2N(a) by a time length L, L >= [2*j*(b-1)+1]*H, and b is greater than or equal to 1.

9. The display panel of claim 2, wherein, j＝2。 10. The display panel of claim 9, wherein, The shift registers of odd stages are connected with the first first voltage signal line, and the shift registers of even stages are connected with the second first voltage signal line.

11. The display panel of claim 9, wherein, The effective level of the first scanning signal output by the output end of the plurality of shift registers progresses by k*H, and H is the scanning time length of a row of pixel circuits. The first scan signal inputted to the gate of the compensation transistor in the pixel circuit in the 2a-1th row is S2N(a), and the second scan signal inputted to the gate of the data write transistor in the pixel circuit in the 2a-1th row is SP(2a-1). The start time of the active level of the second scan signal SP(2a-1) is separated from the start time of the active level of the first scan signal S2N(a) by a time interval t1, t1≥(4*N+0.5)*H, or t1≥4*N*H+0.5us, N≥0, and N is an integer.

12. The display panel of claim 11, wherein, The first scan signal inputted to the gate of the compensation transistor in the pixel circuit in the 2a-1th row is S2N(a), and the second scan signal inputted to the gate of the data write transistor in the pixel circuit in the 2a-1th row is SP(2a-1), The end time of the active level of the second scan signal SP(2a) is separated from the start time of the active level of the first scan signal S2N(a) by a time interval t2, t2<(4*N+4)*H.

13. The display panel of claim 12, wherein, The end time of the active level of the second scan signal SP(2a-1) is separated from the start time of the active level of the second scan signal SP(2a) by a time interval greater than 0.

14. The display panel of claim 1, wherein, The shift register further comprises a second transistor, and the second transistor and the first transistor in the same shift register are electrically connected to the same first voltage signal line.

15. The display panel of claim 1, wherein, The shift register further comprises a second transistor, and the second transistor is electrically connected to a second voltage signal line.

16. The display panel of claim 15, wherein, The second transistor in the i-th shift register and the second transistor in the i+1-th shift register are electrically connected to the same second voltage signal line.

17. The display panel of claim 15, wherein, The second transistor in the i-th shift register and the second transistor in the i+1-th shift register are electrically connected to different second voltage signal lines.

18. The display panel of claim 1, wherein, The display panel at least comprises a first connection line and a second connection line, the first connection line is electrically connected to the j_1th first voltage signal line and the shift register, the second connection line is electrically connected to the j_2th first voltage signal line and the shift register, and the first connection line and the second connection line are electrically connected to different shift registers. The length of the first connection line is less than the length of the second connection line, and the impedance per unit length of the j_1th first voltage signal line is greater than the impedance per unit length of the j_2th first voltage signal line.

19. The display panel of claim 18, wherein, The line width of the j_1th first voltage signal line is less than the line width of the j_2th first voltage signal line.

20. The display panel of claim 1, wherein, The voltages of different signal terminals electrically connected to different first voltage signal lines are the same.

21. The display panel of claim 1, wherein, The shift register inputs a clock signal, and the gate of the data write transistor of the pixel circuit inputs a second scan signal. The transition time of the clock signal does not overlap with the period in which the second scan signal is in an active level.

22. The display panel of claim 21, wherein A time interval between a starting moment of an effective level of the second scan signal and a target transition moment of the clock signal is greater than or equal to 1.2us, the target transition moment is a transition moment of the clock signal from a high level to a low level, the target transition moment is before the starting moment of the effective level of the second scan signal, and among a plurality of transition moments of the clock signal, the target transition moment is closest to the starting moment of the effective level of the second scan signal.

23. A display device comprising: Comprising: The display panel of any one of claims 1 to 22.

Images