Display device

Abstract

The embodiment of the invention provides a display device, which comprises a gate drive circuit, a data drive circuit, a power supply circuit, a plurality of sub-pixels and corresponding sub-pixel drive circuits, in the sub-pixel drive circuits, a storage unit stores first drive data transmitted by a data write-in unit, the adjustable driving unit is provided with a reference driving transistor, at least one compensation driving transistor and a corresponding adjusting unit, and the size compensation state of the compensation driving transistor to the reference driving transistor is regulated and controlled by controlling the on-off state of the adjusting unit. Therefore, the size of an equivalent driving transistor constructed by a compensation driving transistor for compensation and a reference driving transistor is adjusted, the equivalent driving transistors with different sizes can process driving data in different data ranges, different driving signals are generated, different light-emitting requirements of sub-pixels are met, and the light-emitting efficiency of the sub-pixels is improved. The driving function of a plurality of sub-pixel driving circuits is replaced, and the total occupied area of the driving circuit for driving the sub-pixels is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a display device. BACKGROUND

[0002] In recent years, due to the advantages of smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer service life, the display application field based on micro-LED has been rapidly developed, and has become a research hotspot of display devices.

[0003] The display panel has a plurality of pixel units arranged in an array, the pixel unit includes a sub-pixel and a corresponding sub-pixel driving circuit, and the sub-pixel emits light based on a driving signal generated by the corresponding sub-pixel driving circuit. The sub-pixel driving circuit includes a driving transistor, and due to the characteristics of the driving transistor, different transistors can process driving data, and the generated driving signals are different.

[0004] In the related art, at least two sub-pixel circuits are provided in the pixel unit, and the sizes of the driving transistors in each sub-pixel circuit are different to meet the requirements of different data processing and / or driving signal generation, but there is a problem of large occupied area of the pixel unit. Therefore, how to reduce the occupied area of the pixel unit has become a research focus. SUMMARY

[0005] The present application provides a display device to solve the technical problem of reducing the occupied area of the pixel unit.

[0006] The present application provides a display device, comprising:

[0007] a gate driving circuit, a data driving circuit, a power supply circuit, a plurality of sub-pixels and corresponding sub-pixel driving circuits;

[0008] The sub-pixel driving circuit comprises:

[0009] a data writing unit, and the data driving circuit and the gate driving circuit are electrically connected, and configured to obtain first driving data and a scanning signal, and to output the first driving data controlled by the scanning signal;

[0010] a storage unit, and the data writing unit is electrically connected, and configured to store the first driving data;

[0011] an adjustable driving unit, comprising at least two driving transistors and at least one adjusting unit;

[0012] The control end of the driving transistor is electrically connected with the storage unit, the first end of the first driving transistor is coupled with the power supply circuit, the first end of the non-first driving transistor is electrically connected with the second end of the previous-stage driving transistor, and the second end of the last driving transistor is electrically connected with the sub-pixel;

[0013] The at least two driving transistors include a reference driving transistor and at least one compensation driving transistor, and the at least one compensation driving transistor is electrically connected with the at least one adjusting unit in correspondence;

[0014] The adjusting unit is configured to obtain a first electrical signal corresponding thereto, control its conduction state by the first electrical signal, and turn off the compensation driving transistor corresponding thereto when it is in conduction;

[0015] The reference driving transistor and the compensation driving transistor corresponding to the adjusting unit in the off state constitute an equivalent driving transistor, the equivalent driving transistor is electrically connected with the power supply circuit, is configured to obtain a power supply signal and the first driving data, and outputs a driving signal;

[0016] The sub-pixel is configured to emit light based on the driving signal.

[0017] In the above technical solution, the reference driving transistor, the at least one compensation driving transistor and the corresponding adjusting unit are arranged in the sub-pixel driving circuit, the on-off state of the adjusting unit is controlled to adjust the size compensation state of the compensation driving transistor to the reference driving transistor, so as to adjust the size of the equivalent driving transistor constructed by the compensation driving transistor and the reference driving transistor, the equivalent driving transistor with different sizes can process driving data in different data ranges to generate different driving signals to meet the different light emitting requirements of the sub-pixel, and the driving function of the multiple sub-pixel driving circuits is replaced, and the total occupied area of the driving circuit for driving the sub-pixel is reduced.

[0018] In a feasible implementation, the output end of the data writing unit is electrically connected with the first end of the first driving transistor, and is configured to transmit the first driving data to the first end of the first driving transistor when it is in conduction;

[0019] The adjustable driving unit further includes a compensation transistor, the first end of the compensation transistor is electrically connected with the control end of the driving transistor, the second end of the compensation transistor is electrically connected with the second end of the last driving transistor, the control end of the compensation transistor is electrically connected with the gate driving circuit, and is configured to obtain the scanning signal from the control end thereof and control its conduction state by the scanning signal;

[0020] When the adjustable driving unit is turned on, a threshold compensation structure is formed with the equivalent driving transistor, and when the equivalent driving transistor is turned off, the first driving data for threshold voltage compensation of the equivalent driving transistor is determined at the control end of the equivalent driving transistor.

[0021] In the above technical solution, the compensation transistor is arranged in the adjustable driving unit, and after the reference driving transistor and the compensation driving transistor for compensation form the equivalent driving transistor, in the writing process of the first driving data, the compensation transistor is controlled to be turned on, and a threshold compensation structure is formed with the equivalent driving transistor to compensate the threshold voltage of the first driving data, and when the equivalent driving transistor generates the driving signal based on the first driving data, the influence of the threshold voltage drift on the accuracy of the driving signal is avoided.

[0022] In the display device provided by the embodiment of the application, the display device includes a gate driving circuit, a data driving circuit, a power supply circuit, a plurality of sub-pixels, and corresponding sub-pixel driving circuits. In the sub-pixel driving circuit, a storage unit stores first driving data transmitted by a data writing unit, and an adjustable driving unit is provided with a reference driving transistor, at least one compensation driving transistor, and a corresponding adjustment unit. By controlling the on and off states of the adjustment unit, the compensation state of the compensation driving transistor to the reference driving transistor is adjusted, so that the size of the equivalent driving transistor formed by the compensation driving transistor for compensation and the reference driving transistor is adjusted. Different sizes of equivalent driving transistors can process driving data in different data ranges to generate different driving signals to meet the different light-emitting needs of sub-pixels, thereby replacing the driving functions of a plurality of sub-pixel driving circuits and reducing the total occupied area of the driving circuits for driving sub-pixels. BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings, which are incorporated into and form a part of the specification, illustrate one embodiment consistent with the present application and, together with the description, serve to explain the principles of the application.

[0024] Figure 1 A structural schematic diagram of a display provided by the application according to an exemplary embodiment;

[0025] Figure 2 A structural schematic diagram of a display provided by the application according to another exemplary embodiment;

[0026] Figure 3 A circuit structure diagram of a conventional pixel driving circuit provided by the application according to an exemplary embodiment;

[0027] Figure 4A A structural schematic diagram of a pixel driving circuit provided by the application according to an exemplary embodiment;

[0028] Figure 4BA structural schematic diagram of a pixel driving circuit according to an exemplary embodiment of the present application;

[0029] Figure 5 A structural schematic diagram of a pixel driving circuit according to an exemplary embodiment of the present application;

[0030] Figure 6 A driving signal timing diagram of a pixel driving circuit according to an exemplary embodiment of the present application;

[0031] Figures 7A to 7D A running state diagram of a pixel driving circuit according to an exemplary embodiment of the present application;

[0032] Figure 8 A structural schematic diagram of a pixel driving circuit according to another exemplary embodiment of the present application;

[0033] Figure 9 A structural schematic diagram of a pixel driving circuit according to another exemplary embodiment of the present application;

[0034] Figure 10 A driving signal timing diagram of a pixel driving circuit according to another exemplary embodiment of the present application;

[0035] Figures 11A to 11F A running state diagram of a pixel driving circuit according to an exemplary embodiment of the present application.

[0036] The specific embodiments of the present application have been shown by way of example in the above figures, and will be described in more detail hereafter. These figures and the written description together serve to fully disclose the application to those skilled in the art, and are not intended to limit the scope of the application in any way. DETAILED DESCRIPTION

[0037] The exemplary embodiments will be described in detail herein below with reference to the drawings. In the following description, like reference numerals refer to like elements throughout the description. The following exemplary embodiments are not intended to represent all embodiments in accordance with the present application. Rather, they are merely examples in accordance with some aspects of the present application as detailed in the appended claims.

[0038] It should be noted that, in this document, the terms "comprise", "comprising", or any other variant thereof are intended to cover a non-exclusive inclusion, such that processes, methods, articles, or apparatuses that comprise a list of elements are not required to only those elements, but can also include other elements not expressly listed or inherent to such processes, methods, articles, or apparatuses. Without further limitation, an element defined by an "comprising" statement is not excluded from a process, method, article, or apparatus that includes the element, in addition, components, features, elements, etc. having the same name in different embodiments of the application can have the same or different meanings, which are determined by their interpretation in the context of the particular embodiment. It should be further understood that the terms "comprise", "comprising", indicate the presence of the stated features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups.

[0039] In the description of the present disclosure, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise specifically limited. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0040] It should be understood that the specific embodiments described herein are only used to explain the present application, and are not intended to limit the present application.

[0041] In recent years, due to the advantages of smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer service life of micro-LED than AMOLED (Active-matrix organic light emitting diode), the display application field based on micro-LED has been rapidly developed, and has become a research hotspot of display devices.

[0042] The structural schematic diagram of the display device is as follows Figure 1 and Figure 2As shown, the system includes a control circuit 250, a data drive circuit 20, a gate drive circuit 30, a display panel 40, and a power supply circuit 280. The control circuit 250 and the data drive circuit 20 are electrically connected, as are the gate drive circuit 30 and the display panel 40.

[0043] The display panel has a power line 90, multiple gate lines 60, multiple data lines 50 and multiple pixel units 80. The multiple pixel units 80 are arranged in an array, and each pixel unit 80 is located in the area where the gate line 60 and the data line 50 intersect.

[0044] The gate driving circuit 30 is electrically connected to the gate line 60. The gate driving circuit 30 is configured to obtain clock signals and trigger signals from the control circuit 250, generate gate driving signals according to the clock signals and trigger signals, and transmit the gate driving signals to the corresponding pixel unit 80 through the gate line 60 to control the transistors in the pixel unit 80 to be turned on or off.

[0045] More specifically, the gate driving circuit 30 can be fabricated as a separate gate driver integrated circuit (GDIC). Alternatively, the gate driving circuit 30 can be integrated into the display panel; this integration is called gate-in-panel (GIP). In some cases, the GDIC can be electrically connected to the display panel 40 via a COG (Chip on Glass) process, or via a COF (Chipon Film) process. In the COF process, the component is electrically connected to the display panel 40 via a flexible printed circuit (FPC).

[0046] The data driving circuit 20 is a circuit that drives the data line 50. It is configured to acquire display data from the control circuit 250 and convert it into an analog data voltage (Vdata). This analog data voltage is transmitted through the data line 50 to the corresponding pixel unit 80, so that the sub-pixel 813 in the pixel unit 80 emits light according to the analog data voltage. The magnitude of the analog data voltage determines the luminous brightness of the sub-pixel 813.

[0047] The data driving circuit 20 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter, and output buffer, etc.

[0048] The power supply circuit 280 is a circuit that provides stable electrical signals and is configured to provide the corresponding power signals to the display panel 40, control circuit 250, data drive circuit 20 and gate drive circuit 30.

[0049] In one configuration, each pixel unit 80 includes three sub-pixel circuits 810, used to display red light, blue light, and green light respectively. In another configuration, each pixel unit 80 includes four sub-pixel circuits 810, used to display red light, blue light, green light, and white light respectively. No specific limitation is made here.

[0050] The emission color of each sub-pixel unit 810 is determined by the properties of its sub-pixel 813. The sub-pixel 813 can be any light-emitting device, including but not limited to OLED and micro LED.

[0051] A micro LED is a miniature light-emitting device manufactured using inorganic semiconductor layers. A micro LED typically includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The structure of such micro LEDs can be diverse, including vertical, horizontal, and flip-chip types, and is not particularly limited to a specific structure.

[0052] More specifically, a sub-pixel circuit 810 includes a sub-pixel driving circuit 814 and a sub-pixel 813. The sub-pixel driving circuit 814 is electrically connected to the sub-pixel 813 and is configured to drive the sub-pixel 813 to emit light. The signals required by the sub-pixel driving circuit 814 include a driving signal, a scan signal, and an emission control signal (EM control signal).

[0053] The driving signal can be generated by the control circuit 250 or obtained from an external source. This includes, but is not limited to, a start pulse signal, a clock signal, and an enable signal. The light emission control signal can be a global signal provided by the control circuit 250 or a signal generated by the gate driving circuit 30; no specific limitation is made here. The scanning signal is a successive displacement signal generated by the gate driving circuit 30.

[0054] If the EM control signal is a global signal generated by the control circuit 250, the gate drive circuit 30 obtains the EM control signal from the control circuit 250 and transmits the EM control signal to the corresponding pixel drive circuit 814 through the gate line 60.

[0055] If both the EM control signal and the scan signal are generated by the gate drive circuit 30, the gate drive circuit 30 includes a scan signal generation circuit 301 and an EM control signal generation circuit 302. The scan signal is output by the scan signal generation circuit 301, and the EM control signal is output by the EM control signal generation circuit 302.

[0056] Figure 3 This is a circuit structure diagram of a conventional pixel driving circuit provided in accordance with an exemplary embodiment of this application.

[0057] A conventional pixel driving circuit includes at least two driving sub-circuits. Each driving sub-circuit is configured to process driving data within different data ranges, generate corresponding driving signals, and drive the corresponding sub-pixel LED of the conventional pixel driving circuit to emit light. The data ranges corresponding to different driving sub-circuits do not overlap.

[0058] In some embodiments, the data range is not divided according to the grayscale range of the grayscale value corresponding to the driving data;

[0059] In other embodiments, different data ranges are divided according to the current range in which the current value in the generated drive signal is located.

[0060] The following explanation uses a traditional pixel driving circuit, comprising two driving sub-circuits and where each sub-circuit uses P-type transistors, as an example to illustrate the circuit connections and operation of a traditional pixel driving circuit. The two driving sub-circuits respectively process high-grayscale driving data and low-grayscale driving data.

[0061] like Figure 3 As shown, a conventional pixel driving circuit includes a first driving sub-circuit, which includes a first write transistor M01, a first capacitor C1, and a first driving transistor M02.

[0062] The first write transistor M01 turns on when it receives a low level first scan signal Gate1, and outputs the first drive data Vdata1 obtained from its first terminal from its second terminal. The first drive data Vdata1 is low grayscale drive data within a first preset data range.

[0063] The second terminal of the first capacitor C1 is electrically connected to the second terminal of the first write transistor M01, and is configured to obtain and store the voltage value corresponding to the first drive data Vdata1 from its second terminal.

[0064] The control terminal of the first driving transistor M02 is electrically connected to the first terminal of the first capacitor C1, and the first terminal is electrically connected to the power line 90. It is configured to obtain a power signal VDD from its first terminal, obtain first driving data Vdata1 from its control terminal, and generate a first driving signal based on the first driving data Vdata1 and the power signal VDD.

[0065] Among them, the first driving tube M02 can normally expand all low grayscale driving data within the first preset data range, and there will be no situation where low grayscale cannot be expanded and affect the display effect.

[0066] The anode of the sub-pixel LED is electrically connected to the second terminal of the first driving transistor M02, and is configured to receive a first driving signal and emit light based on the first driving signal.

[0067] Continue to refer to Figure 3 The traditional pixel driving circuit also includes a second driving sub-circuit, which further includes a second write transistor M11, a third capacitor C11, and a second driving transistor M12.

[0068] The second write transistor M11 turns on when it receives the second scan signal Gate2 as low, and outputs the third drive data Vdata3 obtained from its second terminal. The third drive data Vdata3 is high-grayscale drive data that is not within the first preset data range.

[0069] The second terminal of the third capacitor C11 is electrically connected to the second terminal of the second write transistor M11, and is configured to obtain and store the voltage value corresponding to the third drive data Vdata3 from its second terminal.

[0070] The control terminal of the second driving transistor M12 is electrically connected to the second terminal of the second capacitor C2, and the second terminal is electrically connected to the power line 90. It is configured to obtain the power signal VDD from its second terminal and the third driving data Vdata3 from its control terminal, and generate the second driving signal based on the third driving data Vdata3 and the power signal VDD.

[0071] The size of the second driving transistor M12, for example, its aspect ratio, is greater than that of the first driving transistor M02, so that the second driving transistor M12 can generate a larger driving current value, thereby enabling the sub-pixel LED to generate brightness corresponding to high grayscale driving data.

[0072] The anode of the sub-pixel LED is electrically connected to the second terminal of the second driving transistor M12, and is configured to receive a second driving signal and emit light based on the second driving signal.

[0073] However, with the development of technology, the demand for higher resolution of display devices is gradually increasing, which requires reducing the pixel size. How to reduce the size of each pixel circuit while ensuring the grayscale processing and current generation has become the focus of research.

[0074] To address the aforementioned problems, this application provides a display device to solve the technical issues described above. The technical concept of this application is as follows: In a sub-pixel driving circuit, at least two driving transistors are connected in series, with their control terminals electrically connected to a single point. At least one driving transistor is controlled to conduct, forming an equivalent driving transistor of a preset size. This transistor processes driving data within a corresponding data range, satisfying different brightness requirements of the sub-pixels. Since the total area occupied by these multiple driving transistors does not exceed the size of a large-size driving transistor in a traditional pixel driving circuit, the size of the sub-pixel driving circuit is reduced, thereby reducing the area occupied by the pixel unit.

[0075] The following is based on Figure 4A and Figure 4B Using the schematic diagram of the sub-pixel driving circuit shown as an example, the pixel driving circuit proposed in this application will be explained in detail. In this sub-pixel driving circuit, each transistor is a P-type transistor.

[0076] In some embodiments, the sub-pixel driving circuit includes a data writing unit 803, which is electrically connected to the gate line 60 and the data line 50, and is configured to obtain first driving data Vdata1 and a scan signal Gate, and the scan signal Gate controls its output of the first driving data Vdata1.

[0077] In some embodiments, the sub-pixel driving circuit includes a storage unit 805 and a data writing unit 803 electrically connected, configured to store first driving data Vdata1.

[0078] In some embodiments, the sub-pixel driving circuit includes an adjustable driving unit 804, and is electrically connected to a power line 90, a storage unit 805, and a data line 50. The adjustable driving unit 804 includes at least two driving transistors and at least one adjustment unit 8041.

[0079] The control terminal of the driving transistor is electrically connected to the storage unit, the first terminal of the first driving transistor is coupled to the power supply circuit, the first terminal of the non-first driving transistor is electrically connected to the second terminal of the preceding driving transistor, and the second terminal of the last driving transistor is electrically connected to the sub-pixel LED.

[0080] The at least two driving transistors include a reference driving transistor M2 and at least one compensation driving transistor Mn21 to Mn2m, and the at least one compensation driving transistor Mn21 to Mn2m and at least one adjustment unit 8041 are electrically connected accordingly.

[0081] In some embodiments, the reference driving transistor M2 is the first driving transistor, and the circuit structure of the adjustable driving unit 804 is as follows: Figure 4AAs shown. The first terminal of the reference driving transistor M2 is electrically connected to the power supply line 90. The first terminal of the first compensation driving transistor is electrically connected to the second terminal of the reference driving transistor M2. The compensation driving transistors are connected in series one after another until the second terminal of the last compensation driving transistor is electrically connected to the sub-pixel LED.

[0082] In other embodiments, the reference driving transistor M2 is a non-first-order driving transistor, and the circuit structure of the adjustable driving unit 804 is as follows: Figure 4B As shown. The first terminal of the first compensation driving transistor is electrically connected to the power supply line 90. The remaining driving transistors are connected in series in a preset order. The reference driving transistor M2 can be connected in series between the two compensation driving transistors, or it can be connected in series between the last compensation driving transistor and the sub-pixel.

[0083] The position of the reference driving transistor M2 can be arranged according to the arrangement requirements of each device in the sub-pixel driving circuit. For example, the reference driving transistor can be placed in the middle of the arrangement of multiple compensation driving transistors so that the compensation driving transistors connected in front and behind can be arranged in two columns. The adjustment unit 8041 corresponding to the compensation driving transistor is set on the outside of the two columns. The reference driving transistor is set at the beginning or end of the two columns of compensation driving transistors to increase the compactness of the sub-pixel driving circuit.

[0084] The position of the reference driving transistor M2 can also be arranged according to the size of each driving transistor in the sub-pixel driving circuit, so that the area occupied by each driving transistor is as regular as possible.

[0085] The adjustment unit 8041 is configured to obtain its corresponding first electrical signal, and control its conduction state by the first electrical signal. When it is on, it turns off its corresponding compensation drive transistor.

[0086] In some embodiments, the input terminal of the adjustment unit 8041 is electrically connected to the first terminal of its corresponding compensation driving transistor, and its output terminal is electrically connected to the second terminal of its corresponding compensation driving transistor.

[0087] The adjustment unit 8041 is also configured to, when it corresponds to the first driving transistor, turn off the corresponding driving transistor and transmit the power signal obtained at its first terminal to the driving transistor electrically connected to its second terminal.

[0088] When it corresponds to a non-first driving transistor, the electrical signal output by the driving transistor or adjustment unit 8041 connected to its first terminal is transmitted to the driving transistor or sub-pixel LED connected to its second terminal to ensure the continuity of electrical signal transmission in the adjustable driving unit 804.

[0089] The first electrical signal may be an electrical signal generated by the data driving circuit 20 or the gate driving circuit 30 based on the first driving data Vdata1.

[0090] The reference driving transistor M2 and the compensation driving transistor corresponding to the adjustment unit 8041 in the off state form an equivalent driving transistor. The first terminal of the equivalent driving transistor is the first terminal of the first driving transistor, the second terminal is the second terminal of the last driving transistor, and the control terminal is the control terminal of each driving transistor.

[0091] The equivalent drive transistor is electrically connected to the power supply line 90 and is configured to obtain the power supply signal VDD and the first drive data Vdata1, and output the drive signal.

[0092] In some embodiments, the drive signal includes a drive current value.

[0093] The magnitude of the drive current is related to the aspect ratio of the equivalent drive transistor, and the specific relationship is as follows:

[0094]

[0095] Where I represents the driving current value, μ represents the electron mobility in the equivalent driving transistor, Cox represents the capacitance of the gate oxide layer in the equivalent driving transistor, W represents the width of the equivalent driving transistor, L represents the length of the equivalent driving transistor, Vgs represents the voltage difference between the control terminal and the first terminal of the equivalent driving transistor, and Vth represents the threshold voltage of the equivalent driving transistor.

[0096] The aspect ratio of the equivalent driving transistor is greater than or equal to that of the reference driving transistor;

[0097] The length of the equivalent driving transistor is the sum of the equivalent length of the reference driving transistor and the equivalent length of the compensation driving transistor corresponding to the adjustment unit in the off state.

[0098] The equivalent length of the driving transistor is the product of the actual length of the driving transistor and the equivalent ratio, and the equivalent ratio is the ratio of the target width of the equivalent driving transistor to the actual width of the driving transistor.

[0099] Taking the equivalent compensation driving transistor, which includes a reference driving transistor M2 and a compensation driving transistor, as an example, the size relationship of the three types of driving transistors is explained.

[0100] Assuming the aspect ratio of the reference driving transistor M2 is L1 / W1, the aspect ratio of the compensation driving transistor is L3 / W1, and the aspect ratio of the compensated equivalent driving transistor is L2 / W2, then the condition that the above three transistors need to satisfy is (L3+L1) / W1=L2 / W2, then L3=(W1*L2) / W2-L1, and this length is the equivalent length of the compensation driving transistor compared to the equivalent driving transistor.

[0101] In some embodiments, if the width of the compensation driving transistor is the same as the width of the reference driving transistor, then when calculating the length of the equivalent driving transistor, the equivalent ratios of each driving transistor are the same.

[0102] In some embodiments, the width of the equivalent driving transistor is the same as the width of the reference driving transistor M2, and the equivalent ratio is 1. Then the length of the compensation driving transistor is the difference between the length of the equivalent driving transistor and the length of the reference driving transistor M2.

[0103] The sub-pixel LEDs are configured to emit light based on a driving signal.

[0104] Among them, the brightness of the sub-pixel LED is positively correlated with the driving current value.

[0105] In the above technical solution, the sub-pixel driving circuit is provided with a reference driving transistor, at least one compensation driving transistor, and a corresponding adjustment unit. By controlling the on and off states of the adjustment unit, the size compensation state of the compensation driving transistor on the reference driving transistor is adjusted, thereby adjusting the size of the equivalent driving transistor constructed by the compensation driving transistor and the reference driving transistor. Equivalent driving transistors of different sizes can process driving data in different data ranges and generate different driving signals to meet the different light emission requirements of the sub-pixel, replacing the driving function of multiple sub-pixel driving circuits and reducing the total area occupied by the driving circuit for driving the sub-pixel.

[0106] The following is based on Figure 5 Using the schematic diagram of the sub-pixel driving circuit shown as an example, the circuit structure of the pixel driving circuit proposed in this application will be explained in detail.

[0107] The data writing unit 803 includes a data writing transistor M1. The first terminal of the data writing transistor M1 is electrically connected to the data line 50, and the control terminal is electrically connected to the gate line 60. It is configured to obtain a scan signal Gate from its control terminal and control its conduction state by the scan signal Gate.

[0108] The data writing transistor M1 is turned on when the scan signal Gate is low, and outputs the first driving data Vdata1 obtained from the first terminal from its second terminal; it is turned off when the scan signal Gate is high, and stops the transmission of the first driving data Vdata1.

[0109] The storage unit 805 includes a first capacitor C1. A first terminal of the first capacitor C1 is electrically connected to a power supply line 90, and a second terminal is electrically connected to the second terminal of a data write transistor M1. It is configured to obtain a stable power supply signal VDD from its first terminal, obtain first drive data Vdata1 from its second terminal, and store the first drive data Vdata1 at its second terminal. The voltage value at the second terminal of the first capacitor C1 is the same as the voltage value corresponding to the first drive data Vdata1.

[0110] The adjustable drive unit 804 includes a reference drive transistor M2, at least one compensation drive transistor, and a corresponding adjustment unit 8041. The circuit connection relationship between the reference drive transistor M2 and the at least one compensation drive transistor has been explained in the foregoing embodiments and will not be repeated here.

[0111] The adjustment unit includes an adjustment transistor, a first terminal of which is electrically connected to the first terminal of a corresponding compensation drive transistor, a second terminal of which is electrically connected to the second terminal of a corresponding compensation drive transistor, and a control terminal of which is electrically connected to a data drive circuit. It is configured to obtain a first electrical signal from its control terminal, the first electrical signal including second drive data Vdata2.

[0112] Its conduction state is controlled by the second driving data.

[0113] The regulating transistor is turned on when the second driving data is in a low-level state, shorting the first and second terminals of the corresponding compensation driving transistor.

[0114] It is turned off when the second drive data is in a high-level state.

[0115] When the first driving data is within the preset data range corresponding to the adjustment unit, the second driving data is in a low-level state.

[0116] When the first driving data is not within the preset data range corresponding to the adjustment unit, the second driving data is in a high-level state.

[0117] In some embodiments, the adjustable drive unit 804 has only one regulating transistor turned off in each display cycle, while the other transistors are turned on. Then, only the compensation drive transistor corresponding to the turned-off regulating transistor compensates for the size of the reference drive transistor to construct an equivalent drive transistor.

[0118] In other embodiments, the adjustable drive unit 804 may have multiple adjustable transistors turned off simultaneously in each display cycle. The compensation drive transistors corresponding to the multiple turned-off adjustable transistors jointly compensate for the size of the reference drive transistor to construct an equivalent drive transistor.

[0119] When the number of the compensation driving transistor and its corresponding adjustment transistor is one, the control circuit 250 compares the grayscale value corresponding to the first driving data Vdata1 with a preset threshold. When the first driving data Vdata1 is greater than the preset threshold, the control data driving circuit 20 outputs the second driving data Vdata2 in a high-level state; when the first driving data Vdata1 is less than or equal to the preset threshold, the control data driving circuit 20 outputs the second driving data Vdata2 in a low-level state.

[0120] When the number of compensation drive data and its corresponding adjustment transistors is at least two, the number of second drive data Vdata2 is multiple, and the number of second drive data Vdata2 is the same as the number of equivalent drive transistors composed of at least one compensation drive transistor and a reference drive transistor M2.

[0121] Within the data range corresponding to the equivalent driving transistor, the second driving data Vdata2 obtained by the corresponding compensation driving transistor is in a low-level state, while the second driving data Vdata2 obtained by other compensation driving transistors is in a high-level state.

[0122] Taking the adjustable drive unit 804, which includes two adjustment units as an example, the equivalent drive transistor composed of the reference drive transistor M2 and the first compensation drive transistor corresponds to the first preset data range, the equivalent drive transistor composed of the reference drive transistor M2 and the second compensation drive transistor corresponds to the second preset data range, and the equivalent drive transistor composed of the reference drive transistor M2, the first compensation drive transistor, and the second compensation drive transistor corresponds to the third preset data range.

[0123] When the first driving data Vdata1 obtained by the first compensation driving transistor is within the first preset data range and the third preset data range, the second driving data Vdata2 obtained by the first compensation driving transistor is in a low level state; when the first driving data Vdata1 obtained by the adjustable driving unit is within the first preset data range and the third preset data range, the second driving data Vdata2 obtained in other data ranges is in a high level state.

[0124] The second compensation driving transistor obtains a second driving data Vdata2 at a low level when the first driving data Vdata1 obtained by the adjustable driving unit is within the second preset data range and the third preset data range, and at a high level when the second driving data Vdata2 obtained in other data ranges.

[0125] The control circuit 250 compares the first driving data Vdata1 with each preset data range. When the first driving data Vdata1 is within the corresponding preset data range, the control data driving circuit 20 generates the second driving data in a low-level state.

[0126] When the first driving data Vdata1 is not within the corresponding preset data range, the control circuit 250 controls the data driving circuit 20 to generate the second driving data Vdata2, which is in a high-level state.

[0127] When the adjustable drive unit 804 includes at least two adjustment units, the control circuit 250 compares the first drive data Vdata1 with the preset data range corresponding to each realizable equivalent drive transistor. When the first preset data Vdata1 is within the target preset data range corresponding to the target equivalent drive transistor, the control data drive data 20 generates at least one second target drive data in a low-level state and other second drive data in a high-level state, so that the adjustment transistor corresponding to the target preset data range is turned off and the adjustment transistors in other adjustment units are turned on.

[0128] When the regulating transistor is in a low-level state, the first and second terminals of its corresponding compensation driving transistor are shorted to control the compensation driving transistor not to perform aspect ratio compensation on the reference driving transistor M2. The device electrically connected to the first terminal and the device electrically connected to the second terminal are electrically connected to keep the circuit conducting.

[0129] The regulating transistor is turned off when the second driving data Vdata2 is high, so as to control its corresponding compensation driving transistor to perform aspect ratio compensation on the reference driving transistor M2. In the above technical solution, by adjusting the short-circuit state of the compensation driving transistor, the size of the equivalent driving transistor of the adjustable driving unit is adjusted. Using a small number of transistors, the adjustable driving unit can process driving data corresponding to gray level values ​​in different gray level ranges, ensuring that the regulating driving unit can be normally deployed for low gray levels and providing a device basis for generating large currents for high gray levels.

[0130] Figure 5 The circuit structure shown is composed of Figure 6 The driving signal timing diagram shown is used for driving.

[0131] The following is combined Figures 7A to 7D The process diagram shown takes a sub-pixel driving circuit that includes two regulating transistors as an example. Figure 5 The circuit structure shown is explained in terms of its operation over two adjacent display cycles. Each display cycle includes a data writing phase and a display phase, respectively.

[0132] During the interval S preceding the first display cycle T1, the level of the first driving data Vdata1 is the first level. This first driving data Vdata1 is the driving data corresponding to a lower grayscale value, or the driving data corresponding to a lower driving current value.

[0133] The control circuit 250 controls the data driving circuit 20 to generate the second driving data Vdata21 in a low-level state according to the first driving data Vdata1 and the preset data range corresponding to the first regulating transistor Mf21.

[0134] The control circuit 250 controls the data driving circuit 20 to generate second driving data Vdata2m in a low-level state based on the first grayscale value and the preset data range corresponding to the second adjustment transistor Mf2m.

[0135] During the data writing phase t11 of the first display cycle T1, the scan signal Gate is at a low level.

[0136] The data writing transistor M1 is turned on according to the scan signal Gate, and the first driving data Vdata1 obtained at its first terminal is transmitted to the second terminal of the first capacitor C1.

[0137] The first capacitor C1 stores the first driving data Vdata1 at its second terminal, and the voltage value at the second terminal is the voltage value corresponding to the first driving data Vdata1.

[0138] In the first adjustment unit, the adjustment transistor Mf21 is turned on according to the second driving data Vdata21, and the first and second terminals of its corresponding compensation driving transistor Mn21 are short-circuited.

[0139] In the second adjustment unit, the adjustment transistor Mf2m is turned on according to the second driving data Vdata2m, and the first and second terminals of its corresponding compensation driving transistor Mn2m are short-circuited.

[0140] During the data writing phase t11 of the first display cycle T1, the operating state of the sub-pixel driving circuit is as follows: Figure 7A As shown, the data writing transistor M1, regulating transistor Mf21, and regulating transistor Mf2m, marked with arrows, are turned on, while other transistors are turned off.

[0141] During the display phase t12 of the first display cycle T1, the scan signal Gate is at a high level.

[0142] The data writing transistor M1 is turned off according to the scan signal Gate, stopping the transmission of the first driving data Vdata1.

[0143] Since the regulating transistors in the first and second regulating units remain on, and both short-circuit the corresponding compensation driving transistors, only the reference driving transistor M2 generates a driving signal in the adjustable driving unit.

[0144] The reference drive transistor generates a drive signal based on the power supply signal VDD obtained from its first terminal and the first drive data Vdata1 obtained from its control terminal.

[0145] The adjustment transistors in the first and second adjustment units transmit the drive signal to the sub-pixel LED;

[0146] Subpixel LEDs emit light based on driving signals.

[0147] During the display phase t12 of the first display cycle T1, the operating state of the sub-pixel driving circuit is as follows: Figure 7B As shown, the reference drive transistor M2, the regulating transistor Mf21, and the regulating transistor Mf2m, which are marked with arrows next to them, are turned on, while the other transistors are turned off.

[0148] During the interval S following the first display cycle T1, the level of the first drive data Vata1 is the second level.

[0149] When the first driving data Vdata1 is data generated based on grayscale values, the grayscale value to be displayed in the second display period T2 is greater than the grayscale value to be displayed in the first display period T1;

[0150] When the first drive data Vdata1 is generated based on the drive current value, the drive current value to be output in the second display period T2 is greater than the drive current value to be output in the first display period T1.

[0151] The control circuit 250 controls the data driving circuit 20 to generate the second driving data Vdata21 in a high-level state according to the first driving data Vdata1 and the preset data range corresponding to the first regulating transistor mf21.

[0152] When the second driving data Vdata21 is adjusted from a low level to a high level, it will be adjusted from the information area to the non-information area and then back to the information area. The data in the non-information area is represented by the intermediate level between the low level and the high level in the figure.

[0153] The control circuit 250 controls the data driving circuit 20 to generate the second driving data Vdata2m in a low-level state according to the preset data range corresponding to the first driving data Vdata1 and the second adjustment transistor mf2m.

[0154] During the data writing phase t21 of the second display cycle T2, the scan signal Gate is at a low level.

[0155] The data writing transistor M1 is turned on according to the scan signal Gate, and the first driving data Vdata1 obtained at its first terminal is transmitted to the second terminal of the first capacitor C1.

[0156] The first capacitor C1 stores the first driving data Vdata1 at its second terminal, and the voltage value at the second terminal is the voltage value corresponding to the first driving data Vdata1.

[0157] In the first adjustment unit, the adjustment transistor Mf21 is turned off according to the second driving data Vdata21, and the first and second terminals of its corresponding compensation driving transistor Mn21 are not short-circuited.

[0158] In the second adjustment unit, the adjustment transistor Mf2m is turned on according to the second driving data Vdata2m, and the first and second terminals of its corresponding compensation driving transistor Mn2m are short-circuited.

[0159] During the data writing phase t21 of the second display cycle T2, the operating state of the sub-pixel driving circuit is as follows: Figure 7C As shown, the data writing transistor M1 and the regulating transistor Mf2m, marked with arrows, are turned on, while the other transistors are turned off.

[0160] During the display phase t22 of the second display cycle T2, the scan signal Gate is at a high level.

[0161] The data writing transistor M1 is turned off according to the scan signal Gate, stopping the transmission of the first driving data Vdata1.

[0162] Since the regulating transistor Mf2m in the second regulating unit remains on, its corresponding compensation driving transistor Mn2m is shorted.

[0163] Since the regulating transistor Mf21 in the first regulating unit is turned off, the reference driving transistor M2 and the compensation driving transistor Mn21 construct an equivalent driving transistor in the adjustable driving unit 804.

[0164] The equivalent driving transistor generates a driving signal based on the first driving data Vdata1 obtained from the control terminal and the power supply signal VDD.

[0165] The adjustment transistor Mf2m in the second adjustment unit transmits the drive signal to the sub-pixel LED;

[0166] Subpixel LEDs emit light based on driving signals.

[0167] Then, during the display phase t22 of the second display cycle T2, the operating state of the sub-pixel driving circuit is as follows: Figure 7D As shown, the reference drive transistor M2, compensation drive transistor Mn21, and adjustment transistor Mf2m, marked with arrows, are turned on, while the other transistors are turned off.

[0168] In some embodiments, the sub-pixel driving circuit can compensate the threshold voltage of the driving transistor. The aspect ratio compensation of the driving transistor proposed in this application can also be applied to sub-pixel driving circuits that can perform threshold voltage compensation.

[0169] The circuit structure of the improved sub-pixel driving circuit will be explained below, taking the traditional sub-pixel driving circuit 7T1C as an example.

[0170] Figure 8 This is a schematic diagram of a sub-pixel driving circuit that can perform threshold voltage compensation and drive transistor size adjustment according to an exemplary embodiment of this application.

[0171] The sub-pixel driving circuit also includes a data writing unit 803, which is electrically connected to the gate line 60 and the data line 50. It is configured to obtain the first driving data Vdata1 and the scan signal Gate, and the scan signal Gate controls its output of the first driving data Vdata1.

[0172] The sub-pixel driving circuit also includes a first light-emitting control transistor M3. The first terminal of the first light-emitting control transistor M3 is electrically connected to the power supply line 90, and its control terminal is electrically connected to the gate line 60. It is configured to obtain a power supply signal VDD from its first terminal and a first light-emitting control signal EM1 from its control terminal, and to control its output power supply signal VDD by the first light-emitting control signal EM1.

[0173] The sub-pixel driving circuit also includes an adjustable driving unit 804, which is electrically connected to the data line 50, the first light-emitting control transistor M3, the data writing unit 803, and the storage unit 805. The adjustable driving unit 804 includes a reference driving transistor M2, at least one compensation driving transistor and its corresponding adjustment transistor, and a compensation unit 8042.

[0174] The circuit connection relationship between the compensation drive transistor and the adjustment transistor within the adjustment unit, as well as the circuit connection relationship between an adjustment unit and the reference drive transistor M2, have been specified. Figure 4A , Figure 4B , Figure 5 The corresponding embodiments will be explained in detail here, and will not be repeated here.

[0175] The compensation unit 8042 is electrically connected to the equivalent driving transistor and is configured to form a threshold compensation structure with the equivalent driving transistor. During the process of writing driving data to the equivalent driving transistor, the terminals of the equivalent driving transistor are charged and discharged. When the potential difference between the control terminal and the first terminal of the equivalent driving transistor is adjusted to the threshold voltage of the equivalent driving transistor, the first driving data Vdata1 for threshold voltage compensation is determined at the control terminal of the equivalent driving transistor.

[0176] In some embodiments, the compensation unit 8042 includes a compensation transistor M5, the first end of which is electrically connected to the second end of the last driving transistor in the adjustable driving unit 804 (i.e., the second end of the equivalent driving transistor), the second end of which is electrically connected to the control end of the driving transistor in the adjustable driving unit 804 (i.e., the control end of the equivalent driving transistor), and the control end of which is electrically connected to the gate line 60. It is configured to obtain a scan signal Gate from its control end and control its conduction state by the scan signal Gate.

[0177] The compensation transistor M5 turns on when it receives a low-level scan signal Gate, forming a threshold compensation structure with the equivalent driving transistor; it turns off when it receives a high-level scan signal Gate.

[0178] Based on the above circuit structure, during the generation of the first driving data Vdata1 for threshold voltage compensation, the sub-pixel driving circuit obtains the second driving data Vdata2 corresponding to each adjustment transistor, and adjusts the conduction state of at least one adjustment transistor based on the second driving data Vdata2, thereby adjusting whether the first and second terminals of the corresponding compensation driving transistor are short-circuited.

[0179] Among them, the second driving data Vdata2 is the data generated by the control circuit 250 based on the first driving data Vdata1 and the preset data range corresponding to each adjustment unit, and controlled by the control data driving circuit 20.

[0180] The adjustable drive unit 804 is configured to obtain first drive data Vdata1. When the first drive data Vdata1 is within a first preset data range, the reference drive transistor M2 and the compensation transistor M5 form a threshold compensation structure. Through the threshold compensation structure and the first drive data Vdata1, the threshold voltage compensation of the reference drive transistor M2 is determined.

[0181] The adjustable drive unit 804 is further configured such that when the first drive data Vdata1 is within the second preset data range, the reference drive transistor M2 and the compensation drive transistor that is not short-circuited constitute an equivalent drive transistor, and the equivalent drive transistor and the compensation transistor M5 form a threshold compensation structure. The threshold compensation structure and the first drive data Vdata1 are used to determine the first drive data Vdata1 for threshold voltage compensation of the equivalent drive transistor.

[0182] The threshold voltage of the equivalent driving transistor is the sum of the threshold voltages of the reference driving transistor M2 and the compensation driving transistor that is not short-circuited.

[0183] The sub-pixel driving circuit also includes a storage unit 805, which is configured to store the first driving data Vdata1 generated by the adjustable driving unit 804 for threshold voltage compensation.

[0184] During the display phase, the states of each regulating transistor in the adjustable drive unit 804 remain unchanged.

[0185] The adjustable drive unit 804 obtains the first drive data Vdata1 with threshold voltage compensation from the storage unit 805 and the power signal VDD from the first light-emitting control transistor M3. Based on the power signal VDD, the first drive data Vdata1 with threshold voltage compensation, and the aspect ratio of the equivalent drive transistor, it adjusts the current value of the drive signal it generates.

[0186] The process of generating drive signals by the adjustable drive unit 804 has already been completed. Figure 4A , Figure 4B The corresponding embodiments will be explained in detail here, and will not be repeated here.

[0187] In some embodiments, the sub-pixel driving circuit further includes an initialization transistor M6.

[0188] The first terminal of the initialization transistor M6 is electrically connected to the power supply line 90, its second terminal is electrically connected to the storage unit 805 and the adjustable drive unit 804, and its control terminal is electrically connected to the gate line 60. It is configured to obtain a reference electrical signal REF from its first terminal and an initialization signal RESET from its control terminal, and its conduction state is controlled by the initialization signal RESET.

[0189] When the initialization signal RESET is low, the initialization transistor M6 is turned on, and the reference electrical signal REF obtained from its first terminal is output from its second terminal to perform a reset operation on the storage terminal of the storage unit 805 (the second terminal of the first capacitor C1) and the control terminal of the adjustable drive unit 804 (the control terminal of the reference drive transistor M2 and the compensation drive transistor); when the initialization signal RESET is high, the initialization transistor M6 is turned off, stopping the transmission of the reference electrical signal REF and stopping the reset operation.

[0190] The voltage value of the storage terminal of the storage unit 805 and the control terminal of the adjustable drive unit 804 after reset is the voltage value of the reference electrical signal REF.

[0191] In some embodiments, the sub-pixel driving circuit further includes an initialization transistor M7.

[0192] The first terminal of the initialization transistor M7 is electrically connected to the power supply line 90, and its second terminal is connected to the driving terminal of the sub-pixel LED (e.g., ...). Figure 8 The sub-pixel LED shown has its anode electrically connected, its control terminal and gate line 60 electrically connected, and is configured to obtain a reference electrical signal REF from its first terminal and an initialization signal RESET from its control terminal, with the initialization signal RESET controlling its conduction state.

[0193] When the initialization signal RESET is low, the initialization transistor M7 is turned on, and the reference electrical signal REF obtained from its first terminal is output from its second terminal to reset the driving terminal of the sub-pixel LED. The voltage value after reset is the voltage value of the reference electrical signal REF. When the initialization signal RESET is high, the initialization transistor M7 is turned off, stopping the transmission of the reference electrical signal REF and stopping the reset operation.

[0194] The sub-pixel driving circuit also includes a second light emission duration control transistor M4. The first terminal of the second light emission duration control transistor M4 is electrically connected to the output terminal of the adjustable driving unit 804 (the first terminal of the compensation transistor M5), the control terminal is electrically connected to the gate line 60 or the light emission duration adjustment circuit 806, and the second terminal is electrically connected to the sub-pixel LED. It is configured to obtain a driving signal from its first terminal and a second light emission control signal from its control terminal, and control its conduction state based on the second light emission control signal.

[0195] The second light emission duration control transistor M4 is turned on when the second light emission control signal is low, and transmits the driving signal obtained from its first terminal to the sub-pixel LED to drive the sub-pixel LED to emit light; when the second light emission control signal is high, it is turned off, stops the transmission of the driving signal, and the sub-pixel LED does not emit light.

[0196] In some embodiments, when the size (e.g., aspect ratio) of the equivalent driving transistor of the adjustable driving unit 804 is different, the waveform of the second light emission control signal applied to the sub-pixel driving circuit is also adjusted accordingly.

[0197] For example, when the size of the equivalent driving transistor of the adjustable driving unit 804 is small, the first driving data Vdata1 processed by this equivalent driving transistor is driving data corresponding to a lower grayscale value or a smaller driving current value. In order to further ensure the normal unfolding of the low grayscale, the second light emission control signal is adjusted to a narrow pulse signal (such as...). Figure 10 The waveforms of the EM21 signal in stages t13 and t23 are shown. By compressing the light-up time of the sub-pixel LEDs, the current value of the driving signal is increased to avoid the range where low grayscale cannot be properly expanded.

[0198] For example, when the size of the equivalent driving transistor of the adjustable driving unit 804 is large, the first driving data Vdata1 processed by this equivalent driving transistor is driving data corresponding to higher grayscale data or larger driving current values. When processing this driving data, the driving transistor does not need to compress the light-up time of the sub-pixel LED. Therefore, the second light-up control signal can be a PWM wave with a preset duty cycle that changes less frequently (e.g., no more than twice). Figure 10 The waveforms of the EM22 signal in stages t13 and t23 are shown.

[0199] In some embodiments, the sub-pixel driving circuit further includes an emission duration adjustment circuit 806, which is electrically connected to the gate line 60 and the data line 50, and is configured to obtain second driving data Vdata2 and at least one original emission control signal (e.g., first original control signal EM21, second original control signal EM22, ..., m-th original control signal EM2m), and output a second emission control signal based on the second driving data Vdata2 and at least one original emission control signal.

[0200] In some embodiments, the light emission duration adjustment circuit 806 and the gate line 60 are electrically connected and configured to obtain at least one modulated photoelectric signal and a plurality of original light emission control signals, and output a light emission control signal based on the at least one modulated photoelectric signal and the plurality of original light emission control signals.

[0201] In some embodiments, the light emission duration adjustment circuit includes a plurality of gating transistors M14, ..., Mm4; the number of gating transistors and the adjustable drive unit 804 are equivalent to the number of drive transistors.

[0202] Each photoelectric signal corresponds to at least one gating transistor, and multiple gating transistors correspond to multiple original light-emitting control signals.

[0203] The first terminal of the selection transistor is electrically connected to the gate drive circuit, the second terminal is electrically connected to the control terminal of the second light emission duration control transistor, and the control terminal is electrically connected to the data drive circuit. It is configured to obtain its corresponding modulation signal from its control terminal and its corresponding original light emission control signal from its first terminal. Its conduction state is controlled by the modulation signal. When it is on, it outputs the original light emission control signal as the second light emission control signal.

[0204] In some embodiments, at any given time, at most one modulated photoelectric signal is at the target level, and the other modulated photoelectric signals are at a non-target level. In this case, the gating transistor that obtains the target level is turned on, and the gating transistor that obtains the non-target level is turned off.

[0205] In some embodiments, the selector transistors are of the same type, such as P-type transistors. At any given time, at most one modulating signal is low and the other modulating signals are high.

[0206] The selector transistor then outputs a second light-emitting control signal during the display phase of each display cycle.

[0207] In some embodiments, in each display cycle, at most one compensation driving transistor performs size compensation on the reference driving transistor, then the dimming signal can be applied to the second driving data, the number of gating transistors is the same as the number of compensation driving transistors, the gating transistors and compensation driving transistors correspond to each other, and the type of gating transistors and the type of compensation driving transistors are different.

[0208] When the compensation driving transistor performs size compensation, its corresponding second driving data is high, and the corresponding gating transistor is turned on according to the high-level second driving data, outputting the corresponding second light emission control signal.

[0209] The waveforms or duty cycles of the original light-emitting control signals obtained by each select transistor are not exactly the same, so that when they are turned on to output the original light-emitting control signals, they can cooperate with the driving process of the corresponding equivalent driving transistor.

[0210] In some embodiments, the light emission duration adjustment circuit 806 includes a control transistor M04.

[0211] The first terminal of the control transistor M04 is electrically connected to the second terminal of each select transistor, and its second terminal is electrically connected to the control terminal of the second light emission duration control transistor M4. Its control terminal is electrically connected to the gate line 60. It is configured to obtain a first light emission control signal EM1 from its control terminal and control its conduction state by the first light emission control signal EM1.

[0212] In some embodiments, the control transistor M04 is a P-type transistor, which is turned on when the first light-emitting control signal EM1 is low, and transmits the second light-emitting control signal obtained at its first terminal to the control terminal of the second light-emitting duration control transistor M4; and is turned off when the first light-emitting control signal EM1 is high, stopping the transmission of the second light-emitting control signal.

[0213] When the sub-pixel driving circuit includes an adjustment unit, its circuit structure is as follows: Figure 9 As shown, it is similar to Figure 8 The circuit structure shown is different. Since the sub-pixel driving circuit only includes one adjustment unit, the light emission duration adjustment circuit 806 only needs two gating transistors (the first gating transistor M14 and the second gating transistor M24) to regulate the output of light emission control signals corresponding to two data ranges.

[0214] The first selector transistor M14 can be a P-type transistor, and the second selector transistor M24 can be an N-type transistor. The control terminals of the first selector transistor M14 and the second selector transistor M24 are electrically connected. This control terminal is electrically connected to the data line 50 and is configured to receive the second drive data Vdata2. When the second drive data Vdata2 is at a low level, the first selector transistor M14 is turned on to transmit a short pulse signal, and the second selector transistor M24 is turned off.

[0215] When the data on the second driver board is at a high level, the first selection transistor M14 is turned off, and the second selection transistor M24 is turned on, outputting a PWM wave with a preset duty cycle. This circuit structure can save the use of data line 50, simplifying the circuit structure.

[0216] The following is combined Figure 10 , Figures 11A to 11F ,right Figure 9 The operation of the sub-pixel driving circuit shown in the diagram during two adjacent display cycles is explained. Specifically, Figure 10 This is the timing diagram for the corresponding drive signals. Figures 11A to 11E This is a diagram illustrating the operation of the sub-pixel driving circuit.

[0217] A display cycle includes an initialization phase, a data writing phase, and a display phase, with an interval S between two adjacent display cycles.

[0218] During the interval S before the first display cycle T1, the level of the first driving data Vdata1 is the first level. The first driving data Vdata1 is the driving data corresponding to the lower grayscale value, or the driving data corresponding to the lower driving current value.

[0219] The control circuit 250 controls the data driving circuit 20 to generate second driving data Vdata2 in a low-level state based on the first driving data Vdata1 and the preset data range corresponding to the first adjustment unit.

[0220] During the initialization phase t11 of the first display cycle T1, the initialization signal RESET is low, the scan signal Gate, the first light emission control signal EM1, the first light emission original control signal EM21, and the second light emission original control signal EM22 are high, and the second driving data Vdata2 is low.

[0221] The initialization transistor M6 is turned on according to the initialization signal RESET, and the reference electrical signal REF obtained by its first terminal is transmitted to the second terminal of the first capacitor C1, the control terminal of the reference driving transistor M2 and the compensation driving transistor Mn2, thereby resetting the second terminal of the first capacitor C1 and the control terminal of the driving transistor. The voltage value after the reset is the voltage value of the reference electrical signal REF.

[0222] The initialization transistor M7 is turned on according to the initialization signal RESET, and the reference electrical signal REF obtained from its first terminal is transmitted to the anode of the sub-pixel LED to reset the anode of the sub-pixel LED.

[0223] Sub-pixel LEDs do not emit light.

[0224] The regulating transistor Mf2 is turned on according to the second driving data Vdata2, which shorts the first and second terminals of the compensation driving transistor Mn2.

[0225] During the initialization phase t11 of the first display cycle T1, the operating state of the sub-pixel driving circuit is as follows: Figure 11A As shown, the initialization transistors M6 and M7, and the regulating transistor Mf2, which are marked with arrows, are turned on, while the other transistors are turned off.

[0226] During the data writing phase t12 of the first display cycle T1, the scan signal Gate is at a low level, the initialization signal RESET, the first light emission control signal EM1, the first light emission original control signal EM21, the second light emission original control signal EM22 are at a high level, and the second driving data Vdata2 is at a low level.

[0227] Initialization transistors M6 and M7 are turned off according to the initialization signal RESET.

[0228] The data writing transistor M1 is turned on according to the scan signal Gate, and the first driving data Vdata1 obtained at its first terminal is transmitted to the first terminal of the reference driving transistor M2.

[0229] The compensation transistor M5 is turned on according to the scan signal Gate, and together with the reference drive transistor M2, they form a threshold compensation structure.

[0230] Since the control terminal of the reference drive transistor M2 is reset during the initialization phase, the reference electrical signal REF is low, and the reference drive transistor M2 is turned on.

[0231] The threshold compensation structure obtains the first driving data Vdata1 from the first terminal of the reference driving transistor M2. As the electrical signal corresponding to the first driving data Vdata1 charges the second terminal of the first capacitor C1, the reference driving transistor M2 is turned off when the voltage value at the control terminal of the reference driving transistor M2 is the voltage value corresponding to the first driving data Vdata1 for the threshold voltage compensation of the reference driving transistor M2.

[0232] The first capacitor C1 stores the first driving data Vdata1 of the threshold voltage compensation at its second terminal.

[0233] Since the second driving data Vdata2 is in a low level state, the first gating transistor M14 is turned on, transmitting the first light-emitting original control signal EM21 to the first terminal of the control transistor M04.

[0234] The second strobe transistor M24 is turned off according to the second drive data Vdata2.

[0235] The control transistor M04 is turned off according to the first light emission control signal EM1, and does not transmit the first light emission original control signal EM21.

[0236] The second light emission duration control transistor M04 did not receive a drive signal, nor did it receive the first light emission original control signal EM21. The sub-pixel LED did not receive the first drive signal, and the sub-pixel LED did not emit light.

[0237] During the data writing phase t12 of the first display cycle T1, the operating state of the sub-pixel driving circuit is as follows: Figure 11B As shown, the data writing transistor M1, adjustment transistor Mf2, compensation transistor M5, reference drive transistor M2, and first strobe transistor M14 are turned on, while the other transistors are turned off.

[0238] During the display phase t13 of the first display cycle T1, the initialization signal RESET and the scan signal Gate are at high level, the first light emission control signal EM1 is at low level, the first light emission original control signal EM21 is a plurality of narrow pulse signals, the second light emission original control signal EM22 is a PWM wave with a preset duty cycle, and the second drive data Vdata2 is at low level.

[0239] Data writing transistor M1 and compensation transistor M5 are turned off according to the scan signal Gate.

[0240] The first light emission duration control transistor M04 is turned on according to the first light emission control signal EM1, and the power signal VDD obtained at its first terminal is transmitted to the first terminal of the reference drive transistor M2.

[0241] Since the compensation drive transistor Mn2 is shorted by the adjustment transistor Mf2, the size of the reference drive transistor M2 is not compensated.

[0242] The reference drive transistor M2 generates a drive signal based on the power supply signal VDD obtained from its first terminal and the first drive data Vdata1, which is compensated for its threshold voltage, obtained from its control terminal. This drive signal is not affected by the threshold voltage.

[0243] Since the first selection transistor M14 maintains the state of transmitting the first light-emitting original control signal EM21, the control transistor M04 is turned on according to the first light-emitting control signal EM1, and transmits the first light-emitting original control signal EM21 as the second light-emitting control signal to the control terminal of the second light-emitting duration control transistor M04.

[0244] The second light-emitting control transistor M04 is turned on when the second light-emitting control signal is low, and transmits the driving signal to the sub-pixel so that the sub-pixel LED emits light.

[0245] The second light-emitting control transistor M04 is turned off when the second light-emitting control signal is at a high level, stopping the transmission of the drive signal, and the sub-pixel LED stops emitting light.

[0246] During the current display phase, the sub-pixel LEDs emit light multiple times.

[0247] Then, during the sub-pixel emission period in the display phase t13 of the first display cycle T1, the operating state of the sub-pixel driving circuit is as follows: Figure 11C As shown, the first light emission duration control transistor M3, the adjustment transistor Mf2, the reference drive transistor M2, the second light emission duration control transistor M4, the first gating transistor M14, and the control transistor M04, marked with arrows, are turned on, while the other transistors are turned off.

[0248] During the interval S following the first display cycle T1, the level of the first drive data Vata1 is the second level.

[0249] When the first driving data Vdata1 is data generated based on grayscale values, the grayscale value to be displayed in the second display period T2 is greater than the grayscale value to be displayed in the first display period T1;

[0250] When the first drive data Vdata1 is generated based on the drive current value, the drive current value to be output in the second display period T2 is greater than the drive current value to be output in the first display period T1.

[0251] The control circuit 250 controls the data driving circuit 20 to generate the second driving data Vdata2, which is in a high-level state, based on the first driving data Vdata1 and the preset data range corresponding to the adjustment unit.

[0252] When the second driving data Vdata2 is adjusted from a low level to a high level, it will move from the information area to the non-information area and then back to the information area. The data in the non-information area is represented by the intermediate level between the low and high levels in the figure.

[0253] During the initialization phase t21 of the second display cycle T2, the initialization signal RESET is low, the scan signal Gate, the first light emission control signal EM1, the first light emission original control signal EM21, and the second light emission original control signal EM22 are high, and the second driving data Vdata2 is in a high-level state.

[0254] The initialization transistor M6 is turned on according to the initialization signal RESET, and the reference electrical signal REF obtained by its first terminal is transmitted to the second terminal of the first capacitor C1, the control terminal of the reference driving transistor M2 and the compensation driving transistor Mn2, thereby resetting the second terminal of the first capacitor C1 and the control terminal of the driving transistor. The voltage value after the reset is the voltage value of the reference electrical signal REF.

[0255] The initialization transistor M7 is turned on according to the initialization signal RESET, and the reference electrical signal REF obtained from its first terminal is transmitted to the anode of the sub-pixel LED to reset the anode of the sub-pixel LED.

[0256] Sub-pixel LEDs do not emit light.

[0257] The regulating transistor Mf2 is turned off according to the second driving data Vdata2, and the compensation driving transistor Mn2 compensates for the size of the reference driving transistor M2 to construct an equivalent driving transistor.

[0258] During the initialization phase t21 of the second display cycle T2, the operating state of the sub-pixel driving circuit is as follows: Figure 11D As shown, the initialization transistors M6 and M7, marked with arrows, are turned on, while the other transistors are turned off.

[0259] During the data writing phase t22 of the second display cycle T2, the scan signal Gate is at a low level, the initialization signal RESET, the first light emission control signal EM1, the first light emission original control signal EM21, the second light emission original control signal EM22 are at a high level, and the second driving data Vdata2 is at a high level.

[0260] Initialization transistors M6 and M7 are turned off according to the initialization signal RESET.

[0261] The data writing transistor M1 is turned on according to the scan signal Gate, and the first driving data Vdata1 obtained at its first terminal is transmitted to the first terminal of the reference driving transistor M2.

[0262] The compensation transistor M5 is turned on according to the scan signal Gate, and together with the equivalent driving transistor, they form a threshold compensation structure.

[0263] The threshold compensation structure determines the threshold voltage of the reference driving transistor M2 and the first driving data Vdata1 for threshold voltage compensation of the compensation driving transistor Mn2 at the control terminal of the reference driving transistor M2 based on the first driving data Vdata1 obtained from the first terminal of the reference driving transistor M2.

[0264] The first capacitor C1 stores the first driving data Vdata1 of the threshold voltage compensation at its second terminal.

[0265] Since the second driving data Vdata2 is in a high-level state, the second gating transistor M24 is turned on, transmitting the second light-emitting original control signal EM22 to the first terminal of the control transistor M04.

[0266] The first gating transistor M14 is turned off according to the second driving data Vdata2.

[0267] The control transistor M04 is turned off according to the first light emission control signal EM1, and does not transmit the second light emission control signal EM22.

[0268] The second light emission duration control transistor M04 did not receive the second driving signal, nor did it receive the second light emission original control signal EM22. The sub-pixel LED did not receive the second driving signal and therefore did not emit light.

[0269] During the data writing phase t22 of the second display cycle T2, the operating state of the sub-pixel driving circuit is as follows: Figure 11E As shown, the data writing transistor M1, compensation transistor M5, reference drive transistor M2, compensation drive transistor Mn2, and second strobe transistor M24 are turned on, while the other transistors are turned off.

[0270] During the display phase t23 of the second display cycle T2, the initialization signal RESET and the scan signal Gate are at high level, the first light emission control signal EM1 is at low level, the first light emission original control signal EM21 is a plurality of narrow pulse signals, the second light emission original control signal EM22 is a PWM wave with a preset duty cycle, and the second drive data Vdata2 is at high level.

[0271] Data writing transistor M1 and compensation transistor M5 are turned off according to the scan signal Gate.

[0272] The first light emission duration control transistor M04 is turned on according to the first light emission control signal EM1, and the power signal VDD obtained at its first terminal is transmitted to the first terminal of the reference drive transistor M2.

[0273] The equivalent driving transistor generates a driving signal based on the power supply signal VDD obtained from the first terminal of the reference driving transistor M2 and the first driving data Vdata1, which is compensated for by the threshold voltage of the equivalent driving transistor, obtained from its control terminal. This driving signal is not affected by the threshold voltage.

[0274] Since the second selection transistor M24 maintains the state of transmitting the second light emission original control signal EM22, the control transistor M04 is turned on according to the first light emission control signal EM1, and transmits the second light emission original control signal EM22 as the second light emission control signal to the control terminal of the second light emission duration control transistor M04.

[0275] The second light-emitting control transistor M04 is turned on when the second light-emitting control signal is low, and transmits the driving signal to the sub-pixel so that the sub-pixel emits light.

[0276] The second light-emitting control transistor M04 is turned off when the second light-emitting control signal is at a high level, stopping the transmission of the drive signal and causing the sub-pixel to stop emitting light.

[0277] Then, during the sub-pixel emission period in the display phase t23 of the second display cycle T2, the operating state of the sub-pixel driving circuit is as follows: Figure 11F As shown, the first light emission duration control transistor M3, the reference drive transistor M2, the compensation drive transistor Mn2, the second light emission duration control transistor M4, the second gating transistor M24, and the control transistor M04, marked with arrows, are turned on, while the other transistors are turned off.

[0278] In some other embodiments, the transistors in the sub-pixel driving circuit provided in this application can be replaced with N-type transistors. In this case, the potential of the corresponding electrical signal will be adjusted accordingly. The high-level electrical signal in the sub-pixel circuit based on the P-type transistor is adjusted to the low-level electrical signal in the sub-pixel circuit based on the N-type transistor, and the low-level electrical signal in the sub-pixel circuit based on the P-type transistor is adjusted to the high-level electrical signal in the sub-pixel circuit based on the N-type transistor. This will not be elaborated further here.

[0279] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0280] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A display device, comprising: Gate driving circuit, data driving circuit, power supply circuit, multiple sub-pixels and corresponding sub-pixel driving circuits; The sub-pixel driving circuit is characterized by comprising: The data writing unit is electrically connected to the data driving circuit and the gate driving circuit, and is configured to obtain first driving data and a scan signal, and the scan signal controls it to output the first driving data. The storage unit, electrically connected to the data writing unit, is configured to store the first driving data; An adjustable drive unit includes at least two drive transistors and at least one adjustment unit; The control terminal of the driving transistor is electrically connected to the storage unit, the first terminal of the first driving transistor is coupled to the power supply circuit, the first terminal of the non-first driving transistor is electrically connected to the second terminal of the preceding driving transistor, and the second terminal of the last driving transistor is electrically connected to the sub-pixel. The at least two driving transistors include a reference driving transistor and at least one compensation driving transistor, and the at least one compensation driving transistor and the at least one adjustment unit are electrically connected accordingly. The adjustment unit is configured to obtain its corresponding first electrical signal, and control its conduction state by the first electrical signal. When it is on, it turns off its corresponding compensation drive transistor. The reference driving transistor and the compensation driving transistor corresponding to the adjustment unit in the off state form an equivalent driving transistor. The equivalent driving transistor is electrically connected to the power supply circuit and is configured to obtain the power supply signal and the first driving data, and output a driving signal. The sub-pixel is configured to emit light based on the driving signal.

2. The display device according to claim 1, characterized in that, The first electrical signal includes the second driving data; The adjustment unit includes an adjustment transistor, the first terminal of which is electrically connected to the first terminal of a corresponding compensation driving transistor, the second terminal of which is electrically connected to the second terminal of a corresponding compensation driving transistor, and the control terminal of which is electrically connected to the data driving circuit. It is configured to obtain second driving data from its control terminal and to conduct when the second driving data is in a first level state, thereby short-circuiting the first and second terminals of the corresponding compensation driving transistor. Turn off when the second drive data is in the second level state; Wherein, when the first driving data is within the preset data range corresponding to the adjustment unit, the second driving data is in a first level state; When the first driving data is not within the preset data range corresponding to the adjustment unit, the second driving data is in the second level state.

3. The display device according to claim 2, characterized in that, When the first terminal of the compensation driving transistor is electrically connected to the power supply circuit, its corresponding regulating transistor is configured to transmit the power signal when it is turned on. When the first terminal of the compensation driving transistor is electrically connected to the preceding driving transistor, its corresponding regulating transistor is configured to transmit the driving signal when it is turned on.

4. The display device according to any one of claims 1 to 3, characterized in that, The aspect ratio of the equivalent driving transistor is greater than or equal to the aspect ratio of the reference driving transistor. The length of the equivalent driving transistor is the sum of the equivalent length of the reference driving transistor and the equivalent length of the compensation driving transistor corresponding to the adjustment unit in the off state. Wherein, the equivalent length of the driving transistor is the product of the actual length of the driving transistor and the equivalent ratio, and the equivalent ratio is the ratio of the target width of the equivalent driving transistor to the actual width of the driving transistor.

5. The display device according to claim 4, characterized in that, The output terminal of the data writing unit is electrically connected to the first terminal of the first driving transistor, and is configured to transmit the first driving data to the first terminal of the first driving transistor when it is turned on. The adjustable drive unit further includes a compensation transistor, the first terminal of which is electrically connected to the control terminal of the drive transistor, the second terminal of which is electrically connected to the second terminal of the last drive transistor, and the control terminal of which is electrically connected to the gate drive circuit. It is configured to obtain the scan signal from its control terminal and control its conduction state by the scan signal. When it is turned on, it forms a threshold compensation structure with the equivalent driving transistor. When the equivalent driving transistor is turned off, the first driving data for threshold voltage compensation of the equivalent driving transistor is determined at the control terminal of the equivalent driving transistor.

6. The display device according to claim 5, characterized in that, The sub-pixel driving circuit also includes: The light emission duration adjustment circuit, which is electrically connected to the gate drive circuit, is configured to obtain at least one modulated photoelectric signal and a plurality of original light emission control signals, and output a light emission control signal based on the at least one modulated photoelectric signal and the plurality of original light emission control signals; The second light emission duration control transistor has its first terminal electrically connected to the second terminal of the last driving transistor, its control terminal electrically connected to the light emission duration adjustment circuit, and its second terminal electrically connected to the sub-pixel. It is configured to obtain a driving signal from its first terminal and the light emission control signal from its control terminal, and to control its output of the driving signal by the light emission control signal.

7. The display device according to claim 6, characterized in that, The light emission duration adjustment circuit includes multiple gating transistors; the light modulation signal corresponds to at least one gating transistor, and the multiple gating transistors correspond to multiple original light emission control signals; The first terminal of the selection transistor is electrically connected to the gate driving circuit, the second terminal is electrically connected to the control terminal of the second light emission duration control transistor, and the control terminal is electrically connected to the data driving circuit. It is configured to obtain its corresponding modulation signal from its control terminal and its corresponding original light emission control signal from its first terminal. Its conduction state is controlled by the modulation signal. When it is on, it outputs the original light emission control signal as the light emission control signal.

8. The display device according to claim 4, characterized in that, The storage terminal of the memory cell is electrically connected to the first terminal of the first driving transistor. A display cycle includes a data writing phase and a display phase; During the display phase, the scanning signal is at the second level; The storage unit outputs the first driving data it stored during the data writing phase; When the regulating transistor receives the second driving data in the first level state, it turns on according to the second driving data and shorts the first and second terminals of the corresponding compensation driving transistor. When the regulating transistor receives second driving data in a second-level state, it is turned off according to the second driving data. The unshort-circuited compensation drive transistor and the reference drive transistor constitute an equivalent drive transistor; The equivalent driving transistor generates the driving signal based on the power supply signal it receives and the first driving data; The sub-pixel emits light according to the driving signal.

9. The display device according to claim 7, characterized in that, A display cycle includes a reset phase, a data writing phase, and a display phase; During the data writing phase, the scan signal is at a first level; The data writing unit is turned on according to the scanning signal and transmits the first driving data obtained at its first end to the first end of the driving transistor located at the first position. When the regulating transistor receives the second driving data in the first level state, it turns on according to the second driving data and shorts the first and second terminals of the corresponding compensation driving transistor. When the regulating transistor receives second driving data in a second-level state, it is turned off according to the second driving data. The unshort-circuited compensation drive transistor and the reference drive transistor constitute an equivalent drive transistor; The compensation transistor is turned on according to the scanning signal, shorting the second terminal and the control terminal of the equivalent driving transistor; The equivalent driving transistor determines its threshold compensation first driving data from its control terminal based on the first driving data obtained from its first terminal. The storage unit stores the first driving data for threshold compensation of the equivalent driving transistor.

10. The display device according to claim 9, characterized in that, During the display phase, the scanning signal is at a second level, and the level state of the second driving data is the same as its level state during the data writing phase. The compensation transistor is turned off according to the scan signal, thus stopping the short circuit between the second terminal and the control terminal of the equivalent driving transistor. The equivalent driving transistor generates the driving signal based on the power supply signal it receives and the first driving data compensated by its threshold voltage. When the selection transistor receives a photoelectric signal that is in the corresponding target level state, it outputs the original light emission control signal it received, which serves as the light emission control signal. The gating transistor is turned off when it receives a photodiode signal that is not in the corresponding target level state; The control terminal of the second light emission duration control transistor receives the light emission control signal, and turns on when the light emission control signal is at a first level, and transmits the driving signal obtained at its first terminal to the sub-pixel so that the sub-pixel emits light according to the driving signal. The second light emission duration control transistor is turned off when the light emission control signal is at the second level, stopping the transmission of the drive signal so that the sub-pixel stops emitting light.

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