Display device and electronic device including the same

Abstract

The invention relates to a display device and an electronic device including the same. The display device includes: sub-pixel circuits arranged in a first direction and a second direction; a horizontal panel constant voltage line extending in a first direction and transmitting a panel constant voltage to the sub-pixel circuit; a vertical panel constant voltage line disposed on the horizontal panel constant voltage line, extending in a second direction, and transmitting a panel constant voltage to the horizontal panel constant voltage line; and a vertical bypass data line disposed on the same layer as the vertical panel constant voltage line, extending in the second direction, and transmitting a data voltage to the sub-pixel circuit.

Description

Technical Field

[0001] Embodiments of this disclosure relate to display devices. Background Technology

[0002] The display device includes sub-pixel circuits and light-emitting diodes (LEDs). The sub-pixel circuits are arranged side-by-side on a substrate, and signals and voltages are provided to the sub-pixel circuits. The sub-pixel circuits generate drive currents based on the signals and voltages, and the LEDs generate light based on the drive currents.

[0003] Examples of signals and voltages supplied to the sub-pixel circuitry may include gate signals, data voltages, and panel constant voltages. Panel constant voltage refers to a constant voltage supplied to the sub-pixel circuitry (e.g., high supply voltage, gate initialization voltage, anode initialization voltage, etc.), and it is necessary to supply a constant level of voltage to all parts of the sub-pixel circuitry. Summary of the Invention

[0004] Embodiments of this disclosure provide a display device.

[0005] Embodiments of this disclosure provide an electronic device including a display device.

[0006] The display device according to the embodiment includes: a sub-pixel circuit disposed on a substrate and arranged in a first direction and a second direction intersecting the first direction; a horizontal panel constant voltage line disposed on the substrate, extending in the first direction, and transmitting a panel constant voltage to the sub-pixel circuit; a vertical panel constant voltage line disposed on the horizontal panel constant voltage line, extending in the second direction, and transmitting a panel constant voltage to the horizontal panel constant voltage line; and a vertical bypass data line disposed on the same layer as the vertical panel constant voltage line, extending in the second direction, and transmitting a data voltage to the sub-pixel circuit.

[0007] In this implementation, the vertical panel constant voltage line can be disconnected from the vertical bypass data line.

[0008] In an embodiment, the display device may further include a panel constant voltage connection pattern disposed between the horizontal panel constant voltage line and the vertical panel constant voltage line and electrically connecting the horizontal panel constant voltage line and the vertical panel constant voltage line.

[0009] In this implementation, the constant voltage of the panel can be transmitted sequentially along the vertical constant voltage line of the panel, the constant voltage connection pattern of the panel, and the horizontal constant voltage line of the panel.

[0010] In an embodiment, the display device may further include: a horizontal low power supply voltage connection pattern disposed on the same layer as the panel constant voltage connection pattern; and a vertical low power supply voltage line disposed on the same layer as the vertical panel constant voltage line, connected to the horizontal low power supply voltage connection pattern, and transmitting low power supply voltage.

[0011] In one implementation, the vertical low power supply voltage line may extend in the second direction and may be arranged parallel to the vertical panel constant voltage line along the first direction.

[0012] In one embodiment, the horizontal low power supply voltage connection pattern and the panel constant voltage connection pattern can extend in a first direction and can be spaced apart from each other along the first direction.

[0013] In this implementation, the horizontal low power supply voltage connection pattern can be disconnected from the panel constant voltage connection pattern.

[0014] In an embodiment, the vertical low power supply voltage line may include a first vertical low power supply voltage line, a second vertical low power supply voltage line, and a third vertical low power supply voltage line, and the first vertical low power supply voltage line, the vertical panel constant voltage line, the second vertical low power supply voltage line, and the third vertical low power supply voltage line may be arranged sequentially from the first side to the second side of the display device, and may be parallel along the first direction.

[0015] In one embodiment, the horizontal low power voltage connection pattern may include a first horizontal low power voltage connection pattern and a second horizontal low power voltage connection pattern. The first horizontal low power voltage connection pattern may be electrically connected to a first vertical low power voltage line, and the second horizontal low power voltage connection pattern may be electrically connected to a second vertical low power voltage line and a third vertical low power voltage line.

[0016] In an embodiment, the first horizontal low power supply voltage connection pattern, the panel constant voltage connection pattern, and the second horizontal low power supply voltage connection pattern can extend in a first direction and can be spaced apart from each other along the first direction.

[0017] In this embodiment, the vertical low power supply voltage line may further include a fourth vertical low power supply voltage line, a fifth vertical low power supply voltage line, and a sixth vertical low power supply voltage line, and the vertical panel constant voltage line may include a first vertical panel constant voltage line and a second vertical panel constant voltage line. The fourth vertical low power supply voltage line, the second vertical panel constant voltage line, the fifth vertical low power supply voltage line, and the sixth vertical low power supply voltage line may be arranged sequentially from the first side to the second side of the display device, and may be parallel along the first direction.

[0018] In this embodiment, the panel constant voltage connection pattern may include a first panel constant voltage connection pattern and a second panel constant voltage connection pattern. The first panel constant voltage connection pattern may be electrically connected to a first vertical panel constant voltage line, and the second panel constant voltage connection pattern may be electrically connected to a second vertical panel constant voltage line.

[0019] In an implementation, the second horizontal low power supply voltage connection pattern may be further electrically connected to the fourth vertical low power supply voltage line, the fifth vertical low power supply voltage line, and the sixth vertical low power supply voltage line.

[0020] In an embodiment, the horizontal low power supply voltage connection pattern may further include a third horizontal low power supply voltage connection pattern and a fourth horizontal low power supply voltage connection pattern. The third horizontal low power supply voltage connection pattern may be electrically connected to the first vertical low power supply voltage line, the second vertical low power supply voltage line, the third vertical low power supply voltage line, and the fourth vertical low power supply voltage line, and the fourth horizontal low power supply voltage connection pattern may be electrically connected to the fifth vertical low power supply voltage line and the sixth vertical low power supply voltage line.

[0021] In the implementation, the third horizontal low power supply voltage connection pattern, the second panel constant voltage connection pattern, and the fourth horizontal low power supply voltage connection pattern can extend in a first direction and can be spaced apart from each other along the first direction, and the first panel constant voltage connection pattern and the second panel constant voltage connection pattern can be spaced apart from each other in a second direction.

[0022] In one embodiment, the vertical low power supply voltage line may include a first vertical low power supply voltage line and a second vertical low power supply voltage line, and the vertical panel constant voltage line may include a first vertical panel constant voltage line and a second vertical panel constant voltage line. The first vertical low power supply voltage line, the second vertical low power supply voltage line, the first vertical panel constant voltage line, and the second vertical panel constant voltage line may be arranged sequentially from the first side to the second side of the display device, and may be parallel along a first direction.

[0023] In an embodiment, the horizontal low power supply voltage connection pattern may include a first horizontal low power supply voltage connection pattern and a second horizontal low power supply voltage connection pattern. The first horizontal low power supply voltage connection pattern and the second horizontal low power supply voltage connection pattern may be arranged parallel to each other along a second direction and may be electrically connected to a first vertical low power supply voltage line and a second vertical low power supply voltage line. The panel constant voltage connection pattern may be arranged spaced apart from the second horizontal low power supply voltage connection pattern along a first direction and may be electrically connected to a first vertical panel constant voltage line and a second vertical panel constant voltage line.

[0024] In this embodiment, the vertical panel constant voltage line may include a first vertical panel constant voltage line and a second vertical panel constant voltage line. The first vertical panel constant voltage line can transmit a first panel constant voltage to a first sub-pixel circuit, and the second vertical panel constant voltage line can transmit a second panel constant voltage, different from the first panel constant voltage, to a second sub-pixel circuit. The panel constant voltage may be the anode initialization voltage for initializing the pixel electrode.

[0025] An electronic device according to an embodiment includes a display device and a power module configured to provide power to the display device. The display device may include: a sub-pixel circuit disposed on a substrate and arranged in a first direction and a second direction intersecting the first direction; a horizontal panel constant voltage line disposed on the substrate, extending in the first direction, and transmitting a constant panel voltage to the sub-pixel circuit; a vertical panel constant voltage line disposed on the horizontal panel constant voltage line, extending in the second direction, and transmitting a constant panel voltage to the horizontal panel constant voltage line; and a vertical bypass data line disposed on the same layer as the vertical panel constant voltage line, extending in the second direction, and transmitting a data voltage to the sub-pixel circuit.

[0026] Therefore, the display device according to embodiments of the present disclosure may include horizontal panel constant voltage lines and vertical panel constant voltage lines formed in the display area. A constant panel voltage can be transmitted to the sub-pixel circuit via the intersecting horizontal and vertical panel constant voltage lines.

[0027] In other words, the horizontal and vertical constant voltage lines of the panel can be arranged in a grid pattern within the display area. Since the constant voltage of the panel is transmitted through the horizontal and vertical constant voltage lines, voltage drop defects in the constant voltage of the panel can be prevented.

[0028] Furthermore, the vertical panel constant voltage lines and the vertical bypass data lines can be formed together and placed on the same layer. Therefore, the separate process for forming the vertical panel constant voltage lines can be omitted. Attached Figure Description

[0029] The above and other features of this disclosure will be more clearly understood with reference to the following detailed description and accompanying drawings.

[0030] Figure 1 This is a plan view showing a display device according to an embodiment of the present disclosure.

[0031] Figure 2 It is shown Figure 1 A side view of the display device.

[0032] Figure 3 It is shown Figure 1 A block diagram of the display device.

[0033] Figure 4 It is shown that it includes Figure 1 The circuit diagram of the sub-pixel circuit and light-emitting diode in the display device.

[0034] Figure 5 It is shown Figure 1 A plan view of the display device.

[0035] Figure 6 It is shown that it includes Figure 1An enlarged view of the bypass data voltage region in the display device.

[0036] Figure 7 It is shown that it includes Figure 1 A block diagram of the voltage region of the grid panel in a display device.

[0037] Figure 8 It is shown Figure 7 A magnified view of the voltage region of the grid panel.

[0038] Figures 9 to 11 It is shown Figure 8 An exploded view of the voltage region of the grid panel.

[0039] Figure 12 It is shown Figure 8 A cross-sectional view of the voltage region of the grid panel.

[0040] Figure 13 It is shown Figure 8 A cross-sectional view of the voltage region of the grid panel.

[0041] Figure 14 This is a plan view showing a display device according to an embodiment of the present disclosure.

[0042] Figure 15 It is shown that it includes Figure 14 A block diagram of the voltage region of the grid panel in a display device.

[0043] Figure 16 It is shown Figure 15 A magnified view of the voltage region of the grid panel.

[0044] Figure 17 This is a plan view showing a display device according to an embodiment of the present disclosure.

[0045] Figure 18 It is shown that it includes Figure 17 A block diagram of the voltage region of the grid panel in a display device.

[0046] Figure 19 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0047] Figure 20 This is a schematic diagram of an electronic device. Detailed Implementation

[0048] In the following description, the display device according to embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same parts in the drawings, and redundant descriptions of the same parts will be omitted.

[0049] Figure 1This is a plan view showing a display device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 A side view of the display device.

[0050] refer to Figure 1 and Figure 2 The display device DD1 according to embodiments of the present disclosure may include a substrate SUB, a display panel PNL, a window WIN, a data driver DDV, a controller CON, and a circuit board CB.

[0051] The substrate SUB can comprise transparent or opaque materials. Examples of materials that can be used as the substrate SUB in implementations include glass, quartz, plastic, etc. These can be used individually or in combination with each other.

[0052] The display panel PNL can be disposed on the substrate SUB. The display panel PNL can generate and emit light. Therefore, the display panel PNL can display images.

[0053] A window (WIN) can be disposed on the display panel (PNL). The window protects the display panel (PNL). In embodiments, examples of materials that can be used as the window include glass, quartz, plastic, etc. These can be used individually or in combination with each other.

[0054] In this implementation, the data driver DDV can be disposed on the substrate SUB. The data driver DDV can provide data voltage to the display panel PNL.

[0055] The controller CON can be mounted on the circuit board CB. The controller CON can be connected to the data driver DDV and / or the display panel PNL via the circuit board CB.

[0056] The circuit board CB can be mounted on the substrate SUB. The circuit board CB can connect the controller CON to the data driver DDV and / or the display panel PNL. Additionally, additional drivers (e.g., touch drivers, etc.) can be mounted on the circuit board CB.

[0057] Figure 3 It is shown Figure 1 A block diagram of the display device. Figure 4 It is shown that it includes Figure 1 The circuit diagram of the sub-pixel circuit and light-emitting diode in the display device.

[0058] refer to Figure 3 The display device DD1 may include a gate driver GDV, an emitter driver EDV, a data driver DDV, a controller CON, a panel constant voltage supply PVD, and a sub-pixel circuit SPC.

[0059] The gate driver (GDV) can generate gate signals. The gate driver (GDV) can sequentially provide gate signals, and the gate signals can be transmitted to the sub-pixel circuit (SPC) via the gate line (GL).

[0060] The transmit driver EDV can generate transmit control signals. The transmit driver EDV can provide transmit control signals sequentially, and the transmit control signals can be transmitted to the sub-pixel circuit SPC via the transmit control line EML.

[0061] The data driver DDV generates a data voltage. This data voltage can be transmitted to the sub-pixel circuit SPC via the data line DL.

[0062] The controller CON can be connected to an external processor (e.g., a GPU) and can control the gate driver GDV, transmit driver EDV, and data driver DDV. For example, the controller CON can transmit gate control signals to the gate driver GDV and data control signals to the data driver DDV.

[0063] The panel constant voltage supply (PVD) generates a constant voltage for the panel. This constant voltage is then transmitted to the sub-pixel circuit (SPC) via the panel constant voltage line (PVL).

[0064] In one embodiment, the panel constant voltage can be a constant voltage transmitted to the sub-pixel circuit SPC. For example, the panel constant voltage can be at least one of an anode initialization voltage, a gate initialization voltage, a high power supply voltage, and a bias voltage. In another embodiment, the panel constant voltage can be the anode initialization voltage that initializes the pixel electrode.

[0065] refer to Figure 4 The sub-pixel circuit (SPC) can receive the constant panel voltage (PV), data voltage (DATA), gate signals (GW, GC, GI, and GB), and transmit control signal (EM), and can generate drive current. The SPC can be connected to a light-emitting diode (LED), and the drive current can be transferred to the LED.

[0066] In an implementation, the sub-pixel circuit SPC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor CST.

[0067] The first transistor T1 may include a first terminal, a second terminal, a gate terminal, and a back gate terminal. The first terminal may be connected to the second transistor T2. The second terminal may be connected to the third transistor T3. The gate terminal may be connected to the third transistor T3. The back gate terminal may be provided with a high supply voltage ELVDD.

[0068] The first transistor T1 can generate a drive current based on the voltage difference between the first terminal and the gate terminal.

[0069] The second transistor T2 may include a first terminal, a second terminal, and a gate terminal. The first terminal can provide a data voltage DATA. The second terminal can be connected to the first transistor T1. The gate terminal can provide a first gate signal GW.

[0070] The second transistor T2 can transmit the data voltage DATA in response to the first gate signal GW.

[0071] The third transistor T3 may include a first terminal, a second terminal, and a gate terminal. The first terminal may be connected to the second terminal of the first transistor T1. The second terminal may be connected to the gate terminal of the first transistor T1. The gate terminal may provide a second gate signal GC.

[0072] The third transistor T3 can compensate the threshold voltage of the first transistor T1 in response to the second gate signal GC.

[0073] The fourth transistor T4 may include a first terminal, a second terminal, and a gate terminal. The first terminal can provide a gate initialization voltage VINT. The second terminal can be connected to the gate terminal of the first transistor T1. The gate terminal can provide a third gate signal GI.

[0074] The fourth transistor T4 can initialize the gate terminal of the first transistor T1 in response to the third gate signal GI.

[0075] The fifth transistor T5 may include a first terminal, a second terminal, and a gate terminal. The first terminal can provide a high supply voltage ELVDD. The second terminal can be connected to the first transistor T1. The gate terminal can provide an emit control signal EM.

[0076] The fifth transistor T5 can transmit the high supply voltage ELVDD to the first transistor T1 in response to the transmit control signal EM.

[0077] The sixth transistor T6 may include a first terminal, a second terminal, and a gate terminal. The first terminal may be connected to the first transistor T1. The second terminal may be connected to a light-emitting diode (LED). The gate terminal may provide an emission control signal EM.

[0078] The sixth transistor T6 can transmit drive current to the light-emitting diode (LED) in response to the emitter control signal EM.

[0079] The seventh transistor T7 may include a first terminal, a second terminal, and a gate terminal. The first terminal can provide the anode initialization voltage VAINT. The second terminal can be connected to a light-emitting diode (LED). The gate terminal can provide a fourth gate signal GB.

[0080] The seventh transistor T7 can transmit the anode initialization voltage VAINT to the light-emitting diode LED in response to the fourth gate signal GB.

[0081] The eighth transistor T8 may include a first terminal, a second terminal, and a gate terminal. The first terminal may provide a bias voltage VBIAS. The second terminal may be connected to the first transistor T1. The gate terminal may provide a fourth gate signal GB.

[0082] The eighth transistor T8 can transmit the bias voltage VBIAS to the first transistor T1 in response to the fourth gate signal GB.

[0083] The storage capacitor CST may include a first terminal and a second terminal. The first terminal may be connected to a high power supply voltage line providing a high power supply voltage ELVDD. The second terminal may be connected to a first transistor T1. The storage capacitor CST may store a voltage corresponding to the data voltage DATA.

[0084] In this embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be a PMOS transistor, and each of the third transistor T3 and the fourth transistor T4 may be an NMOS transistor. However, this disclosure is not limited thereto.

[0085] Furthermore, as described above, the first gate signal GW, the second gate signal GC, the third gate signal GI, and the fourth gate signal GB, the transmit control signal EM, the data voltage DATA, and the panel constant voltage PV can be provided to the sub-pixel circuit SPC. The panel constant voltage PV can refer to a constant voltage provided to the sub-pixel circuit SPC, and can be at least one of, for example, the anode initialization voltage VAINT, the gate initialization voltage VINT, the high supply voltage ELVDD, and the bias voltage VBIAS.

[0086] The following description illustrates an implementation of the panel constant voltage PV as the anode initialization voltage VAINT, but this disclosure is not limited thereto.

[0087] A light-emitting diode (LED) may include a first terminal and a second terminal. The first terminal may be connected to a sixth transistor T6 and a seventh transistor T7. The second terminal may be supplied with a low power supply voltage ELVSS. The first terminal of the LED may receive a drive current from the sixth transistor T6 and may receive an anode initialization voltage VAINT from the seventh transistor T7.

[0088] Figure 5 It is shown Figure 1 A plan view of the display device. Figure 6It is shown that it includes Figure 1 An enlarged view of the bypass data voltage region in the display device.

[0089] refer to Figure 5 The display device DD1 can be divided into a display area DA and a non-display area NDA. The display area DA can be an area for displaying images and can be an area where light-emitting diodes (LEDs) are arranged. The non-display area NDA can be an area surrounding at least a portion of the display area DA.

[0090] In an embodiment, at least one horizontal line extending in a first direction D1 and at least one vertical line extending in a second direction D2 intersecting the first direction D1 may be provided on the substrate SUB.

[0091] For example, the horizontal line may include a horizontal bypass data line HBDL extending in the first direction D1. The vertical line may include a vertical bypass data line VBDL, a vertical panel constant voltage line VPVL, and a vertical low power supply voltage line VSL extending in the second direction D2.

[0092] In this implementation, the vertical bypass data line VBDL and the vertical panel constant voltage line VPVL can be formed together and can be disposed on the same layer. For example, the vertical bypass data line VBDL can be connected to the horizontal bypass data line HBDL through a contact hole and can transmit data voltage DATA.

[0093] In this implementation, the vertical panel constant voltage line VPVL can be disposed on the same layer as the vertical bypass data line VBDL, and can also be disconnected from the vertical bypass data line VBDL. For example, the vertical panel constant voltage line VPVL can be disconnected from the vertical bypass data line VBDL around the area where the contact hole is formed. Therefore, the vertical panel constant voltage line VPVL can be decoupled from the vertical bypass data line VBDL and can transmit the panel constant voltage PV.

[0094] Furthermore, in this embodiment, the vertical low power supply voltage line (VSL) can be disposed on the same layer as the vertical bypass data line (VBDL) and can be disconnected from the vertical bypass data line (VBDL). For example, the vertical low power supply voltage line (VSL) can be disconnected from the vertical bypass data line (VBDL) around the area where the contact hole is formed. Therefore, the vertical low power supply voltage line (VSL) can be de-electrically connected to the vertical bypass data line (VBDL) and can transmit the low power supply voltage (ELVSS).

[0095] In the implementation, the display area DA can be divided into the bypass data voltage area BDA and the grid panel voltage area MPVA.

[0096] For example, the bypass data voltage region BDA can be an area adjacent to the data driver DDV and is the area where the horizontal bypass data line HBDL and the vertical bypass data line VBDL are set. The data voltage DATA can be transmitted in the bypass data voltage region BDA.

[0097] For example, the grid panel voltage region MPVA can be an area other than the bypass data voltage region BDA, and can be an area where the vertical panel constant voltage line VPVL and / or the vertical low power supply voltage line VSL are set. Within the grid panel voltage region MPVA, the panel constant voltage PV and / or the low power supply voltage ELVSS can be transmitted.

[0098] In this implementation, the panel constant voltage bus PVB, low power supply voltage bus VSSB, data driver DDV, and pad portion PDP can be arranged in the non-display area NDA. The panel constant voltage bus PVB can receive the panel constant voltage PV from the pad portion PDP and can be configured to surround the display area DA. The low power supply voltage bus VSSB can receive the low power supply voltage ELVSS from the pad portion PDP and can be configured to surround the panel constant voltage bus PVB.

[0099] refer to Figure 6 The vertical bypass data line VBDL can extend in the second direction D2 and can be connected between the data driver DDV and the horizontal bypass data line HBDL. The horizontal bypass data line HBDL can extend in the first direction D1 and can be connected between the vertical bypass data line VBDL and the data line DL. The data voltage DATA can be transmitted from the data driver DDV to the data line DL through the vertical bypass data line VBDL and the horizontal bypass data line HBDL.

[0100] Figure 7 It is shown that it includes Figure 1 A block diagram of the voltage region of the grid panel in a display device. Figure 8 It is shown Figure 7 A magnified view of the voltage region of the grid panel. Figures 9 to 11 It is shown Figure 8 An exploded view of the voltage region of the grid panel. Figure 12 It is shown Figure 8 A cross-sectional view of the voltage region of the grid panel. Figure 13 It is shown Figure 8 A cross-sectional view of the voltage region of the grid panel.

[0101] refer to Figure 7In the grid panel voltage region MPVA, on the substrate SUB, sub-pixel circuit SPC, first horizontal panel constant voltage line HPVL1, second horizontal panel constant voltage line HPVL2, first horizontal low power supply voltage connection pattern HSP1, second horizontal low power supply voltage connection pattern HSP2, third horizontal low power supply voltage connection pattern HSP3, fourth horizontal low power supply voltage connection pattern HSP4, first vertical low power supply voltage line VSL1, first vertical panel constant voltage line VPVL1, second vertical low power supply voltage line VSL2, third vertical low power supply voltage line VSL3, fourth vertical low power supply voltage line VSL4, second vertical panel constant voltage line VPVL2, fifth vertical low power supply voltage line VSL5, and sixth vertical low power supply voltage line VSL6 can be provided.

[0102] In this implementation, the sub-pixel circuits (SPCs) can be arranged in a first direction D1 and a second direction D2. For example, the SPCs can be arranged in a matrix shape. The SPCs can be electrically connected to the first horizontal panel constant voltage line HPVL1 and / or the second horizontal panel constant voltage line HPVL2. The SPCs can receive a constant panel voltage PV from the first horizontal panel constant voltage line HPVL1 and / or the second horizontal panel constant voltage line HPVL2.

[0103] The first horizontal panel constant voltage line HPVL1 can extend in the first direction D1 and can transmit the panel constant voltage PV to the sub-pixel circuit SPC.

[0104] In this implementation, the first horizontal panel constant voltage line HPVL1 can be electrically connected to the first vertical panel constant voltage line VPVL1 via the first panel constant voltage connection pattern PVP1. The first horizontal panel constant voltage line HPVL1 can receive the panel constant voltage PV via the first vertical panel constant voltage line VPVL1 and the first panel constant voltage connection pattern PVP1.

[0105] In this implementation, the first horizontal panel constant voltage line HPVL1 can be electrically connected to the panel constant voltage bus PVB. The first horizontal panel constant voltage line HPVL1 can receive the panel constant voltage PV through the panel constant voltage bus PVB.

[0106] The second horizontal panel constant voltage line HPVL2 can extend in the first direction D1 and can transmit the panel constant voltage PV to the sub-pixel circuit SPC.

[0107] In this embodiment, the second horizontal panel constant voltage line HPVL2 can be electrically connected to the second vertical panel constant voltage line VPVL2 via the second panel constant voltage connection pattern PVP2. The second horizontal panel constant voltage line HPVL2 can receive the panel constant voltage PV via the second vertical panel constant voltage line VPVL2 and the second panel constant voltage connection pattern PVP2.

[0108] In this implementation, the second horizontal panel constant voltage line HPVL2 can be electrically connected to the panel constant voltage bus PVB. The second horizontal panel constant voltage line HPVL2 can receive the panel constant voltage PV through the panel constant voltage bus PVB.

[0109] The first horizontal low power supply voltage connection pattern HSP1 may extend in the first direction D1. In an embodiment, the first horizontal low power supply voltage connection pattern HSP1 may be connected to the first vertical low power supply voltage line VSL1 via a contact hole.

[0110] The second horizontal low power supply voltage connection pattern HSP2 may extend in the first direction D1. In an embodiment, the second horizontal low power supply voltage connection pattern HSP2 may be connected via a contact hole to at least one of the second vertical low power supply voltage line VSL2, the third vertical low power supply voltage line VSL3, the fourth vertical low power supply voltage line VSL4, the fifth vertical low power supply voltage line VSL5, and the sixth vertical low power supply voltage line VSL6.

[0111] In this implementation, the first low power supply voltage connection pattern HSP1 and the second low power supply voltage connection pattern HSP2 can be disconnected from each other. For example, the first low power supply voltage connection pattern HSP1 and the second low power supply voltage connection pattern HSP2 can be disconnected through the first panel constant voltage connection pattern PVP1.

[0112] The third horizontal low power supply voltage connection pattern HSP3 may extend in the first direction D1. In an embodiment, the third horizontal low power supply voltage connection pattern HSP3 may be connected to at least one of the first vertical low power supply voltage line VSL1, the second vertical low power supply voltage line VSL2, the third vertical low power supply voltage line VSL3, and the fourth vertical low power supply voltage line VSL4 via contact holes.

[0113] The fourth horizontal low power supply voltage connection pattern HSP4 may extend in the first direction D1. In an embodiment, the fourth horizontal low power supply voltage connection pattern HSP4 may be connected to at least one of the fifth vertical low power supply voltage line VSL5 and the sixth vertical low power supply voltage line VSL6 via contact holes.

[0114] In this implementation, the third low power supply voltage connection pattern HSP3 and the fourth low power supply voltage connection pattern HSP4 can be disconnected from each other. For example, the third low power supply voltage connection pattern HSP3 and the fourth low power supply voltage connection pattern HSP4 can be disconnected through the second panel constant voltage connection pattern PVP2.

[0115] The first vertical low power supply voltage line VSL1 may extend in the second direction D2. In an embodiment, the first vertical low power supply voltage line VSL1 may be connected to the first horizontal low power supply voltage connection pattern HSP1 and the third horizontal low power supply voltage connection pattern HSP3 via contact holes. The first vertical low power supply voltage line VSL1 may transmit a low power supply voltage ELVSS.

[0116] The first vertical panel constant voltage line VPVL1 can extend in the second direction D2. In an embodiment, the first vertical panel constant voltage line VPVL1 can be electrically connected to the first horizontal panel constant voltage line HPVL1 via the first panel constant voltage connection pattern PVP1. The first vertical panel constant voltage line VPVL1 can transmit the panel constant voltage PV.

[0117] The second vertical low power supply voltage line VSL2 may extend in the second direction D2. In an embodiment, the second vertical low power supply voltage line VSL2 may be connected to the second horizontal low power supply voltage connection pattern HSP2 and the third horizontal low power supply voltage connection pattern HSP3 via contact holes. The second vertical low power supply voltage line VSL2 may transmit a low power supply voltage ELVSS.

[0118] The third vertical low power supply voltage line VSL3 may extend in the second direction D2. In an embodiment, the third vertical low power supply voltage line VSL3 may be connected to the second horizontal low power supply voltage connection pattern HSP2 and the third horizontal low power supply voltage connection pattern HSP3 via contact holes. The third vertical low power supply voltage line VSL3 may transmit a low power supply voltage ELVSS.

[0119] The fourth vertical low power supply voltage line VSL4 may extend in the second direction D2. In an embodiment, the fourth vertical low power supply voltage line VSL4 may be connected to the second horizontal low power supply voltage connection pattern HSP2 and the third horizontal low power supply voltage connection pattern HSP3 via contact holes. The fourth vertical low power supply voltage line VSL4 may transmit a low power supply voltage ELVSS.

[0120] The second vertical panel constant voltage line VPVL2 can extend in the second direction D2. In an embodiment, the second vertical panel constant voltage line VPVL2 can be electrically connected to the second horizontal panel constant voltage line HPVL2 via the second panel constant voltage connection pattern PVP2.

[0121] The fifth vertical low power supply voltage line VSL5 may extend in the second direction D2. In an embodiment, the fifth vertical low power supply voltage line VSL5 may be connected to the second horizontal low power supply voltage connection pattern HSP2 and the fourth horizontal low power supply voltage connection pattern HSP4 via contact holes. The fifth vertical low power supply voltage line VSL5 may transmit a low power supply voltage ELVSS.

[0122] The sixth vertical low power supply voltage line VSL6 may extend in the second direction D2. In an embodiment, the sixth vertical low power supply voltage line VSL6 may be connected to the second horizontal low power supply voltage connection pattern HSP2 and the fourth horizontal low power supply voltage connection pattern HSP4 via contact holes. The sixth vertical low power supply voltage line VSL6 may transmit a low power supply voltage ELVSS.

[0123] In this implementation, the constant panel voltage PV can be transmitted to the sub-pixel circuit SPC via a horizontal constant voltage line extending in the first direction D1 and a vertical constant voltage line extending in the second direction D2. For example, as... Figure 7 As shown, the constant voltage PV of the panel can be transmitted to the sub-pixel circuit SPC through the first horizontal panel constant voltage line HPVL1 and the second horizontal panel constant voltage line HPVL2 extending in the first direction D1, and the first vertical panel constant voltage line VPVL1 and the second vertical panel constant voltage line VPVL2 extending in the second direction D2.

[0124] In other words, the horizontal and vertical constant voltage lines of the panel can be arranged in a grid pattern within the display area DA. When the constant voltage PV of the panel is transmitted through the horizontal and vertical constant voltage lines, voltage drop defects in the constant voltage PV of the panel can be prevented.

[0125] In addition, as mentioned above Figure 5 As described, the vertical panel constant voltage line VPVL can be formed together with the vertical bypass data line VBDL and disposed on the same layer as the vertical bypass data line VBDL, and each of the first panel constant voltage connection pattern PVP1 and the second panel constant voltage connection pattern PVP2 can be formed together with the horizontal bypass data line HBDL and disposed on the same layer as the horizontal bypass data line HBDL. Therefore, separate processes for forming the vertical panel constant voltage line and / or the panel constant voltage connection pattern can be eliminated.

[0126] In this implementation, the low power supply voltage ELVSS can be transmitted via a horizontal low power supply voltage connection pattern extending in a first direction D1 and a vertical low power supply voltage line extending in a second direction D2. For example, as... Figure 7 As shown, the low power supply voltage ELVSS can be transmitted via a first horizontal low power supply voltage connection pattern HSP1, a second horizontal low power supply voltage connection pattern HSP2, a third horizontal low power supply voltage connection pattern HSP3 and a fourth horizontal low power supply voltage connection pattern HSP4 extending in the first direction D1, and a first vertical low power supply voltage line VSL1, a second vertical low power supply voltage line VSL2, a third vertical low power supply voltage line VSL3, a fourth vertical low power supply voltage line VSL4, a fifth vertical low power supply voltage line VSL5 and a sixth vertical low power supply voltage line VSL6 extending in the second direction D2.

[0127] In other words, the horizontal low power supply voltage connection pattern and the vertical low power supply voltage line can be arranged in a grid shape within the display area DA. When the low power supply voltage ELVSS is transmitted through the horizontal low power supply voltage connection pattern and the vertical low power supply voltage line, voltage drop defects of the low power supply voltage ELVSS can be prevented.

[0128] In addition, as mentioned above Figure 5 As described, the vertical low power supply voltage line can be formed together with the vertical bypass data line VBDL and disposed on the same layer as the vertical bypass data line VBDL, and the horizontal low power supply voltage connection pattern can be formed together with the horizontal bypass data line HBDL and disposed on the same layer as the horizontal bypass data line HBDL. Therefore, separate processes for forming the vertical low power supply voltage line and / or the horizontal low power supply voltage connection pattern can be eliminated.

[0129] refer to Figure 8 and Figure 9 A first horizontal panel constant voltage line HPVL1 and a second horizontal panel constant voltage line HPVL2 can be formed. For example, the first horizontal panel constant voltage line HPVL1 and the second horizontal panel constant voltage line HPVL2 can be formed together on the same layer. The first horizontal panel constant voltage line HPVL1 and the second horizontal panel constant voltage line HPVL2 can extend in a first direction D1 and can be arranged parallel to each other along a second direction D2.

[0130] refer to Figure 8 and Figure 10 The system can form a first horizontal low power supply voltage connection pattern HSP1, a first panel constant voltage connection pattern PVP1, a second horizontal low power supply voltage connection pattern HSP2, a third horizontal low power supply voltage connection pattern HSP3, a second panel constant voltage connection pattern PVP2, and a fourth horizontal low power supply voltage connection pattern HSP4. For example, the first horizontal low power supply voltage connection pattern HSP1, the first panel constant voltage connection pattern PVP1, the second horizontal low power supply voltage connection pattern HSP2, the third horizontal low power supply voltage connection pattern HSP3, the second panel constant voltage connection pattern PVP2, and the fourth horizontal low power supply voltage connection pattern HSP4 can be formed together on the same layer.

[0131] In this embodiment, the first horizontal low power supply voltage connection pattern HSP1, the first panel constant voltage connection pattern PVP1, and the second horizontal low power supply voltage connection pattern HSP2 can be arranged parallel to each other along the first direction D1. Furthermore, the first panel constant voltage connection pattern PVP1 can be disconnected from the first horizontal low power supply voltage connection pattern HSP1 and the second horizontal low power supply voltage connection pattern HSP2.

[0132] In this embodiment, the first panel constant pressure connection pattern PVP1 can overlap with the first horizontal panel constant pressure line HPVL1, and can be connected to the first horizontal panel constant pressure line HPVL1 through a contact hole.

[0133] In this embodiment, the third horizontal low power supply voltage connection pattern HSP3, the second panel constant voltage connection pattern PVP2, and the fourth horizontal low power supply voltage connection pattern HSP4 can be arranged parallel to each other along the first direction D1. Furthermore, the second panel constant voltage connection pattern PVP2 can be disconnected from the third horizontal low power supply voltage connection pattern HSP3 and the fourth horizontal low power supply voltage connection pattern HSP4.

[0134] In this embodiment, the second panel constant pressure connection pattern PVP2 can overlap with the second horizontal panel constant pressure line HPVL2, and can be connected to the second horizontal panel constant pressure line HPVL2 through contact holes.

[0135] refer to Figure 8 and Figure 11 A first vertical low power supply voltage line VSL1, a first vertical panel constant voltage line VPVL1, a second vertical low power supply voltage line VSL2, a third vertical low power supply voltage line VSL3, a fourth vertical low power supply voltage line VSL4, a second vertical panel constant voltage line VPVL2, a fifth vertical low power supply voltage line VSL5, and a sixth vertical low power supply voltage line VSL6 can be formed together on the same layer.

[0136] In this embodiment, the first vertical low power supply voltage line VSL1, the first vertical panel constant voltage line VPVL1, the second vertical low power supply voltage line VSL2, the third vertical low power supply voltage line VSL3, the fourth vertical low power supply voltage line VSL4, the second vertical panel constant voltage line VPVL2, the fifth vertical low power supply voltage line VSL5, and the sixth vertical low power supply voltage line VSL6 can be arranged in parallel along the first direction D1.

[0137] However, this disclosure is not limited thereto, and the number of vertical low power supply voltage lines, the number of vertical panel constant voltage lines, and the arrangement of the vertical low power supply voltage lines and the vertical panel constant voltage lines can be appropriately set as needed. Furthermore, the number and arrangement of the horizontal low power supply voltage connection patterns and the panel constant voltage connection patterns can also be appropriately set according to the arrangement of the vertical low power supply voltage lines and the vertical panel constant voltage lines.

[0138] refer to Figure 12In the grid panel voltage region MPVA, the display device DD1 may include a substrate SUB, a lower metal layer BML, a first insulating layer IL1, a first active pattern ACT1, a second insulating layer IL2, a first gate electrode GAT1, a second gate electrode GAT2, a third insulating layer IL3, a capacitor electrode CSTE, a fourth insulating layer IL4, a second active pattern ACT2, a fifth insulating layer IL5, a third gate electrode GAT3, a first horizontal panel constant voltage line HPVL1, a sixth insulating layer IL6, a first panel constant voltage connection pattern PVP1, a first connection electrode SD1, a seventh insulating layer IL7, a first vertical panel constant voltage line VPVL1, a second connection electrode SD2, an eighth insulating layer IL8, a pixel electrode PXE, a pixel limiting layer PDL, an emitter layer EL, a common electrode CTE, a first encapsulation inorganic layer EIL1, an encapsulation organic layer EOL, and a second encapsulation inorganic layer EIL2.

[0139] The lower metal layer (BML) can be disposed on the substrate (SUB). For example, a high power supply voltage (ELVDD) can be provided to the lower metal layer (BML). In embodiments, the lower metal layer (BML) can include metals, alloys, conductive metal oxides, etc. For example, the lower metal layer (BML) can include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0140] The first insulating layer IL1 may cover the lower metal layer BML and may be disposed on the substrate SUB. In an embodiment, the first insulating layer IL1 may include an insulating material. For example, the first insulating layer IL1 may include silicon oxide, silicon nitride, titanium oxide, tantalum oxide, etc.

[0141] The first active pattern ACT1 may be disposed on the first insulating layer IL1. In an embodiment, the first active pattern ACT1 may include silicon semiconductor, oxide semiconductor, etc. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. The first active pattern ACT1 may allow current to flow or block current in response to a gate signal provided to the first gate electrode GAT1 or the second gate electrode GAT2, wherein the first gate electrode GAT1 or the second gate electrode GAT2 is disposed on the first active pattern ACT1 and overlaps with the first active pattern ACT1.

[0142] The second insulating layer IL2 may cover the first active pattern ACT1 and may be disposed on the first insulating layer IL1. In an embodiment, the second insulating layer IL2 may include an insulating material.

[0143] The first gate electrode GAT1 can be disposed on the second insulating layer IL2 and can overlap with the first active pattern ACT1 and the lower metal layer BML. In an embodiment, the first gate electrode GAT1 may include a metal, an alloy, a conductive metal oxide, etc.

[0144] The second gate electrode GAT2 can be disposed on the second insulating layer IL2 and can overlap with the first active pattern ACT1. In an embodiment, the second gate electrode GAT2 may include a metal, an alloy, a conductive metal oxide, etc.

[0145] In an embodiment, the first gate electrode GAT1 and the second gate electrode GAT2 can be disposed on the same layer and formed together.

[0146] The third insulating layer IL3 may cover the first gate electrode GAT1 and the second gate electrode GAT2, and may be disposed on the second insulating layer IL2. The third insulating layer IL3 may include insulating material.

[0147] The capacitor electrode CSTE can be disposed on the third insulating layer IL3 and can overlap with the first gate electrode GAT1. The capacitor electrode CSTE can form a storage capacitor CST together with the first gate electrode GAT1. In an embodiment, the capacitor electrode CSTE can include a metal, alloy, conductive metal oxide, etc.

[0148] The fourth insulating layer IL4 may cover the capacitor electrode CSTE and may be disposed on the third insulating layer IL3. The fourth insulating layer IL4 may include insulating material.

[0149] The second active pattern ACT2 can be disposed on the fourth insulating layer IL4. In an embodiment, the second active pattern ACT2 can include silicon semiconductors, oxide semiconductors, etc. For example, oxide semiconductors can include zinc (Zn), indium (In), gallium (Ga), tin (Sn), aluminum (Al), zinc oxide (ZnO), indium oxide (InO), indium gallium zinc oxide (In-Ga-Zn-O), zinc tin oxide (Zn-Sn-O), etc. The second active pattern ACT2 can allow current to flow or block current in response to a gate signal provided to the third gate electrode GAT3.

[0150] The fifth insulating layer IL5 may cover the second active pattern ACT2 and may be disposed on the fourth insulating layer IL4. The fifth insulating layer IL5 may include insulating material.

[0151] The third gate electrode GAT3 can be disposed on the fifth insulating layer IL5 and can overlap with the second active pattern ACT2. In an embodiment, the third gate electrode GAT3 may include a metal, an alloy, a conductive metal oxide, etc.

[0152] The first horizontal panel constant voltage line HPVL1 can be arranged on the fifth insulating layer IL5. In an embodiment, the first horizontal panel constant voltage line HPVL1 may include metal, alloy, conductive metal oxide, etc.

[0153] In an implementation, the first horizontal panel constant voltage line HPVL1 can be disposed on the same layer as the third gate electrode GAT3, and can be formed together with the third gate electrode GAT3.

[0154] The sixth insulating layer IL6 may cover the first horizontal panel constant voltage line HPVL1 and the third gate electrode GAT3, and may be disposed on the fifth insulating layer IL5. In an embodiment, the sixth insulating layer IL6 may include an insulating material. For example, the sixth insulating layer IL6 may include organic materials such as photoresist, polyacrylic resin, polyimide resin, or acrylic resin.

[0155] The first panel constant voltage connection pattern PVP1 can be disposed on the sixth insulating layer IL6. In an embodiment, the first panel constant voltage connection pattern PVP1 may include metal, alloy, conductive metal oxide, etc.

[0156] In this embodiment, the first panel constant voltage connection pattern PVP1 may overlap with the first active pattern ACT1 and the first horizontal panel constant voltage line HPVL1. Furthermore, the first panel constant voltage connection pattern PVP1 may be connected to the first active pattern ACT1 and the first horizontal panel constant voltage line HPVL1. Therefore, the first panel constant voltage connection pattern PVP1 can electrically connect the first active pattern ACT1 and the first horizontal panel constant voltage line HPVL1.

[0157] The first connecting electrode SD1 can be disposed on the sixth insulating layer IL6. In an embodiment, the first connecting electrode SD1 may include a metal, alloy, conductive metal oxide, etc. The first connecting electrode SD1 can be connected to the first active pattern ACT1.

[0158] In an implementation, the first panel constant voltage connection pattern PVP1 can be disposed on the same layer as the first connection electrode SD1, and can be formed together with the first connection electrode SD1.

[0159] The seventh insulating layer IL7 may cover the first panel constant voltage connection pattern PVP1 and the first connection electrode SD1, and may be disposed on the sixth insulating layer IL6. In an embodiment, the seventh insulating layer IL7 may include an insulating material.

[0160] The first vertical panel constant voltage line VPVL1 can be disposed on the seventh insulating layer IL7. In an embodiment, the first vertical panel constant voltage line VPVL1 may include metal, alloy, conductive metal oxide, etc.

[0161] In this implementation, the first vertical panel constant voltage line VPVL1 can overlap with and connect to the first panel constant voltage connection pattern PVP1. In other words, the first vertical panel constant voltage line VPVL1 can be electrically connected to the first active pattern ACT1 and the first horizontal panel constant voltage line HPVL1 via the first panel constant voltage connection pattern PVP1. The first vertical panel constant voltage line VPVL1 can transmit the constant panel voltage PV to the first active pattern ACT1 and the first horizontal panel constant voltage line HPVL1.

[0162] The second connecting electrode SD2 can be disposed on the seventh insulating layer IL7. In an embodiment, the second connecting electrode SD2 may include a metal, alloy, conductive metal oxide, etc. The second connecting electrode SD2 can be connected to the first connecting electrode SD1.

[0163] In one embodiment, the first vertical panel constant voltage line VPVL1 can be disposed on the same layer as the second connecting electrode SD2, and can be formed together with the second connecting electrode SD2.

[0164] The eighth insulating layer IL8 may cover the first vertical panel constant voltage line VPVL1 and the second connecting electrode SD2, and may be disposed on the seventh insulating layer IL7. In an embodiment, the eighth insulating layer IL8 may include an insulating material.

[0165] The pixel electrode PXE can be disposed on the eighth insulating layer IL8. In an embodiment, the pixel electrode PXE may include metal, alloy, conductive metal oxide, etc. Furthermore, the pixel electrode PXE can be connected to the second connection electrode SD2.

[0166] The constant voltage PV supplied from the first vertical panel constant voltage line VPVL1 can be transmitted to the first active pattern ACT1 via the first panel constant voltage connection pattern PVP1. The constant voltage PV can be transmitted to the pixel electrode PXE via the first connection electrode SD1 and the second connection electrode SD2 in response to the gate signal transmitted to the second gate electrode GAT2.

[0167] The pixel defining layer (PDL) may be disposed on the eighth insulating layer (IL8). In embodiments, the pixel defining layer (PDL) may include organic materials such as polyimide-based resins (e.g., photosensitive polyimide-based resins (PSPI)), photoresists, polyacrylic acid-based resins, or acrylic resins, or the pixel defining layer (PDL) may include inorganic materials such as silicon oxide or silicon nitride.

[0168] An emitter layer (EL) can be disposed on the pixel electrode (PXE). The emitter layer (EL) can generate light based on the voltage difference between the pixel electrode (PXE) and the common electrode (CTE).

[0169] The common electrode CTE can be located on the emitter layer EL. A low supply voltage ELVSS can be provided to the common electrode CTE.

[0170] The first encapsulation inorganic layer EIL1 can be disposed on the common electrode CTE and may include inorganic materials. The encapsulation organic layer EOL can be disposed on the first encapsulation inorganic layer EIL1 and may include organic materials. The second encapsulation inorganic layer EIL2 can be disposed on the encapsulation organic layer EOL and may include inorganic materials.

[0171] refer to Figure 13 The first horizontal low power supply voltage connection pattern HSP1, the first panel constant voltage connection pattern PVP1, and the second horizontal low power supply voltage connection pattern HSP2 can be disposed on the sixth insulating layer IL6.

[0172] As described above, the first horizontal low power supply voltage connection pattern HSP1, the first panel constant voltage connection pattern PVP1, and the second horizontal low power supply voltage connection pattern HSP2 can be disposed on the same layer and can be formed together.

[0173] In addition, such as Figure 8 As depicted, the first horizontal low power supply voltage connection pattern HSP1, the first panel constant voltage connection pattern PVP1, and the second horizontal low power supply voltage connection pattern HSP2 can extend in the first direction D1 and be spaced apart from each other along the first direction D1.

[0174] In addition, the first panel constant voltage connection pattern PVP1 can be disconnected from the first horizontal low power supply voltage connection pattern HSP1 and the second horizontal low power supply voltage connection pattern HSP2.

[0175] The first vertical low power supply voltage line VSL1, the first vertical panel constant voltage line VPVL1, the second vertical low power supply voltage line VSL2, and the third vertical low power supply voltage line VSL3 can be disposed on the seventh insulating layer IL7.

[0176] As described above, the first vertical low power supply voltage line VSL1, the first vertical panel constant voltage line VPVL1, the second vertical low power supply voltage line VSL2, and the third vertical low power supply voltage line VSL3 can be disposed on the same layer and formed together.

[0177] In addition, such as Figure 8 As depicted, the first vertical low power supply voltage line VSL1, the first vertical panel constant voltage line VPVL1, the second vertical low power supply voltage line VSL2, and the third vertical low power supply voltage line VSL3 can extend in the second direction D2 and be arranged parallel to the first direction D1.

[0178] The first vertical low power supply voltage line VSL1 can be connected to the first horizontal low power supply voltage connection pattern HSP1, and the second vertical low power supply voltage line VSL2 and the third vertical low power supply voltage line VSL3 can be connected to the second horizontal low power supply voltage connection pattern HSP2.

[0179] The first cathode connection electrode CEP1, the pixel electrode PXE, the second cathode connection electrode CEP2, and the third cathode connection electrode CEP3 can be disposed on the eighth insulating layer IL8.

[0180] In this embodiment, the first cathode connection electrode CEP1, the pixel electrode PXE, the second cathode connection electrode CEP2, and the third cathode connection electrode CEP3 can be disposed on the same layer and formed together.

[0181] The first cathode connection electrode CEP1 can be connected to the first vertical low power supply line VSL1, the second cathode connection electrode CEP2 can be connected to the second vertical low power supply line VSL2, and the third cathode connection electrode CEP3 can be connected to the third vertical low power supply line VSL3.

[0182] The common electrode CTE can be connected to the first cathode connection electrode CEP1, the second cathode connection electrode CEP2, and the third cathode connection electrode CEP3.

[0183] In this implementation, the low power supply voltage ELVSS can be transmitted to the common electrode CTE via a horizontal low power supply voltage connection pattern extending in the first direction D1 and a vertical low power supply voltage line extending in the second direction D2. For example, the low power supply voltage ELVSS can be transmitted to the common electrode CTE via a first horizontal low power supply voltage connection pattern HSP1 and a second horizontal low power supply voltage connection pattern HSP2 extending in the first direction D1, and a first vertical low power supply voltage line VSL1, a second vertical low power supply voltage line VSL2, and a third vertical low power supply voltage line VSL3 extending in the second direction D2.

[0184] In other words, the horizontal low power supply voltage connection pattern and the vertical low power supply voltage line can be arranged in a grid shape within the display area DA. When the low power supply voltage ELVSS is transmitted through the horizontal low power supply voltage connection pattern and the vertical low power supply voltage line, voltage drop defects of the low power supply voltage ELVSS can be prevented.

[0185] In addition, as mentioned above Figure 5As described, the vertical low power supply voltage line can be formed together with the vertical bypass data line VBDL and disposed on the same layer as the vertical bypass data line VBDL, and the horizontal low power supply voltage connection pattern can be formed together with the horizontal bypass data line HBDL and disposed on the same layer as the horizontal bypass data line HBDL. Therefore, separate processes for forming the vertical low power supply voltage line and / or the horizontal low power supply voltage connection pattern can be eliminated.

[0186] Figure 14 This is a plan view showing a display device according to an embodiment of the present disclosure. Figure 15 It is shown that it includes Figure 14 A block diagram of the voltage region of the grid panel in a display device. Figure 16 It is shown Figure 15 A magnified view of the voltage region of the grid panel.

[0187] refer to Figure 14 According to embodiments of the present disclosure, the display device DD2 can be divided into a display area DA and a non-display area NDA. The display area DA can be an area for displaying images and can be an area where light-emitting diodes are arranged. The non-display area NDA can be an area surrounding at least a portion of the display area DA.

[0188] However, apart from what is described below, the display device DD2 may be compatible with the reference. Figure 5 The described display device DD1 is essentially the same.

[0189] refer to Figure 15 In the grid panel voltage region MPVA, the sub-pixel circuit SPC, the first horizontal panel constant voltage line HPVL1, the second horizontal panel constant voltage line HPVL2, the first horizontal low power supply voltage connection pattern HSP1, the second horizontal low power supply voltage connection pattern HSP2, the third horizontal low power supply voltage connection pattern HSP3, the first vertical low power supply voltage line VSL1, the second vertical low power supply voltage line VSL2, the first vertical panel constant voltage line VPVL1, the second vertical panel constant voltage line VPVL2, the third vertical low power supply voltage line VSL3, the fourth vertical low power supply voltage line VSL4, the third vertical panel constant voltage line VPVL3, and the fourth vertical panel constant voltage line VPVL4 can be disposed on the substrate SUB.

[0190] In this implementation, the sub-pixel circuits (SPCs) can be arranged in a first direction D1 and a second direction D2. For example, the SPCs can be arranged in a matrix shape. The SPCs can be electrically connected to the first horizontal panel constant voltage line HPVL1 and / or the second horizontal panel constant voltage line HPVL2. The SPCs can receive a constant panel voltage PV from the first horizontal panel constant voltage line HPVL1 and / or the second horizontal panel constant voltage line HPVL2.

[0191] The first horizontal panel constant voltage line HPVL1 can extend in the first direction D1 and can transmit the panel constant voltage PV to the sub-pixel circuit SPC.

[0192] In this implementation, the first horizontal panel constant voltage line HPVL1 can be electrically connected to the third vertical panel constant voltage line VPVL3 and the fourth vertical panel constant voltage line VPVL4 via the second panel constant voltage connection pattern PVP2. The first horizontal panel constant voltage line HPVL1 can receive the panel constant voltage PV via the third vertical panel constant voltage line VPVL3, the fourth vertical panel constant voltage line VPVL4, and the second panel constant voltage connection pattern PVP2.

[0193] The second horizontal panel constant voltage line HPVL2 can extend in the first direction D1 and can transmit the panel constant voltage PV to the sub-pixel circuit SPC.

[0194] In this embodiment, the second horizontal panel constant voltage line HPVL2 can be electrically connected to the first vertical panel constant voltage line VPVL1 and the second vertical panel constant voltage line VPVL2 via the first panel constant voltage connection pattern PVP1. The second horizontal panel constant voltage line HPVL2 can receive the panel constant voltage PV via the first vertical panel constant voltage line VPVL1, the second vertical panel constant voltage line VPVL2, and the first panel constant voltage connection pattern PVP1.

[0195] The first horizontal low power supply voltage connection pattern HSP1 may extend in the first direction D1. In an embodiment, the first horizontal low power supply voltage connection pattern HSP1 may be connected to at least one of the first vertical low power supply voltage line VSL1, the second vertical low power supply voltage line VSL2, the third vertical low power supply voltage line VSL3, and the fourth vertical low power supply voltage line VSL4.

[0196] The second horizontal low power supply voltage connection pattern HSP2 may extend in the first direction D1. The first horizontal low power supply voltage connection pattern HSP1 and the second horizontal low power supply voltage connection pattern HSP2 are arranged parallel to each other along the second direction D2 and spaced apart from each other. In an embodiment, the second horizontal low power supply voltage connection pattern HSP2 may be connected to at least one of the first vertical low power supply voltage line VSL1 and the second vertical low power supply voltage line VSL2.

[0197] The third horizontal low power supply voltage connection pattern HSP3 may extend in the first direction D1. In an embodiment, the third horizontal low power supply voltage connection pattern HSP3 may be connected to at least one of the third vertical low power supply voltage line VSL3 and the fourth vertical low power supply voltage line VSL4 via a contact hole.

[0198] In this implementation, the second low power supply voltage connection pattern HSP2 and the third low power supply voltage connection pattern HSP3 can be disconnected from each other. For example, the second low power supply voltage connection pattern HSP2 and the third low power supply voltage connection pattern HSP3 can be disconnected through the first panel constant voltage connection pattern PVP1.

[0199] The first vertical low power supply voltage line VSL1 may extend in the second direction D2. In an embodiment, the first vertical low power supply voltage line VSL1 may be connected to a first horizontal low power supply voltage connection pattern HSP1 and a second horizontal low power supply voltage connection pattern HSP2 via contact holes. The first vertical low power supply voltage line VSL1 may transmit a low power supply voltage ELVSS.

[0200] The second vertical low power supply voltage line VSL2 may extend in the second direction D2. In an embodiment, the second vertical low power supply voltage line VSL2 may be connected to the first horizontal low power supply voltage connection pattern HSP1 and the second horizontal low power supply voltage connection pattern HSP2 via contact holes. The second vertical low power supply voltage line VSL2 may transmit a low power supply voltage ELVSS.

[0201] The first vertical panel constant voltage line VPVL1 can extend in the second direction D2. In an embodiment, the first vertical panel constant voltage line VPVL1 can be electrically connected to the second horizontal panel constant voltage line HPVL2 via a first panel constant voltage connection pattern PVP1. The first vertical panel constant voltage line VPVL1 can transmit a constant panel voltage PV.

[0202] The second vertical panel constant voltage line VPVL2 can extend in the second direction D2. In an embodiment, the second vertical panel constant voltage line VPVL2 can be electrically connected to the second horizontal panel constant voltage line HPVL2 via the first panel constant voltage connection pattern PVP1. The second vertical panel constant voltage line VPVL2 can transmit the panel constant voltage PV.

[0203] The third vertical low power supply voltage line VSL3 may extend in the second direction D2. In an embodiment, the third vertical low power supply voltage line VSL3 may be connected to the first horizontal low power supply voltage connection pattern HSP1 and the third horizontal low power supply voltage connection pattern HSP3 via contact holes. The third vertical low power supply voltage line VSL3 may transmit a low power supply voltage ELVSS.

[0204] The fourth vertical low power supply voltage line VSL4 may extend in the second direction D2. In an embodiment, the fourth vertical low power supply voltage line VSL4 may be connected to the first horizontal low power supply voltage connection pattern HSP1 and the third horizontal low power supply voltage connection pattern HSP3 via contact holes. The fourth vertical low power supply voltage line VSL4 may transmit a low power supply voltage ELVSS.

[0205] The third vertical panel constant voltage line VPVL3 can extend in the second direction D2. In an embodiment, the third vertical panel constant voltage line VPVL3 can be electrically connected to the first horizontal panel constant voltage line HPVL1 via the second panel constant voltage connection pattern PVP2. The third vertical panel constant voltage line VPVL3 can transmit the panel constant voltage PV.

[0206] The fourth vertical panel constant voltage line VPVL4 can extend in the second direction D2. In an embodiment, the fourth vertical panel constant voltage line VPVL4 can be electrically connected to the first horizontal panel constant voltage line HPVL1 via the second panel constant voltage connection pattern PVP2. The fourth vertical panel constant voltage line VPVL4 can transmit the panel constant voltage PV.

[0207] refer to Figure 16 A first horizontal panel constant voltage line HPVL1 and a second horizontal panel constant voltage line HPVL2 can be formed. For example, the first horizontal panel constant voltage line HPVL1 and the second horizontal panel constant voltage line HPVL2 can be formed together on the same layer. The first horizontal panel constant voltage line HPVL1 and the second horizontal panel constant voltage line HPVL2 can extend in a first direction D1 and can be arranged parallel to each other along a second direction D2.

[0208] A first horizontal low power supply voltage connection pattern HSP1, a second horizontal low power supply voltage connection pattern HSP2, a first panel constant voltage connection pattern PVP1, a third horizontal low power supply voltage connection pattern HSP3, and a second panel constant voltage connection pattern PVP2 can be formed. For example, the first horizontal low power supply voltage connection pattern HSP1, the second horizontal low power supply voltage connection pattern HSP2, the first panel constant voltage connection pattern PVP1, the third horizontal low power supply voltage connection pattern HSP3, and the second panel constant voltage connection pattern PVP2 can be formed together on the same layer.

[0209] In one embodiment, the first horizontal low power supply voltage connection pattern HSP1 and the second panel constant voltage connection pattern PVP2 can extend along a first direction D1 and be spaced apart from each other along the first direction D1. Furthermore, the second panel constant voltage connection pattern PVP2 can be disconnected from the first horizontal low power supply voltage connection pattern HSP1.

[0210] In this embodiment, the second panel constant pressure connection pattern PVP2 can overlap with the first horizontal panel constant pressure line HPVL1, and can be connected to the first horizontal panel constant pressure line HPVL1 through contact holes.

[0211] In this embodiment, the second horizontal low power supply voltage connection pattern HSP2, the first panel constant voltage connection pattern PVP1, and the third horizontal low power supply voltage connection pattern HSP3 may extend in the first direction D1 and be spaced apart from each other along the first direction D1. Furthermore, the first panel constant voltage connection pattern PVP1 may be disconnected from the second horizontal low power supply voltage connection pattern HSP2 and the third horizontal low power supply voltage connection pattern HSP3.

[0212] In this embodiment, the first panel constant pressure connection pattern PVP1 can overlap with the second horizontal panel constant pressure line HPVL2, and can be connected to the second horizontal panel constant pressure line HPVL2 through contact holes.

[0213] A first vertical low power supply voltage line VSL1, a second vertical low power supply voltage line VSL2, a first vertical panel constant voltage line VPVL1, a second vertical panel constant voltage line VPVL2, a third vertical low power supply voltage line VSL3, a fourth vertical low power supply voltage line VSL4, a third vertical panel constant voltage line VPVL3, and a fourth vertical panel constant voltage line VPVL4 can be formed together on the same layer.

[0214] In the implementation, the first vertical low power supply voltage line VSL1, the second vertical low power supply voltage line VSL2, the first vertical panel constant voltage line VPVL1, the second vertical panel constant voltage line VPVL2, the third vertical low power supply voltage line VSL3, the fourth vertical low power supply voltage line VSL4, the third vertical panel constant voltage line VPVL3, and the fourth vertical panel constant voltage line VPVL4 can extend in the second direction D2 and be arranged parallel to the first direction D1.

[0215] Figure 17 This is a plan view showing a display device according to an embodiment of the present disclosure. Figure 18 It is shown that it includes Figure 17 A block diagram of the voltage region of the grid panel in a display device.

[0216] refer to Figure 17 According to embodiments of the present disclosure, the display device DD3 can be divided into a display area DA and a non-display area NDA. The display area DA may be an area for displaying an image and may be an area where light-emitting diodes are arranged. The non-display area NDA may be an area surrounding at least a portion of the display area DA.

[0217] However, apart from what is described below, the display device DD3 may be compatible with the reference. Figure 5 The described display device DD1 is essentially the same.

[0218] refer to Figure 18 In the grid panel voltage region MPVA, the first sub-pixel circuit SPC1, the second sub-pixel circuit SPC2, the first horizontal panel constant voltage line HPVL1, the second horizontal panel constant voltage line HPVL2, the third horizontal panel constant voltage line HPVL3, the fourth horizontal panel constant voltage line HPVL4, the first horizontal low power supply voltage connection pattern HSP1, the second horizontal low power supply voltage connection pattern HSP2, the third horizontal low power supply voltage connection pattern HSP3, the fourth horizontal low power supply voltage connection pattern HSP4, the first vertical low power supply voltage line VSL1, the second vertical low power supply voltage line VSL2, the first vertical panel constant voltage line VPVL1, the second vertical panel constant voltage line VPVL2, the third vertical low power supply voltage line VSL3, the fourth vertical low power supply voltage line VSL4, the fifth vertical low power supply voltage line VSL5, the sixth vertical low power supply voltage line VSL6, the third vertical panel constant voltage line VPVL3, the fourth vertical panel constant voltage line VPVL4, the seventh vertical low power supply voltage line VSL7, and the eighth vertical low power supply voltage line VSL8 can be disposed on the substrate SUB.

[0219] In one implementation, the panel constant voltage bus PVB may include a first panel constant voltage bus PVB1 and a second panel constant voltage bus PVB2. In another implementation, the sub-pixel circuit SPC may include a first sub-pixel circuit SPC1 and a second sub-pixel circuit SPC2. For example, the first sub-pixel circuit SPC1 may provide a first panel constant voltage, and the second sub-pixel circuit SPC2 may provide a second panel constant voltage different from the first panel constant voltage. For example, the first sub-pixel circuit SPC1 may be a sub-pixel circuit electrically connected to a red light-emitting diode (LED). The second sub-pixel circuit SPC2 may be a sub-pixel circuit electrically connected to a green or blue LED. Furthermore, the first panel constant voltage may be a first anode initialization voltage, and the second panel constant voltage may be a second anode initialization voltage.

[0220] The first sub-pixel circuit SPC1 can be electrically connected to the first horizontal panel constant voltage line HPVL1 and / or the third horizontal panel constant voltage line HPVL3. The first sub-pixel circuit SPC1 can receive the first panel constant voltage from the first horizontal panel constant voltage line HPVL1 and / or the third horizontal panel constant voltage line HPVL3.

[0221] The second sub-pixel circuit SPC2 can be electrically connected to the second horizontal panel constant voltage line HPVL2 and / or the fourth horizontal panel constant voltage line HPVL4. The second sub-pixel circuit SPC2 can receive the second panel constant voltage from the second horizontal panel constant voltage line HPVL2 and / or the fourth horizontal panel constant voltage line HPVL4.

[0222] The first horizontal panel constant voltage line HPVL1 can extend in the first direction D1 and can transmit the first panel constant voltage to the first sub-pixel circuit SPC1.

[0223] In this implementation, the first horizontal panel constant voltage line HPVL1 can be electrically connected to the first vertical panel constant voltage line VPVL1 via the first panel constant voltage connection pattern PVP1. The first horizontal panel constant voltage line HPVL1 can receive the first panel constant voltage via the first vertical panel constant voltage line VPVL1 and the first panel constant voltage connection pattern PVP1.

[0224] The second horizontal panel constant voltage line HPVL2 can extend in the first direction D1 and can transmit the constant voltage of the second panel to the second sub-pixel circuit SPC2.

[0225] In this embodiment, the second horizontal panel constant voltage line HPVL2 can be electrically connected to the second vertical panel constant voltage line VPVL2 via the second panel constant voltage connection pattern PVP2. The second horizontal panel constant voltage line HPVL2 can receive the second panel constant voltage via the second vertical panel constant voltage line VPVL2 and the second panel constant voltage connection pattern PVP2.

[0226] The third horizontal panel constant voltage line HPVL3 can extend in the first direction D1 and can transmit the first panel constant voltage to the first sub-pixel circuit SPC1.

[0227] In this implementation, the third horizontal panel constant voltage line HPVL3 can be electrically connected to the third vertical panel constant voltage line VPVL3 via the third panel constant voltage connection pattern PVP3. The third horizontal panel constant voltage line HPVL3 can receive the constant voltage from the first panel via the third vertical panel constant voltage line VPVL3 and the third panel constant voltage connection pattern PVP3.

[0228] The fourth horizontal panel constant voltage line HPVL4 can extend in the first direction D1 and can transmit the second panel constant voltage to the second sub-pixel circuit SPC2.

[0229] In this implementation, the fourth horizontal panel constant voltage line HPVL4 can be electrically connected to the fourth vertical panel constant voltage line VPVL4 via the fourth panel constant voltage connection pattern PVP4. The fourth horizontal panel constant voltage line HPVL4 can receive the constant voltage from the second panel via the fourth vertical panel constant voltage line VPVL4 and the fourth panel constant voltage connection pattern PVP4.

[0230] The first horizontal low power supply voltage connection pattern HSP1 may extend in the first direction D1. In an embodiment, the first horizontal low power supply voltage connection pattern HSP1 may be connected to at least one of the first vertical low power supply voltage line VSL1, the second vertical low power supply voltage line VSL2, the third vertical low power supply voltage line VSL3, the fourth vertical low power supply voltage line VSL4, the fifth vertical low power supply voltage line VSL5, and the sixth vertical low power supply voltage line VSL6.

[0231] The second horizontal low power supply voltage connection pattern HSP2 may extend in the first direction D1. In an embodiment, the second horizontal low power supply voltage connection pattern HSP2 may be connected to at least one of the first vertical low power supply voltage line VSL1, the second vertical low power supply voltage line VSL2, the third vertical low power supply voltage line VSL3, the fourth vertical low power supply voltage line VSL4, the fifth vertical low power supply voltage line VSL5, and the sixth vertical low power supply voltage line VSL6.

[0232] The third horizontal low power supply voltage connection pattern HSP3 may extend in the first direction D1. In an embodiment, the third horizontal low power supply voltage connection pattern HSP3 may be connected to at least one of the seventh vertical low power supply voltage line VSL7 and the eighth vertical low power supply voltage line VSL8.

[0233] The fourth horizontal low power supply voltage connection pattern HSP4 may extend in the first direction D1. In an embodiment, the fourth horizontal low power supply voltage connection pattern HSP4 may be connected to at least one of the seventh vertical low power supply voltage line VSL7 and the eighth vertical low power supply voltage line VSL8.

[0234] The first vertical low power supply voltage line VSL1 may extend in the second direction D2. In an embodiment, the first vertical low power supply voltage line VSL1 may be connected to a first horizontal low power supply voltage connection pattern HSP1 and a second horizontal low power supply voltage connection pattern HSP2 via contact holes. The first vertical low power supply voltage line VSL1 may transmit a low power supply voltage ELVSS.

[0235] The second vertical low power supply voltage line VSL2 may extend in the second direction D2. In an embodiment, the second vertical low power supply voltage line VSL2 may be connected to the first horizontal low power supply voltage connection pattern HSP1 and the second horizontal low power supply voltage connection pattern HSP2 via contact holes. The second vertical low power supply voltage line VSL2 may transmit a low power supply voltage ELVSS.

[0236] The first vertical panel constant voltage line VPVL1 can extend in the second direction D2. In an embodiment, the first vertical panel constant voltage line VPVL1 can be electrically connected to the first horizontal panel constant voltage line HPVL1 via the first panel constant voltage connection pattern PVP1. The first vertical panel constant voltage line VPVL1 can transmit the first panel constant voltage.

[0237] The second vertical panel constant voltage line VPVL2 can extend in the second direction D2. In an embodiment, the second vertical panel constant voltage line VPVL2 can be electrically connected to the second horizontal panel constant voltage line HPVL2 via the second panel constant voltage connection pattern PVP2. The second vertical panel constant voltage line VPVL2 can transmit the constant voltage of the second panel.

[0238] A third vertical low power supply voltage line VSL3 may extend in the second direction D2. In an embodiment, the third vertical low power supply voltage line VSL3 may be connected to the first horizontal low power supply voltage connection pattern HSP1 and the second horizontal low power supply voltage connection pattern HSP2 via contact holes. The third vertical low power supply voltage line VSL3 may transmit a low power supply voltage ELVSS.

[0239] The fourth vertical low power supply voltage line VSL4 may extend in the second direction D2. In an embodiment, the fourth vertical low power supply voltage line VSL4 may be connected to the first horizontal low power supply voltage connection pattern HSP1 and the second horizontal low power supply voltage connection pattern HSP2 via contact holes. The fourth vertical low power supply voltage line VSL4 may transmit a low power supply voltage ELVSS.

[0240] The fifth vertical low power supply voltage line VSL5 can extend in the second direction D2. In an embodiment, the fifth vertical low power supply voltage line VSL5 can be connected to the first horizontal low power supply voltage connection pattern HSP1 and the second horizontal low power supply voltage connection pattern HSP2 via contact holes. The fifth vertical low power supply voltage line VSL5 can transmit a low power supply voltage ELVSS.

[0241] The sixth vertical low power supply voltage line VSL6 may extend in the second direction D2. In an embodiment, the sixth vertical low power supply voltage line VSL6 may be connected to the first horizontal low power supply voltage connection pattern HSP1 and the second horizontal low power supply voltage connection pattern HSP2 via contact holes. The sixth vertical low power supply voltage line VSL6 may transmit a low power supply voltage ELVSS.

[0242] The third vertical panel constant voltage line VPVL3 can extend in the second direction D2. In an embodiment, the third vertical panel constant voltage line VPVL3 can be electrically connected to the third horizontal panel constant voltage line HPVL3 via the third panel constant voltage connection pattern PVP3. The third vertical panel constant voltage line VPVL3 can transmit the constant voltage of the first panel.

[0243] The fourth vertical panel constant voltage line VPVL4 can extend in the second direction D2. In an embodiment, the fourth vertical panel constant voltage line VPVL4 can be electrically connected to the fourth horizontal panel constant voltage line HPVL4 via the fourth panel constant voltage connection pattern PVP4. The fourth vertical panel constant voltage line VPVL4 can transmit the constant voltage of the second panel.

[0244] The seventh vertical low power supply voltage line VSL7 can extend in the second direction D2. In an embodiment, the seventh vertical low power supply voltage line VSL7 can be connected to the third horizontal low power supply voltage connection pattern HSP3 and the fourth horizontal low power supply voltage connection pattern HSP4 via contact holes. The seventh vertical low power supply voltage line VSL7 can transmit a low power supply voltage ELVSS.

[0245] The eighth vertical low power supply voltage line VSL8 may extend in the second direction D2. In an embodiment, the eighth vertical low power supply voltage line VSL8 may be connected to the third horizontal low power supply voltage connection pattern HSP3 and the fourth horizontal low power supply voltage connection pattern HSP4 via contact holes. The eighth vertical low power supply voltage line VSL8 may transmit a low power supply voltage ELVSS.

[0246] In this embodiment, the first vertical low power supply voltage line VSL1, the second vertical low power supply voltage line VSL2, the first vertical panel constant voltage line VPVL1, the second vertical panel constant voltage line VPVL2, the third vertical low power supply voltage line VSL3, the fourth vertical low power supply voltage line VSL4, the fifth vertical low power supply voltage line VSL5, the sixth vertical low power supply voltage line VSL6, the third vertical panel constant voltage line VPVL3, the fourth vertical panel constant voltage line VPVL4, the seventh vertical low power supply voltage line VSL7, and the eighth vertical low power supply voltage line VSL8 can be disposed on the same layer and formed together.

[0247] In this embodiment, the first vertical low power supply voltage line VSL1, the second vertical low power supply voltage line VSL2, the first vertical panel constant voltage line VPVL1, the second vertical panel constant voltage line VPVL2, the third vertical low power supply voltage line VSL3, the fourth vertical low power supply voltage line VSL4, the fifth vertical low power supply voltage line VSL5, the sixth vertical low power supply voltage line VSL6, the third vertical panel constant voltage line VPVL3, the fourth vertical panel constant voltage line VPVL4, the seventh vertical low power supply voltage line VSL7, and the eighth vertical low power supply voltage line VSL8 can extend in the second direction D2 and be arranged parallel to the first direction D1.

[0248] The display devices DD1, DD2, and DD3 according to the embodiments can be applied to various electronic devices. The electronic devices according to the embodiments may include the aforementioned display devices DD1, DD2, and DD3, and may also include modules or devices with additional functions in addition to the display devices DD1, DD2, and DD3.

[0249] Figure 19 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0250] refer to Figure 19 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0251] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0252] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application program stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0253] The power module 14 may include a power supply module such as a power adapter, a battery device, etc., and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0254] At least one of the components of the electronic device 10 described above may be included in the display device according to the embodiment. Furthermore, some of the individual modules functionally comprised in a single module may be included in the display device, and other individual modules may be disposed separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be configured as other devices in the electronic device 10 besides the display device.

[0255] Figure 20 This is a schematic diagram of an electronic device.

[0256] refer to Figure 20The various electronic devices using the display device according to the embodiments may include not only image display electronic devices, but also wearable electronic devices including display modules, vehicle electronic devices 10_3 including display modules, etc. Image display electronic devices may be smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, desktop monitors 10_1e, etc. Wearable electronic devices may be smart glasses 10_2a, head-mounted displays 10_2b, smartwatches 10_2c, etc. Vehicle electronic devices 10_3 may be central information displays (CIDs) installed on the vehicle's dashboard and central instrument panel, interior mirror displays, etc.

[0257] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A display device comprising: a sub-pixel circuit disposed on a substrate and arranged in a first direction and a second direction intersecting the first direction; a horizontal panel constant voltage line disposed on the substrate, extending in the first direction, and transmitting a panel constant voltage to the sub-pixel circuit; a vertical panel constant voltage line disposed on the horizontal panel constant voltage line, extending in the second direction, and transmitting the panel constant voltage to the horizontal panel constant voltage line; and a vertical bypass data line disposed on the same layer as the vertical panel constant voltage line, extending in the second direction, and transmitting a data voltage to the sub-pixel circuit. The vertical panel constant voltage line is disconnected from the vertical bypass data line.

2. The display device according to claim 1, wherein 3.The display device of claim 1, further comprising: a panel constant voltage connection pattern disposed between the horizontal panel constant voltage line and the vertical panel constant voltage line, and electrically connecting the horizontal panel constant voltage line and the vertical panel constant voltage line. The panel constant voltage is sequentially transmitted along the vertical panel constant voltage line, the panel constant voltage connection pattern, and the horizontal panel constant voltage line.

4. The display device according to claim 3, wherein 5.The display device of claim 3, further comprising: a horizontal low power voltage connection pattern disposed on the same layer as the panel constant voltage connection pattern; and a vertical low power voltage line disposed on the same layer as the vertical panel constant voltage line, connected to the horizontal low power voltage connection pattern, and transmitting a low power voltage. The vertical low power voltage line extends in the second direction and is arranged parallel to the vertical panel constant voltage line along the first direction. The horizontal low power voltage connection pattern and the panel constant voltage connection pattern extend in the first direction and are spaced apart from each other along the first direction.

6. The display device of claim 5, wherein, The horizontal low power voltage connection pattern is disconnected from the panel constant voltage connection pattern.

7. The display device according to claim 5, wherein The vertical low power voltage line includes a first vertical low power voltage line, a second vertical low power voltage line, and a third vertical low power voltage line, and 8. The display device of claim 7, wherein, wherein the first vertical low power voltage line, the vertical panel constant voltage line, the second vertical low power voltage line, and the third vertical low power voltage line are sequentially arranged from a first side to a second side of the display device and are parallel along the first direction.

9. The display device according to claim 5, wherein The horizontal low power voltage connection pattern includes a first horizontal low power voltage connection pattern and a second horizontal low power voltage connection pattern, wherein the first horizontal low power voltage connection pattern is electrically connected to the first vertical low power voltage line, and 10. The display device of claim 9, wherein, wherein the second horizontal low power voltage connection pattern is electrically connected to the second vertical low power voltage line and the third vertical low power voltage line. The first horizontal low power voltage connection pattern, the panel constant voltage connection pattern, and the second horizontal low power voltage connection pattern extend in the first direction and are spaced apart from each other along the first direction. The vertical low power voltage line further includes a fourth vertical low power voltage line, a fifth vertical low power voltage line, and a sixth vertical low power voltage line, 11. The display device of claim 10, wherein, wherein the vertical panel constant voltage line includes a first vertical panel constant voltage line and a second vertical panel constant voltage line, and 12. The display device of claim 10, wherein, wherein the first vertical panel constant voltage line is electrically connected to the fourth vertical low power voltage line, and wherein the second vertical panel constant voltage line is electrically connected to the fifth vertical low power voltage line and the sixth vertical low power voltage line. The fourth vertical low power voltage line, the second vertical panel constant voltage line, the fifth vertical low power voltage line, and the sixth vertical low power voltage line are sequentially arranged from the first side to the second side of the display device and are parallel along the first direction.

13. The display device of claim 12, wherein, The panel constant voltage connection pattern includes a first panel constant voltage connection pattern and a second panel constant voltage connection pattern, The first panel constant voltage connection pattern is electrically connected to the first vertical panel constant voltage line, and The second panel constant voltage connection pattern is electrically connected to the second vertical panel constant voltage line.

14. The display device of claim 12, wherein, The second horizontal low power voltage connection pattern is further electrically connected to the fourth vertical low power voltage line, the fifth vertical low power voltage line, and the sixth vertical low power voltage line.

15. The display device of claim 13, wherein, The horizontal low power voltage connection pattern further includes a third horizontal low power voltage connection pattern and a fourth horizontal low power voltage connection pattern, The third horizontal low power voltage connection pattern is electrically connected to the first vertical low power voltage line, the second vertical low power voltage line, the third vertical low power voltage line, and the fourth vertical low power voltage line, and The fourth horizontal low power voltage connection pattern is electrically connected to the fifth vertical low power voltage line and the sixth vertical low power voltage line.

16. The display device of claim 15, wherein, The third horizontal low power voltage connection pattern, the second panel constant voltage connection pattern, and the fourth horizontal low power voltage connection pattern extend in the first direction and are spaced apart from each other along the first direction, and The first panel constant voltage connection pattern and the second panel constant voltage connection pattern are spaced apart from each other along the second direction.

17. The display device of claim 5, wherein, The vertical low power voltage line includes a first vertical low power voltage line and a second vertical low power voltage line, The vertical panel constant voltage line includes a first vertical panel constant voltage line and a second vertical panel constant voltage line, and The first vertical low power voltage line, the second vertical low power voltage line, the first vertical panel constant voltage line, and the second vertical panel constant voltage line are sequentially arranged from the first side to the second side of the display device and are parallel along the first direction.

18. The display device of claim 17, wherein, The horizontal low power voltage connection pattern includes a first horizontal low power voltage connection pattern and a second horizontal low power voltage connection pattern, The first horizontal low power voltage connection pattern and the second horizontal low power voltage connection pattern are arranged in parallel along the second direction and are electrically connected to the first vertical low power voltage line and the second vertical low power voltage line, and The panel constant voltage connection pattern is arranged spaced apart from the second horizontal low power voltage connection pattern along the first direction and is electrically connected to the first vertical panel constant voltage line and the second vertical panel constant voltage line.

19. The display device of claim 5, wherein the vertical panel constant voltage line includes a first vertical panel constant voltage line and a second vertical panel constant voltage line, wherein The first vertical panel constant voltage line transmits a first panel constant voltage to a first sub-pixel circuit, The second vertical panel constant voltage line transmits a second panel constant voltage to a second sub-pixel circuit, and The first horizontal low power voltage connection pattern is electrically connected to the first vertical low power voltage line, and The second horizontal low power voltage connection pattern is electrically connected to the second vertical low power voltage line. Specifically, the second vertical panel constant voltage line transmits a second panel constant voltage, different from the first panel constant voltage, to the second sub-pixel circuit. The constant voltage of the panel is the anode initialization voltage for initializing the pixel electrode.

20. An electronic device comprising: Display device; as well as The power module is configured to provide power to the display device. The display device includes: Sub-pixel circuitry is disposed on a substrate and arranged in a first direction and a second direction intersecting the first direction; A horizontal panel constant voltage line is disposed on the substrate, extends in the first direction, and transmits the panel constant voltage to the sub-pixel circuit. A vertical panel constant voltage line, disposed on the horizontal panel constant voltage line, extends in the second direction and transmits the panel constant voltage to the horizontal panel constant voltage line; and The vertical bypass data line is disposed on the same layer as the vertical panel constant voltage line, extends in the second direction, and transmits the data voltage to the sub-pixel circuit.

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