Wafer transfer control method and transfer control system

Abstract

The application provides a wafer conveying control method and a conveying control system, which comprises the following steps: collecting equipment state and position data through a sensor network to form an equipment state matrix; determining an available equipment set of each process node according to the matrix and a processing flow; constructing a directed weighted graph with the equipment as a node and the transmission distance and real-time load as an edge weight; searching for multiple paths from a starting point to an ending point by using a path search algorithm to generate a cost ranking list; selecting a path with the lowest cost as a scheme and simulating and verifying the transmission time of the path, if the efficiency is not up to the standard, iteratively adjusting the edge weight to integrate the real-time load change and optimizing the path ranking; and finally issuing an optimal path instruction to a conveying track through a controller. The application can realize real-time sensing, dynamic mapping and path optimization, effectively improve the conveying efficiency, reduce the delay, and enhance the production line stability and equipment utilization.

Description

Technical Field

[0001] This invention relates to the field of wafer transfer control technology, and in particular to a wafer transfer control method and transfer control system. Background Technology

[0002] Semiconductor manufacturing, as the core foundation of the modern electronics industry, directly impacts the development level of the entire electronics supply chain through its production efficiency and product quality. During semiconductor production, wafers need to be frequently transferred between different process equipment, and the wafer transfer control system plays a crucial role in ensuring the safe, accurate, and efficient flow of wafers. As chip manufacturing processes become increasingly complex, a single production line may involve hundreds of processes and dozens of different types of processing equipment, highlighting the growing importance of wafer transfer control.

[0003] Current wafer transport systems generally employ a pre-defined fixed path control method, which demonstrates significant inadequacy in adapting to changes in the production environment. Existing systems often determine the transport path based on the initial equipment configuration and process flow. Once the production line needs to adjust the equipment layout or introduce a new process flow, the entire transport system requires large-scale hardware modifications and software reconfigurations. This rigid design philosophy makes the production line lack the necessary flexibility to cope with changes in market demand and technological upgrades, resulting in high modification costs and long downtime for enterprises during production line adjustments.

[0004] In real-world production environments, the reconfigurability of conveyor paths and the intelligence of path selection are closely related. The reconfigurability of the conveyor track determines how many different path combinations the system can support, while the intelligence level of the path selection algorithm directly affects whether the system can make optimal path decisions based on real-time production conditions. When a critical piece of equipment on the production line malfunctions and requires maintenance, if the conveyor system cannot quickly reconfigure an alternative path, the entire production line will come to a standstill. Furthermore, even if the hardware has the physical foundation for path reconfiguration, the lack of an intelligent path selection mechanism cannot fully leverage this flexibility, and the system will still struggle to cope with complex and ever-changing production scheduling demands.

[0005] This technological limitation is particularly pronounced in real-world business scenarios. For example, when a production line needs to process two different wafer products using different manufacturing processes simultaneously, the two products require different equipment sequences due to the differences in process flows. Traditional fixed-path systems often operate only according to a pre-set single process, unable to simultaneously accommodate the transport needs of two products, leading to a significant decrease in production efficiency. A more complex situation arises when a process equipment temporarily fails and needs to be switched to a backup device; the entire transport path needs to be adjusted accordingly, but existing systems lack dynamic path planning capabilities, making smooth path switching impossible. Summary of the Invention

[0006] Therefore, the technical problem to be solved by the present invention is to overcome the lack of dynamic path planning capability in the existing wafer transfer control and the inability to achieve smooth path switching. The present invention provides a wafer transfer control method and a transfer control system that can effectively improve wafer transfer efficiency, reduce transmission delay and enhance the overall stability of the production line and equipment utilization by sensing the equipment status and load in real time, dynamically constructing and optimizing the path planning diagram, and adjusting the transmission path based on iterative feedback.

[0007] To address the aforementioned technical problems, this invention provides a wafer transfer control method, comprising the following steps:

[0008] By collecting real-time operating status and location coordinate data of all processing equipment in the wafer production line through a sensor network, an equipment status matrix containing equipment availability indicators and load levels is obtained.

[0009] Based on the equipment status matrix and the preset wafer process flow sequence, the set of processing equipment that can be used for the wafer process flow sequence is determined, and the set of processing equipment is mapped to the corresponding wafer process flow sequence.

[0010] Using the processing equipment in the set of processing equipment as nodes, the edge weights are calculated based on the transmission distance between wafer process flow sequences and the real-time load level to construct a directed weighted graph for path planning;

[0011] A path search algorithm is used to search for multiple alternative paths from the starting node to the target node in the directed weighted graph, and the cost of each path is calculated to generate a path cost ranking list.

[0012] The path with the lowest cost is selected as the current transmission scheme based on the path cost ranking list, and the transmission time of the path under the load level is verified by simulation. When the transmission efficiency does not meet the expected requirements, the edge weights are iteratively adjusted to incorporate real-time load changes, and an optimized path cost ranking list is obtained.

[0013] The controller sends a sequence of instructions to the preferred path from the optimized path cost ranking list to the transport track, thereby obtaining the wafer processing transport execution plan.

[0014] In one embodiment of the present invention, a sensor network is used to collect real-time operating status and location coordinate data of all processing equipment in the wafer production line, and an equipment status matrix including equipment availability identifiers and load levels is obtained, including:

[0015] By distributing multiple types of sensors at key monitoring points of the processing equipment, real-time data on operating status, including equipment start / stop status, operating power, wafer in-situ signals, and absolute coordinate data of the equipment obtained through the positioning module are collected.

[0016] The collected raw status and coordinate data are processed by signal filtering and outlier removal to generate standardized equipment status messages;

[0017] The standardized device status messages are associated and matched with device identifiers, and availability identifiers including "normal", "busy" and "faulty" are generated according to the preset device health assessment rules.

[0018] Real-time statistics are collected on the number of wafers to be processed and the estimated processing time for each device, and the dynamic load level is calculated based on the current operating power.

[0019] The device identifier, availability identifier, dynamic load level value and location coordinate data are integrated and updated to the device status matrix at a preset cycle.

[0020] In one embodiment of the present invention, a set of processing equipment that can be used for the wafer process sequence is determined based on a device state matrix and a preset wafer process sequence, and the set of processing equipment is mapped to the corresponding wafer process sequence, including:

[0021] Generate a process node allocation template based on the preset wafer process flow sequence;

[0022] By using a mapping relationship, the subset of available equipment is matched with the process node allocation template to generate an equipment process allocation matrix;

[0023] By analyzing the equipment process allocation matrix, the node allocation status of each device can be obtained to determine whether there are node allocation conflicts.

[0024] If node allocation conflicts exist, the equipment process allocation matrix is ​​readjusted according to the priority of the wafer process flow sequence to obtain an optimized allocation matrix.

[0025] Based on the optimized allocation matrix, a device operation scheduling sequence is generated to determine the final execution order of process nodes.

[0026] In one embodiment of the present invention, using the processing equipment in the set of processing equipment as nodes, edge weights are calculated based on the transmission distance between wafer process flow sequences and the real-time load level to construct a directed weighted graph for path planning, including:

[0027] Based on the sequence of wafer fabrication processes, determine the connection relationships between each processing device and establish a preliminary device connection topology.

[0028] Obtain the actual physical location coordinates of all available processing equipment between adjacent process nodes, and calculate the actual transmission path distance between the equipment;

[0029] Real-time monitoring of the current load status of each processing equipment, acquisition of equipment load level data, and calculation of the load impact coefficient based on the equipment processing capacity;

[0030] The transmission path distance and load impact coefficient are weighted and fused to generate edge weight values ​​that characterize the path transmission cost.

[0031] Based on the device connection topology and the calculated edge weight values, a complete directed weighted graph structure is constructed.

[0032] In one embodiment of the present invention, the connectivity of the constructed directed weighted graph is verified to ensure that there are reachable paths between all process nodes;

[0033] If there are disconnected process nodes in the path planning graph, the list of idle processing equipment in the spare equipment pool is obtained through the graph search algorithm, and the updated set of available processing equipment is obtained.

[0034] Based on the set of available processing equipment, extract the operating parameters of the currently idle processing equipment from the equipment status matrix to determine the priority order of the equipment to be activated;

[0035] The device activation state is switched from idle to running through the state update mechanism to obtain the updated device state matrix;

[0036] Based on the updated equipment status matrix, the connectivity between process nodes in the path planning graph is recalculated using a depth-first search algorithm to determine whether the connectivity has been restored.

[0037] If connectivity is restored, the directed weighted graph used for path planning is updated by expanding the set of devices.

[0038] In one embodiment of the present invention, a path search algorithm is used to search for multiple candidate paths from the starting node to the target node in the directed weighted graph, and the cost of each path is calculated to generate a path cost ranking list, including:

[0039] Identify the equipment nodes corresponding to the starting process node and the target process node from the directed weighted graph, and use them as the starting and ending points for path search;

[0040] Starting from the origin, explore all possible device node transfer paths step by step according to the connection relationships and edge weights between device nodes;

[0041] During the path exploration process, the sequence of device nodes traversed and the accumulated edge weight values ​​are recorded in real time, forming multiple complete device node transfer paths;

[0042] For each device node transfer path, the overall path cost is calculated based on its cumulative edge weight, the load level of the devices in the path, and the path length.

[0043] Sort all the discovered device node transfer paths from low to high according to the overall path cost, and generate a path cost sorting list.

[0044] In one embodiment of the present invention, selecting the path with the lowest cost as the current transmission scheme according to the path cost ranking list, and verifying the transmission time of the path under load level through simulation, includes:

[0045] Select the device node transfer path with the lowest cumulative cost value from the path cost ranking list as the preferred transmission scheme;

[0046] In the preferred transmission scheme, obtain real-time load level data for each device node;

[0047] Based on the physical distance between device nodes and the current load status of each device, the transmission time of the wafer between each device node is simulated and calculated.

[0048] By summing the transmission times between each segment of device nodes, the total transmission time estimate of the preferred transmission scheme is obtained.

[0049] The estimated total transmission time is compared with the preset standard transmission time threshold to verify the timeliness feasibility of the transmission scheme.

[0050] Generate a transmission scheme evaluation report that includes the device node sequence, estimated transmission time, and verification results.

[0051] In one embodiment of the present invention, when the transmission scheme evaluation report shows that the total transmission time exceeds the standard transmission time threshold, the edge weight adjustment process is initiated;

[0052] Obtain the latest load status data of each device node in the directed weighted graph;

[0053] The edge weights between the corresponding device nodes are dynamically adjusted based on changes in the load levels of the device nodes.

[0054] Based on the adjusted edge weights, the cumulative cost of the transfer path for each device node is recalculated;

[0055] Reorder the device node transfer paths according to the updated cumulative cost values;

[0056] Generate an optimized path cost ranking list, and re-select the transmission scheme and verify the transmission time;

[0057] Repeat the above adjustment process until a transmission scheme that meets the transmission time requirements is obtained, or select the current optimal scheme when the maximum number of iterations is reached.

[0058] In one embodiment of the present invention, a wafer processing transport execution plan is obtained by issuing a sequence of instructions for the preferred path in the optimized path cost ranking list to the transport track via a controller, including:

[0059] The controller sends a sequence of commands to the transport track to determine the track control parameters;

[0060] Based on the track control parameters, a wafer transfer execution plan is generated;

[0061] Obtain real-time feedback data of the execution plan; if the feedback data exceeds a preset threshold, adjust the instruction sequence.

[0062] Based on the adjusted instruction sequence, update the track control parameters and generate a new execution plan;

[0063] The controller issues an updated execution plan, which yields the final wafer transfer execution result.

[0064] To address the aforementioned technical problems, the present invention also provides a wafer transfer control system for implementing the above-mentioned wafer transfer control method, comprising:

[0065] The data acquisition module is used to collect real-time operating status and location coordinate data of all processing equipment in the wafer production line through a sensor network, and obtain an equipment status matrix that includes equipment availability indicators and load levels;

[0066] The equipment set determination module is used to determine the set of processing equipment that can be used for the wafer process flow sequence based on the equipment status matrix and the preset wafer process flow sequence, and to map the set of processing equipment to the corresponding wafer process flow sequence.

[0067] The graph construction module is used to construct a directed weighted graph for path planning by using the processing equipment in the set of processing equipment as nodes and calculating the edge weights based on the transmission distance between wafer process flow sequences and the real-time load level.

[0068] The path search module is used to search for multiple alternative paths from the starting node to the target node in the directed weighted graph using a path search algorithm, calculate the cost of each path, and generate a path cost ranking list.

[0069] The path optimization module is used to select the path with the lowest cost as the current transmission scheme according to the path cost ranking list, and to verify the transmission time of the path under the load level through simulation; when the transmission efficiency does not meet the expected requirements, the edge weights are iteratively adjusted to incorporate real-time load changes to obtain the optimized path cost ranking list.

[0070] The execution control module is used to send the instruction sequence of the preferred path in the optimized path cost ranking list to the transport track through the controller, so as to obtain the wafer processing transport execution plan.

[0071] The technical solution of the present invention has the following advantages over the prior art:

[0072] This invention provides a wafer transport control method. First, a sensor network is deployed to continuously collect the operating status, position coordinates, and real-time load data of each processing device, constructing a device status matrix reflecting the real-time status of the entire production line. This provides a precise data foundation for subsequent dynamic decision-making. Next, the device status is matched with a predefined wafer processing flow, selecting a set of processing devices suitable for each process node. This ensures that path planning is based on currently available resources, avoiding the risk of assigning tasks to faulty or busy devices from the outset. Based on this, a graph theory modeling method is used to abstract each available device as a node in the graph. Edge weights are dynamically calculated based on the actual transmission distance between devices and the real-time load level, thereby constructing a directed weighted graph that maps the physical world state. This step significantly reduces the complexity of the process. The physical layout and dynamic production status of the graph are transformed into a computable mathematical model, providing a structured optimization framework for subsequent path search. Then, a path search algorithm is used to efficiently retrieve multiple feasible paths from the starting point to the end point in the graph, and a ranking list is generated based on the cost model, enabling rapid comparison among multiple alternatives. Notably, this method does not stop at a single calculation but introduces an optimization mechanism based on simulation verification and iterative feedback: by simulating the transmission time of the initially selected scheme and dynamically adjusting edge weights to incorporate the latest load changes when efficiency is insufficient, online self-optimization of path planning is achieved, significantly enhancing the adaptability to dynamic changes in the production environment. Finally, the optimized optimal path instruction sequence is sent to the transmission track for execution through the controller, forming a complete closed-loop control.

[0073] From a theoretical perspective, this technical solution effectively addresses the issues of insufficient dynamic response and limited global optimization capabilities identified in the background technology through the synergy of multiple layers of technical features. Real-time data acquisition and the construction of the state matrix lay the foundation for global perception, enabling the system to "see" the status of the entire production line. The determination of the equipment set based on the processing flow ensures resource availability under process constraints. The construction of the directed weighted graph transforms the scheduling problem in physical space into a graph optimization problem in the mathematical domain, making complex multi-objective decisions computable and optimizable. Dynamic path search and cost ranking enable rapid global optimization among multiple paths. The iterative weight adjustment mechanism based on simulation verification introduces a feedback loop, enabling dynamic route adjustment based on real-time road conditions (load), much like "autonomous driving," thus avoiding the inherent lag in response of traditional static rule systems.

[0074] Therefore, the beneficial effects of this method are obvious: it can significantly improve the overall efficiency and flexibility of the conveying system, effectively reduce wafer waiting time and transmission delay through dynamic obstacle avoidance and load balancing, and enhance the overall stability and capacity of the production line by improving equipment utilization and reducing the risk of blockage; the whole process does not require human intervention, providing an effective technical means for achieving efficient and reliable material conveying in semiconductor intelligent manufacturing. Attached Figure Description

[0075] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein:

[0076] Figure 1 This is a flowchart of the wafer transfer control method of the present invention;

[0077] Figure 2 This is a flowchart of the steps for data acquisition and device status matrix generation in this invention;

[0078] Figure 3 This is a flowchart illustrating the steps of determining the set of processing equipment and mapping it to a process sequence according to the present invention.

[0079] Figure 4 This is a flowchart of the steps for constructing a directed weighted graph according to the present invention;

[0080] Figure 5 This is a flowchart of the steps involved in generating the path search and cost sorting list according to the present invention;

[0081] Figure 6 This is a flowchart of the path simulation verification and iterative optimization steps of the present invention;

[0082] Figure 7 This is a flowchart illustrating the steps involved in generating and issuing an execution plan according to the present invention.

[0083] Figure 8 This is a structural framework diagram of the wafer transfer control system of the present invention. Detailed Implementation

[0084] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0085] Reference Figure 1As shown, this invention discloses a wafer transport control method, comprising the following steps: collecting real-time operating status and position coordinate data of all processing equipment in the wafer production line through a sensor network to obtain an equipment status matrix containing equipment availability identifiers and load levels; determining a set of processing equipment that can be used for the wafer process flow sequence based on the equipment status matrix and a preset wafer process flow sequence, and mapping the set of processing equipment to the corresponding wafer process flow sequence; using the processing equipment in the set of processing equipment as nodes, calculating edge weights based on the transmission distance between wafer process flow sequences and the real-time load level to construct a directed weighted graph for path planning; using a path search algorithm to search for multiple alternative paths from the starting node to the target node in the directed weighted graph, calculating the cost of each path, and generating a path cost ranking list; selecting the path with the lowest cost as the current transport scheme based on the path cost ranking list, and verifying the transmission time of the path under the load level through simulation; when the transmission efficiency does not meet the expected requirements, iteratively adjusting the edge weights to incorporate real-time load changes to obtain an optimized path cost ranking list; and issuing an instruction sequence of the preferred path in the optimized path cost ranking list to the transport track through the controller to obtain a wafer processing transport execution plan.

[0086] The sensor network refers to various types of sensing devices deployed at key monitoring points of the processing equipment. Specifically, it can be implemented using distributed pressure sensors, infrared positioning modules, and power monitoring units to capture real-time equipment start-up and shutdown status and spatial location data. The equipment status matrix is ​​a structured dataset containing equipment availability, load level, and coordinate information. It can be generated by associating equipment identifiers with standardized status messages to reflect the real-time operating status of the equipment. The directed weighted graph is a network topology with processing equipment as nodes and transmission paths as edges. It can be constructed using Dijkstra's algorithm, with edge weights calculated by weighting transmission distance and load coefficients to quantify path transmission costs. The path search algorithm is a computational method for finding the optimal equipment node transfer path. It can be implemented using the A* algorithm or dynamic programming, generating multiple candidate paths by traversing node connections. Simulation verification refers to the process of estimating the transmission time of the selected path. It can be implemented using a discrete event simulation model, verifying path feasibility by loading real-time load data.

[0087] Specifically, the sensor network continuously collects operating power, wafer in-situ signals, and 3D coordinate data from each processing device. After filtering, standardized device status messages are generated. These messages are associated with device identifiers, and a device status matrix containing availability status is generated based on health assessment rules. A set of available devices is matched according to a preset process sequence, establishing a mapping relationship between process nodes and physical devices. The transmission distance between adjacent nodes is calculated using devices as nodes, and edge weights are generated based on real-time load coefficients to construct a directed weighted graph reflecting the current production status. An improved A* algorithm is used to search for multiple paths from the starting node to the target node, and a cost list is generated by sorting the paths according to cumulative weight values. The lowest-cost path is selected for discrete event simulation to simulate the transmission time of the wafer between device nodes. When the simulation results exceed a preset threshold, the edge weights are dynamically adjusted and the path cost is recalculated, iteratively optimizing until a feasible solution is obtained. Finally, the optimized path command sequence is sent to the conveyor track actuator via an industrial controller.

[0088] Compared to existing technologies, traditional methods rely on fixed path configuration tables for unidirectional transmission control. This solution achieves multi-dimensional path planning by dynamically constructing a weighted graph. Existing methods only activate backup paths in case of equipment failure, while this solution continuously monitors load changes and adjusts weight parameters in real time. Conventional path search only considers physical distance factors, while this solution comprehensively calculates transmission costs and load impacts to achieve global optimization. Traditional verification methods rely on manual estimation, while this solution uses digital twin technology to simulate transmission under load conditions.

[0089] Through the above technical solutions, this application achieves dynamic perception of production line equipment status and real-time optimization of path planning, effectively solving the path conflict problem during multi-process parallel production. In the event of sudden equipment failure, alternative paths can be quickly generated to avoid production interruptions. Dynamic weighted calculation of load coefficients balances the contradiction between equipment utilization and transmission efficiency. Simulation verification mechanisms ensure the reliability of the selected path in actual operation, reducing wafer congestion caused by improper path selection.

[0090] Reference Figure 2As shown, this application further proposes to collect real-time operating status and location coordinate data of all processing equipment in the wafer production line through a sensor network, and obtain an equipment status matrix containing equipment availability identifiers and load levels. This includes: collecting real-time operating status data, including equipment start / stop status, operating power, and wafer in-situ signals, as well as absolute coordinate data of the equipment obtained through a positioning module, using multiple types of sensors distributed at key monitoring points of the processing equipment; performing signal filtering and outlier removal processing on the collected raw status and coordinate data to generate standardized equipment status messages; associating and matching the standardized equipment status messages with equipment identifiers, and generating availability identifiers including normal, busy, and faulty based on preset equipment health assessment rules; calculating the number of wafers to be processed and the estimated processing time for each equipment in real time, and calculating the dynamic load level value based on the current operating power; and integrating the equipment identifiers, availability identifiers, dynamic load level values, and location coordinate data, and updating them to the equipment status matrix at preset intervals.

[0091] Among these, distributed multi-sensor deployment refers to various types of sensing devices distributed at key monitoring points of the processing equipment. Specifically, this can be achieved using a combination of temperature sensors, pressure sensors, and photoelectric sensors to comprehensively perceive the equipment's operating status. Signal filtering and outlier removal refers to the process of denoising and correcting the raw data. This can be implemented using a Kalman filter algorithm to eliminate random interference during signal acquisition. Equipment health assessment rules refer to the logical conditions for judging the equipment's operating status. These can be implemented using a combination of preset power thresholds and wafer in-situ time thresholds to form a quantitative standard for judging the equipment's availability status. Dynamic load level values ​​are indicators reflecting the equipment's current working pressure. These values ​​are calculated by multiplying the number of wafers to be processed by the unit processing time and then adding the ratio of operating power to rated power, representing the equipment's real-time workload.

[0092] Specifically, in a wafer fabrication line, a distributed sensor network is first used to collect real-time operating parameters and location information of each processing device. For example, photoelectric sensors are deployed at the feed inlet to detect wafer presence, and power sensors are installed at the motors to monitor operating power. The collected raw data is filtered to remove noise interference and then bound to a unique device identifier to form a standardized status message. Further, based on device health assessment rules, such as when operating power continuously exceeds 80% of the rated value, a busy state is determined, and an availability identifier is generated. Simultaneously, the load level is dynamically calculated by combining the length of the wafer queue and the current operating efficiency. Finally, all data is integrated into a matrix structure at a preset cycle, for example, updating the device status matrix every 5 seconds, providing real-time data support for subsequent path planning.

[0093] Compared to existing technologies, traditional methods typically rely on fixed-cycle manual inspections or single-sensor data collection, resulting in delayed data updates and limited data dimensionality. This solution, however, utilizes a distributed deployment of multiple sensors to achieve multi-dimensional real-time monitoring of operational status, such as simultaneously collecting key parameters like power and wafer in-situ signals. Furthermore, existing technologies lack effective mechanisms for handling abnormal data; this solution improves data reliability through signal filtering and outlier removal. Regarding load calculation, existing methods often use static queue length as a load indicator, while this solution combines dynamic calculations of processing time and power parameters to more accurately reflect the actual operating pressure of the equipment.

[0094] Through the above technical solutions, this application can acquire high-precision equipment status data in real time, solving the problems of incomplete equipment status information and update delays in traditional methods. For example, in the event of a sudden equipment failure, unavailable equipment can be quickly eliminated through immediate updates of fault indicators. Accurate calculation of dynamic load levels provides more realistic equipment load data for path planning, avoiding production delays caused by allocating wafers to overloaded equipment. The adoption of standardized data formats enables unified processing of status information from different devices, improving system compatibility and data processing efficiency.

[0095] Reference Figure 3 As shown, this application further proposes a method for determining the set of processing equipment that can be used for a wafer process sequence and mapping it to the corresponding wafer process sequence based on the equipment status matrix and a preset wafer process sequence. The method includes generating a process node allocation template; matching the available equipment subset with the process node allocation template to generate an equipment process allocation matrix; obtaining the node allocation status of each equipment by analyzing the equipment process allocation matrix and determining whether there is a node allocation conflict; if there is a conflict, readjusting the equipment process allocation matrix according to the priority of the wafer process sequence; generating an equipment operation scheduling sequence based on the optimized allocation matrix and determining the final process node execution order.

[0096] The process node allocation template refers to the pre-defined correspondence between process steps and equipment types based on the wafer process flow. This can be implemented using XML configuration files or database table structures, guiding the matching process between available equipment and process nodes. The equipment process allocation matrix is ​​a two-dimensional data structure reflecting the correspondence between equipment and process nodes. This can be implemented using hash tables or adjacency matrices, visually displaying the allocation of equipment within the process flow. Node allocation conflict refers to the situation where the same equipment is simultaneously allocated to multiple process nodes. This can be detected by traversing the rows and columns of the equipment process allocation matrix, identifying equipment resource contention issues. The priority adjustment mechanism refers to the reallocation of equipment resources based on the urgency of different processes in the flow. This can be implemented using weighted scoring algorithms or rule engines, resolving dynamic scheduling issues when equipment resource conflicts occur.

[0097] Specifically, the process node allocation template is pre-configured as structured data containing the equipment types and their order relationships required for each process step. When the equipment status matrix is ​​updated, a subset of available equipment is matched against the equipment type requirements in the template to generate an allocation matrix containing the correspondence between equipment and process nodes. By traversing the column vectors of the allocation matrix, it is detected whether the same equipment appears in multiple process nodes. If a conflict is detected, based on the priority weights marked in the process flow, the high-priority process node retains its original equipment allocation, while the low-priority node is re-matched with available equipment in the backup equipment pool. The adjusted allocation matrix is ​​then converted into an equipment operation scheduling sequence, forming a list of the order in which equipment executes process steps.

[0098] Compared to existing technologies, traditional methods employ fixed equipment allocation strategies, which prevent dynamic adjustments when equipment resource conflicts occur. This solution, however, generates a real-time equipment process allocation matrix and detects node allocation conflicts, combining this with a priority mechanism to achieve dynamic resource reallocation. Existing technologies suffer from excessive coupling between equipment allocation and process flow; this solution achieves flexible decoupling of equipment resource allocation through an independent matching mechanism between process node allocation templates and equipment state matrices.

[0099] Through the above technical solution, this application effectively solves the production line stagnation problem caused by equipment resource conflicts when multiple processes are running in parallel, ensuring that processes of different priorities can obtain the necessary equipment resources. The dynamic adjustment mechanism avoids the inefficient operation of manual intervention in equipment allocation, and improves equipment resource utilization through automated conflict detection and priority scheduling. The visualized structure of the equipment process allocation matrix provides decision support for production line scheduling, making the optimization and adjustment of the execution order of process nodes traceable.

[0100] Reference Figure 4As shown, this application further proposes to construct a directed weighted graph for path planning by using processing equipment in the processing equipment set as nodes and calculating edge weights based on the transmission distance and real-time load level between wafer process flow sequences. This includes: determining the connection relationships between processing equipment according to the sequence of wafer process flows and establishing a preliminary equipment connection topology; obtaining the actual physical coordinates of all available processing equipment between adjacent process nodes and calculating the actual transmission path distance between equipment; monitoring the current load status of each processing equipment in real time, obtaining equipment load level data, and calculating the load impact coefficient based on the equipment processing capacity; weighting and fusing the transmission path distance and load impact coefficient to generate edge weight values ​​characterizing the path transmission cost; and constructing a complete directed weighted graph structure based on the equipment connection topology and the calculated edge weight values.

[0101] The device connection topology refers to the logical connection relationship between devices established based on the wafer fabrication process sequence. This can be implemented using an adjacency list or adjacency matrix data structure to represent the reachability relationships between device nodes. The actual transmission path distance refers to the spatial interval between the physical locations of devices. This can be calculated using the Euclidean distance formula in a three-dimensional coordinate system to quantify the impact of path length on transmission costs. The load impact coefficient is the ratio of the device's current processing capacity to the number of tasks to be processed. This can be achieved by normalizing the device load level to a value in the 0-1 range, reflecting the impact of device processing latency on path selection. The edge weight value is a comprehensive evaluation index combining path length and device load. This can be achieved by using a linear weighting method to integrate transmission distance and load coefficients according to a preset ratio, characterizing the overall transmission cost of the path.

[0102] Specifically, in the wafer fabrication process, the logical connection topology between equipment is first established according to the process flow sequence. For example, a unidirectional connection is established between etching equipment and cleaning equipment. The physical location coordinates of equipment between adjacent process nodes are used to calculate the actual transmission distance. For instance, when the etching equipment and the cleaning equipment are located at coordinates (10,20,5) and (15,25,8) respectively, their distance can be calculated as follows: Meanwhile, the equipment load status is collected in real time by sensors. For example, if an etching machine currently has three wafers waiting to be processed in its processing queue, the expected load duration can be calculated by combining this with the processing time per wafer. Transmission distance and load coefficients are fused according to a preset weight ratio; for example, the distance weight is set to 0.6 and the load weight to 0.4, ultimately generating edge weight values. The weight values ​​of all device nodes and their connected edges together form a directed weighted graph, providing a data foundation for subsequent path planning.

[0103] Compared to existing technologies, traditional path planning methods only consider the physical distance between devices or fixed path costs, without incorporating dynamic load conditions into the calculation. For example, in existing technologies, when a device experiences processing delays due to excessive load, the path for that device is still selected according to a preset distance weight. This solution, however, collects device load data in real time and dynamically calculates edge weights based on physical distance, enabling path planning to automatically avoid high-load devices. For instance, when the load factor of a cleaning device reaches 0.8, the edge weight of its path will significantly increase, prompting the selection of other available paths.

[0104] Through the above technical solution, this application effectively solves the transmission delay problem caused by ignoring the real-time load status of equipment in traditional path planning. In wafer fabrication scenarios, when multiple optional devices exist for a certain process node, the path selection strategy can be dynamically adjusted according to the current load level of the devices. For example, in the lithography process, it can automatically avoid queued device nodes, thereby reducing the waiting time of the wafer during transmission. At the same time, by integrating the dual factors of physical distance and dynamic load, it avoids the path selection bias that may be caused by relying solely on distance indicators. For example, when a nearby device is under high load, it can automatically select a slightly farther but idle device path, achieving overall optimization of transmission efficiency.

[0105] Specifically, during the long-term use of processing equipment, malfunctions are inevitable, leading to breakpoints in the constructed directed weighted graph. Therefore, this application further proposes to verify the connectivity of the constructed directed weighted graph to ensure that there are reachable paths between all process nodes. If there are disconnected process nodes in the path planning graph, a graph search algorithm is used to obtain a list of idle processing equipment in the backup equipment pool, resulting in an updated set of available processing equipment. Based on the set of available processing equipment, the operating parameters of the currently idle processing equipment are extracted from the equipment state matrix to determine the priority order of the equipment to be activated. The activation state of the equipment is switched from idle to running through a state update mechanism, resulting in an updated equipment state matrix. Based on the updated equipment state matrix, a depth-first search algorithm is used to recalculate the connectivity between process nodes in the path planning graph to determine whether connectivity has been restored. If connectivity has been restored, the directed weighted graph used for path planning is updated by expanding the equipment set.

[0106] Connectivity verification refers to detecting the existence of unreachable process nodes in a directed weighted graph using algorithms. This can be implemented using depth-first search (DFS) or breadth-first search (BFS) algorithms to ensure the effectiveness of path planning. The backup equipment pool is a pre-configured set of processing equipment in standby mode, which can be obtained by filtering based on availability indicators in the equipment state matrix. It provides alternative equipment resources when paths break down. Priority ranking determines the activation order of equipment based on parameters such as processing capacity and idle time. This can be implemented using a weighted scoring model to optimize the selection efficiency of backup equipment. The depth-first search algorithm is a graph traversal method that explores deeply along the connection paths of equipment nodes. It can be implemented recursively or using a stack structure to quickly verify the connectivity relationships between nodes.

[0107] Specifically, when a path break is detected between process nodes, the system automatically retrieves idle equipment from the backup equipment pool that meets the process requirements and generates a priority list based on equipment processing capacity and idle status. After activating the highest-priority idle equipment through a status update mechanism, a directed weighted graph including the newly added equipment node is reconstructed, and a depth-first search algorithm is used to verify the connectivity between process nodes. If the verification passes, the path planning graph structure is updated to ensure that subsequent path searches can cover the newly added equipment node. For example, when a failure of an etching machine causes downstream nodes to become unreachable, a backup etching machine can be activated and the path weights recalculated to form a new equipment connection topology.

[0108] Compared to existing technologies, traditional wafer transport methods often require manual intervention to adjust path configurations in the event of equipment failure, and cannot automatically call upon backup equipment to restore path connectivity. This solution, however, through dynamically activating backup equipment and an automated connectivity verification mechanism, can quickly reconstruct the transport path in the event of equipment failure or excessive load, avoiding production line shutdowns due to single points of failure.

[0109] Through the above technical solution, this application can proactively identify connectivity defects between device nodes during the path planning stage and promptly repair path breakage problems by intelligently scheduling backup device resources. This mechanism effectively solves the path unreachability problem caused by equipment failure in traditional methods, improving the fault tolerance and dynamic adjustment efficiency of wafer delivery.

[0110] Reference Figure 5As shown, this application further proposes a path search algorithm to search for multiple alternative paths from the starting node to the target node in a directed weighted graph, calculate the cost of each path, and generate a path cost ranking list. This includes: identifying the equipment nodes corresponding to the starting process node and the target process node from the directed weighted graph, serving as the starting and ending points of the path search; starting from the starting point, exploring all possible equipment node transfer paths step by step according to the connection relationships and edge weights between equipment nodes; during the path exploration process, recording the sequence of traversed equipment nodes and the accumulated edge weights in real time to form multiple complete equipment node transfer paths; for each equipment node transfer path, comprehensively calculating the overall path cost based on its accumulated edge weights, the load level of the equipment in the path, and the path length; and sorting all explored equipment node transfer paths from low to high according to their overall path cost to generate a path cost ranking list.

[0111] The path search algorithm refers to the mathematical method used to find paths between nodes in a directed weighted graph. Specifically, it can be implemented using Dijkstra's algorithm or the A* algorithm. Its function is to cover all possible device node transfer paths through a systematic search process. Edge weight values ​​are a comprehensive indicator reflecting the transmission cost between devices. This can be achieved through a weighted calculation of transmission distance and load impact coefficients, used to quantify the actual transmission cost of different paths. The overall path cost is a multi-dimensional evaluation indicator that integrates path length, device load, and transmission efficiency. It can be achieved by using a weighted summation method to transform different influencing factors into a unified dimension, providing a comparable quantitative basis for path selection. The path cost ranking list is a set of candidate paths sorted according to their overall cost. This can be implemented using a priority queue data structure, used to quickly obtain the optimal or suboptimal transmission scheme.

[0112] Specifically, when a wafer needs to be transferred from the initial process equipment to the target process equipment, the starting and ending points of the path search are first determined based on a constructed directed weighted graph. By traversing the connections between device nodes, all possible transmission paths are explored step by step, recording the sequence of nodes traversed and the accumulated transmission cost in real time during the exploration process. The cost of each path considers not only the physical transmission distance but also the impact of the device's real-time load on transmission efficiency. For example, when a device is under high load, its corresponding edge weight value will dynamically increase, thus reflecting the transmission delay risk in the path cost calculation. After all feasible paths are summarized, a priority list is generated through comprehensive cost calculation and sorting, providing a decision-making basis for subsequent path selection.

[0113] Compared to existing technologies, traditional fixed-path planning methods only consider static equipment layout and cannot respond to dynamic changes in equipment load. This solution, however, dynamically adjusts edge weights by introducing real-time load data, enabling path cost calculations to accurately reflect the current production status. For example, when a device experiences processing delays due to excessive load, the edge weights of related paths automatically increase, prompting the selection of load-balanced alternative paths. This avoids the overall transmission efficiency degradation caused by equipment overload in traditional methods.

[0114] Through the above technical solution, this application achieves dynamic optimization selection of wafer transport paths, effectively solving the problem that traditional fixed paths cannot adapt to changes in equipment status. In the event of sudden equipment failure or load fluctuations, alternative path solutions can be quickly generated, ensuring that the wafer transport process always maintains optimal efficiency. For example, when a device is detected to be in a fault state, the path search algorithm automatically excludes that device node and recalculates available paths based on the updated directed weighted graph, significantly improving the production line's responsiveness to unexpected situations.

[0115] Reference Figure 6 As shown, this application further proposes selecting the path with the lowest cost as the current transmission scheme based on the path cost ranking list, and verifying the transmission time of the path under the load level through simulation. This includes: selecting the device node transfer path with the lowest cumulative cost value from the path cost ranking list as the preferred transmission scheme; obtaining real-time load level data of each device node in the preferred transmission scheme; simulating and calculating the transmission time of the wafer between each segment of device nodes based on the physical distance between device nodes and the current load status of each device; summing the transmission times between each segment of device nodes to obtain the total transmission time estimate of the preferred transmission scheme; comparing the total transmission time estimate with a preset standard transmission time threshold to verify the timeliness and feasibility of the transmission scheme; and generating a transmission scheme evaluation report containing the device node sequence, estimated transmission time, and verification results.

[0116] The path cost ranking list refers to a set of candidate paths sorted from low to high based on overall path cost. This can be achieved using a weighted calculation of cumulative edge weights, equipment load levels, and path lengths, used to quickly identify the optimal transport path. Real-time load level data refers to the ratio of the number of wafers currently being processed by the equipment to its processing capacity. This can be calculated by comparing the number of wafers to be processed collected by sensors to the equipment's rated processing speed, reflecting the current workload of the equipment. Simulated transmission time prediction refers to the prediction of wafer transport time based on the physical distance between equipment and load status. This can be calculated by dividing the path distance by the transport speed and adding a load impact factor, used to assess the actual efficiency of the path in advance. The standard transmission time threshold refers to the maximum transmission time limit allowed by process requirements. This can be set according to the time constraints of the wafer process flow sequence, used to determine the feasibility of the transport scheme. The transport scheme evaluation report is a structured document containing path selection results and verification data. It can be generated using a combination of equipment node sequences and time data, used to guide subsequent path optimization decisions.

[0117] Specifically, in the wafer transport control process, the transport path with the lowest cumulative cost is first selected from the path cost ranking list as the preferred solution. By acquiring real-time load data of each device node along this path, and combining the physical distance between devices and the operating speed of the transport mechanism, the transmission time of the wafer between adjacent device nodes is calculated segment by segment. For example, when the transmission distance of a certain segment is 5 meters and the transmission speed is 0.5 meters / second, the basic transmission time is 10 seconds. If the load level of the target device in this segment reaches 80%, a delay of 3 seconds is added according to a preset load impact coefficient. The cumulative result of all segment transmission times is the total estimated transmission time. By comparing it with a preset standard threshold, for example, when the total estimated time exceeds 120 seconds, it is determined that the path cannot meet the timeliness requirements, triggering the edge weight adjustment process. The resulting evaluation report will contain complete path node information, time calculation details, and verification conclusions, providing data support for subsequent optimization.

[0118] Specifically, when the transmission scheme evaluation report shows that the total transmission time exceeds the standard transmission time threshold, the edge weight adjustment process is initiated; the latest load status data of each device node in the directed weighted graph is obtained; the edge weight values ​​between the corresponding device nodes are dynamically adjusted according to the changes in the load level of the device nodes; based on the adjusted edge weight values, the cumulative cost of the transfer path of each device node is recalculated; the transfer paths of the device nodes are reordered according to the updated cumulative cost values; an optimized path cost ranking list is generated, and the transmission scheme selection and transmission time verification are performed again; the above adjustment process is repeated until a transmission scheme that meets the transmission time requirements is obtained, or the current optimal scheme is selected when the maximum number of iterations is reached.

[0119] The edge weight adjustment process refers to the mechanism of updating path cost calculation parameters based on dynamic changes in equipment load during path planning. Specifically, this can be achieved through the linkage of the load monitoring module and the weight calculation module, reflecting the impact of equipment operating status on path selection in real time. Dynamically adjusting edge weight values ​​involves correcting path weights based on the ratio of current equipment load to processing capacity. This can be achieved using a linear weighted algorithm to integrate the load influence coefficient with physical distance, ensuring that path cost calculations include real-time operating conditions. Recalculating cumulative costs involves a secondary evaluation of candidate paths based on the updated edge weight values. This can be achieved by recalculating the total cost of each path using a graph traversal algorithm, ensuring that the path ranking results adapt to the latest production environment.

[0120] Specifically, when the total transmission time of the preferred transmission scheme exceeds a preset threshold, a weight adjustment mechanism is immediately triggered. The latest load data for each process node is obtained through the equipment status monitoring interface; for example, the load rate of an etching machine may increase from 30% to 75%. The weight calculation module, based on the magnitude of the load change (e.g., using an exponential function to convert the load rate change into a weight correction coefficient), adjusts the edge weights of the relevant paths for that machine from the initial value of 1.2 to 2.5. The path search engine re-executes path calculations based on the updated weight values, generating an optimized ranking list containing the new paths. Continuous optimization is achieved through an iterative mechanism; for example, in three consecutive iterations, schemes with estimated transmission times of 58 seconds, 53 seconds, and 49 seconds are obtained respectively, until a preset 45-second threshold is met or the maximum number of iterations is reached.

[0121] Compared to existing technologies, current fixed-path methods select transmission paths based solely on static parameters, failing to dynamically adjust path selection in response to fluctuations in equipment load. For example, when a device experiences processing delays due to a sudden increase in load, traditional methods still use the original path, causing wafers to accumulate at the fault node. This solution, however, simulates transmission time using real-time load data, enabling the identification of potential bottlenecks before path execution and effectively avoiding transmission delays caused by equipment overload by dynamically adjusting edge weights. Traditional wafer transmission methods lack dynamic adjustment capabilities after path planning, continuing to use the initial path scheme when equipment load changes abruptly. This solution, through a closed-loop feedback mechanism, continuously verifies and optimizes the scheme before path execution. For instance, when a sudden equipment failure causes a surge in load, weight updates and alternative paths can be completed within 2 seconds, while traditional methods require manual intervention and take more than 10 minutes.

[0122] Through the above technical solution, this application effectively solves the problem of path failure caused by sudden changes in equipment load during wafer transfer, and realizes dynamic optimization of path planning. When the load of a certain process equipment exceeds the limit, the priority of the path containing that equipment is automatically reduced, guiding the wafer to select an alternative path with a lower load, thus avoiding production delays caused by path rigidity in traditional methods.

[0123] Reference Figure 7 As shown, this application further proposes to obtain a wafer processing and transfer execution plan by issuing an instruction sequence of the preferred path from the optimized path cost ranking list to the transfer track through a controller. This includes: issuing an instruction sequence to the transfer track through the controller to determine track control parameters; generating a wafer transfer execution plan based on the track control parameters; obtaining real-time feedback data of the execution plan; adjusting the instruction sequence if the feedback data exceeds a preset threshold; updating the track control parameters based on the adjusted instruction sequence to generate a new execution plan; and issuing the updated execution plan through the controller to obtain the final wafer transfer execution result.

[0124] The instruction sequence refers to a data set containing the transfer order of equipment nodes and corresponding control commands. Specifically, it can be implemented using a sequence of pulse signals sent by a PLC controller to precisely control the start, stop, and steering of the conveyor track. Track control parameters are adjustable variables affecting the operating state of the conveyor track, including parameters such as conveyor speed, acceleration, and direction switching interval. These parameters are matched with preset values ​​by collecting actual track operating data from an encoder. Real-time feedback data refers to the status monitoring data generated during the execution of instructions by the conveyor track. Specifically, it can use infrared sensors to detect wafer position offsets and pressure sensors to obtain track mechanical load data to determine whether the execution process deviates from expectations. The threshold is a pre-set allowable range for parameter fluctuations, which can be determined based on statistical analysis of historical operating data. When the sensor detection value exceeds the threshold, an instruction adjustment mechanism is triggered.

[0125] Specifically, the controller translates the optimized path into specific track control commands and sends them to the conveyor track actuator via the industrial bus protocol. Track control parameters are dynamically configured based on the path planning results; for example, a higher conveying speed is set for long-distance transmission segments, while the speed is reduced before heavily loaded device nodes to ensure accurate positioning. During execution, the track's operating status is collected in real time through a distributed sensor network, comparing the actual wafer position with the planned path. When a wafer transmission delay exceeds a set threshold, the control algorithm immediately initiates a command sequence adjustment process, such as recalculating the transmission priority between device nodes or switching to an alternative path. The updated track control parameters are written to the conveyor track drive module through the controller, forming a closed-loop control circuit, ultimately achieving dynamically optimized wafer transfer execution.

[0126] In some specific implementations, a communication architecture based on the OPC UA protocol can be used to realize data interaction between the controller and the transmission track, ensuring the real-time performance and reliability of command issuance. For example, when an abnormal load is detected on a certain track segment, the controller can achieve load balancing by adjusting the acceleration parameters of adjacent tracks.

[0127] Compared to existing technologies, traditional wafer transfer methods use fixed parameters to execute preset paths, making it impossible to dynamically adjust control strategies based on real-time operating conditions. This solution introduces a closed-loop feedback mechanism to continuously monitor the track's operating status during the command execution phase and dynamically update control parameters based on real-time data, effectively solving the problem of path execution deviations caused by equipment load fluctuations or mechanical failures.

[0128] Through the above technical solution, this application can respond in real time to changes in the operating status of the transfer track and dynamically adjust control commands to adapt to actual production conditions. When wafer transfer delay or abnormal track load is detected, a corrected execution plan can be quickly generated to avoid the entire production line from being halted due to local faults. This dynamic adjustment mechanism significantly improves the adaptability of the wafer transfer method to complex production environments, ensuring the continuity and stability of the processing flow.

[0129] Reference Figure 8 As shown, in order to implement the above-mentioned wafer transfer control method, the present invention also discloses a wafer transfer control system, comprising:

[0130] The data acquisition module is used to collect real-time operating status and location coordinate data of all processing equipment in the wafer production line through a sensor network, and obtain an equipment status matrix that includes equipment availability indicators and load levels;

[0131] The equipment set determination module is used to determine the set of processing equipment that can be used for the wafer process flow sequence based on the equipment status matrix and the preset wafer process flow sequence, and to map the set of processing equipment to the corresponding wafer process flow sequence.

[0132] The graph construction module is used to construct a directed weighted graph for path planning by using the processing equipment in the set of processing equipment as nodes and calculating the edge weights based on the transmission distance between wafer process flow sequences and the real-time load level.

[0133] The path search module is used to search for multiple alternative paths from the starting node to the target node in the directed weighted graph using a path search algorithm, calculate the cost of each path, and generate a path cost ranking list.

[0134] The path optimization module is used to select the path with the lowest cost as the current transmission scheme according to the path cost ranking list, and to verify the transmission time of the path under the load level through simulation; when the transmission efficiency does not meet the expected requirements, the edge weights are iteratively adjusted to incorporate real-time load changes to obtain the optimized path cost ranking list.

[0135] The execution control module is used to send the instruction sequence of the preferred path in the optimized path cost ranking list to the transport track through the controller, so as to obtain the wafer processing transport execution plan.

[0136] Specifically, the data acquisition module acquires equipment operating parameters and coordinate data in real time through distributed sensors, and generates a dynamic matrix containing equipment health status and load levels after standardization processing; the equipment set determination module filters available equipment based on the process sequence and establishes process node mapping relationships; the graph construction module calculates edge weights based on physical distance and real-time load to form a topology network reflecting actual transmission costs; the path search module generates multiple candidate paths using a graph traversal algorithm and sorts them by cost; the path optimization module optimizes path selection through simulation verification and iterative weight adjustment; and the execution control module finally converts the optimized path into track control commands. Through the coordinated operation of these modules, the system achieves closed-loop control from data acquisition to path execution.

[0137] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A wafer transfer control method characterized by comprising: The method comprises the following steps: Collecting real-time running state and position coordinate data of all processing equipment in a wafer production line through a sensor network, obtaining a device state matrix containing device availability identification and load level; According to the device state matrix and combining a preset wafer process flow sequence, determining a processing equipment set available for the wafer process flow sequence, and mapping the processing equipment set to the corresponding wafer process flow sequence; Taking the processing equipment in the processing equipment set as a node, calculating edge weight according to the transmission distance and real-time load level between wafer process flow sequences, and constructing a directed weighted graph for path planning; including: determining the connection relationship between each processing equipment according to the sequence of wafer process flow sequences, establishing a preliminary device connection topology; obtaining the actual physical position coordinates of all available processing equipment between adjacent process nodes, calculating the actual transmission path distance between devices; real-time monitoring of the current load state of each processing equipment, obtaining device load level data, and combining device processing capacity to calculate the load influence coefficient; weighting and fusing the transmission path distance and the load influence coefficient to generate edge weight values representing path transmission cost; according to the device connection topology and the calculated edge weight values, constructing a complete directed weighted graph structure; Verifying the connectivity of the constructed directed weighted graph to ensure that there is a reachable path between all process nodes; if there are disconnected process nodes in the path planning graph, obtaining the list of idle processing equipment in the standby equipment pool through a graph search algorithm to obtain an updated available processing equipment set; according to the available processing equipment set, extracting the running parameters of the current idle processing equipment from the device state matrix to determine the priority order of the to-be-activated device; through a state update mechanism, switching the device activation state from idle to running to obtain an updated device state matrix; according to the updated device state matrix, using a depth-first search algorithm to recalculate the connectivity between process nodes in the path planning graph to determine whether the connectivity is restored; if the connectivity is restored, updating the directed weighted graph for path planning through an extended equipment set; Using a path search algorithm to search for multiple alternative paths from the starting node to the target node in the directed weighted graph, and calculating the cost of each path to generate a path cost ranking list; According to the path cost ranking list, selecting the path with the lowest cost as the current transmission scheme, and verifying the transmission time of the path under the load level through simulation; when the transmission efficiency does not meet the expected requirement, iteratively adjusting the edge weight to include real-time load changes to obtain an optimized path cost ranking list; The controller issues an instruction sequence of a preferred path in the optimized path cost ranking list to the conveying track to obtain a wafer processing conveying execution plan; including: issuing an instruction sequence to the conveying track through the controller to determine track control parameters; generating a wafer conveying execution plan according to the track control parameters; obtaining real-time feedback data of the execution plan, if the feedback data exceeds a preset threshold, adjusting the instruction sequence; updating the track control parameters according to the adjusted instruction sequence, generating a new execution plan; issuing the updated execution plan through the controller to obtain the final wafer conveying execution result.

2. The wafer transfer control method according to claim 1, characterized by: The real-time running state and position coordinate data of all processing equipment in the wafer production line are collected through a sensor network, and a device state matrix containing device availability identification and load level is obtained, including: Real-time collection of running state data including device start-stop state, running power, and wafer in-place signal through a plurality of sensors distributed at key monitoring points of the processing equipment, and collection of absolute coordinate data of the equipment through a positioning module; Signal filtering and outlier rejection processing are performed on the collected original state and coordinate data to generate standardized device state messages; The standardized device state messages are associated and matched with the device identifiers, and the availability identification containing "normal", "busy", and "fault" is generated according to the preset device health evaluation rules; Real-time statistics of the number of wafers to be processed and the estimated processing time of each device, combined with the current running power to calculate the dynamic load level value; Integrate the device identifier, availability identification, dynamic load level value, and position coordinate data, and update to the device state matrix according to the preset period.

3. The wafer transfer control method according to claim 1, characterized by: According to the device state matrix and the preset wafer process flow sequence, a set of processing equipment that can be used for the wafer process flow sequence is determined, and the set of processing equipment is mapped to the corresponding wafer process flow sequence, including: Generating a process node allocation template according to the preset wafer process flow sequence; Using the mapping relationship, the available device subset is matched with the process node allocation template to generate a device process allocation matrix; By analyzing the device process allocation matrix, the node allocation state of each device is obtained, and whether there is a node allocation conflict is judged; If there is a node allocation conflict, the device process allocation matrix is adjusted according to the priority of the wafer process flow sequence to obtain an optimized allocation matrix; According to the optimized allocation matrix, a device running scheduling sequence is generated to determine the final process node execution order.

4. The wafer transfer control method according to claim 1, characterized by: A path search algorithm is used to search for multiple candidate paths from the starting node to the target node in the directed weighted graph, and the cost of each path is calculated to generate a path cost ranking list, including: Identify the device nodes corresponding to the starting process node and the device nodes corresponding to the target process node from the directed weighted graph as the starting point and the end point of path search; Starting from the starting point, gradually explore all possible device node transfer paths according to the connection relationship between device nodes and edge weight values; During the path exploration process, the sequence of device nodes passed through and the accumulated edge weight values are recorded in real time to form multiple complete device node transfer paths; For each device node transfer path, the overall path cost is calculated based on the accumulated edge weight value, the load level of the devices in the path, and the path length; All the device node transfer paths obtained through exploration are sorted in ascending order of the overall path cost to generate a path cost sorting list.

5. The wafer transfer control method according to claim 1, characterized by: According to the path cost sorting list, the path with the lowest cost is selected as the current transfer scheme, and the transmission time of the path under the load level is verified through simulation, including: Selecting the device node transfer path with the smallest accumulated cost value from the path cost sorting list as the preferred transfer scheme; In the preferred transfer scheme, the real-time load level data of each device node is obtained; Based on the physical distance between the device nodes and the current load state of each device, the transmission time of the wafer between each segment of the device nodes is simulated and calculated; The transmission time of each segment of the device nodes is accumulated to obtain the total transmission time estimate of the preferred transfer scheme; The total transmission time estimate is compared with the preset standard transmission time threshold to verify the timeliness feasibility of the transfer scheme; A transfer scheme evaluation report containing the device node sequence, the estimated transmission time, and the verification result is generated.

6. The wafer transfer control method according to claim 5, characterized in that: When the transfer scheme evaluation report shows that the total transmission time exceeds the standard transmission time threshold, the edge weight adjustment process is started; The latest load state data of each device node in the directed weighted graph is obtained; According to the changes in the load level of the device nodes, the edge weight values between the corresponding device nodes are dynamically adjusted; Based on the adjusted edge weight values, the accumulated costs of each device node transfer path are recalculated; According to the updated accumulated cost values, the device node transfer paths are reordered; An optimized path cost sorting list is generated, and the transfer scheme selection and transmission time verification are performed again; The above adjustment process is repeated until a transfer scheme that meets the transmission time requirement is obtained, or the maximum number of iterations is reached and the current optimal scheme is selected.

7. A wafer transfer control system for implementing the wafer transfer control method according to any one of claims 1 to 6, characterized by: including: A data acquisition module for acquiring real-time running state and position coordinate data of all processing devices in the wafer production line through a sensor network, and obtaining a device state matrix containing device availability identifiers and load levels; A device set determination module for determining a set of processing devices that can be used for the wafer process flow sequence according to the device state matrix and a preset wafer process flow sequence, and mapping the set of processing devices to the corresponding wafer process flow sequence; A graph construction module for constructing a directed weighted graph for path planning by taking the processing devices in the set of processing devices as nodes and calculating edge weights based on the transmission distance and real-time load level between the wafer process flow sequences; A path search module for searching for multiple candidate paths from the start node to the target node in the directed weighted graph using a path search algorithm and calculating the cost of each path to generate a path cost sorting list; a path optimization module configured to select a path with the lowest cost from the path cost ranking list as a current transfer scheme, and verify the transmission time of the path under a load level through simulation; when the transmission efficiency does not meet the expected requirement, iteratively adjust the edge weight to take into account real-time load changes, and obtain an optimized path cost ranking list; an execution control module configured to issue, by a controller, an instruction sequence of a first selected path in the optimized path cost ranking list to a transfer track, and obtain a wafer processing transfer execution plan.

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