Ethercat master station control system based on cpu and fpga

Abstract

The application provides a CPU and FPGA-based EtherCAT master station control system, which comprises: a CPU terminal system for respectively communicating with an upper computer, an algorithm server and an FPGA terminal through a CPU terminal peripheral interface; and controlling the FPGA terminal to perform a control operation according to a business logic; an FPGA terminal system for performing analysis and processing on communication data from a slave station system after receiving the communication data from the CPU terminal and / or reading configuration parameters of the CPU terminal, and feeding back the analysis result to the slave station system; an upper computer for respectively configuring parameters of the CPU terminal and the slave station system, and monitoring the running state of the whole system; and an algorithm server for receiving communication data uploaded by the CPU terminal, and feeding back the communication data to the CPU terminal after control calculation is performed on the communication data. Thus, the embodiment adopts a heterogeneous dual-system scheme, and can be applied to a high-speed and high-precision EtherCAT scene.

Description

Technical Field

[0001] This invention belongs to the field of Ethernet communication technology, and in particular relates to an EtherCAT master station control system based on CPU and FPGA. Background Technology

[0002] Currently, EtherCAT master controllers face the following challenges in application: Traditional master implementations mostly employ Beckhoff's TwinCAT software-based solutions under Windows operating systems and embedded Linux operating systems. Essentially, these solutions rely on the CPU for protocol stack processing within the operating system and then connect to slave devices via network interfaces. Since CPU latency is unpredictable, as the workload increases, the CPU needs to perform task scheduling and reordering, often leading to uncontrollable increases in processing latency. Therefore, these solutions cannot achieve extremely short control cycles and minimal control jitter, failing to meet application requirements in high-speed motion and high-precision control scenarios.

[0003] To address the above issues, existing technologies have proposed several improvement strategies, primarily using FPGAs to improve the EtherCAT master station solution. These strategies leverage the excellent deterministic low latency and high-speed parallel computing capabilities of FPGAs to assemble and parse data frames, thereby improving the real-time performance and stability of communication. The disadvantages of these strategies are as follows: (1) The complete EtherCAT protocol stack is not deployed on the FPGA side; the application layer of the protocol stack is still deployed on the CPU side, failing to fully utilize the advantages of the FPGA and completely relieve the processing pressure on the CPU side. (2) The CPU and FPGA sides do not use a high-speed communication bus, which increases communication latency and cannot meet communication requirements for scenarios with ultra-low control cycles. (3) The CPU side is user-facing and does not provide an operation interface or standard calling interface.

[0004] To address this issue, this invention proposes an EtherCAT master controller system based on CPU and FPGA, which can play a significant role in high-speed, high-precision EtherCAT control scenarios. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this invention provides an EtherCAT master control system based on CPU and FPGA. This system has extremely small control cycles and minimal control jitter. Furthermore, since the EtherCAT protocol stack is deployed on the FPGA subsystem, the computing resources of the CPU subsystem are completely released, enabling the CPU subsystem to deploy more complex algorithms.

[0006] According to a first aspect of the present invention, an EtherCAT master station control system based on a CPU and an FPGA is provided. The system includes: a host computer, an algorithm server, a CPU terminal system, an FPGA terminal system, a CPU peripheral interface, and an FPGA peripheral interface. The CPU terminal system is used to communicate with the host computer, the algorithm server, and the FPGA terminal system via the CPU peripheral interface; and to control the FPGA terminal system to execute control operations satisfying the EtherCAT protocol according to business logic. The FPGA terminal system includes an EtherCAT protocol stack; the EtherCAT protocol stack mainly operates in a state machine manner; and is used to communicate with the host computer, the algorithm server, and the FPGA terminal system via the FPGA peripheral interface. The slave system performs data communication and, after receiving communication data from the CPU terminal system and / or reading the configuration parameters of the CPU terminal system, parses and processes the communication data received from the slave system and feeds back the parsing results to the slave system; the host computer is used to configure parameters for the CPU terminal system and the slave system through a visual interface, and to monitor the entire operating status of the EtherCAT master control system; wherein, the slave system includes at least one slave station; the algorithm server is used to receive communication data uploaded by the CPU terminal system according to the business logic provided by the EtherCAT master control system, and feeds back the communication data to the CPU terminal system after performing control calculations on the communication data.

[0007] According to a second aspect of the present invention, an EtherCAT master station control method based on a CPU and an FPGA is also provided, wherein the FPGA subsystem includes: a state machine, an EtherCAT data link layer, a transmitting module, and a receiving module; the method is applied to the FPGA subsystem and includes: the state machine transmitting communication data to the transmitting module; wherein the communication data includes: DC message data, message data generated by the state machine, PDO communication data, or SDO communication data; the transmitting module assembles the communication data into a first EtherCAT message and transmits the first EtherCAT message to the slave system through the EtherCAT data link layer; the EtherCAT data link layer receives a second EtherCAT message from the slave system in response to the first EtherCAT message and transmits the second EtherCAT message to the receiving module; the receiving module parses the second EtherCAT message and feeds back the parsing result to the state machine.

[0008] According to a third aspect of the present invention, a computer-readable medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the method as described in the second aspect.

[0009] This invention provides an EtherCAT master station control system based on CPU and FPGA. One embodiment of the control system includes: a host computer, an algorithm server, a CPU terminal system, an FPGA terminal system, a CPU peripheral interface, and an FPGA peripheral interface. The CPU terminal system is used to communicate with the host computer, the algorithm server, and the FPGA terminal system via the CPU peripheral interface, respectively. It also controls the FPGA terminal system to execute control operations that satisfy the EtherCAT protocol according to business logic. The FPGA terminal system includes an EtherCAT protocol stack. The EtherCAT protocol stack mainly operates in a state machine manner and is used to communicate with slave stations via the FPGA peripheral interface. The system performs data communication, and after receiving communication data from the CPU terminal system and / or reading the configuration parameters of the CPU terminal system, it parses and processes the communication data received from the slave system and feeds back the parsing results to the slave system. The host computer is used to configure the parameters of the CPU terminal system and the slave system through a visual interface, and to monitor the entire operating status of the EtherCAT master control system. The slave system includes at least one slave station. The algorithm server is used to receive the communication data uploaded by the CPU terminal system according to the business logic provided by the EtherCAT master control system, and feeds back the communication data to the CPU terminal system after performing control calculations on the communication data. Therefore, this embodiment adopts a heterogeneous dual-system solution of CPU+FPGA. The host computer enables parameter configuration and status monitoring of the EtherCAT master control system, thereby reducing the learning curve. The algorithm server allows deployment of algorithms requiring high computing power and with low update frequencies to adapt to more complex application scenarios. By deploying the entire EtherCAT protocol stack on the FPGA subsystem, the computing resources of the CPU subsystem are fully released, enabling the CPU subsystem to deploy more complex algorithms. Due to the excellent deterministic low latency and high-speed parallel computing characteristics of FPGA, this embodiment achieves extremely short control cycles and minimal control jitter, thus playing a significant role in high-speed, high-precision EtherCAT control scenarios. Attached Figure Description

[0010] The following sections will describe some specific embodiments of the invention in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0011] Figure 1This is a schematic diagram of the architecture of an EtherCAT master station control system based on CPU and FPGA, provided as an embodiment of the present invention.

[0012] Figure 2 A flowchart illustrating an EtherCAT master station control method based on CPU and FPGA, provided as an embodiment of the present invention;

[0013] Figure 3 This is a schematic diagram of the structure of an EtherCAT master station control device based on CPU and FPGA, provided as an embodiment of the present invention. Detailed Implementation

[0014] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0015] EtherCAT is a high-performance real-time Ethernet communication protocol used for real-time control and communication in industrial automation. Developed by Beckhoff Automation in Germany in 2003, it was standardized by the International Electrotechnical Commission (IEC) as IEC 61158. EtherCAT is designed to achieve extremely low communication latency and high-bandwidth data transmission to meet the demands of high-speed control and data acquisition. It is implemented through a special master-slave architecture, where an EtherCAT master control system coordinates the entire network, while slave systems provide input / output functions.

[0016] An FPGA is an integrated circuit that can be programmed and configured as needed. Unlike fixed-function chips, the hardware structure of an FPGA can be changed through programming, making it suitable for a variety of applications. It is typically used in scenarios requiring high-speed processing and customized circuit design, such as digital signal processing, communication, and image processing. By using FPGAs, developers can implement specific functions at the hardware level without designing new application-specific integrated circuits (ASICs).

[0017] like Figure 1 The diagram shown is an architectural schematic of an EtherCAT master station control system based on CPU and FPGA provided in an embodiment of the present invention.

[0018] An EtherCAT master station control system based on CPU and FPGA includes: a host computer 101, an algorithm server 102, a CPU terminal system 103, an FPGA terminal system 104, a CPU peripheral interface, and an FPGA peripheral interface.

[0019] The CPU terminal system 103 is used to communicate with the host computer 101, the algorithm server 102, and the FPGA terminal system 104 via the CPU peripheral interface; and to control the FPGA terminal system 104 to perform control operations that satisfy the EtherCTA protocol according to the business logic.

[0020] The FPGA terminal system 104 includes an EtherCAT protocol stack. The EtherCAT protocol stack mainly operates in the form of a state machine. It is used to communicate with the slave system through the FPGA terminal peripheral interface, and after receiving the communication data from the CPU terminal system 103 and / or reading the configuration parameters of the CPU terminal system 103, it parses and processes the communication data received from the slave system and feeds back the parsing result to the slave system.

[0021] The host computer 101 is used to configure parameters of the CPU terminal system 103 and the slave system through a visual interface, and to monitor the entire operating status of the EtherCAT master control system; wherein the slave system includes at least one slave station.

[0022] The algorithm server 102 is used to receive communication data uploaded by the CPU terminal system 103 according to the business logic provided by the EtherCAT master station control system, and to feed back the communication data to the CPU terminal system 103 after performing control calculation on the communication data.

[0023] Specifically, the host computer 101, the algorithm server 102, and the FPGA terminal system 104 are respectively connected to the CPU terminal system 103 via a CPU peripheral interface. The FPGA terminal system 104 is connected to the slave system via an FPGA peripheral interface 106. The FPGA terminal system 104 and the CPU terminal system 103 are connected via a high-speed communication bus 110. The high-speed communication bus type is either a PCIe communication bus or an AXI communication bus.

[0024] The host computer 101 configures the parameters of the CPU terminal system 103 and the slave system respectively. The FPGA terminal system 104 reads the configuration parameters of the CPU terminal system 103 and configures the parameters of the slave system based on the read configuration parameters.

[0025] The FPGA terminal system 104 receives communication data from the slave system and parses the communication data using the ETHERCAT protocol stack. The FPGA terminal system 104 sends the parsed result to the algorithm server 102 via the CPU terminal system 103. The algorithm server 102 performs control calculations on the parsed result and feeds back the calculation result to the CPU terminal system 103. The CPU terminal system 103 then feeds back the calculation result to the slave system via the FPGA terminal system 104.

[0026] For example, the host computer provides a visual interface for configuring the entire EtherCAT master control system. Its main functions include configuring parameters for both the master and slave systems, as well as monitoring the operational status of the EtherCAT master control system. Parameter configuration for the master system primarily includes control frequency, on / off status of functional modules, and EtherCAT process data communication length. Slave system parameter configuration mainly includes slave RXPDO information, TXPDO information, DC parameters, and synchronization manager parameters. Operational status monitoring of the EtherCAT master control system primarily includes master station operating status, slave status information, and process communication data.

[0027] The algorithm server is a computer platform with high computing power. It receives real-time data uploaded by the CPU terminal system of the EtherCAT master control system, calls algorithms to perform control calculations, and the algorithms include but are not limited to reinforcement learning, trajectory planning and target detection. The algorithm outputs control commands and sends them to the CPU terminal system of the EtherCAT master control system for corresponding control.

[0028] It should be noted that the CPU terminal system can run not only the Linux-RT real-time operating system, but also other real-time operating systems such as FreeRTOS.

[0029] This embodiment employs a heterogeneous dual-system solution of CPU+FPGA. Since the EtherCAT protocol stack is fully deployed on the FPGA subsystem, the computing resources of the CPU subsystem are effectively freed up, allowing the CPU subsystem to deploy more complex algorithms. Furthermore, this embodiment leverages the excellent deterministic low latency and high-speed parallel computing characteristics of FPGA, resulting in an EtherCAT master control system with extremely short control cycles and minimal control jitter. This enables it to play a significant role in high-speed, high-precision EtherCAT control scenarios.

[0030] This embodiment communicates with the CPU terminal system through a visual interface provided by the host computer. As a result, not only can the EtherCAT master station control system be directly configured and monitored, but the learning curve of the EtherCAT master station control system is also reduced.

[0031] This embodiment adds support for algorithm servers to the CPU subsystem, enabling the CPU subsystem to deploy algorithms that require massive computing power and have low update frequency to the algorithm server for operation, in order to adapt to more complex application scenarios.

[0032] In a preferred embodiment of this example, the CPU terminal system 103 includes: a user application program 1031, an EtherCAT control module 1032, and a communication bus driver 1033; the CPU peripheral interface includes an EtherNet communication interface 106 and a first high-speed communication bus interface. The user application program is used to communicate data with the host computer and the algorithm server via the EtherNet communication interface, and to send control commands corresponding to business logic to the EtherCAT control module via the EtherCAT control interface; the EtherCAT control module is used to perform control operations conforming to the EtherCAT protocol on the FPGA terminal system according to the control commands; the communication bus driver is used to connect to the FPGA terminal system via the first high-speed communication bus interface and to provide hardware-level support for the first high-speed communication bus interface.

[0033] More preferably, the CPU peripheral interface further includes a UART and CAN communication interface 107; the UART and CAN communication interface 107 is used to connect external UART or CAN devices, or to debug the CPU terminal system.

[0034] Specifically, the CPU-side peripheral interfaces include an EtherNet communication chip 105 and an EtherNet communication interface 106, UART and CAN communication interfaces 107, and a first high-speed communication bus interface. The EtherNet communication chip and interface primarily provide upward network communication support for communication between the CPU terminal system and the host computer and algorithm server. The UART and CAN communication interfaces serve as external expansion interfaces for the CPU terminal system, allowing connection to external UART or CAN devices, or acting as debugging interfaces for the CPU terminal system. The first high-speed communication bus interface is primarily used for high-speed data communication with the FPGA terminal system.

[0035] The CPU terminal system runs the Linux-RT real-time operating system and consists of three parts: a user application, an EtherCAT control module, and a communication bus driver.

[0036] The user application is the business logic part of the EtherCAT master control system. Upward, the user application communicates with the host computer and the algorithm server via the EtherNet communication interface. This communication includes the status parameters of the EtherCAT master control system, periodic communication data between the EtherCAT master control system and the slave stations, and control commands output between the EtherCAT master control system and the algorithm server. Downward, the user application calls the EtherCAT control interface to execute control operations on the EtherCAT control modules.

[0037] The EtherCAT control module provides methods for operating the EtherCAT master control system. It offers a unified interface for user applications and interacts with the FPGA terminal system via the communication bus driver. The module's functions include: EtherCAT master control system initialization, EtherCAT master control system deinitialization, slave PDO communication length configuration, slave PDO communication parameter list configuration, SDO communication data setting, synchronization manager parameter configuration, EtherCAT master control system control frequency setting, EtherCAT master control system status monitoring, EtherCAT master control system start / stop, PDO data transmission, PDO data reception, and distributed clock parameter configuration.The EtherCAT master control system initialization function opens the communication bus driver device file and initializes the resources used by the module; the EtherCAT master control system deinitialization function closes the communication bus driver device file and cleans up the resources used by the module; the slave PDO communication length configuration function configures the communication data length of the connected slave PDOs in the EtherCAT master control system. The configuration data includes the number of slaves, the node number of each slave, and the RXPDO and TXPDO lengths of each slave. The slave PDO communication parameter list configuration function configures the communication parameter list for each slave PDO, including the number of slaves, the location of each slave, the number of synchronization managers for each slave, and the synchronization manager configuration for each slave. Each synchronization manager configuration includes the synchronization manager ID, the number of PDOs, and the PDO configuration. Each PDO configuration includes the PDO ID, the number of ENTRYs, and the ENTRY configuration. Each ENTRY configuration includes an index, sub-index, and data length. The SDO communication data setting function is used for SDO communication between the master and slave. The communication data content includes the slave node number, COE header, and SDO data. The SDO data includes control words, indexes, sub-indexes, and data segments. The synchronization manager parameter configuration function sets the parameters for each slave synchronization manager, including the slave ID and the starting physical coordinates of each slave synchronization manager. Address, data length, control word, and enable flag; EtherCAT master control system control frequency setting function sets the master controller PDO communication cycle, with control frequencies including 500Hz, 1000Hz, 2000Hz, 80000Hz, and 320000Hz; EtherCAT master control system status monitoring function monitors the master EtherCAT communication status; EtherCAT master control system start / stop function mainly provides signals to open and close the FPGA terminal system master protocol stack; PDO data transmission function sends the current cycle's PDO communication data to the FPGA terminal system, including the byte length and PDO data content; PDO data reception function reads the PDO data returned by the FPGA terminal system, including the byte length and PDO data content. Distributed clock parameter configuration sets the distributed clock parameters of the EtherCAT bus, mainly including CYCLE_TIME and SHIFT_TIME for SYNC0 and CYCLE_TIME and SHIFT_TIME for SYNC1.

[0038] In this embodiment, the CPU terminal system is responsible for encapsulating the EtherCAT master station control logic into a standard and easy-to-use calling interface and running the specific business control logic; it also communicates upwards with the algorithm server and the host computer; and a complete EtherCAT protocol stack for processing EtherCAT protocol logic is deployed in the FPGA terminal system. Therefore, the EtherCAT master station control system possesses both the ease of development of the CPU terminal system and the parallel, high-efficiency, and low-latency characteristics of the FPGA terminal system.

[0039] In a preferred embodiment of this example, the communication data between the FPGA terminal system and the CPU terminal system includes, but is not limited to, slave PDO configuration information, SDO communication data, TX PDO communication data, RX PDO communication data, DC configuration information, general parameter information, slave SM configuration information, and slave dynamic PDO configuration.

[0040] This embodiment uses an AXI or PCIE high-speed communication bus to communicate between the CPU terminal system and the FPGA terminal system, which not only has lower communication latency but also improves the real-time performance of the controller system.

[0041] In a preferred embodiment of this example, the FPGA terminal system 104 includes an EtherCAT protocol stack 1041 and an EtherCAT data link layer 1042; the FPGA peripheral interface includes a second high-speed communication interface 1043 and an EtherNet bus interface 109; the EtherCAT protocol stack is used to communicate with the CPU terminal system via the second high-speed communication interface; and to process the communication of state machine and process data after the communication network is initialized; the EtherCAT protocol stack is also used to provide non-cyclic access for the exchange of parameter data between the application programs of the EtherCAT master station and the slave station system; the EtherCAT data link layer is used to connect with the slave station system via the EtherNet bus interface and to provide a real-time and reliable communication data transmission channel for the FPGA terminal system and the slave station system.

[0042] The FPGA terminal system 104 communicates with the slave system through the EtherNet communication chip 108 and the EtherNet bus interface 109.

[0043] Specifically, the FPGA terminal system consists of a second high-speed communication interface, an EtherNet bus interface, an EtherCAT protocol stack, and an EtherNet data link layer. The second high-speed communication interface of the EtherCAT protocol stack and the first high-speed communication interface corresponding to the communication bus driver are connected via a high-speed communication bus 108. The high-speed communication bus type is either a PCIe communication bus or an AXI communication bus.

[0044] In a preferred embodiment of this example, the state machine includes, but is not limited to, a master station state machine, a slave station scanning state machine, a process data object reading state machine, a process data object entry reading state machine, a slave station information interface state machine, a process data configuration state machine, a process data object entry configuration state machine, a slave station configuration state machine, a state transition state machine, and a service data object download state machine.

[0045] The master station state machine is used to read the number of slave stations in the system network segment that are in operation from the slave stations, and then clear the configuration address and delay register of the slave stations in sequence; then it calls the slave station scanning state machine.

[0046] The slave scanning state machine is used to set the node address of the slave station, and to call the slave station information interface state machine after reading the initial application layer state, basic information in physical memory and information about physical ports from the slave station.

[0047] The slave information interface state machine is used to read the size and SII data of the slave; parse the SII data; and then call the slave configuration state machine.

[0048] The slave configuration state machine is used to set the slave to the initial INIT state, and after clearing the FMMU parameters, synchronization manager parameters, and distributed clock related parameters in sequence, configures the synchronization manager parameters and related registers of the PDI type interface inside the slave; then it calls the state transition state machine.

[0049] The state transition state machine is used to call the process data object to read the state machine after the slave station enters the PREOP state.

[0050] The process data object reading state machine is used to read relevant information parameters of the PDO type data supported by the slave station and then detect whether the operation object is the last slave station in the system network segment. If the detection result indicates that it is not the last slave station, the process data object reading state machine updates the slave station number to be operated and calls the slave station scanning state machine again to perform relevant operations until the detection result indicates that all slave stations in the network segment have been operated, and then returns to the running state of the master station state machine.

[0051] The master station state machine is also used to, when all slave stations in the network segment are in the PREOP state, control the XML configuration module to parse the configuration information for the slave stations according to the XML configuration information sent by the user application, and control the FMMU configuration module to configure the SYNC parameters and FMMU parameters for the slave stations; after the configuration parameter operation is completed, the slave station's state is adjusted to run OP, and the slave station configuration state machine is called.

[0052] The slave configuration state machine is used to set the slave to the initial INIT state, and after clearing the FMMU parameters, synchronization manager parameters, and distributed clock related parameters in sequence, configure the synchronization manager parameters and related registers of the PDI type interface inside the slave. When the slave enters PREOP, if there is a CPU terminal system-defined PDO configuration, the process data configuration state machine is called.

[0053] The process data configuration state machine is used to sequentially configure custom PDO parameters, SYNC parameters, and FMMU parameters for the slave stations; if distributed clock settings are required, the DC module is called to perform clock synchronization operations between slave stations, and the state transition state machine is called after the clock synchronization operation is completed.

[0054] The state transition state machine is used to transition the slave to the SAFEOP state when it detects that the slave is in the PREOP state, and to the OP state when it detects that the slave is in the SAFEOP state.

[0055] Existing technologies deploy the EtherCTA protocol stack application layer on the CPU subsystem, which cannot fully leverage the advantages of the FPGA and completely relieve the processing pressure on the CPU. In contrast, this embodiment deploys the EtherCTA protocol stack as a state machine entirely on the FPGA subsystem. Therefore, the EtherCTA protocol stack application layer of this application is deployed on the FPGA subsystem, thus completely freeing up the computing resources of the CPU subsystem, which is beneficial for deploying more complex algorithms on the CPU subsystem.

[0056] like Figure 2 The diagram shown is a flowchart of an EtherCAT master station control method based on CPU and FPGA provided in an embodiment of the present invention.

[0057] An EtherCAT master station control method based on CPU and FPGA, wherein the FPGA subsystem includes: a state machine, an EtherCAT data link layer, a transmitting module, and a receiving module; the method is applied to the FPGA subsystem; and includes at least the following steps:

[0058] S201, the state machine sends communication data to the sending module; the communication data includes: DC message data, message data generated by the state machine, PDO communication data, or SDO communication data;

[0059] S202, the sending module assembles the communication data into a first EtherCAT message and sends the first EtherCAT message to the slave system through the EtherCAT data link layer;

[0060] S203, the EtherCAT data link layer receives the second EtherCAT message from the slave system in response to the first EtherCAT message, and sends the second EtherCAT message to the receiving module;

[0061] S204, The receiving module parses the second EtherCAT message and feeds back the parsing result to the state machine.

[0062] Specifically, the state machine includes, but is not limited to, the master station state machine, the slave station scanning state machine, the process data object reading state machine, the slave station information interface state machine, the slave station configuration state machine, and the state transition state machine.

[0063] The master station state machine reads the number of running slave stations in the system network segment from the slave stations and then clears the configuration addresses and delay registers of the slave stations sequentially. Next, it calls the slave station scanning state machine. The slave station scanning state machine sets the node address for the slave station and reads the initial application layer state, basic information in physical memory, and information about relevant physical ports from the slave station, then calls the slave station information interface state machine. The slave station information interface state machine reads the size and data of the slave station's SII data and parses the SII data. Then, it calls the slave station configuration state machine. The slave station configuration state machine sets the slave station to the initial INIT state and then clears the FMMU parameters, synchronization manager parameters, and distributed clock-related parameters sequentially. Afterwards, the synchronization manager parameters and related registers of the PDI type interface inside the slave station are configured; then, the state transition state machine is called; after the state transition state machine transitions the slave station into the PREOP state, it calls the process data object reading state machine; the process data object reading state machine reads the relevant information parameters of the PDO type data supported by the slave station and checks whether the operation object is the last slave station in the system network segment; if the detection result indicates that it is not the last slave station, the process data object reading state machine updates the slave station number to be operated and calls the slave station scanning state machine again to perform related operations until the detection result indicates that all slave stations in the network segment have been operated, then returns to the running state of the master station state machine.

[0064] In a preferred embodiment of this example, the state machine further includes a process data configuration state machine. When all slave stations in the network segment are in the PREOP state, the master station state machine controls the XML configuration module to parse the configuration information for the slave stations according to the XML configuration information sent by the user application, and controls the FMMU configuration module to configure SYNC parameters and FMMU parameters for the slave stations. After the configuration parameter operation is completed, the master station state machine sets the slave station's state to OP and calls the slave station configuration state machine. The slave station configuration state machine sets the slave station to the initial INIT state, and after clearing the FMMU parameters, synchronization manager parameters, and distributed clock related parameters in sequence, it checks the synchronization manager parameters inside the slave station. The system configures the relevant registers of the PDI type interface. When the slave station enters PREOP, if there is a custom PDO configuration of the CPU subsystem, the process data configuration state machine is called. The process data configuration state machine configures the custom PDO parameters, SYNC parameters, and FMMU parameters of the slave station in sequence. If distributed clock setting is required, the DC module is called to perform clock synchronization operation between slave stations, and the state transition state machine is called after the clock synchronization operation is completed. When the state transition state machine detects that the slave station is in PREOP state, it transitions the slave station to SAFEOP state. When the state transition state machine detects that the slave station is in SAFEOP state, it transitions the slave station to OP state.

[0065] This embodiment proposes a method for implementing an EtherCAT master control system based on a CPU and an FPGA. The CPU subsystem runs a Linux-RT real-time operating system to handle the system's business logic. The CPU subsystem connects to the host computer and algorithm server via an EtherNet interface and to the FPGA subsystem via a high-speed bus. The FPGA subsystem handles the EtherCAT protocol stack, which includes a data link layer and an application layer. Communication between the CPU and FPGA subsystems occurs via high-speed buses such as AXI and PCIe. Benefiting from the deterministic low latency and high-speed parallel computing capabilities of the FPGA subsystem, the EtherCAT master control system, acting as an EtherCAT master, exhibits extremely short control cycles and minimal control jitter. Furthermore, deploying the EtherCAT protocol stack on the FPGA completely frees up the CPU's computing power for processing complex business logic within the system. Therefore, this invention can play a significant role in high-speed, high-precision EtherCAT control scenarios.

[0066] In another preferred embodiment of this example, the step of calling the DC module to perform clock synchronization between slave stations includes: obtaining DC support information and port switch information corresponding to each slave station in the slave station system from the CPU terminal system; if the DC support information indicates that the CPU terminal system has not specified a reference slave station, then the first slave station that supports DC function is designated as the reference slave station according to the DC support information; calculating the topology of the slave station system according to the reference slave station and the port switch information of each slave station to obtain the port connection information of all slave stations; and for the slave station system... For any slave station: Obtain the time when the slave station port receives the delay calculation instruction and use this time as the port time information; calculate the delay and clock compensation of the slave station based on the slave station's port connection information, slave station port time information, current slave station system time, and current FPGA system time; check whether all slave stations have completed delay and clock compensation; if not, continue to perform delay and clock compensation on the slave station corresponding to the slave station address; until all slave stations have completed delay and clock compensation, all slave stations enter the PREOP state; perform dynamic drift compensation operation on each slave station.

[0067] Specifically, the delay and clock compensation of the slave station are calculated based on the slave station's port connection information, slave station port time information, current slave station system time, and current FPGA system time; including: obtaining the slave station's delay based on the slave station's port connection information and slave station port time information; and calculating the current clock compensation of the slave station based on the slave station's previous clock compensation information, the current slave station system time, and the current FPGA system time corresponding to the FPGA terminal system.

[0068] This embodiment forms a complete distributed clock synchronization mechanism, from "information acquisition" to "reference determination," and then to "static compensation (delay and initial clock calibration)" and "dynamic maintenance (drift compensation)." Static compensation can solve "fixed deviations" (such as physical transmission delay and initial clock error); dynamic compensation can solve "dynamic deviations" (such as clock drift); and finally, through state transition, it can ensure that all slave stations reach a consistent time reference, laying the foundation for subsequent SYNC signal activation and system collaborative operation.

[0069] In a preferred embodiment of this first example, the step of calling the DC module to perform clock synchronization between slave stations further includes: for any slave station in the slave system: writing the DC cycle time obtained from the CPU terminal system to the slave station so that the slave station can trigger the issuance of a synchronization signal based on the DC cycle time; obtaining the current slave station system time and the current FPGA system time, and detecting the time difference between the current slave station system time and the current FPGA system time; if the time difference is less than a preset threshold, determining that the time synchronization between the slave station and the FPGA terminal system is successful; if the time difference is not less than the preset threshold, continuing to detect the time difference between the two; until the time synchronization between the slave station and the FPGA terminal system is successful; determining the start time of the synchronization signal, writing the start time to the slave station, and activating the synchronization signal based on the DC cycle time.

[0070] Specifically, determining the start time of the synchronization signal includes: determining the start time of the synchronization signal based on the system time of the FPGA terminal system, the message cycle time issued by the FPGA, and the DC function activation time.

[0071] The following section provides a detailed explanation of the method for calling the DC module to perform clock synchronization between slave stations, based on specific application scenarios.

[0072] A method for invoking the DC module to perform clock synchronization between slave stations includes at least the following steps:

[0073] S301, obtain DC support information and port switch information corresponding to each slave station in the slave station system from the CPU terminal system. If the DC support information indicates that the CPU terminal system has not specified a reference slave station, then proceed to step S302; if the DC support information indicates that the CPU terminal system has specified a reference slave station, then proceed to step S303.

[0074] S302, the first slave station that supports DC function is selected as the reference slave station according to the DC support information.

[0075] S303, Based on the reference slave station and the port switch information of each slave station, calculate the topology of the slave station system and obtain the port connection information of all slave stations.

[0076] S304, for any slave station in the slave station system: obtain the time when the slave station port receives the delay calculation instruction, and use this time as the port time information; obtain the delay of the slave station according to the port connection information and the slave station port time information; calculate the current clock compensation of the slave station according to the previous clock compensation information of the slave station, the current slave station system time, and the current FPGA system time corresponding to the FPGA terminal system.

[0077] S305, check if all slave stations have completed delay and clock compensation; if not, proceed to S306; if yes, proceed to S307.

[0078] S306, continue to perform delay and clock compensation on the slave station corresponding to the slave station address according to the slave station address; until all slave stations have completed the delay and clock compensation.

[0079] S307, all slave stations enter PREOP state; then execute step S308 or S309.

[0080] S308, Perform dynamic drift compensation operation for each of the slave stations.

[0081] S309, for any slave station in the slave station system: write the DC cycle time obtained from the CPU terminal system to the slave station so that the slave station can trigger the issuance of a synchronization signal based on the DC cycle time; obtain the current slave station system time and the current FPGA system time, and detect the time difference between the current slave station system time and the current FPGA system time; if the time difference is less than a preset threshold, determine that the time synchronization between the slave station and the FPGA terminal system is successful; if the time difference is not less than the preset threshold, continue to detect the time difference between the two; until the time synchronization between the slave station and the FPGA terminal system is successful; determine the start time of the synchronization signal, write the start time to the slave station, and activate the synchronization signal based on the DC cycle time.

[0082] For example: The CPU terminal system determines whether to enable the DC function and send relevant parameters. After the process data configuration state machine scan is completed, it obtains the DC support information and port switch information of each slave station. If the CPU terminal system does not specify a reference slave station, the first slave station that supports the DC function is used as the reference slave station. The process data configuration state machine calculates the topology of the slave station system based on the switch information obtained in the previous step, and obtains the port connection information of all slave stations. The process data configuration state machine obtains the time information of each port of each slave station, and combines it with the port connection information in the previous step to obtain the routing delay information between all slave stations. The process data configuration state machine calculates the routing delay information between all slave stations based on the existing previous clock compensation information of the slave station, the current slave station system time, and the current FPGA system time corresponding to the FPGA terminal system. The current clock compensation of the station; according to the above steps, the delay and clock compensation are completed for all slave stations in sequence, and all slave stations are waited to enter the PREOP state; after entering the state, the process data configuration state machine starts to continuously perform dynamic drift compensation, and each slave station fine-tunes its local clock rate according to the process data configuration state machine clock; the process data configuration state machine writes the SYNC signal cycle time obtained from the CPU to each slave station, and reads the time difference between the current slave station system time and the current FPGA system time. If the time difference is less than the threshold, it is considered that the slave station and the FPGA terminal system are successfully synchronized; otherwise, the above steps continue; the FPGA terminal system calculates the start time of the SYNC signal and writes the start time to the slave station; the SYNC signal is activated. After all slave stations have completed the above steps, the DC function is completed.

[0083] This embodiment uses "all slave stations completing the synchronization step" as the trigger condition for DC function activation. A closed-loop verification process ensures DC function reliability: from DC cycle time writing and time difference detection to start time configuration and SYNC signal activation, each step uses "all slave stations completing the operation" as the node, forming a closed-loop control of "configuration-detection-feedback-adjustment". This design avoids functional abnormalities caused by individual slave stations not being ready, ensuring that the entire slave system is fully synchronized when the DC function is activated, providing a stable and reliable time triggering foundation for subsequent high real-time applications (such as motion synchronization and data sampling synchronization in industrial control).

[0084] For example, an EtherCAT master station control method or system based on CPU and FPGA can be applied to humanoid robots; wherein the robotic arm motors of the humanoid robot can be assumed to be slave stations; here, DC functions are invoked to control different robotic arms of the humanoid robot to perform synchronous operations.

[0085] It should be understood that, in the various embodiments of the present invention, the order of the above-mentioned process numbers does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0086] like Figure 3 The diagram shown is a structural schematic of an EtherCAT master station control device based on a CPU and FPGA according to an embodiment of the present invention.

[0087] An EtherCAT master station control device based on CPU and FPGA, wherein the FPGA terminal system 104 includes: a state machine 1041, an EtherCAT data link layer 1042, a transmitting module 1043, and a receiving module 1044; the device is applied to the FPGA terminal system; including:

[0088] The state machine 1041 is used to send communication data to the sending module 1043; wherein the communication data includes: DC message data, message data generated by the state machine, PDO communication data, or SDO communication data;

[0089] The sending module 1043 is used to assemble the communication data into a first EtherCAT message and send the first EtherCAT message to the slave system through the EtherCAT data link layer 1042.

[0090] The EtherCAT data link layer 1042 is used to receive the second EtherCAT message from the slave system in response to the first EtherCAT message, and send the second EtherCAT message to the receiving module 1044.

[0091] The receiving module 1044 is used to parse the second EtherCAT message and feed back the parsing result to the state machine 1041.

[0092] The above-described device can execute an EtherCAT master station control method based on CPU and FPGA provided in an embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing an EtherCAT master station control method based on CPU and FPGA. Technical details not described in detail in this embodiment can be found in the EtherCAT master station control method based on CPU and FPGA provided in an embodiment of the present invention.

[0093] The present invention also provides an electronic device, comprising: a processor; a memory for storing executable instructions of the processor; the processor being configured to read the executable instructions from the memory and execute the instructions to implement the EtherCAT master station control method based on CPU and FPGA described in the present invention.

[0094] In addition to the methods and apparatus described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods according to various embodiments of this application described in the "Exemplary Methods" section above.

[0095] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0096] Furthermore, embodiments of this application may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the methods according to the following embodiments of this application described in the "Exemplary Methods" section above.

[0097] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0098] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0099] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0100] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0101] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0102] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

[0103] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0104] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0105] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An EtherCAT master station control system based on CPU and FPGA, characterized in that, include: Host computer, algorithm server, CPU terminal system, FPGA terminal system, CPU peripheral interface and FPGA peripheral interface; The CPU terminal system is used to communicate with the host computer, the algorithm server, and the FPGA terminal system via the CPU peripheral interface; and to control the FPGA terminal system to perform control operations that satisfy the EtherCAT protocol according to the business logic. The FPGA terminal system includes an EtherCAT protocol stack. The EtherCAT protocol stack primarily operates in state machine form. It is used to communicate with the slave system via the FPGA peripheral interface, and after receiving communication data from the CPU terminal system and / or reading the configuration parameters of the CPU terminal system, it parses and processes the communication data received from the slave system and feeds back the parsed results to the slave system. The state machine includes, but is not limited to, a master station state machine, a slave scanning state machine, a process data object reading state machine, a process data object entry reading state machine, a slave information interface state machine, a process data configuration state machine, a process data object entry configuration state machine, a slave configuration state machine, a state transition state machine, and a service data object download state machine. The FPGA peripheral interfaces include: a second high-speed communication interface and an EtherNet bus interface; The EtherCAT protocol stack is used to communicate with the CPU terminal system via the second high-speed communication interface; and to process the communication of state machine and process data after the communication network is initialized; the EtherCAT protocol stack is also used to provide non-cyclic access for the exchange of parameter data between the application programs of the EtherCAT master station and the slave station system. The host computer is used to configure parameters for the CPU terminal system and the slave system through a visual interface, and to monitor the overall operating status of the EtherCAT master control system; wherein the slave system includes at least one slave station. The algorithm server is used to receive communication data uploaded by the CPU terminal system according to the business logic provided by the EtherCAT master station control system; The FPGA terminal system sends the parsed result to the algorithm server through the CPU terminal system; the algorithm server controls the calculation of the parsed result and feeds back the calculation result to the CPU terminal system; the CPU terminal system feeds back the calculation result to the slave system through the FPGA terminal system.

2. The system according to claim 1, characterized in that, The CPU terminal system includes: a user application program, an EtherCAT control module, and a communication bus driver; the CPU peripheral interface includes an EtherNet communication interface and a first high-speed communication bus interface. The user application is used to communicate data with the host computer and the algorithm server via the EtherNet communication interface, and to send control commands corresponding to the business logic to the EtherCAT control module via the EtherCAT control interface. The EtherCAT control module is used to perform control operations conforming to the EtherCAT protocol on the FPGA terminal system according to the control instructions. The communication bus driver is used to connect to the FPGA terminal system through the first high-speed communication bus interface; and to provide hardware-level support for the first high-speed communication bus interface.

3. The system according to claim 1, characterized in that, The FPGA terminal system also includes: an EtherCAT data link layer; The EtherCAT data link layer is used to connect to the slave system via the EtherNet bus interface and to provide a real-time and reliable communication data transmission channel for the FPGA terminal system and the slave system.

4. The system according to claim 1, characterized in that, The CPU peripheral interface also Includes: UART and CAN communication interfaces; the UART and CAN communication interfaces are used to connect external UART or CAN devices, or to debug the CPU terminal system.

5. The system according to claim 1, characterized in that, The communication data between the FPGA terminal system and the CPU terminal system includes, but is not limited to, slave PDO configuration information, SDO communication data, TX PDO communication data, RX PDO communication data, DC configuration information, general parameter information, slave SM configuration information, and slave dynamic PDO configuration.

6. A CPU and FPGA-based EtherCAT master station control method, wherein the method is applied to the CPU and FPGA-based EtherCAT master station control system as described in any one of claims 1-5, characterized in that, The FPGA terminal system includes: a state machine, an EtherCAT data link layer, a transmitting module, and a receiving module; the FPGA terminal system performs the following steps: The state machine sends communication data to the sending module; wherein the communication data includes: DC message data, message data generated by the state machine, PDO communication data, or SDO communication data; The sending module assembles the communication data into a first EtherCAT message and sends the first EtherCAT message to the slave system through the EtherCAT data link layer. The EtherCAT data link layer receives the second EtherCAT message from the slave system in response to the first EtherCAT message, and sends the second EtherCAT message to the receiving module. The receiving module parses the second EtherCAT message and feeds back the parsing result to the state machine.

7. The method according to claim 6, characterized in that, The master station state machine reads the number of slave stations in the system network segment that are in operation from the slave stations and then clears the configuration address and delay register of the slave stations in sequence; Then the slave scanning state machine is invoked; The slave scanning state machine sets the node address for the slave station, and after reading the initial application layer state, basic information in physical memory and information about the physical port from the slave station, it calls the slave information interface state machine. The slave information interface state machine reads the size and SII data of the slave's SII data; parses the SII data; and then calls the slave configuration state machine. The slave configuration state machine sets the slave to the initial INIT state, and after clearing the FMMU parameters, synchronization manager parameters, and distributed clock related parameters in sequence, it configures the synchronization manager parameters and related registers of the PDI type interface inside the slave. Then the state transition state machine is invoked; After the state transition state machine transitions the slave station into the PREOP state, it calls the process data object to read the state machine. The process data object reads the relevant information parameters of the PDO type data supported by the slave station from the slave station through the state machine, and then checks whether the operation object is the last slave station in the system network segment; If the detection result indicates that the last slave station is not the last slave station, the process data object reads the state machine to update the slave station number to be operated and calls the slave station scanning state machine again to perform the relevant operations until all slave stations in the network segment represented by the detection result have been operated and then returns to the running state of the master station state machine. When all slave stations in the network segment are in the PREOP state, the master station state machine controls the XML configuration module to parse the configuration information for the slave stations according to the XML configuration information sent by the user application, and controls the FMMU configuration module to configure the SYNC parameters and FMMU parameters for the slave stations; after the configuration parameter operation is completed, the master station state machine sets the slave station's state to run OP and calls the slave station configuration state machine. The slave configuration state machine sets the slave to the initial INIT state, and after clearing the FMMU parameters, synchronization manager parameters, and distributed clock related parameters in sequence, it configures the synchronization manager parameters and related registers of the PDI type interface inside the slave. When the slave enters PREOP, if there is a CPU terminal system-defined PDO configuration, the process data configuration state machine is called. The process data configuration state machine sequentially configures custom PDO parameters, as well as SYNC and FMMU parameters for the slave station; If distributed clock settings are required, the DC module is called to perform clock synchronization between slave stations, and the state transition state machine is called after the clock synchronization operation is completed. When the state transition state machine detects that the slave is in the PREOP state, it transitions the slave to the SAFEOP state. When the state transition state machine detects that the slave is in the SAFEOP state, it transitions the slave to the OP state.

8. The method according to claim 7, characterized in that, The invocation of the DC module to perform clock synchronization between slave stations includes: Obtain DC support information and port switch information corresponding to each slave station in the slave station system from the CPU terminal system; If the DC support information indicates that the CPU terminal system has not specified a reference slave, then the first slave that supports DC function will be used as the reference slave according to the DC support information. Based on the reference slave station and the port switch information of each slave station, the topology of the slave station system is calculated to obtain the port connection information of all slave stations; For any slave station in the slave station system: obtain the time when the slave station port receives the delay calculation instruction, and use this time as the port time information; calculate the delay and clock compensation of the slave station based on the port connection information, slave station port time information, current slave station system time, and current FPGA system time; Check whether all slave stations have completed delay and clock compensation; if not, continue to perform delay and clock compensation on the slave station corresponding to the slave station address according to the slave station address; until all slave stations have completed delay and clock compensation, all slave stations enter the PREOP state; Perform dynamic drift compensation operation on each of the slave stations.

9. The method according to claim 8, characterized in that, The step of calculating the delay and clock compensation of the slave station based on the slave station's port connection information, slave station port time information, current slave station system time, and current FPGA system time includes: The delay of the slave station is obtained based on the port connection information and port time information of the slave station; The current clock compensation of the slave station is calculated based on the previous clock compensation information of the slave station, the current slave station system time, and the current FPGA system time corresponding to the FPGA terminal system.

10. The method according to claim 8, characterized in that, Also includes: For any slave station in the slave station system: the DC cycle time obtained from the CPU terminal system is written to the slave station so that the slave station can trigger the issuance of a synchronization signal based on the DC cycle time; Obtain the current slave system time and the current FPGA system time, and detect the time difference between the current slave system time and the current FPGA system time; If the time difference is less than a preset threshold, it is determined that the slave station and the FPGA terminal system are successfully synchronized in time; if the time difference is not less than the preset threshold, the time difference between the two continues to be detected until the slave station and the FPGA terminal system are successfully synchronized in time; the start time of the synchronization signal is determined and written to the slave station, and the synchronization signal is activated based on the DC cycle time.

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