Sensor module for scanning electron microscope applications

Abstract

The invention relates to a sensor module for scanning electron microscope applications, and discloses a scanning electron microscope (SEM) system. The SEM system includes an electron source configured to generate an electron beam and a set of electron optics configured to scan the electron beam across a sample and focus electrons scattered by the sample onto one or more imaging planes. The SEM system includes a first detector module positioned at the one or more imaging planes, wherein the first detector module includes a multi-pixel solid state sensor configured to convert scattered particles, such as electrons and / or x-rays, from the sample into a set of equivalent signal charges. The multi-pixel solid state sensor is connected to two or more application specific integrated circuits (ASICs) configured to process the set of signal charges from one or more pixels of the sensor.

Description

[0001] Related Application

[0002] This application is a divisional application. The parent of this divisional application is the invention patent application with the application date of August 25, 2020, the application number of 202080060224.5, and the invention name of “Sensor Module for Scanning Electron Microscope Applications”.

[0003] Cross-Reference to Related Applications

[0004] This application claims priority to U.S. Provisional Patent Application No. 62 / 892,545, filed August 28, 2019, in the name of Marcel Trimpl, the contents of which are incorporated by reference in its entirety. TECHNICAL FIELD

[0005] The present invention relates generally to the field of scanning electron microscopy, and more particularly to a versatile sensor module for scanning electron microscope applications, which provides an adaptive clustering and distributed digitization scheme. BACKGROUND

[0006] Manufacturing semiconductor devices, such as logic and memory devices, generally includes processing substrates, e.g., semiconductor wafers, using a large number of semiconductor manufacturing processes to form various features and multiple levels of the semiconductor devices. As semiconductor device sizes become increasingly smaller, there is a growing need to develop enhanced semiconductor device and photomask inspection and review apparatuses. Scanning electron microscope (SEM) systems are one such technology used to inspect and review samples. SEM systems incorporate particle detectors for detecting secondary electrons, backscattered electrons, and x-rays scattered from or emitted by a sample in response to a beam of primary electrons scanned across the sample. To improve the efficiency and accuracy of SEM systems, it is desirable to provide improved particle (e.g., electron and x-ray) sensor apparatuses and methods. SUMMARY

[0007] A scanning electron microscope system is disclosed. In one illustrative embodiment, the system includes an electron source configured to generate an electron beam. In another illustrative embodiment, the system includes a set of electron optics configured to scan the electron beam across a sample and focus electrons scattered by the sample onto one or more imaging planes. In another illustrative embodiment, the system includes a first detector module positioned at the one or more imaging planes. In another illustrative embodiment, the first detector module includes a multi-pixel solid-state sensor configured to convert scattered particles from the sample into a set of equivalent signal charges. In another illustrative embodiment, the multi-pixel solid-state sensor is connected to two or more application specific integrated circuits (ASICs) configured to process the set of signal charges from one or more pixels of the sensor.

[0008] An additional and / or alternative scanning electron microscope is disclosed. In one illustrative embodiment, the system includes an electron source configured to generate an electron beam. In another illustrative embodiment, the system includes a set of electron optics configured to scan the electron beam across a sample and focus electrons scattered by the sample onto one or more imaging planes. In another illustrative embodiment, the system includes a first detector module positioned at the one or more imaging planes. In another illustrative embodiment, the first detector module includes a multi-pixel application specific integrated circuit (ASIC). In another illustrative embodiment, each pixel of the multi-pixel ASIC comprises a photodiode configured to convert particles scattered by the sample into an equivalent electrical signal, and each pixel of the multi-pixel ASIC includes circuitry to process the equivalent electrical signal.

[0009] A method of inspecting a sample is disclosed. In one illustrative embodiment, the method includes generating a scan clock signal. In another illustrative embodiment, the method includes generating a first electron beam. In another illustrative embodiment, the method includes deflecting the first electron beam synchronized with the scan clock signal to scan an area on the sample. In another illustrative embodiment, the method includes directing a signal generated by the sample in response to the electron beam to a cluster comprising two or more pixels. In another illustrative embodiment, the method includes detecting a charge collected by the cluster in a first time interval, where the first time interval is synchronized with a scan clock to generate a first electrical signal corresponding to the charge collected by the cluster in the first time interval and convert the first electrical signal to a first digital signal. In another illustrative embodiment, the method includes detecting a charge collected by the cluster in a second time interval, where the second time interval is synchronized with a scan clock to generate a second electrical signal corresponding to the charge collected in the second time interval and convert the second electrical signal to a second digital signal, where converting the second electrical signal is started before converting the first electrical signal is completed. In another illustrative embodiment, the method includes determining that a defect is present by analyzing the first digital signal and the second digital signal.

[0010] An additional and / or alternative method of inspecting a sample is disclosed. In one illustrative embodiment, the method includes generating a scan clock signal. In another illustrative embodiment, the method includes generating a first electron beam. In another illustrative embodiment, the method includes deflecting the first electron beam to a first location on the sample. In another illustrative embodiment, the method includes directing a signal generated by the sample in response to the first electron beam to a pixel. In another illustrative embodiment, the method includes detecting a charge collected by the pixel to generate an electrical signal corresponding to the charge collected by the pixel. In another illustrative embodiment, the method includes comparing the electrical signal to a first threshold value and a second threshold value and determining that an element is present if the electrical signal is greater than the first threshold value and the electrical signal is less than the second threshold value.

[0011] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the application as claimed. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the general description, serve to explain the principles of the application. BRIEF DESCRIPTION OF DRAWINGS

[0012] Many of the advantages of the present disclosure can be better understood by referring to the accompanying drawings.

[0013] Figure 1Scanning electron microscope systems according to one or more embodiments of the disclosure are described.

[0014] Figure 2A Multi-pixel detector modules configured as secondary electron detectors according to one or more embodiments of the disclosure are described.

[0015] Figure 2B Multi-pixel detector modules configured as backscattered electron and / or x-ray detectors according to one or more embodiments of the disclosure are described.

[0016] Figure 2C Multi-pixel detector modules arranged in a multi-electron beam configuration according to one or more embodiments of the disclosure are described.

[0017] Figures 3A to 3D Combinations of clusters delivered to a selected number of channels by an ASIC according to one or more embodiments of the disclosure are described.

[0018] Figure 4A Block diagram views of connections between sensors and an ASIC and operations within one readout channel according to one or more embodiments of the disclosure are described.

[0019] Figure 4B Conceptual diagrams of a rough plan view of sensor pixels according to one or more embodiments of the disclosure are described.

[0020] Figures 5A to 5B Physical assemblies of detector modules according to one or more embodiments of the disclosure are described, respectively.

[0021] Figures 5C to 5D Physical assemblies of detector modules according to one or more additional and / or alternative embodiments of the disclosure are described, respectively.

[0022] Figure 6A Conceptual diagrams of a distributed digitization scheme using several ADCs within an ASIC to handle timing of clusters according to one or more embodiments of the disclosure are described.

[0023] Figure 6B Conceptual diagrams of the application of a sample-and-hold circuit to signals from one or more pixels and subsequent analog-to-digital conversion of the signals according to one or more embodiments of the disclosure are described.

[0024] Figure 7 Block diagram views of analog-to-digital conversion (ADC) units implemented within pixels of a readout ASIC according to one or more embodiments of the disclosure are described.

[0025] Figure 8 Flowcharts depicting methods of inspecting a specimen according to one or more embodiments of the disclosure are described.

[0026] Figure 9 A flowchart depicting a method of inspecting a specimen is illustrated in accordance with one or more additional and / or alternative embodiments of the disclosure. DETAILED DESCRIPTION

[0027] The present disclosure has been particularly shown and described with respect to certain embodiments thereof and specific features thereof. The embodiments set forth herein are considered to be illustrative and not restrictive. Various changes and modifications can become apparent to the skilled artisan from the disclosure herein without departing from the spirit and scope of the present disclosure. Reference will now be made in detail to the disclosed subject matter, which is illustrated in the accompanying drawings.

[0028] Embodiments of the present disclosure relate to a multi-purpose sensor module and method suitable for scanning electron microscope applications with adaptive clustering and distributed digitization schemes.

[0029] Figure 1 A conceptual diagram of a scanning electron microscope (SEM) system 100 is illustrated in accordance with one or more embodiments of the present disclosure. The SEM system 100 can be configured as an inspection and / or review tool. In this regard, the SEM system 100 can be used to review and / or inspect a specimen 128 for defects and reveal the material composition of the specimen 128 and / or defects. Alternatively, the SEM system 100 can be configured as an imaging-based overlay metrology tool. In this regard, the SEM system 100 can be used to acquire images of an overlay metrology target disposed on the specimen 128, which can then be used to determine overlay errors between successive layers of the specimen 128.

[0030] In embodiments, the SEM system 100 includes an electron source 102. The electron source 102 can include any electron source suitable for generating one or more electron beams 150. The electron source 102 can include one or more electron emitters 101. For example, the one or more electron emitters 101 can include a single electron emitter. By way of another example, the one or more electron emitters 101 can include a plurality of electron emitters. The one or more electron emitters 101 can include any electron emitter known in the art of electron emission technology. The electron source 102 can include one or more extractors 103.

[0031] In embodiments, the SEM system 100 includes an electron-optical system 111 including a set of electron-optical devices arranged into an electron-optical column. The electron-optical system 111 can include one or more focusing optics for focusing the electron beam 106 onto the sample 128. The electron-optical system 111 can include one or more deflection optics configured to scan the beam 106 across the sample 128. The electron-optical system 111 can include any focusing and deflection optics known in scanning electron microscopy technology. For example, the one or more focusing optics can include, but are not limited to, one or more condenser lenses 107 and one or more objective lenses 110. The one or more deflection optics can include, but are not limited to, one or more deflectors (e.g., scanning coils). For example, the electron-optical system 111 can include one or more deflectors 105 and one or more lower deflectors 109. During operation, the electron source 102 generates the electron beam 106. The electron beam 106 can be focused and deflected onto the sample 128 positioned on a moving stage 130 by the multiple focusing and deflection optics 105, 107, 109, 110 of the electron-optical system 111. In embodiments, the electron source 102 can generate multiple beams that are deflected and focused onto the sample 128. It should be noted that the electron source 102 and the electron-optical column 111 can be arranged into a single-beam configuration or into a multi-beam configuration including multiple sources / columns.

[0032] In embodiments, the system 100 includes one or more detector modules positioned at one or more selected locations within the electron-optical system 111. The one or more detector modules each include one or more multi-pixel solid-state sensors. For example, the detector modules 122a, 122b, and / or 122c can each include one or more solid-state sensors. For example, a first multi-pixel detector module 122a can be placed away from the sample 128 to collect secondary electrons 129 scattered from the sample and accelerated by the electrodes 121 onto the detector plane of the one or more multi-pixel solid-state sensors of the detector module 122a. In another example, the detector modules 122b and / or 122c can be placed close to the sample 128 to collect particles such as, but not limited to, backscattered electrons, x-rays, and / or Auger electrons (e.g., particles emitted from the sample at very high solid angles) emitted from the sample 128. As shown in Figure 1 In embodiments, one or more of the detector modules 122a-122c can be positioned within the electron-optical column. It should be noted that the scope of the present disclosure is not limited to the number or position of the detector modules depicted in Figure 1 In embodiments, one or more of the detector modules 122a-122c can be positioned within the electron-optical column. It should be noted that the scope of the present disclosure is not limited to the number or position of the detector modules depicted in

[0033] In embodiments, one or more of the multi-pixel solid-state sensors, detector modules 122a, 122b, and / or 122c, are connected to two or more logic elements. For example, one or more of the multi-pixel solid-state sensors may be connected to two or more application-specific integrated circuits (ASICs). In embodiments, the two or more logic elements are configured to process the group of signal charges from the pixels of a given multi-pixel solid-state sensor. While it should be noted that one or more detector modules can utilize any suitable logic element known in the art to process the signal charges from the pixels, for simplicity, detector modules are described in the background of ASICs. This configuration should not be construed as limiting the scope of this disclosure.

[0034] Figures 2A to 2C This describes different configurations of the multi-pixel detector module 122 applicable to system 100 according to one or more embodiments of this disclosure. Figure 2A This describes a configuration suitable for use as a multi-pixel detector module as a secondary electronic detector. Figure 2B This describes a multi-pixel detector module configuration suitable for use as a backscattered electron and / or X-ray detector. Figure 2C This describes the configuration of a multi-pixel detector module for a multi-electron beam system, wherein the deflection signals from all electron beams are detected simultaneously by the multi-pixel detector module.

[0035] In an embodiment, such as Figure 2A As shown, the multi-pixel detector module 122 includes a substrate carrier 201. For example, the substrate carrier 201 may comprise a ceramic material on which a multi-pixel solid-state sensor read out via an ASIC is mounted. The substrate carrier 201 includes a set of electrical contacts 203 for manipulating and controlling voltage and provides a data path, thereby allowing data to be collected by the module. Region 202 represents the area covered by an ASIC. For example, such as... Figure 2B As shown in the diagram, region 202 represents an area covered by an ASIC with a size of 4mm × 4mm that can contain 16 × 16 pixel readout channels. It should be noted that... (The sentence is incomplete and requires further context to be translated accurately.) Figure 2A The number, size, or location of the ASIC clusters of pixels shown in the diagram limits the scope of this disclosure. Rather, it should be noted that different ASIC clustering configurations can be implemented for different use cases. Table I illustrates the cluster size and the resulting cluster conversion rate.

[0036] Table I. Cluster conversion rates for various cluster sizes.

[0037]

[0038] An example uses 250 μιη sensor pixels, and a total of 16x16 sensor pixels read out per ASIC and data converters with a conversion rate of 3 MHz incorporated into each readout pixel.

[0039] In Figure 2A an example, a cluster size of 8x8 pixels is configured and a total of 4 clusters per ASIC are generated. Such a configuration can be particularly useful in the case of a secondary electron detector. The conversion rate per cluster in this configuration is approximately 200 MHz. Further, the clusters generated by the ASIC can be further processed in the downstream data path to generate one or more sub-channels of the detector. Note that, Figure 2B A case is illustrated where 5 channels are generated by the module.

[0040] In an embodiment, as Figure 2B shown in Figure 2B an example depicted in Figure 2B one application shown in Figure 2B the set of detector modules shown in

[0041] In embodiments, one or more of the detector modules 122 can include a screen 204. The screen 204 can be inserted on top of one or more modules 122. The screen can be formed of a thin material with low atomic number. For example, the screen 204 can include, but is not limited to, a 50-150 pm thin beryllium screen. For example, the screen can be a 100 pm beryllium screen. By way of another example, the screen can include a layer of material formed directly onto the sensor module 122. For example, the screen can include, but is not limited to, a layer of boron or carbon or aluminum deposited directly onto the sensor module 122. During operation, the screen 204 absorbs electrons scattered by the sample during scanning and allows a majority of the x-rays generated by the sample during scanning to pass through, providing more efficient detection. The screen 204 can be added to one or more of the detector modules and it can be permanently installed or can be inserted and retracted to change the configuration of the modules 122. It should be noted that the utilization of the screen 204 is not limited to the configuration depicted in Figure 2B and one or more screens 204 can be utilized with any number of detection modules 122 and in any arrangement.

[0042] In embodiments, as shown in Figure 2C , the ASIC of the detector module 122 is configured with a cluster size of 4x4. It should be noted that if this one detector module is implemented with a multi-beam configuration of the SEM system 100, then this module would be utilized to detect a total of 400 scattered beams at a rate of close to 50 MHz.

[0043] Figures 3A to 3D A combination of clusters delivering to a select number of channels by the ASIC is illustrated in accordance with one or more embodiments of the present disclosure. It should be noted that the formation of multiple channels as shown in Figures 3A to 3D can be adjusted for different use cases of the SEM system 100. For example, as shown in Figure 3A , a configuration with one center channel 301 and 4 side channels 302a, 302b, 302c, 302d is illustrated. The combination of clusters can be performed dynamically during scanning, whereby the shape and size of the channels can change within the module 122. This feature can accommodate changes in the scattered beams 129 during scanning, for example, changes in the focus / defocus of the primary beam 106 or shifts in the scattered beams 129. For example, the cluster configuration of Figure 3B can be implemented to accommodate situations where the scattered electron beams 129 are shifted or drifted (moved from a central position to a non-central position) of the module.

[0044] By way of another example, the cluster configuration of Figure 3C can be implemented to accommodate situations where a larger center channel is needed. By way of another example, the cluster configuration of Figure 3D can be implemented to accommodate situations where a smaller center channel is needed. By way of another example, multiple individual clusters can be combined into a single center channel.

[0045] Figure 4A A block diagram view of connections between a sensor and an ASIC and operation within one readout channel according to one or more embodiments of the disclosure is illustrated.

[0046] In an embodiment, the sensor 401 is attached to one or more ASICs 402 with at least one connection per pixel. In one configuration, the sensor pixel 403 can be composed of a floating diffusion node (FD), such as a floating diffusion capacitor, which collects charge generated within the pixel in the volume connected to the gate of an amplifier stage. In this example, the amplifier stage can be biased by a common voltage VOD (voltage drain). The output (OS) of the amplifier stage can be connected to an individual readout pixel 404 of the ASIC for further processing. In an embodiment, the amplifiers in the sensor pixels can be connected such that the source potential is biased at a constant voltage and the signal is read out at the drain.

[0047] In an embodiment, the voltage of the floating diffusion node is controlled by a reset stage. In this configuration, the reset stage can include a simple reset transistor, whereby the drain of the transistor is connected to a global reset voltage (RD). The reset stage can be controlled via a reset gate (RG).

[0048] In an embodiment, the reset gate can provide a global signal common to all pixels of the sensor array.

[0049] In an embodiment, an additional contact per pixel can be provided between the reset gate of the pixel of the sensor layer and the reset circuit unit within each pixel of the ASIC.

[0050] The top sensor stack 401 of the assembly can be a sensor layer utilizing resistive gate and floating diffusion technology as described in U.S. Patent No. 9,767,986, entitled “Scanning Electron Microscope and Method for Inspection and Review Samples,” issued to Brown et al. on September 19, 2017, which is incorporated by reference herein in its entirety.

[0051] In an embodiment, instead of using a sensor layer 401 attached to a readout ASIC, a photodiode can be implemented in each pixel of the ASIC to detect particles deflected from the sample 128 during scanning. The photodiode can be implemented by using deep implants of a high voltage (HV) process with 10V or more power rails.

[0052] In an embodiment, the pixel of the readout ASIC 404 receives a signal from the sensor pixel with an input stage. The parasitic impedance between the amplifier output and the input stage can be kept to a minimum to achieve maximum processing speed at a given power consumption. The input stage is connected by a cluster summing circuit that sums the signals from this pixel and neighboring pixels to a cluster. Figure 4AThe connections from the center pixel and two immediate neighbors are shown, indicating additional input from nearby other pixels. The physical size of the cluster should be in the range of 1 to 10 pixels, with cluster 1 indicating a disabled summation and each pixel is processed individually (see the example given in Table 1, for example). The cluster signal can then be further processed by digitization and additional processing. The digitization step can include a standard analog-to-digital conversion with an equidistant quantization step or a multi-threshold chemical element search, as further described in Figure 7 For applications involving the detection of individual events, a time stamping unit can be implemented to record the arrival of each event with a scan clock and assign the event to a scan position on the sample. It should be noted that part of the post-processing involves the data flow handling necessary to decouple the data from each pixel from each ASIC. The summation of pixel values can be performed in the post-processing unit after digitization.

[0053] In embodiments, a reset circuit can be triggered by the digitization unit to control the voltage of the reset gate of the sensor pixels. The reset circuit can use high voltage process components to provide sufficient voltage to make the reset stage functional (e.g., 10V to 30V). Control of the reset gate can be in the form of a reset pulse to reset the floating diffusion. Pixel-by-pixel reset can extend the dynamic range of the sensor pixels indefinitely and accommodate particle flux variations between pixels within the sensor. This reset pulse can be synchronized for all pixels of the sensor to mimic the functionality of a global reset. Utilization of pixel-by-pixel reset can achieve very fast reset with low power because much smaller capacitance is driven compared to a global reset that is routed throughout the sensor array. The reset circuit can also provide an analog voltage to form a closed feedback loop control to the floating diffusion to enhance immunity to pixel-to-pixel transistor variations and thermal drift.

[0054] Figure 4B Conceptual diagrams illustrating a rough plan view of a sensor pixel according to one or more embodiments of the disclosure. Figure 4B A rough plan view of a sensor pixel is depicted, with reset gate (RG) and output signal (OS) connections to the readout ASIC and other bias points, reset drain (RD) and voltage drain (VOD) of the sensor pixel as global signal routing for the entire sensor array. In embodiments, where a reset gate (RG) is not provided for each pixel from the ASIC, the reset gate (RG) can be routed row-by-row or globally across the sensor similar to the reset drain and voltage drain signals.

[0055] Figures 5A to 5B Physical assemblies of a detector module 122 according to one or more embodiments of the disclosure are illustrated, respectively.

[0056] Figure 5AA backside view of one embodiment of a multi-pixel detector module is depicted, with several ASICs 507 connected to the sensor. The view is onto the backside of the ASICs. Figure 5B A side view of a detector module 122 containing a multi-pixel solid state sensor 502 with backside processing 501 is depicted. In embodiments, the backside processing can include a boron coating. In embodiments, the sensor layer is connected to a through-silicon via interposer (TSI) 504 via solder bumps. Other assembly techniques such as direct bond interconnect (DBI) can be utilized. A TSI of about 100 pm thickness can utilize fine pitch (10 pm to 20 pm). Through-silicon vias 505 can electrically connect the front side with the backside of the TSI. The pitch of the TSVs in the TSI can be much denser than the pixel pitch in the sensor or ASIC. A multi-metal redistribution layer (RDL) including multiple metal layers 506 (e.g., 4 or more) is used on the backside of the TSI to route different pixel outputs from the sensor to the inputs of the ASIC 507, which can be at different pitches. For example, 250 pm x 250 pm size pixels on the sensor layer can be matched by about 180 pm x 180 pm size pixels in the ASIC.

[0057] In embodiments, as shown in Figure 5B , the ASICs can implement TSVs and the inputs and outputs of the ASICs can be connected on the backside of the ASICs to electrical connections on a mechanical substrate 509. In the case of 16 x 16 pixels covered by each ASIC, the difference in pixel size between the ASICs and the sensor can leave about 1 mm of space between the ASICs as an assembly margin.

[0058] In embodiments, the ASICs can not contain TSVs. In this case, as shown in Figure 5C and 5D , an alternative assembly can be implemented. In this embodiment, one row of ASICs 511 at the side of the sensor is offset so that wire bond pads are exposed and accessible to connect to a substrate. The transfer of steering signals and data from one ASIC to the other ASICs under the sensor area can be done via additional solder connections to the TSI and routed within the RDL of the TSI to the other ASICs.

[0059] It is noted that in embodiments where the detector module 122 utilizes one or more TSVs in the ASICs, it is possible to construct a detector module that can scale indefinitely without creating a gap in the sensitive area of the module.

[0060] The following procedure can be used to manufacture the assembly depicted in Figure 5D .

[0061] TSI 504 can be fabricated with a selected thickness (e.g., approximately 100 pm), ASIC 507 can be thinned to the selected thickness (e.g., approximately 100 pm), and an unthinned sensor 502 can be provided. First, a handling wafer (not shown) can be attached to the front side of sensor 502 (i.e., the top side of sensor 502 as shown in Figure 5D FIG. 1). Next, the back side of sensor 502 can be thinned. After thinning, the back side of sensor 502 can be processed. For example, the back side of sensor 502 can be processed with a boron implant process to form boron implant layer 501. Next, a handling wafer (not shown) can be attached to the back side of sensor 502 (i.e., the bottom side of sensor 502 as shown in Figure 5D FIG. 1). In turn, the handling wafer can be removed from the front side of sensor 502. Next, the front side of sensor 502 can be electrically connected to the front side of the TSI via one or more connection mechanisms 503 (e.g., with solder bumps or direct bond interconnect (DBI) technology). Additionally, ASIC 507 can be electrically connected to the back side of TSI 504 with redistribution layer 506. Finally, the handling wafer can be removed from the back side of sensor 502 and the sensor / TSI / ASIC assembly can be attached to substrate 509. The handling wafer can be removed after the sensor / TSI / ASIC assembly is attached to substrate 509.

[0062] It should be noted that the procedure for fabricating the assembly depicted in Figure 5B may employ methods similar to the procedure for the assembly depicted in Figure 5D . Additionally, fabricating the assembly of Figure 5B may include an ASIC with TSVs (through-silicon vias) and additional steps whereby a handling wafer is used to thin and mount ASIC 507 to substrate 509 and to electrically connect pads with solder bumps 513.

[0063] Figure 6A Conceptual diagram 600 illustrates the concept of a distributed digitization scheme that uses several ADCs within an ASIC to process the timing of a cluster, in accordance with one or more embodiments of the present disclosure. It should be noted that the distributed digitization scheme can employ any number of ADCs, such as (but not limited to) 256. Figure 6B Conceptual diagram 610 depicts a sample-and-hold (S&H) circuit for a signal from one or more pixels and the subsequent analog-to-digital conversion of the signal. As Figure 6BAs shown, each digitizer can employ a fast S&H circuit that can hold the analog value at the speed of the sample scan clock ti, at which the electron beam is rasterized across the sample. Then, each ADC can convert the analog value to a digital value in a conversion time t2that is significantly slower than ti. Conversion time t2is compatible with the number of sample scans and the number of pixels (and thus ADCs) combined into a cluster. In one example, 8x8 pixels of a sensor can be combined into one cluster and 64 ADCs are used for conversion of this cluster. In this example, a single conversion frequency of 3MHz can then support a wafer scan clock of 192MHz.

[0064] Figure 7 Analog-to-digital conversion (ADC) unit 700 within each pixel of a readout ASIC according to one or more embodiments of the disclosure is illustrated. In embodiments, an initial S&H unit stores the acquired signal from the detector for each clock cycle of the sample scan. Then, ADC 700 can be used in a classical analog-to-digital conversion following the SAR (successive approximation register) ADC principle. In the 'ADC mode', a DAC (digital-to-analog converter) is supplied by a look-up table (LUT) which is a standard conversion table containing standard conversion steps from a binary search leading to equidistant digitization.

[0065] In embodiments, a DAC can also be driven by a look-up table (LUT) containing reference levels equivalent to the upper and lower thresholds (defining an energy window) of the chemical elements (e.g. silicon, aluminum, copper, titanium and other elements) that can be present during the sample scan. The comparison of each signal with the energy window results in the presence of a specific chemical element. This mode can be referred to as the 'element ID mode'. In embodiments, ADC unit 700 can switch between the ADC mode and the element ID mode. It should be noted that switching between the ADC mode and the element ID mode can only require a different configuration of the look-up table used in the ADC. The ADC unit can contain multiple comparators, one for the upper threshold and one for the lower threshold, defining the energy window of each specific element to be detected.

[0066] Figure 8 A flowchart of a method 800 for inspecting a sample according to one or more embodiments of the disclosure is illustrated. It should be noted herein that the steps of method 800 can be implemented in whole or in part by system 100. However, it should be further appreciated that method 800 is not limited to system 100, as additional or alternative system-level embodiments can carry out all or part of the steps of method 800.

[0067] In step 802, the method includes generating a scan clock signal. In step 804, the method includes generating a first electron beam. In step 806, the method includes deflecting the first electron beam synchronized with the scan clock signal to scan an area on a sample. In step 808, the method includes directing a signal generated by the sample in response to the electron beam to a cluster comprising two or more pixels. In step 810, the method includes detecting a charge collected by the cluster in a first time interval, wherein the first time interval is synchronized with the scan clock to generate a first electrical signal corresponding to the charge collected by the cluster in the first time interval and convert the first electrical signal to a first digital signal. In step 812, the method includes detecting a charge collected by the cluster in a second time interval, wherein the second time interval is synchronized with the scan clock to generate a second electrical signal corresponding to the charge collected in the second time interval and convert the second electrical signal to a second digital signal, wherein converting the second electrical signal is started before converting the first electrical signal is completed. In step 814, the method includes determining that a defect is present by analyzing the first digital signal and the second digital signal.

[0068] Figure 9 A flowchart of a method 900 for inspecting a sample according to one or more additional and / or alternative embodiments of the present disclosure is illustrated. It is noted herein that the steps of the method 900 can be implemented in whole or in part by the system 100. However, it is further recognized that the method 900 is not limited to the system 100, as additional or alternative system-level embodiments can carry out all or part of the steps of the method 900.

[0069] In step 902, the method includes generating a scan clock signal. In step 904, the method includes generating a first electron beam. In step 906, the method includes deflecting the first electron beam to a first location on a sample. In step 908, the method includes directing a signal generated by the sample in response to the first electron beam to a pixel. In step 910, the method includes detecting a charge collected by the pixel to generate an electrical signal corresponding to the charge collected by the pixel. In step 912, the method includes comparing the electrical signal to a first threshold value and a second threshold value and determining that an element is present if the electrical signal is greater than the first threshold value and the electrical signal is less than the second threshold value.

[0070] Referring again to Figure 1In embodiments, the system 100 includes a controller 140. The controller 140 can be used to provide one or more control signals C to the electron source 102, the electron optical column 111, and / or the detector assembly 122a-c. In this regard, the controller 140 can control any aspect of the SEM system 100. In embodiments, the controller 140 can receive from the detector assembly 122a-c one or more image data signals ID1, ID2 indicative of or containing one or more images of one or more features (e.g., defects, pattern features, metrology targets, and the like) of the specimen 128. The controller 140 can include one or more processors configured to execute program instructions maintained in a memory medium. In this regard, the one or more processors of the controller 140 can perform any of the various process steps described throughout this disclosure.

[0071] All of the methods described herein can include storing results of one or more steps of the method embodiments in a memory. The results can include any of the results described herein and can be stored in any manner known in the art. The memory can include any memory described herein or any other suitable storage medium known in the art. After the results have been stored, the results can be accessed in the memory and used by any of the method or system embodiments described herein, formatted for display to a user, used by another software module, method, or system, and the like. Further, the results can be stored "permanently," "semi-permanently," "temporarily," or for some period of time. For example, the memory can be random access memory (RAM) and the results can not necessarily remain in the memory indefinitely.

[0072] It is further contemplated that each of the embodiments of the methods described above can include any other step(s) of any other method(s) described herein. Additionally, each of the embodiments of the methods described above can be performed by any of the systems described herein.

[0073] Those skilled in the art will recognize that the discussion of components, operations, devices, objects, and the like in this description is intended to be examples only and is not intended to limit the concepts described herein to the examples described herein. Thus, the specific examples described herein are intended to be representative only and not exhaustive. In general, the use of any specific example is intended to be illustrative and not limiting.

[0074] As used herein, directional terms such as "top," "bottom," "above," "below," "upper," "upward," "lower," "downward," and the like, are intended to provide relative positions for purposes of description and are not intended to be limiting of an absolute reference frame. One of ordinary skill in the art will appreciate the various modifications to the described embodiments, and the general principles defined herein can be applied to other embodiments as well.

[0075] With respect to essentially any plural and / or singular terms used herein, one of ordinary skill in the art can convert from plural to singular and / or from singular to plural depending on the context and / or application. For clarity, various singular / plural permutations are not explicitly addressed herein.

[0076] The subject matter described herein is sometimes illustrated describing various components contained within other components or connected thereto. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermediate components. Likewise, any two components so associated can also be viewed as being "connected" or "coupled" to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being "couplable" to each other to achieve the desired functionality. Specific examples of couplable include but are not limited to physically mateable and / or physically interacting components and / or wirelessly interactable and / or wirelessly interacting components and / or logically interacting and / or logically interactable components.

[0077] Furthermore, it is to be understood that the invention is defined by the appended claims. Those skilled in the art will appreciate that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are general, and are not to be construed as limiting. Terms such as "including," "having," "containing," or "encompassing" are inclusive and do not exclude additional, unrecited elements or method steps. The terms "comprises", "comprising", "includes", "including", "such as" and "including" specify the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. The term "about" when used before a numerical designation, has its ordinary meaning in common speech. It is commonly used to indicate approximations of a numerical value in whole or in part. Numerical designations that are not preceded by the term "about" are to be interpreted in a literal sense. It is to be understood that the terms so used are merely descriptive, and do not limit the scope of items described, nor the scope of protection to be afforded.For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

[0078] It is believed that the disclosure and many of its attendant advantages will be understood by the foregoing description, and it will be apparent that various changes can be made in the form, construction and arrangement of the components without departing from the disclosed subject matter or without sacrificing all of its material advantages. The form described is merely exemplary and the actual disclosure is intended to encompass and to be limited to the scope of the appended claims.

Claims

1. A method for testing a sample, comprising: Generate a scan clock signal; The first electron beam is generated; The first electron beam is deflected to a first position on the sample; The signal generated by the sample in response to the first electron beam is directed to the pixel; The charge collected by the pixel is detected to generate an electrical signal corresponding to the charge collected by the pixel; and The presence of an element is determined by comparing the electrical signal with a first threshold and a second threshold, and by the condition that the electrical signal is greater than the first threshold and less than the second threshold.

2. The method according to claim 1, wherein the first threshold is less than the electrical signal corresponding to the characteristic energy of the element, and the second threshold is greater than the electrical signal corresponding to the characteristic energy of the element.

3. The method of claim 1, wherein the element comprises at least one of silicon, aluminum, copper, tungsten, or titanium.

4. The method of claim 1, further comprising: The first electron beam is deflected to a second position on the sample; The second signal generated by the sample in response to the first electron beam is guided to the pixel; Detect the second charge collected by the pixel to generate a second electrical signal corresponding to the second charge collected by the pixel; The element is determined to exist if the second electrical signal is greater than the first threshold and less than the second threshold. and Generate a map of the locations where the element exists on the sample.

5. The method of claim 4, further comprising: The first electrical signal and the second electrical signal are compared with the third threshold and the fourth threshold, and it is determined that a second element exists when the second electrical signal is greater than the third threshold and the second electrical signal is less than the fourth threshold; and Generate a map of the location on the sample where at least one of the first element or the second element exists.

6. A method for testing a sample, comprising: Generate a scan clock signal; The first electron beam is generated; The first electron beam, synchronized with the scanning clock signal, is deflected to scan a region on the sample; The signal generated by the sample in response to the electron beam is directed to a cluster comprising two or more pixels; Detecting the charge collected by the cluster in a first time interval, wherein the first time interval is synchronized with a scan clock to generate a first electrical signal corresponding to the charge collected by the cluster in the first time interval and converting the first electrical signal into a first digital signal; Detecting the charge collected by the cluster during a second time interval, wherein the second time interval is synchronized with the scan clock to generate a second electrical signal corresponding to the charge collected during the second time interval and converting the second electrical signal into a second digital signal, wherein the conversion of the second electrical signal begins before the conversion of the first electrical signal is completed; and The existence of a defect was determined by analyzing the first digital signal and the second digital signal.

7. The method of claim 6, wherein detecting the charge comprises summing the charges from the two pixels.

8. The method of claim 7, wherein the summation comprises summing over one of the voltage domain and the current domain.

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