Coherent speed measurement processing device

Abstract

The invention discloses a coherent velocity measurement processing device, which is characterized in that the coherent velocity measurement processing device comprises a work clock generator used for providing a frequency conversion filter local oscillation frequency, a sampling clock of an analog-to-digital converter AD and a work clock of an FPGA chip; the frequency conversion filter is used for converting the received downlink radio frequency signal into an intermediate frequency and obtaining an intermediate frequency signal after band-pass filtering of the signal; the analog-to-digital converter AD is used for carrying out AD sampling on the signal sent by the frequency conversion filter to obtain a digital signal; and the FPGA chip receives the digital signal sent by the analog-to-digital converter AD, completes phase-locked tracking, extracts a real-time Doppler value, smooths and samples the real-time Doppler value, and completes conversion calculation in the speed calculation module, thereby completing calculation of the radial speed of the target. According to the coherent velocity measurement processing device, the coherent velocity measurement precision is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of spaceflight measurement and control and target range measurement, and particularly relates to a phase reference velocity measurement processing device. BACKGROUND

[0002] In the field of spaceflight measurement and control and target range measurement, a measurement and control system based on two-way Doppler velocity measurement is widely used. The velocity measurement system generally comprises a ground transmitter, an aircraft transponder and a ground receiver. The transponder is a phase-locked phase reference transponder. In the measurement process, the transponder locks the uplink radio frequency measurement signal transmitted by the ground transmitter, and then transmits the measurement signal to the ground receiver after frequency conversion to the downlink radio frequency according to the set forwarding ratio, and the ground receiver completes the velocity measurement. Compared with one-way Doppler velocity measurement, two-way Doppler velocity measurement based on phase reference forwarding has high measurement accuracy. The measurement accuracy of the current advanced velocity measurement system in China can reach the centimeter level.

[0003] The flight parameters of an inertial trajectory aircraft can be calculated from the real-time measurement data of the velocity, distance and other indexes of the aircraft, so as to obtain the orbit information of the aircraft. For an inertial trajectory aircraft with a super-long range, it is required to accurately evaluate the landing point accuracy and guidance error of the aircraft, and the measurement accuracy of the external trajectory is required to be higher. In order to reduce the test cost, China adopts the method of a small number of special trajectory tests for type selection, and the measurement accuracy of the external trajectory is required to be higher, especially the velocity measurement accuracy, and the type department proposes a super-high velocity measurement requirement of better than 0.01 m / s. Therefore, based on the existing measurement system, how to improve the phase reference velocity measurement accuracy to the millimeter level has become a key difficulty. SUMMARY

[0004] The purpose of the present application is to overcome the problems of the prior art and disclose a phase reference velocity measurement processing device to improve the phase reference velocity measurement accuracy.

[0005] The purpose of the present application is achieved by the following technical solutions. A phase reference velocity measurement processing device, comprising: a working clock generator for providing a frequency conversion filter local oscillator frequency, an analog-to-digital converter AD sampling clock and a working clock of an FPGA chip; a frequency conversion filter for frequency conversion of a received downlink radio frequency signal to an intermediate frequency and completion of band pass filtering of the signal to obtain an intermediate frequency signal; an analog-to-digital converter AD for AD sampling of the signal sent by the frequency conversion filter to obtain a digital signal; an FPGA chip for receiving the digital signal sent by the analog-to-digital converter AD, completing phase-locked tracking, extracting a real-time Doppler value and smoothing and sampling, completing conversion calculation in a velocity calculation module, and thus completing calculation of the target radial velocity.

[0006] According to a preferred embodiment, the working clock generator generates the frequency conversion filter local oscillator frequency, the analog-to-digital converter (ADC) sampling clock and the FPGA chip working clock based on frequency multiplication or direct digital frequency synthesis (DDS) with bit width not less than 48 bits.

[0007] According to a preferred embodiment, the working clock generator comprises a 10MHz source and a frequency synthesizer, The 10MHz source is based on a frequency source structure with accuracy and stability better than 10e-11, and the output 10MHz frequency is used as the frequency reference in the frequency synthesizer.

[0008] According to a preferred embodiment, the FPGA chip comprises a down-conversion DDC module, a first automatic gain control (AGC) circuit, a second AGC circuit, a carrier loop module, a sampler, a speed calculation module, The first AGC circuit is composed of a first low-pass filter, a first gain calculation module and a first gain adjustment module; the second AGC circuit is composed of a second gain adjustment module and a second gain calculation module; the carrier loop module is composed of a carrier single loop module and a loop parameter adaptive decision module; the sampler is composed of a sampling pulse generator, a B code decoding module and a smoothing and sampling module. The frequency capture module is bypassed after the first AGC circuit to complete coarse carrier synchronization and output the carrier reference frequency to the carrier loop module to complete subsequent fine carrier synchronization.

[0009] According to a preferred embodiment, the signal output by the frequency conversion DDC module is filtered to remove noise and image frequencies by the first low-pass filter in the first AGC circuit, the current signal amplitude is calculated in the first gain calculation module, and the adjusted gain coefficient G1 value is obtained by comparing with the preset control amplitude. The signal output by the frequency conversion DDC module is adjusted in the first gain adjustment module according to the real-time adjusted G1 value, thereby obtaining the final output signal of the first AGC circuit.

[0010] According to a preferred embodiment, the passband cutoff frequency of the first low-pass filter is set as According to the following formula:

[0011] Wherein, is the maximum Doppler range of the downlink radio frequency signal, is the envelope bandwidth of the downlink radio frequency signal.

[0012] According to a preferred embodiment, the real-time Doppler signal output by the carrier single loop module is conjugate multiplied with the signal output by the first automatic gain control AGC circuit after equal delay correction alignment in the second gain calculation module, and low-pass filtering is realized by ID integral zeroing to obtain a real-time amplitude value. The real-time amplitude value is compared with a preset control amplitude value to obtain an adjusted gain coefficient G2 value. The signal output by the first automatic gain control AGC circuit is adjusted in signal level according to the real-time adjusted G2 value in the second gain adjustment module and then output.

[0013] According to a preferred embodiment, the carrier single loop module is realized in a second-order phase-locked loop mode. The loop parameter adaptive decision module is configured to automatically determine the current working condition to make parameter decisions, so as to adaptively optimize the current loop parameter of the carrier single loop. The adaptive parameter decision strategy is as follows: When the carrier single loop has not been locked or is out of lock, the loop bandwidth is set to an initial value which is relatively wide to realize fast locking. After the loop converges and is locked, the loop bandwidth is doubled step by step until the loop bandwidth is narrowed to the minimum loop bandwidth. .

[0014] According to a preferred embodiment, the minimum loop bandwidth is related to the maximum Doppler rate that the system needs to support, and is set according to the following formula:

[0015] wherein, is a preset protection bandwidth value, that is, the minimum loop bandwidth can meet the loop convergence requirement for supporting the maximum Doppler rate .

[0016] According to a preferred embodiment, the sampling pulse generator in the sampler generates sampling pulses at a preset speed sampling rate , taking the externally input 1pps second pulse as a reference, and the sampling rate is generated by frequency division of the FPGA working clock . The sampling pulse sequence generated by the sampling pulse generator drives the smoothing and sampling module to perform ID integral zeroing processing on the real-time Doppler value output by the carrier loop to realize smoothing of the Doppler value and down-sampling of the sampling rate to . ​​The downsampled Doppler value sequence is time-stamped, with the portion of the time stamp above the second representing the time code decoded by the B-code module, denoted as [missing information]. ; The calibration of the portion of the sampling timescale below the second is as follows: assuming the sampling pulse that is approximately aligned with the 1pps second pulse is the first, then there are a total of [number missing] sampling pulses within the second. The sampled values ​​are grouped together, and the time (seconds or less) of the sampling time corresponding to the nth sampling pulse is marked as... The same logic applies to the following formula:

[0017] Doppler sampling values Corresponding real time for:

[0018] The velocity calculation module calculates the Doppler sample values. Calculate using the following formula to obtain... Radial velocity measurement at time 10:00 :

[0019] in, is the downlink radio frequency value, and c is the speed of light.

[0020] The aforementioned main solution and its various further alternative solutions can be freely combined to form multiple solutions, all of which are solutions that can be adopted and are claimed in this application. Those skilled in the art, after understanding the solution of this application, will realize that there are many combinations based on the prior art and common general knowledge, all of which are technical solutions to be protected in this application, and will not be exhaustively listed here.

[0021] The beneficial effects of this application are: The coherent velocity processing device used in this invention can perform coherent velocity measurement very well. It takes into account the thorough purification of the signal and the precise calibration of the sampling time. Actual measurements show that it can support velocity measurement accuracy at the millimeter level or even the sub-millimeter level. This allows the final system velocity measurement performance to approach the theoretical threshold of velocity measurement under the influence of thermal noise alone. Compared with the current advanced level of coherent measurement at the centimeter level in China, the accuracy is improved by almost an order of magnitude.

[0022] Compared to conventional coherent velocity measurement methods, this invention addresses the signal image spectrum and incomplete noise suppression caused by the out-of-band slow decay characteristics of traditional AGC circuits based on ID integration and zeroing, as well as the signal-to-noise ratio degradation caused by folding into the effective bandwidth after downsampling. This improves the stability of signal amplitude fluctuation control and facilitates the improvement of measurement accuracy.

[0023] The application designs a second-order phase-locked loop with variable loop bandwidth, and through adaptive parameter decision, fast locking is realized with a conventional wide loop bandwidth, and high-precision convergence is completed with an extremely narrow loop bandwidth, so that the best stable tracking of the signal carrier is obtained.

[0024] Based on the traditional sampling time mark method of B code decoding, the mark precision of time code is 0.1us, the sampler designed in the application introduces 1pps second pulse as accurate second timing reference, and the time mark method based on analogy and combined with processing delay correction can improve the mark precision to better than 10ns.

[0025] The self-noise of a conventional phase tracking velocity processing machine is difficult to be deeply suppressed to improve the measurement performance at a high signal-to-noise ratio, and the phase tracking velocity processing device designed in the application is designed and optimized from multiple aspects such as sampling quantization, weak interference and weak noise elimination, and can not only realize millimeter-level velocity measurement precision close to the theoretical threshold of thermal noise in a low signal-to-noise ratio range, but also continuously approach the velocity measurement precision theoretical threshold corresponding to the signal-to-noise ratio in a high signal-to-noise ratio range, and the actual measurement can reach a measurement precision resolution of 0.01mm, thereby supporting the system to realize sub-millimeter-level velocity measurement precision. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a principle block diagram of the phase tracking velocity processing device of the application. DETAILED DESCRIPTION

[0027] The embodiments of the application are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the application from the disclosure of the specification. The application can also be implemented or applied through other different specific embodiments, and the details in the specification can be modified or changed based on different views and applications without departing from the spirit of the application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0028] In the description of the application, it should be noted that unless otherwise explicitly specified and limited, the terms "arrangement", "installation", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected, it can be mechanically connected, or it can be electrically connected, it can be directly connected, or indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meanings of the above terms in the application can be understood according to the specific circumstances.

[0029] In addition, it is pointed out that, in the present application, if the specific structure, connection relationship, position relationship, power source relationship, etc. are not specifically written, the structure, connection relationship, position relationship, power source relationship, etc. involved in the present application can be known by those skilled in the art on the basis of the prior art without creative labor.

[0030] Reference Figure 1 As shown in the figure, a phase tracking velocity processing device is shown, which comprises a working clock generator, a frequency conversion filter, an analog-to-digital converter AD, and an FPGA chip.

[0031] The working clock generator is used to provide the frequency conversion filter local oscillator frequency, the analog-to-digital converter AD sampling clock, and the FPGA chip working clock. The frequency conversion filter is used to convert the received downlink radio frequency signal to an intermediate frequency, and complete the band-pass filtering of the signal to obtain the intermediate frequency signal. The analog-to-digital converter AD is used to AD sample the signal sent by the frequency conversion filter to obtain a digital signal. The FPGA chip receives the digital signal sent by the analog-to-digital converter AD, and completes phase-locked tracking, extracts real-time Doppler values and smoothes and samples, and completes conversion calculation in the speed calculation module, thereby completing the calculation of the target radial velocity.

[0032] Preferably, the working clock generator comprises a 10MHz source and a frequency synthesizer, the 10MHz source is constructed based on a frequency source with accuracy and stability better than 10e-11 (such as a rubidium clock or the like), and the output 10MHz frequency is used as a frequency reference in the frequency synthesizer.

[0033] Further, the working clock generator generates the frequency conversion filter local oscillator frequency, the analog-to-digital converter AD sampling clock, and the FPGA chip working clock based on frequency multiplication or a direct digital frequency synthesizer DDS with bit width not less than 48 bits.

[0034] Preferably, the FPGA chip comprises a down-conversion DDC module, a first automatic gain control AGC circuit, a second automatic gain control AGC circuit, a carrier loop module, a sampler, and a speed calculation module.

[0035] The first automatic gain control AGC circuit is composed of a first low-pass filter, a first gain calculation module, and a first gain adjustment module; the second automatic gain control AGC circuit is composed of a second gain adjustment module and a second gain calculation module; the carrier loop module is composed of a carrier single loop module and a loop parameter adaptive decision module; and the sampler is composed of a sampling pulse generator, a B code decoding module, and a smoothing and sampling module.

[0036] And, the frequency capture module is bypassed after the first automatic gain control AGC circuit to complete the coarse carrier synchronization, and outputs the carrier reference frequency to the carrier loop module to complete the subsequent carrier fine synchronization.

[0037] Preferably, the signal output by the frequency conversion DDC module is filtered by a first low-pass filter in the first automatic gain control AGC circuit to remove noise and image frequencies, and then the current signal amplitude is calculated in the first gain calculation module, and the adjusted gain coefficient G1 value is obtained by comparing with the preset control amplitude. The signal output by the frequency conversion DDC module is adjusted in the first gain adjustment module according to the real-time adjusted G1 value, so as to obtain the final output signal of the first automatic gain control AGC circuit.

[0038] Further, the passband cutoff frequency of the first low-pass filter is It is set according to the following formula:

[0039] Wherein, is the maximum Doppler range of the downlink radio frequency signal, is the envelope bandwidth of the downlink radio frequency signal.

[0040] Preferably, the real-time Doppler signal output by the carrier single loop module is conjugate multiplied with the signal output by the first automatic gain control AGC circuit after equal delay correction alignment in the second gain calculation module, and low-pass filtering is realized by ID integral zeroing to obtain a real-time amplitude value. The real-time amplitude value is compared with the preset control amplitude value to obtain the adjusted gain coefficient G2 value.

[0041] Further, the signal output by the first automatic gain control AGC circuit is output after adjusting the signal level according to the real-time adjusted G2 value in the second gain adjustment module.

[0042] Preferably, the carrier single loop module is realized by a second-order phase-locked loop, and the loop parameter adaptive decision module is configured to automatically determine the current working condition to make parameter decisions, so as to adaptively optimize the current loop parameters of the carrier single loop. The adaptive parameter decision strategy is: When the carrier single loop has not been locked or is out of lock, the loop bandwidth is set to a wide initial value to realize fast locking, and after the loop converges and locks, the loop bandwidth is stepped down by a factor of two until the loop bandwidth is reduced to the minimum loop bandwidth according to the preset stabilization time The application realizes fast locking with a conventional wide loop bandwidth and high-precision convergence with an extremely narrow loop bandwidth by designing parameter adaptive decision, so as to obtain the best stable tracking of the signal carrier.

[0043] Further, the minimum loop bandwidth correlates with the maximum Doppler rate that the system needs to support , which is set according to the following formula:

[0044] wherein, is a preset guard bandwidth value, i.e., the minimum loop bandwidth can meet the support for loop convergence to the maximum Doppler rate .

[0045] Preferably, the sampling pulse generator in the sampler is set to a preset speed sampling rate , taking the externally input 1pps second pulse as a reference, and the FPGA working clock generates sampling pulses with a sampling rate of by frequency division.

[0046] The sampling pulse sequence generated by the sampling pulse generator drives the smoothing and sampling module to perform ID integral zero processing on the real-time Doppler value output by the carrier loop, so as to realize smoothing of the Doppler value and down-sampling rate to . The sampling time mark is marked on the down-sampled Doppler value sequence, wherein the second part above of the sampling time mark is the time code translated by the B code module, and is marked as . The second part below of the sampling time mark is marked as follows: assuming that the sampling pulse substantially aligned with the 1pps second pulse is the first one, there are totally groups of sampling values in a second, and the second part below of the sampling time mark of the sampling time of the sampling value corresponding to the nth sampling pulse is marked as , and the following formula is used for analogy:

[0047] and based on the traditional sampling time mark method based on B code decoding, the marking precision of the time code is 0.1us, the sampler designed in the present application introduces the 1pps second pulse as an accurate second timing reference, the second time is marked based on analogy, and in combination with the time mark method for processing delay correction, the marking precision can be improved to better than 10ns.

[0048] Doppler sampling value corresponding real time is:

[0049] The speed calculation module calculates the Doppler sampling value according to the following formula, and obtains Instantaneous radial velocity measurement :

[0050] wherein, is a downlink radio frequency value and c is the speed of light.

[0051] The above description is merely that of the preferred embodiments of the application and is not to be taken in a limiting sense but is made merely for the purpose of providing some preferred embodiments of the application and the full scope of the application should be determined by the appended claims.

Claims

1. A phase-locked speed measurement processing device, characterized by comprising: The phase tracking speed processing device comprises: a working clock generator for providing a variable frequency filter local frequency, an analog-to-digital converter (ADC) sampling clock and a FPGA chip working clock; a variable frequency filter for converting a received downlink radio frequency signal to an intermediate frequency and completing band pass filtering of the signal to obtain an intermediate frequency signal; an ADC for AD sampling the signal sent by the variable frequency filter to obtain a digital signal; a FPGA chip for receiving the digital signal sent by the ADC, completing phase-locked tracking, extracting a real-time Doppler value and smoothing and sampling, completing conversion calculation in a speed calculation module and thus completing calculation of a target radial speed.

2. The phase-locked speed measurement processing apparatus according to claim 1, wherein The working clock generator generates the variable frequency filter local frequency, the ADC sampling clock and the FPGA chip working clock by using a frequency multiplication method or a direct digital frequency synthesizer (DDS) with a bit width not less than 48 bits.

3. The phase-locked speed measurement processing apparatus of claim 2, wherein The working clock generator comprises a 10MHz source and a frequency synthesizer, the 10MHz source is constructed based on a frequency source with an accuracy and stability better than 10e-11, and the output 10MHz frequency is used as a frequency reference in the frequency synthesizer.

4. The phase-locked speed measurement processing apparatus of claim 1, wherein The FPGA chip comprises a down-conversion DDC module, a first automatic gain control (AGC) circuit, a second AGC circuit, a carrier loop module, a sampler and a speed calculation module, the first AGC circuit is composed of a first low pass filter, a first gain calculation module and a first gain adjustment module; the second AGC circuit is composed of a second gain adjustment module and a second gain calculation module; the carrier loop module is composed of a carrier single loop module and a loop parameter adaptive decision module; the sampler is composed of a sampling pulse generator, a B code decoding module and a smoothing and sampling module; a frequency capture module is connected in bypass to the first AGC circuit to complete coarse carrier synchronization and output a carrier reference frequency to the carrier loop module to complete subsequent fine carrier synchronization.

5. The phase-locked speed measurement processing apparatus of claim 1, wherein The signal output by the variable frequency DDC module is filtered to remove noise and image frequencies by the first low pass filter in the first AGC circuit, the current signal amplitude is calculated in the first gain calculation module, and the adjusted gain coefficient G1 value is obtained by comparison with a preset control amplitude; the signal output by the variable frequency DDC module is adjusted in the first gain adjustment module according to the real-time adjusted G1 value, and thus the final output signal of the first AGC circuit is obtained.

6. The phase-locked speed measurement processing apparatus of claim 5, wherein The passband cutoff frequency of the first lowpass filter is set according to the following equation: wherein, is the maximum Doppler range for the downlink radio frequency signal, is the downlink radio frequency signal envelope bandwidth.

7. The phase-locked speed measurement processing apparatus of claim 5, wherein The real-time Doppler signal output by the carrier single loop module is conjugate multiplied with the signal output by the first AGC circuit after equal delay correction alignment in the second gain calculation module, low pass filtering is realized by ID integral zeroing and a real-time amplitude value is obtained, the real-time amplitude value is compared with a preset control amplitude value to obtain an adjusted gain coefficient G2 value; the signal output by the first AGC circuit is output after adjustment of the signal level according to the real-time adjusted G2 value in the second gain adjustment module.

8. The phase-locked speed measurement processing apparatus of claim 7, wherein The carrier single loop module is realized by using a second-order phase-locked loop method, The loop parameter adaptive decision module is configured to automatically determine the current working condition to make parameter decision, so as to adaptively optimize the current loop parameter of the load single loop, and the adaptive parameter decision strategy is: When the single ring is not locked or is unlocked, the loop bandwidth is set to an initial value of a wide bandwidth To achieve fast locking, after the loop converges and is locked, the preset stable time is followed To step, the loop bandwidth is doubled and narrowed successively until the loop bandwidth is lowered to the minimum loop bandwidth .

9. The phase-locked speed measurement processing apparatus of claim 8, wherein Minimum loop bandwidth in relation to the maximum Doppler variation rate that the system needs to support is set according to the following equation: wherein, is a preset guard bandwidth value, i.e., a minimum loop bandwidth can satisfy the support for loop convergence of a maximum Doppler variation rate .

10. The phase-locked speed measurement processing apparatus of claim 8, wherein The sampling pulse generator in the sampler generates sampling pulses at a preset speed sampling rate , taking the externally input 1pps second pulse as a reference, and the FPGA working clock generates sampling pulses with a sampling rate of by frequency division The sampling pulse sequence generated by the sampling pulse generator drives the smoothing and sampling module to perform ID integral zero processing on the real-time Doppler value output by the carrier ring, so as to realize smoothing of the Doppler value and reduction of the sampling rate to ; The down-sampled Doppler value sequence is marked with a sampling time stamp, wherein the part of the sampling time stamp above the second is marked as the time code translated by the B code module ; The calibration of the part of the sampling time scale below the second is as follows: assuming that the sampling pulse substantially aligned with the 1 pps second pulse is the first one, then there are totally group sampling values, the sampling time of the sampling value corresponding to the nth sampling pulse is marked as , and the analogy is made according to the following formula: Doppler sample value corresponding real time is: a speed calculation module to calculate radial velocity measurements from Doppler sample values The radial velocity measurements are calculated according to the following equation at a time instant : wherein is the downlink radio frequency value and c is the speed of light.

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