Method and device for detecting communication interface chip

Abstract

The invention relates to the technical field of chip detection, in particular to a detection method and device for a communication interface chip. The method comprises the following steps: firstly sending a first detection data frame to a chip to be detected, then obtaining a second detection data frame fed back by the chip to be detected, then sequentially analyzing a data frame header, data content and a first check code in the second detection data frame, and finally executing a corresponding detection instruction according to an analysis result. Compared with the prior art, the method provided by the invention can be used for accurately and quickly detecting the communication interface chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip detection, and in particular to a detection method and device for a communication interface chip. BACKGROUND

[0002] The communication interface chip is widely used in various systems related to instrument communication, data acquisition and testing, and its function stability and performance reliability directly affect the operation quality of the entire system. Therefore, the detection of such chips is particularly important.

[0003] For the detection of the communication interface chip, the patent application with publication number CN116795703A discloses a test system for a high-speed communication interface chip. The test system includes a handler, a chip separator connected to a loading board, the loading board is connected to an interface board through a cable, the interface board is connected to a tester, the tester is connected to a workstation through a category 6 network cable, and the workstation is connected to the handler through a GPIB (General Purpose Interface Bus) communication interface. The test system realizes automatic testing of the communication interface chip through the close cooperation of each part, and improves the testing efficiency.

[0004] However, in actual applications, the detection of the communication interface chip, especially the detection of the TNT4882 chip, still relies on manual detection. During detection, oscilloscopes, logic analyzers and other devices are often used to measure the timing, voltage tolerance and other parameters of the chip to determine whether the chip is qualified. However, these parameters can only simply verify the basic communication function of the chip, and the detection accuracy is low. In addition, the chip needs to be repeatedly disassembled and assembled at different detection links, which not only increases the complexity and time cost of the operation, but also may cause damage to the chip.

[0005] Therefore, how to improve the detection accuracy and efficiency of the communication interface chip is a technical problem that needs to be solved at present. SUMMARY

[0006] To solve the technical problems that the basic communication function can only be verified and the detection efficiency is low when detecting the communication interface chip, the present application provides solutions in the following aspects.

[0007] In a first aspect, the present application provides a detection method for a communication interface chip, comprising: sending a first detection data frame to a to-be-detected chip; the first detection data frame comprises a temperature setting instruction and a temperature reading instruction; obtaining a second detection data frame fed back by the to-be-detected chip; analyzing a data frame header, data content and a first check code in the second detection data frame; executing a corresponding detection instruction according to the analysis result; the detection instruction comprises a temperature setting instruction, a temperature reading instruction and an error type feedback instruction.

[0008] Further, the analysis result includes analysis success and analysis failure; and the corresponding detection instruction is executed according to the analysis result, including: if the analysis result is analysis success, setting temperature and reading temperature; and if the analysis result is analysis failure, outputting a corresponding error type.

[0009] Further, the data frame header, the data content and the first check code in the second detection data frame are analyzed, including: checking whether the data frame header conforms to the standard of the communication protocol corresponding to the chip under test; if not, determining that the analysis fails, and determining that the error type of the second detection data frame is a frame header error; if yes, judging whether the instruction code obtained by analyzing the data content conforms to the standard of the communication protocol corresponding to the chip under test; if not, determining that the analysis fails, and determining that the error type of the second detection data frame is an instruction code error; if yes, calculating a second check code according to the data content, judging whether the second check code is consistent with the first check code, if not, determining that the analysis fails, and determining that the error type of the second detection data frame is a check error; and if yes, determining that the analysis succeeds.

[0010] Further, the chip under test is a TNT4882 chip.

[0011] In a second aspect, the application provides a detection device of a communication interface chip, which is used for executing the detection method of the communication interface chip in the first aspect, and includes: a chip test seat module, which is used for accessing a chip under test; a parameter configuration module, which is connected to the chip under test, and is used for receiving test parameters, generating a first detection data frame according to the test parameters, and sending the first detection data frame to the chip under test; a processor module, which is connected to the chip under test through the chip test seat module, and is used for receiving and analyzing a second detection data frame sent by the chip under test; and a controller module, which is connected to the processor module, and is used for executing a corresponding detection instruction according to an analysis result of the processor module.

[0012] Further, the processor module includes a central processing unit, a register, a first inverter and a second inverter; wherein a data bus of the central processing unit is connected to a corresponding data input pin of the register, an address latch enable pin of the central processing unit is connected to a latch enable pin of the register, a first address pin of the central processing unit is connected to an input end of the first inverter, and a reset pin of the central processing unit is connected to the second inverter.

[0013] Further, the chip test seat module comprises a chip test seat, a write enable pin of the chip test seat is connected to a write enable pin of the central processor, a read enable pin of the chip test seat is connected to a read enable pin of the central processor, a chip select pin of the chip test seat is connected to an output end of the first inverter, an interrupt request pin of the chip test seat is connected to an interrupt request pin of the central processor, a data bus of the chip test seat is connected to a corresponding data bus of the central processor, and an address bus of the chip test seat is connected to corresponding data output pins of the register respectively.

[0014] Further, the device further comprises a storage module connected to the processor module, for providing the processor module with a pre-stored test algorithm.

[0015] Further, the device further comprises a serial communication module, and the processor module is connected to the controller module through the serial communication module.

[0016] Further, the device further comprises a reset module and a power module; wherein the reset module is connected to the processor module, for providing a signal for triggering the reset of the processor module; and the power module is connected to the processor module, the chip test seat module, the controller module and the reset module respectively, for providing power supply for the processor module, the chip test seat module, the controller module and the reset module.

[0017] The present application has the advantages that: the manual detection in the prior art can only measure the instantaneous parameters in a static environment, and it is difficult to truly reflect the performance of the chip in the communication process, while the method of the present application can determine the processing capacity and error types of the chip to be detected by sending a detection data frame to the chip to be detected and then analyzing the detection data frame forwarded by the chip to be detected, thereby improving the detection accuracy; and the chip to be detected does not need to be repeatedly disassembled and assembled during the detection process, so that the chip can be quickly and batch detected with less human intervention, and therefore, the communication interface chip can be comprehensively, accurately and quickly detected by the method of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a flow chart schematically showing a detection method of a communication interface chip according to an embodiment of the present application; Figure 2 is a structural block diagram schematically showing a detection device of a communication interface chip according to an embodiment of the present application; Figure 3 is a topology diagram of a processor module in a detection device of a communication interface chip according to an embodiment of the present application; Figure 4A topology diagram of a chip test seat module in a communication interface chip detection device according to an embodiment of the present application; Figure 5 A topology diagram of a storage module in a communication interface chip detection device according to an embodiment of the present application; Figure 6 A topology diagram of a serial port communication module in a communication interface chip detection device according to an embodiment of the present application; Figure 7 A topology diagram of a power supply module in a communication interface chip detection device according to an embodiment of the present application; Figure 8 A topology diagram of a crystal oscillator module in a communication interface chip detection device according to an embodiment of the present application Figure 9 A topology diagram of a reset module in a communication interface chip detection device according to an embodiment of the present application; Figure 10 A topology diagram of an address configuration module in a communication interface chip detection device according to an embodiment of the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0020] The specific embodiments of the present application will be described in detail below with reference to the drawings.

[0021] Figure 1 A flow chart of a communication interface chip detection method according to an embodiment of the present application is schematically shown.

[0022] In a first aspect, the present application provides a communication interface chip detection method, as shown in Figure 1 The method of the present application comprises the following steps.

[0023] S101, sending a first detection data frame to a chip to be tested.

[0024] In the present embodiment, the first detection data frame comprises a temperature setting instruction, a temperature reading instruction and a running state reading instruction.

[0025] Specifically, the parameter configuration module in the detection device generates a first detection data frame according to the received test parameters, and periodically sends the first detection data frame to the chip to be tested through the GPIB interface. For example, the test software installed in the parameter configuration module sends the first detection data frame to the chip to be tested every 1 second. The test software is provided with an operation interface, through which the test personnel can configure the test parameters, start and stop the detection process, and display and store the detection results, thereby realizing the full-automatic detection of the communication interface chip.

[0026] The test parameters can include communication time and data volume. The communication time refers to the time spent for one communication, which is set according to the test requirements, for example, 500 ms or 200 ms. When the communication time is set to be relatively short, if the performance of the chip to be tested is poor, it can not respond quickly within the specified time, thereby causing transmission errors. Therefore, by setting different communication times according to different requirements, it can be determined whether the performance of the chip to be tested meets the requirements.

[0027] In addition, the performance of the chip to be tested can also be detected by setting different data volumes. For example, when a large amount of data is sent, if the performance of the chip to be tested is poor, it can only transmit a part of the data, and therefore the performance of the chip to be tested can be judged according to the difference between the sent data volume and the received data volume.

[0028] S102, acquiring the second detection data frame fed back by the chip to be tested.

[0029] Specifically, the chip test seat module in the detection device converts the first detection data frame into a test excitation of the chip to be tested, and at the same time collects the signal output by the chip to be tested, which is the second detection data frame, and transmits the second detection data frame to the processor module in the detection device through the communication protocol corresponding to the chip to be tested.

[0030] Further, the processor module stores the received second detection data frame in the data buffer area in binary form, and at the same time marks the flag bit indicating that the receiving is completed. It can be understood that, under normal circumstances, the chip to be tested should forward the detection data frame to the processor module completely and accurately, and if the chip to be tested is abnormal or has poor performance, it can not correctly and completely forward the detection data frame to the processor module, for example, the second detection data frame fed back by the chip to be tested has an error compared with the first detection data frame.

[0031] S103, analyzing the data frame header, data content and first check code in the second detection data frame to obtain an analysis result.

[0032] In this embodiment, the analysis result includes analysis failure and analysis success.

[0033] Specifically, the processor module takes out the second detection data frame from the data buffer area, and sequentially parses the data frame header, the data content and the first check code in the second detection data frame according to the preset test algorithm, if all the checks pass, it is determined that the parsing is successful; if one of the check links does not pass, it stops parsing the second detection data frame, and determines that the parsing fails.

[0034] More specifically, the data frame header is checked first to determine whether the data frame header conforms to the standard of the communication protocol corresponding to the chip under test, that is, whether it is consistent with the byte sequence specified by the communication protocol corresponding to the chip under test, if yes, it is consistent; if no, it is not consistent. If it is not consistent, it is determined that the parsing fails, and the error type of the second detection data frame is determined as a frame header error, and then the next second detection data frame is parsed; if it is consistent, the instruction code of the data content is parsed to determine whether the instruction code conforms to the standard of the communication protocol corresponding to the chip under test, if no, it is determined that the parsing fails, and the error type of the second detection data frame is determined as an instruction code error, and then the next second detection data frame is parsed; if yes, the second check code is calculated according to the data content, and it is determined whether the second check code is consistent with the received first check code, if no, it is determined that the parsing fails, and the error type of the second detection data frame is determined as a check error, and then the next second detection data frame is parsed; if yes, it is determined that the parsing is successful.

[0035] Among them, whether the first check code and the second check code are consistent can be determined by the CRC (Cyclic Redundancy Check) algorithm. Since the CRC algorithm is prior art, it will not be described here.

[0036] S104, execute the corresponding detection instruction according to the parsing result.

[0037] In this embodiment, the detection instruction includes a temperature setting instruction, a temperature reading instruction, a running state reading instruction and an error type feedback instruction.

[0038] Specifically, if the parsing result is parsing failure, it is recorded as an error once, and the error type corresponding to this parsing failure is fed back to the parameter configuration module, and then the parameter configuration module periodically counts the number of errors. Through the number of errors, the performance of the chip under test can be determined, that is: if the number of errors is large, it indicates that the performance of the chip under test is poor; if the number of errors is small, it indicates that the performance of the chip under test is good. In addition, the proportion of the number of errors of each error type in the total number of errors can also be counted, so that the main reason for the abnormal chip can be determined.

[0039] When the error times exceed the set times, it is determined that the to-be-tested chip has an abnormality and does not meet the requirements; when the error times do not exceed the set times, it is determined that the address bus, the data bus, the read enable pin, the write enable pin, the clock signal and other pin functions of the to-be-tested chip are normal.

[0040] Compared with the prior art which can only simply verify the basic communication function, the present application can determine which errors occur in the process from receiving data to sending data of the to-be-tested chip when the analysis result of the second detection data frame is an analysis failure, thereby improving the detection accuracy. In addition, the performance of the to-be-tested chip under different data amounts and different communication times can be determined.

[0041] If the analysis result is an analysis success, the data content in the second detection data frame is processed, the extracted temperature data is written into the temperature register in the central processing unit in the processor module, the flag bit is updated, and the processing result is converted into a data frame recognizable by the controller in the controller module according to the standard of the communication protocol corresponding to the to-be-tested chip, and the data frame is sent to the controller module through the serial communication module in the detection device, and the flag bit is updated. The data content in the data frame includes a temperature setting instruction, a temperature reading instruction and a running state reading instruction.

[0042] Further, after the controller module receives the data frame of the processor module, the data frame is analyzed, the analysis process is consistent with the analysis process of the second detection data frame of the processor module, and thus details are not repeated here, but only the error times corresponding to the second detection data frame are counted to avoid the interference of the controller module on the detection.

[0043] After the controller module analyzes successfully, the temperature setting instruction, the temperature reading instruction and the running state reading instruction are executed, and the execution result is converted into a data frame and fed back to the processor module through the serial communication module. After the processor module receives the data frame fed back by the controller module, the data frame is analyzed, the analysis process is consistent with the analysis process of the second detection data frame of the processor module, and thus details are not repeated here.

[0044] After the analysis is successful, the processor module returns the analyzed data to the parameter configuration module through the to-be-tested chip, and then the test software in the parameter configuration module prints the test result and records the test times.

[0045] It should be noted that, in order to avoid the interference of the detection device on the test / detection, before the detection, the modules of the detection device need to be checked, for example, whether the detection controller and its wiring are normal, so as to avoid the problems of the modules themselves affecting the accuracy of the detection. Or after the detection device outputs the abnormal chip to be detected, the detection device is checked again, so as to reduce the number of times of checking the detection device and improve the detection efficiency.

[0046] By periodically sending the detection data frame to the chip to be detected, and then analyzing the detection data frame forwarded by the chip to be detected, the function and performance of the communication interface chip can be determined, and the consistency of the corresponding communication protocol of the chip to be detected can also be detected synchronously. If the central processor can correctly analyze the second detection data frame, it indicates that the chip to be detected strictly follows the standard of the corresponding communication protocol of the chip to be detected in the communication process. In addition, in the detection process, the chip to be detected does not need to be repeatedly inserted, so that the chip damage and time cost caused by repeatedly inserting the chip are avoided. Therefore, the method of the present application can accurately and quickly detect the communication interface chip.

[0047] In the optional embodiment, after the controller module obtains the execution result, the execution result can be directly fed back to the parameter configuration module, without being fed back to the parameter configuration module through the processor module and the chip to be detected.

[0048] In the embodiment, the chip to be detected is a TNT4882 chip, and the corresponding communication protocol of the chip to be detected is an IEEE488 communication protocol. The TNT4882 chip is a special chip for GPIB interface launched by the National Instruments (NI), mainly used for realizing high-speed data communication conforming to the IEEE 488 communication protocol standard, and widely applied in industrial automation, test and measurement equipment and ATE (automatic test equipment) system.

[0049] Figure 2 is a structural block diagram of a detection device of a communication interface chip according to an embodiment of the present application.

[0050] In the second aspect, the present application provides a detection device of a communication interface chip, which is used to realize the detection method of the communication interface chip in the first aspect.

[0051] As Figure 2As shown, the device of the present application comprises a parameter configuration module, a chip test seat module, a processor module, a controller module, a storage module and a serial communication module. Among them, the parameter configuration module is connected to the chip to be tested through the GPIB interface, used to receive the test parameters configured by the tester, and generate the first detection data frame according to the test parameters, and send the first detection data frame to the chip to be tested; the chip test seat module is connected to the processor module, used to access the chip to be tested; the processor module is connected to the chip to be tested through the chip test seat module, used to receive and analyze the second detection data frame sent by the chip to be tested; the storage module is connected to the processor module, used to provide the processor module with test algorithms; the controller module is connected to the processor module through the serial communication module, used to receive the analysis results of the processor module, and execute the corresponding detection instructions according to the analysis results.

[0052] Specifically, as shown in the figure, Figure 3 The processor module comprises a central processing unit CPU, a register IC3, a first inverter U1F and a second inverter U1E. Among them, the data bus D0~D7 of the central processing unit CPU is connected to the corresponding data input pin D0~D7 of the register IC3, the address latch enable pin ALE of the central processing unit CPU is connected to the latch enable pin LE of the register IC3, the first address pin P27 of the central processing unit CPU is connected to the input end of the first inverter U1F, and the reset signal pin RESET of the central processing unit CPU is connected to the second inverter U1E.

[0053] Specifically, when the chip select pin CS is valid and the read enable pin RD is valid, the central processing unit CPU receives the second detection data frame from the chip to be tested through the address bus A0~A4 and the data bus D0~D7; when the chip select pin CS is valid and the write enable pin WR is valid, the central processing unit CPU sends the execution result of the detection instruction to the chip to be tested through the address bus A0~A4 and the data bus D0~D7. In addition, the central processing unit CPU can generate an interrupt signal through the detection data valid signal and the not ready data signal.

[0054] In this embodiment, the chip to be tested is TNT4882 chip, so the chip test seat module set is the physical connection carrier of TNT4882 chip, which can accurately adapt to the pin definition of TNT4882 chip, realizing the electrical connection between the chip to be tested and the detection device. Specifically, as shown in the figure, Figure 4As shown, the chip test seat module includes a chip test seat (i.e. IC seat in the figure), the write enable pin RD of the chip test seat is connected with the write enable pin P37 of the central processor CPU, the read enable pin WD of the chip test seat is connected with the read enable pin P36 of the central processor CPU, the chip select pin CS of the chip test seat is connected with the output end of the first inverter U1F, the interrupt request pin INTR of the chip test seat is connected with the interrupt request pins P14, P15 of the central processor CPU, the data bus D0~D7 of the chip test seat is connected with the data bus D0~D7 of the central processor CPU in correspondence, and the address bus ADDR0~ADDR4 of the chip test seat is connected with the data output pins Q7~Q3 (i.e. address bus A0~A4) of the register IC3 in correspondence.

[0055] The storage module is used for storing system firmware, initialization program and test algorithm. After power-on, the processor module loads the start code from the storage module to complete system initialization; in the test process, the processor module calls the pre-stored test algorithm from the storage module, and the test algorithm provides logical support for chip testing, such as providing operation rules for the first check code check. By calling the pre-stored test algorithm for testing, the standardization and automation of the test process are guaranteed, and the interference of human factors on the test accuracy is avoided.

[0056] Specifically, as shown in Figure 5 The storage module includes a memory IC4, the data bus D0~D7 of the memory IC4 is connected with the data bus D0~D7 of the central processor CPU in correspondence, the address bus A0~A7 of the memory IC4 is connected with the data input pins Q0~Q7 of the register IC3 in correspondence, the address bus A8~A15 of the memory IC4 is connected with the address bus P20~P27 of the central processor CPU in correspondence, the output enable pin OE of the memory IC4 is connected with the program storage enable pin P21 of the central processor CPU. The output enable pin OE of the memory IC4 is connected with the program storage enable pin P21 of the central processor CPU.

[0057] The serial communication module is used for building a communication bridge between the processor module and the controller module, and adopts a standard serial communication protocol. The processor module sends detection instructions and test parameter configuration information to the controller module through the serial communication module, the controller module returns the execution results through the serial communication module, so as to realize remote control and data acquisition. In an embodiment, as shown in Figure 6 The serial communication module includes an RS-485 transceiver IC5, the sending pin TX of the RS-485 transceiver IC5 is connected with the data receiving pin P13 of the central processor CPU, and the receiving pin RX of the RS-485 transceiver IC5 is connected with the data sending pin P12 of the central processor CPU; the connection relationship between other pins of the RS-485 transceiver IC5 and other components is shown in​Figure 6 The description is not repeated here.

[0058] It should be noted that the controller module can be composed of an existing and conventional controller, as long as the data receiving, sending and detection instruction execution can be realized, which can be used as the controller module of the device.

[0059] In an embodiment, the detection device further comprises a power module connected with the controller module, the processor module, the serial communication module, the test chip seat module, the storage module, etc., for providing stable and adaptive voltage for each module, and having overcurrent and overvoltage protection functions to ensure system hardware safety and provide reliable support for chip detection. Figure 7 The description is not repeated here.

[0060] In an embodiment, the detection device further comprises a crystal oscillator module connected to the processor module for providing a stable clock signal. Figure 8 The description is not repeated here.

[0061] In an embodiment, the detection device further comprises a reset module connected to the processor module for providing a reset function for the central processing unit CPU and associated circuits, and being capable of manual reset and automatic reset. Figure 9 The description is not repeated here.

[0062] In an embodiment, the detection device further comprises an address configuration module connected to the processor module for allocating a communication address for the central processing unit CPU. Figure 10 The description is not repeated here.

[0063] Through the detection device of the application, the tester only needs to set the test parameters to automatically detect the performance and function of the chip to be tested, which avoids the problems of low detection accuracy and low efficiency caused by human factors compared with the detection method using an oscilloscope and a logic analyzer, thereby improving the efficiency and accuracy of the communication interface chip detection.

[0064] In the description of the present specification, the meaning of "a plurality of" is at least two, such as two, three or more, and the like, unless otherwise explicitly specified. In addition, the division of steps of the above method is only for the purpose of clear description, and when implemented, it can be combined into one step or some steps can be split and decomposed into multiple steps, as long as the same logical relationship is included.

[0065] While the present specification has shown and described several embodiments of the present application, it is to be understood that the same are presented by way of example only and not limitation. As such, numerous changes, modifications and substitutions can be made by one having ordinary skill in the art without departing from the spirit and scope of the present application. It should be understood that in the process of practicing the present application, various alternatives to the embodiments of the present application described herein can be employed.

Claims

1. A method for detecting a communication interface chip, characterized in that, include: Send a first detection data frame to the chip under test; the first detection data frame includes a temperature setting command and a temperature reading command; Acquire the second detection data frame fed back by the chip under test; The data frame header, data content, and first checksum in the second detection data frame are parsed. The corresponding detection instructions are executed based on the analysis results; the detection instructions include temperature setting instructions, temperature reading instructions, and error type feedback instructions.

2. The method for detecting a communication interface chip according to claim 1, characterized in that, The parsing result includes successful parsing and parsing failure; Execute the corresponding detection instructions based on the analysis results, including: if the analysis result is successful, set the temperature and read the temperature; If the parsing result is a parsing failure, the corresponding error type will be output.

3. The method for detecting a communication interface chip according to claim 2, characterized in that, The data frame header, data content, and first checksum in the second detection data frame are parsed, including: Verify whether the data frame header conforms to the standard of the communication protocol corresponding to the chip under test; If not, the parsing is deemed to have failed, and the error type of the second detected data frame is determined to be a frame header error; If so, parse the instruction code of the data content and determine whether the instruction code conforms to the standard of the communication protocol corresponding to the chip under test; If not, the parsing is deemed to have failed, and the error type of the second detection data frame is determined to be an instruction code error; If yes, calculate the second checksum based on the data content, and determine whether the second checksum is consistent with the first checksum. If not, determine that the parsing has failed, and determine that the error type of the second detection data frame is a checksum error; if yes, determine that the parsing has succeeded.

4. The method for detecting a communication interface chip according to claim 3, characterized in that, The chip under test is a TNT4882 chip.

5. A testing device for a communication interface chip, used to execute the testing method for a communication interface chip according to any one of claims 1-4, characterized in that, include: Chip test socket module, used to connect the chip under test; A parameter configuration module, connected to the chip under test, is used to receive test parameters, generate a first detection data frame according to the test parameters, and send the first detection data frame to the chip under test. The processor module is connected to the chip under test via the chip test socket module and is used to receive and parse the second detection data frame sent by the chip under test. The controller module, connected to the processor module, is used to execute corresponding detection instructions based on the parsing results of the processor module.

6. The detection device for the communication interface chip according to claim 5, characterized in that, The processor module includes a central processing unit (CPU), a register, a first inverter, and a second inverter; wherein, the CPU's data bus is connected to the corresponding data input pin of the register, the CPU's address latch enable pin is connected to the register's latch enable pin, the CPU's first address pin is connected to the input of the first inverter, and the CPU's reset pin is connected to the second inverter.

7. The detection device for the communication interface chip according to claim 6, characterized in that, The chip test socket module includes a chip test socket, a write enable pin of the chip test socket connected to the write enable pin of the central processing unit (CPU), a read enable pin of the chip test socket connected to the read enable pin of the CPU, a chip select pin of the chip test socket connected to the output of the first inverter, an interrupt request pin of the chip test socket connected to the interrupt request pin of the CPU, a data bus of the chip test socket connected to the corresponding data bus of the CPU, and an address bus of the chip test socket connected to the corresponding data output pin of the register.

8. The detection device for the communication interface chip according to claim 5, characterized in that, It also includes a storage module connected to the processor module, which is used to provide the processor module with pre-stored test algorithms.

9. The detection device for the communication interface chip according to claim 5, characterized in that, It also includes a serial communication module, through which the processor module is connected to the controller module.

10. The detection device for the communication interface chip according to claim 5, characterized in that, It also includes a reset module and a power module; wherein, the reset module is connected to the processor module and is used to provide a signal to trigger the processor module to reset; the power module is connected to the processor module, the chip test socket module, the controller module and the reset module respectively, and is used to supply power to the processor module, the chip test socket module, the controller module and the reset module.

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