Controller memory buffer management method, system, device, medium and product

Abstract

The invention discloses a controller memory buffer management method, system and device, a medium and a product, and relates to the technical field of data storage, and the method comprises the following steps: obtaining state information of a memory block; determining a first to-be-processed memory block and a second to-be-processed memory block according to the state information; if the size of the fragments is greater than a threshold value, recycling the fragments; and generating a virtual address according to the physical address of the second to-be-processed memory block, and mapping the second to-be-processed memory block into a continuous memory space. The problem that discontinuous memory blocks and memory blocks containing fragments are prone to occurring in a memory buffer area of a controller, and communication delay of SSD access of a host is increased can be solved. According to the method, the fragments of the memory blocks can be rapidly detected and arranged, the fragments are recycled, the space utilization rate of the CMB is improved, the second to-be-processed memory block is mapped into the continuous memory space through the virtual address, it is ensured that the host can logically access the continuous memory space, and the addressing frequency is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data storage, and in particular to a controller memory buffer management method, system, device, medium and product. BACKGROUND

[0002] In a storage system, a CMB (Controller Memory Buffer) is a buffer in an SSD (Solid State Drive) controller. Through the CMB, a host can directly read and write controller memory, avoiding additional transmission of data between a DRAM (Dynamic Random Access Memory) and the SSD controller, thereby improving data access efficiency.

[0003] During long-time operation of an SSD, due to frequent data writing, deletion and updating, memory blocks in a CMB space can be fragmented, and fragmentation can cause a large number of memory blocks to be unable to be effectively utilized, reducing cache hit rate and data transmission efficiency. In addition, there are often many discontinuous memory blocks in the CMB space, causing a non-continuous memory mapping problem in the CMB space, and the host needs to address multiple times when accessing the SSD, increasing communication delay.

[0004] Therefore, the related art has the problem that discontinuous memory blocks and memory blocks containing fragments can easily occur in the controller memory buffer, increasing communication delay of the host accessing the SSD. SUMMARY

[0005] Therefore, the present application provides a controller memory buffer management method, system, device, medium and product to solve the problem that discontinuous memory blocks and memory blocks containing fragments can easily occur in the controller memory buffer, increasing communication delay of the host accessing the SSD.

[0006] In a first aspect, the present application provides a controller memory buffer management method, which comprises: obtaining state information of a first preset number of memory blocks in a controller memory buffer; determining a first to-be-processed memory block and a second to-be-processed memory block according to the state information, wherein the first to-be-processed memory block is a memory block containing fragments, and the second to-be-processed memory block is an idle memory block and is not adjacent to other idle memory blocks; recycling the fragments in the first to-be-processed memory block in a case where the size of the fragments in the first to-be-processed memory block is greater than a first preset threshold; generate a virtual address according to the physical address of the second to-be-processed memory block, wherein the virtual address is used to map the second to-be-processed memory block as a continuous memory space.

[0007] In a second aspect, the present application provides a controller memory buffer management system, which comprises a memory scanning module and a memory conversion module. The memory scanning module is configured to acquire state information of a first preset number of memory blocks in the controller memory buffer. The memory scanning module is configured to determine a first to-be-processed memory block according to the state information, wherein the first to-be-processed memory block is a memory block with fragmentation. The memory conversion module is configured to determine a second to-be-processed memory block according to the state information, wherein the second to-be-processed memory block is an idle memory block and the second to-be-processed memory block is not adjacent to other idle memory blocks. The memory scanning module is configured to recycle the fragmentation in the first to-be-processed memory block in a case where the size of the fragmentation in the first to-be-processed memory block is greater than a first preset threshold. The memory conversion module is configured to generate a virtual address according to the physical address of the second to-be-processed memory block, wherein the virtual address is used to map the second to-be-processed memory block as a continuous memory space.

[0008] In a third aspect, the present application provides a controller memory buffer management device, which comprises: The information acquisition module is configured to acquire state information of a first preset number of memory blocks in the controller memory buffer. The memory block determination module is configured to determine a first to-be-processed memory block and a second to-be-processed memory block according to the state information, wherein the first to-be-processed memory block is a memory block with fragmentation, and the second to-be-processed memory block is an idle memory block and the second to-be-processed memory block is not adjacent to other idle memory blocks. The fragmentation recycling module is configured to recycle the fragmentation in the first to-be-processed memory block in a case where the size of the fragmentation in the first to-be-processed memory block is greater than a first preset threshold. The address generation module is configured to generate a virtual address according to the physical address of the second to-be-processed memory block, wherein the virtual address is used to map the second to-be-processed memory block as a continuous memory space.

[0009] In a fourth aspect, the present application provides a computer device, which comprises a memory and a processor, the memory and the processor are communicatively connected with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the controller memory buffer management method of the first aspect or any of the corresponding embodiments thereof.

[0010] In a fifth aspect, the present application provides a computer readable storage medium, which stores computer instructions for causing a computer to execute the controller memory buffer management method of the first aspect or any of the corresponding embodiments thereof.

[0011] In a sixth aspect, the present application provides a computer program product, which comprises computer instructions for causing a computer to execute the controller memory buffer management method of the first aspect or any of the corresponding embodiments thereof.

[0012] According to the present application, the state information of the memory block is acquired; the first to-be-processed memory block and the second to-be-processed memory block are determined according to the state information; the fragments in the first to-be-processed memory block are recycled if the size of the fragments is greater than a threshold; and the second to-be-processed memory block is mapped into a continuous memory space according to the virtual address generated according to the physical address of the second to-be-processed memory block. The problem that the controller memory buffer is prone to contain discontinuous memory blocks and memory blocks containing fragments and increases the communication delay of the host accessing the SSD can be solved. The method can quickly detect and sort the fragments of the memory block, recycle the fragments, improve the space utilization of the CMB, map the second to-be-processed memory block into a continuous memory space through a dynamic mapping mechanism using a virtual address, ensure that the host can access the continuous memory space logically, reduce the number of addressing, and improve the data transmission speed. The storage efficiency and access performance of the SSD system can be significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the specific embodiments or related art, the following will briefly introduce the drawings needed to be used in the specific embodiments or related art descriptions. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0014] Figure 1 is a flowchart of the controller memory buffer management method according to an embodiment of the present application; Figure 2 is a flowchart of calculating the block internal offset according to an embodiment of the present application; Figure 3 is a structural schematic diagram of the controller memory buffer management system according to an embodiment of the present application; Figure 4 is a structural schematic diagram of the memory conversion module according to an embodiment of the present application; Figure 5 is a structural schematic diagram of the event monitoring and triggering module according to an embodiment of the present application; Figure 6is a structural schematic diagram of a memory scanning module according to an embodiment of the present application; Figure 7 is a structural block diagram of a controller memory buffer management device according to an embodiment of the present application; Figure 8 is a hardware structure schematic diagram of a computer device of an embodiment of the present application. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0016] It should be noted that, in the description of the present application, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0017] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0018] In modern storage systems, the controller memory buffer is located inside the SSD controller and is directly accessible by the host, used to improve the efficiency of data transmission and cache management, allowing the host to directly access the controller memory through the bus, thereby reducing the data transmission delay between the host and the device and improving the throughput and response speed of the system. Through CMB, the host can directly read and write the controller memory, avoiding additional transmission of data between DRAM and the controller, thereby improving data access efficiency. In addition, CMB also allows the host to combine transmission commands and data, reducing communication overhead and enhancing system performance. Current CMB management is mainly through static configuration and software layer management. Static configuration pre-allocates CMB size during SSD initialization phase, which can maintain system stability under low load, but performance will decrease significantly when load fluctuates or storage fragmentation intensifies. Software layer management controls CMB allocation and use through the host operating system, but since allocation adjustment needs to be completed through communication between the host and the controller, data transmission delay is increased and access speed is reduced. In addition, the existing scheme lacks the ability to dynamically consolidate CMB fragmentation, resulting in high delay and low throughput when the host accesses CMB.

[0019] Although CMB has significant advantages in data transmission and system performance improvement, there are still many problems in practical application. The first is the fragmentation problem. Due to frequent data writing, deleting and updating, the CMB space is fragmented during a long period of operation. Fragmentation will cause a large number of small memory blocks to be unable to be effectively utilized, reducing cache hit rate and data transmission efficiency. The second is the non-continuous memory mapping problem. The physical storage space of SSD is often non-continuous, and the host needs to address multiple times when accessing, increasing the communication delay. In addition, the existing CMB management mechanism mostly adopts static configuration, which cannot be dynamically adjusted according to load changes. In high load or burst traffic scenarios, static configuration may cause cache shortage or resource waste, further limiting system performance.

[0020] Based on the above, the controller memory buffer management method provided by the embodiments of the present application realizes dynamic arrangement and efficient management of the CMB space inside the SSD through the integration of the memory scanning module, the memory conversion module and the event monitoring and triggering module. The memory scanning module is responsible for real-time monitoring of the memory usage state inside the SSD, detecting and classifying fragments, and generating a memory usage report. Through the combination of regular scanning and dynamic scanning, the memory scanning module can quickly identify and merge fragments, improving the utilization rate of the CMB space. The memory conversion module maps the non-continuous memory blocks into a logically continuous space recognizable by the host, reducing the number of addressing times when the host accesses the CMB, and reducing the access delay. The event monitoring and triggering module dynamically triggers memory allocation and configuration adjustment by monitoring key performance indicators such as I / O (Input / Output, read / write) requests, cache hit rate and delay, improving the system's adaptability and response speed under dynamic load. This method maintains the stability and efficiency of system performance through real-time monitoring and dynamic adjustment. The memory scanning module improves the speed of fragment detection and integration through parallel processing and cache mechanism, ensuring the real-time nature of memory management. The memory conversion module provides continuous memory space required by the host through logical mapping mechanism, enhancing data transmission efficiency. The event monitoring and triggering module ensures that the system can make rapid adjustments when performance bottlenecks occur, maintaining the overall stability and efficiency of the system through multi-level interrupt mechanism.

[0021] According to the embodiments of the present application, a controller memory buffer management method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a group of computer executable instructions, for example: computer, server, etc., and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from here.

[0022] A controller memory buffer management method is provided in the embodiment, Figure 1 is a flowchart of the controller memory buffer management method according to the embodiment of the application, as shown in the figure, the flow includes the following steps: Figure 1 Step S101, obtaining state information of a first preset number of memory blocks in the controller memory buffer.

[0023] Specifically, the controller memory buffer management method of the embodiment is executed by a controller memory buffer management system, which realizes dynamic arrangement and efficient utilization of the internal fragmented memory of the SSD by integrating a memory scanning module, a memory conversion module and an event monitoring and triggering module. The memory scanning module is responsible for real-time monitoring of the SSD memory usage state, detecting and marking fragments, and generating a memory usage report. Through efficient hardware design and algorithms, effective management of memory space and timely recovery of fragments are ensured. The following is a detailed description of the functions and implementation principles of the memory scanning module.

[0024] The memory scanning module divides the memory space of the controller memory buffer into multiple small blocks, each block is usually 4KB, 1MB or other standard sizes, depending on the actual situation. Each memory block will be processed as an independent unit to ensure fine-grained memory monitoring.

[0025] The memory scanning module obtains the state information of a first preset number of memory blocks in the controller memory buffer, for example: the memory scanning module first scans the SSD memory area to obtain the state of each memory block in real time, each memory block corresponds to a register entry to store the state. These memory blocks include free space, allocated areas and historical usage information. The memory space of the SSD is divided into memory blocks of fixed size, and each memory block is monitored as an independent object during the scanning process. The engine updates the state of the memory block periodically or in real time.

[0026] Step S102, determining a first to-be-processed memory block and a second to-be-processed memory block according to the state information, wherein the first to-be-processed memory block is a memory block with fragments, and the second to-be-processed memory block is a free memory block and the second to-be-processed memory block is not adjacent to other free memory blocks.

[0027] ​Specifically, the memory scanning module is responsible for monitoring the usage state of the internal memory of the SSD in real time, detecting and classifying fragments, and generating a memory usage report. The memory conversion module maps the scattered physical memory blocks into a continuous CMB area accessible by the host. The memory scanning module identifies and classifies memory fragments. Fragmented memory areas are usually represented as idle space that cannot be effectively utilized, or multiple small free areas scattered in the memory, which makes it impossible to allocate continuous memory space for large data. The scanning engine helps the system determine which areas can be recycled by detecting and classifying fragmented areas. The scanning engine identifies memory blocks with fragments by monitoring the free space, allocated areas, and historical usage data of the memory blocks, and takes the memory blocks with fragments as the first to-be-processed memory blocks.

[0028] The memory conversion module determines the physically discontinuous memory blocks, such as a memory block that is not occupied and whose adjacent memory blocks are occupied, as the second to-be-processed memory blocks according to the state information.

[0029] Step S103, in the case where the size of the fragments in the first to-be-processed memory block is greater than a first preset threshold, the fragments in the first to-be-processed memory block are recycled.

[0030] Specifically, the detected fragments are classified according to size, type, and location. For example, fragments with free space less than 4KB may have less impact on system performance, so they are not recycled, while fragments greater than 1MB are preferentially recycled. The first preset threshold is, for example, 1MB, 2MB, or other values. In the case where the size of the fragments in the first to-be-processed memory block is greater than the first preset threshold, the fragments in the first to-be-processed memory block are recycled.

[0031] Step S104, generating a virtual address according to the physical address of the second to-be-processed memory block, wherein the virtual address is used to map the second to-be-processed memory block into a continuous memory space.

[0032] Specifically, the memory conversion module is responsible for mapping physically discontinuous memory blocks into logically continuous space for direct access by the host, ensuring that the host can access the CMB area on demand. In the case of load fluctuations or fragmentation, the mapping relationship can be dynamically adjusted. A virtual address is generated according to the physical address of the second to-be-processed memory block, and the second to-be-processed memory block is mapped into a continuous memory space using the virtual address, ensuring that the host can always access continuous memory space when reading or writing data, thereby reducing access latency.

[0033] The controller memory buffer management method provided by the embodiment comprises the following steps: obtaining state information of memory blocks; determining a first to-be-processed memory block and a second to-be-processed memory block according to the state information; recycling fragments in the first to-be-processed memory block if the size of the fragments is greater than a threshold; and generating a virtual address according to the physical address of the second to-be-processed memory block and mapping the second to-be-processed memory block into a continuous memory space. The method can quickly detect and arrange the fragments of the memory blocks, recycle the fragments, improve the space utilization of the CMB, map the second to-be-processed memory block into a continuous memory space through a dynamic mapping mechanism using the virtual address, ensure that the host can access the continuous memory space logically, reduce the number of addressing, and improve the data transmission speed. The storage efficiency and access performance of the SSD system can be significantly improved. The problem of the discontiguous memory blocks and the memory blocks containing fragments in the controller memory buffer is solved, and the communication delay of the host accessing the SSD is reduced.

[0034] As an optional embodiment, after obtaining the state information of the first preset number of memory blocks in the controller memory buffer, the method further comprises: obtaining performance information of the storage device, and obtaining a target parameter according to the performance information and the state information; generating an interrupt signal containing a priority in the case where the target parameter exceeds a corresponding preset interval, wherein the priority is determined according to the comparison result of the target parameter and the preset interval; in the case where the interrupt signal exists, determining an adjustment strategy of the controller memory buffer according to the priority of the interrupt signal and the target parameter, and adjusting the controller memory buffer according to the adjustment strategy.

[0035] Specifically, the controller memory buffer management system further comprises an event monitoring and triggering module. The event monitoring and triggering module triggers a dynamic adjustment mechanism by monitoring key performance indicators such as I / O requests, cache hit rates, and delays in real time, and optimizes the allocation and management of the CMB. The system improves the utilization rate of the SSD cache and the overall performance of the system through dynamic fragment integration and address mapping, and ensures stability and efficiency in high-load or performance bottleneck situations. Data collection is the first step of the event monitoring and triggering module, and the goal is to obtain various key performance indicators inside the SSD in real time. In order to ensure the accuracy and real-time performance of data collection, the hardware counter and the sensor interface module play a crucial role.

[0036] The event monitoring and triggering module is provided with a counter and a sensor interface. The event monitoring and triggering module acquires performance information of the storage device, including: collecting I / O request related data inside the SSD by using the counter. For example, the number of I / O requests per second, the number of read and write requests, the number of cache hits and misses, request delays, etc. These counters can capture the workload and performance of the SSD in real time at a high frequency, helping the system accurately grasp the current performance state. In addition to I / O related data, environmental data closely related to the performance of the SSD is collected by using the sensor interface, such as temperature, power consumption, storage unit health status, etc. These sensors can monitor the temperature changes, power consumption fluctuations, and possible hardware failures or wear of the SSD in real time, providing more dimensional performance data.

[0037] The target parameters are obtained according to the performance information and the state information, such as cache hit rate, I / O request delay, throughput, etc.

[0038] After data collection, the threshold judgment unit in the event monitoring module compares the target parameters with the corresponding preset intervals to determine whether the set preset threshold is exceeded. The core of the threshold judgment process is to ensure that the system can respond in time when the performance appears bottleneck. The preset threshold usually includes but is not limited to cache utilization rate, delay, throughput and other key performance indicators. By dynamically adjusting these thresholds, the system can cope with changes under different load conditions and ensure the stability of performance under high load or abnormal conditions. The setting of the threshold considers the normal operation range of the system and the potential performance bottleneck. The comparator is the core component in the threshold judgment unit, which is responsible for comparing the real-time monitoring data with the preset threshold item by item. Whenever a performance indicator exceeds the preset threshold, the comparator will send a signal to the subsequent interrupt generator, informing the system that it needs to be adjusted. The trigger condition not only depends on a single performance indicator, but also considers multiple performance data. In a high load environment, a joint trigger condition may be set, which triggers an interrupt when both the delay and the cache hit rate are abnormal. This can avoid too frequent adjustments and improve the stability of the system.

[0039] When the threshold judgment unit finds an anomaly, the interrupt generation logic responds immediately, generating an interrupt signal and notifying the system to adjust the size of the CMB space. This mechanism is the key to the event monitoring and triggering module. Through the interrupt mechanism, the system can make adjustments at the moment when the performance bottleneck appears to avoid performance degradation. The interrupt generator is one of the core components of the event monitoring module. It generates a hardware-level interrupt request immediately based on the trigger signal output by the threshold judgment unit. The interrupt signal is delivered to other modules of the system (such as the reconfiguration controller, memory management module, etc.) through hardware, ensuring that the system can respond in a timely manner and make dynamic adjustments. Once the interrupt signal reaches the reconfiguration controller, the controller will automatically adjust the size of the CMB (Controller Memory Buffer) based on the current load and requirements, increasing the cache space or optimizing cache allocation. Through the interrupt mechanism, the system can quickly respond to changing load conditions, maintaining high performance and high stability.

[0040] The interrupt generation logic supports multi-level interrupt response, allowing the system to set different priorities based on the severity and urgency of the anomaly. Therefore, in the case where the target parameter exceeds the corresponding preset interval, an interrupt signal containing a priority is generated based on the comparison result of the target parameter and the preset interval, for example, a low cache hit rate may trigger a low-priority interrupt, while a high delay may trigger a high-priority interrupt, ensuring that more serious performance bottlenecks are handled first.

[0041] In the presence of an interrupt signal, the adjustment strategy for the controller memory buffer is determined based on the priority of the interrupt signal and the target parameter, and the controller memory buffer is adjusted according to the adjustment strategy, for example: when the cache hit rate is below 80%, the system may determine that the cache efficiency is low and needs to increase the cache size; or when the I / O request delay exceeds 10ms, the system may determine that the current cache allocation is insufficient or other performance bottlenecks, triggering an interrupt for processing; increasing or decreasing the size of the CMB, etc.

[0042] In this embodiment, the event monitoring and triggering module ensures that the system can make quick adjustments when performance bottlenecks occur, maintaining the overall stability and efficiency of the system. In addition, by monitoring key performance indicators in real time and dynamically adjusting the size and allocation strategy of the CMB, the system can maintain performance stability under dynamic load, breaking through the limitations of existing static CMB configuration and software layer management, and improving the utilization efficiency and access performance of the CMB in high-load and dynamic environments.

[0043] As an optional embodiment, the virtual address is generated according to the physical address of the second to-be-processed memory block, comprising: According to the physical address, the starting address and the virtual address base address of the second to-be-processed memory block are obtained; According to the physical address and the start address, a block offset of the second to-be-processed memory block is determined, and a virtual address of the second to-be-processed memory block is obtained according to the block offset and a virtual address base address.

[0044] Specifically, after the SSD controller receives the physical address of the memory block, the physical address is composed of a series of binary bits, which internally contains two main parts: one part is used to represent the memory block number, and the other part represents the offset within the memory block. The physical address can be decomposed into two parts: "block number" and "in-block offset".

[0045] In this way, the mapping unit can quickly determine the specific information of the memory block where the physical address is located, and calculate the corresponding virtual address. The mapping algorithm usually uses formula (1).

[0046] (1) Wherein, represents the virtual address obtained by conversion, is the virtual address base address mapped to, is the input physical address, is the start address of the memory block. Formula (1) obtains the offset within the memory block by subtracting the block start address in the physical address, and then adds the offset to the predetermined virtual address base address, so as to construct the logically continuous virtual address.

[0047] According to the physical address and the start address, a block offset of the second to-be-processed memory block is determined. The block offset and the virtual address base address are substituted into formula (1) to calculate the virtual address of the second to-be-processed memory block.

[0048] In this embodiment, the non-continuous memory block is mapped to a continuous memory address through a virtual address, for subsequent access by the host or the SSD controller. Through the data transmission interface, the SSD feeds back the logically continuous CMB state to the host, so that the host transparently accesses the cache area. This can significantly reduce the conversion delay, ensure the continuity of the virtual address space, and enhance the data transmission efficiency.

[0049] As an optional embodiment, according to the physical address, the start address and the virtual address base address of the second to-be-processed memory block are obtained, including: determining the memory block number of the second to-be-processed memory block in the physical address; determining a target entry containing the memory block number in the memory management table containing the state information; determining the start address and the virtual address base address of the second to-be-processed memory block in the target entry.

[0050] Specifically, a physical address is composed of a series of binary bits, which internally contains two main parts: one part is used to represent the memory block number, and the other part represents the offset within the memory block. The physical address can be decomposed into two parts: "memory block number" and "in-block offset". For example, a physical address is composed of a block number composed of the first several bits, and an in-block offset composed of the remaining bits. Then, the address resolution logic is started in the hardware circuit, and its main task is to split and interpret the input physical address. The resolution unit first sends the input address to the address resolution module, then performs bit-level splitting on the address, extracts the part representing the memory block number, and uses it as a lookup key to access the memory management table stored in the hardware register in advance.

[0051] The memory management table contains detailed information of each memory block, such as physical starting address, size, status (free or occupied), etc. The resolution unit uses the extracted memory block number to quickly find the target entry containing the memory block number in the memory management table, thereby determining which memory block the physical address belongs to. Once the memory block information is determined, the resolution unit further obtains the starting address and size information of the memory block from the memory management table to determine the starting address and virtual address base address of the second to-be-processed memory block in the target entry.

[0052] Next, the resolution logic takes the remaining bits of the input physical address as the in-block offset except for the memory block number part; this step can be obtained by directly reading the remaining bits, or by calculating the formula (physical address minus the starting address of the memory block). The obtained in-block offset represents the specific data storage location of the address within the memory block. Finally, the resolution unit packs the resolved memory block identifier (i.e. block number) and the calculated in-block offset into a data structure, which contains all the necessary conversion information and is passed to the subsequent mapping unit as the result of address conversion. The mapping unit then uses this information to convert the physical address to a logically continuous virtual address, thereby realizing the integration and management of multiple non-contiguous memory blocks. This series of processes realizes high-speed and low-latency address resolution through dedicated hardware circuit, laying a solid foundation for the dynamic management and efficient access of CMB inside the SSD.

[0053] The above process is shown in Figure 2 The physical address is input into the memory conversion module; the address resolution unit is started; the block number part is extracted, and the offset is separated; the memory management table is searched; the belonging memory block is determined and the starting address is obtained; the in-block offset is calculated = physical address - block starting address.

[0054] As an optional embodiment, before obtaining the state information of the first preset number of memory blocks in the controller memory buffer area, the method further comprises: According to the preset size, the memory space of the controller memory buffer is divided into a first preset number of memory blocks; Obtain the initial state information and position information of the memory block; According to the initial state information and position information, generate a memory management table.

[0055] Specifically, the preset size is, for example: 4KB, 1MB or other standard sizes.

[0056] In the initialization phase of the SSD system, the controller divides the CMB space into memory blocks of a preset size. The size of each memory block is determined according to the hardware design and load condition, and depends on the actual situation.

[0057] In order to manage these memory blocks, the controller will establish a memory management table (Memory Management Table, MMT) in the hardware register or dedicated storage area, which is used to store the state and position information of each memory block. Obtain the initial state information and position information of the memory block, and write the initial state information and position information into the memory management table.

[0058] The state of each memory block includes state markers such as "free", "allocated", "fragmented" and "in use". Write the above state markers into the memory management table, and the system will determine the use of the memory block according to these markers.

[0059] In this embodiment, each memory block will be processed as an independent unit to ensure fine-grained memory monitoring, and the initial state information and position information of the memory block are written into the memory management table to facilitate the system to determine the use of the memory block.

[0060] As an optional embodiment, the state information of the first preset number of memory blocks in the controller memory buffer is obtained, including: In the case of performing data modification operation on the storage device, generate a second preset number of scanning tasks, or generate a second preset number of scanning tasks according to a preset period; Parallelly execute the scanning tasks to obtain the state information; Write the state information into the memory management table.

[0061] Specifically, to efficiently monitor the usage status of the memory, the memory scanning module adopts a combination of periodic scanning and dynamic scanning to track the status of the memory blocks. The memory scanning module will periodically scan the status of the memory blocks according to a set period (such as every second, every minute, etc.). At each scan, the scanning engine will check the current usage of each memory block and update the status in real time. Periodic scanning ensures that the usage status of the memory blocks can reflect the resource utilization of the system under regular load. Dynamic scanning responds immediately when the storage device performs data modification operations, and scans the status of the memory blocks. Data modification operations, for example, when the SSD performs write, delete or update operations. Dynamic scanning can timely capture the memory fragmentation phenomenon caused by frequent I / O operations, data writing and deletion, and ensure timely detection and recycling of fragmented areas. Dynamic response enables the system to efficiently handle sudden loads and changes, improving the flexibility of memory management.

[0062] In the case of performing data modification operations on the storage device, a second preset number of scanning tasks are generated, or a second preset number of scanning tasks are generated according to a preset period.

[0063] To improve scanning efficiency and reduce latency, the memory scanning module uses parallel processing technology to simultaneously scan multiple memory blocks using multiple processing units. In addition, through the cache mechanism, the scanning engine can effectively speed up the scanning process and reduce dependence on the main memory. The scanning tasks are executed in parallel to obtain the status information. This enables the entire scanning process to be completed in a short time, especially under high load conditions, which effectively guarantees real-time performance. The status information is written to the memory management table.

[0064] In addition, the scanning engine will cache frequently accessed data (such as the usage status of the memory blocks) to high-speed storage. Through this caching mechanism, the scanning engine can quickly access the latest status of the memory blocks without having to re-read from the main memory each time, further improving scanning efficiency.

[0065] As an optional embodiment, determining the first to-be-processed memory block according to the status information comprises: determining the free space, the allocated space of the memory block, and the historical usage data of the memory block according to the status information; determining whether there is fragmentation in the memory block according to the free space, the allocated space, and the historical usage data; the memory block containing the fragmentation is taken as the first to-be-processed memory block.

[0066] In particular, one of the core tasks of the memory scanning module is to identify and classify memory fragmentation. The scanning engine helps the system determine which regions can be reclaimed by detecting and classifying fragmented regions. By scanning the state of memory blocks, the memory scanning module can detect which memory blocks contain fragmentation. A fragmented memory block is typically characterized by inefficient use of free space, leading to inefficient use of memory.

[0067] The memory scanning module determines the free space, allocated space, and historical usage data of the memory block based on the state information, and identifies these fragmented regions based on the free space, allocated space, and historical usage data to determine whether fragmentation exists in the memory block. The memory block containing fragmentation is taken as a first to-be-processed memory block.

[0068] As an optional embodiment, the fragmentation in the first to-be-processed memory block is reclaimed, including: In a case where the proportion of memory space occupied by the fragmentation in the first to-be-processed memory block is greater than a second preset threshold, or the size of the fragmentation in the first to-be-processed memory block is greater than a first preset threshold, contiguous third preset number of adjacent fragments in the fragmentation of the first to-be-processed memory block are obtained, and the adjacent fragments are merged. According to the state information, the idle time of the first to-be-processed memory block is determined. In a case where the idle time is greater than a third preset threshold, the first to-be-processed memory block is released as a new memory block.

[0069] In particular, the detected fragmentation is classified according to size, type, and location. For example, fragmentation with a free space less than 4 KB can have less impact on system performance, and thus is not reclaimed, while fragmentation greater than 1 MB is preferentially reclaimed. Classification of fragmentation helps preferentially process fragmented regions that have a greater impact on performance, improving the efficiency of memory reclamation. The first preset threshold is, for example, 4 KB, 1 MB, or other size. Therefore, if the size of the fragmentation in the first to-be-processed memory block is greater than the first preset threshold, contiguous third preset number of adjacent fragments in the fragmentation of the first to-be-processed memory block are obtained, and the adjacent fragments are merged. In addition, if the proportion of memory space occupied by the fragmentation in the first to-be-processed memory block is greater than a second preset threshold, for example, 50%, 60%, or other proportion, the fragmentation in the first to-be-processed memory block is reclaimed if the proportion of memory space occupied by the fragmentation is greater than the second preset threshold, contiguous third preset number of adjacent fragments in the fragmentation of the first to-be-processed memory block are obtained, and the adjacent fragments are merged.

[0070] The reclamation mechanism automatically identifies and reclaims free regions based on the usage state and historical access data of the memory regions. According to the state information, the idle time of the first to-be-processed memory block is determined. The system can set a reclamation time threshold, i.e., a third preset threshold, which is, for example, 1 hour, 2 hours, or other duration.

[0071] In the case where the idle time is greater than a third preset threshold, when it is determined that the memory block is idle beyond the threshold and is not frequently accessed, the memory block is automatically marked as a recyclable area, a priority queue is established, and the first to-be-processed memory block is released as a new memory block. Larger and continuous fragmented areas are given priority, and after recycling, the idle area can be used for memory allocation in high-load situations, ensuring efficient operation of the system.

[0072] As an optional embodiment, the controller memory buffer is adjusted according to an adjustment strategy, including: In the case where the load processing frequency of the storage device is greater than a fourth preset threshold according to the target parameter, the memory space of the controller memory buffer is increased, and the fragmentation of the memory block in the controller memory buffer is recycled; In the case where the load processing frequency of the storage device is less than or equal to the fourth preset threshold according to the target parameter, the memory space of the controller memory buffer is reduced, and the frequency of obtaining the target parameter is reduced.

[0073] Specifically, in the case where the load processing frequency of the storage device is greater than the fourth preset threshold according to the target parameter, it is determined that the CMB is in a high-load state. The controller memory buffer is adjusted according to an adjustment strategy, for example: in a high-load state, the system increases the cache space of the CMB, adjusts the memory mapping strategy, and preferentially merges and arranges fragmented areas, to ensure efficient data access capability of the host in a high-concurrency scenario. In addition, the system uses an intelligent learning mechanism based on historical access data and performance records to dynamically optimize the mapping method and the fragmentation management strategy, further improving the overall system performance.

[0074] In the case where the load processing frequency of the storage device is greater than the fourth preset threshold according to the target parameter, it is determined that the CMB is in a low-load state. The controller memory buffer is adjusted according to an adjustment strategy, for example: in the case where the load fluctuates or the storage state changes, the system can automatically perform dynamic optimization according to the current running state. In a low-load state, the system appropriately reduces the size of the CMB and reduces the frequency of fragment scanning, saving system resources.

[0075] In this embodiment, the event monitoring module dynamically adjusts the size and allocation strategy of the CMB by monitoring key performance indicators in real time, to ensure stable performance of the system under dynamic load. By implementing hardware-level parallel processing and cache mechanisms in the controller, the speed of fragment integration and memory mapping is improved, and access delay is reduced. This breaks through the limitations of existing static configuration and software layer management of the CMB, and improves the utilization efficiency and access performance of the CMB under high load and dynamic environment.

[0076] As an optional embodiment, the step S103 of "recycling the fragments in the first to-be-processed memory block" can further include steps A1 to A4.

[0077] Step A1, determining the address information of the fragments corresponding to each namespace in the memory pool.

[0078] Specifically, the memory pool refers to a Fragement Pool, that is, when each namespace is created on the disk, the corresponding address is selected according to the specific space distribution information of the disk, and each piece of discontinuous address corresponds to a fragment group to form an information pool. The fragments and the corresponding address information of the memory pool can be determined by scanning the data, so as to arrange the data of the namespace according to the address information.

[0079] Step A2, selecting the target namespace and the to-be-arranged namespace based on the distribution information of the address information inside the disk.

[0080] Specifically, the target namespace refers to the namespace that needs to be adjusted, which can be the first namespace in the discontinuous logical address segment or any discontinuous namespace, and the to-be-arranged namespace refers to one or more namespaces in the discontinuous logical address segment of the target namespace.

[0081] Step A3, after storing the to-be-arranged namespace into the garbage collection buffer, modifying the logical addresses of the multiple discontinuous memory segments of the target namespace into continuous logical addresses based on the logical address of the first fragment of the target namespace; Specifically, in the optional embodiment of modifying the logical addresses of the multiple discontinuous memory segments of the namespace into continuous logical addresses, after storing the to-be-arranged namespace into the garbage collection buffer, the tail address of the first fragment, the head address and the address length of the second fragment are determined, then the logical addresses of the second fragment are modified into the target logical addresses of the address segment with the same address length starting from the next address of the tail address, and finally the above address conversion processing action is repeatedly performed based on the modified fragments until the address conversion of the last fragment of the target namespace is completed.

[0082] Step A4, adding the memory segment corresponding to the to-be-arranged namespace in the garbage collection buffer to the rear of the target namespace.

[0083] Specifically, the initial address and memory segment length of the target namespace located in a contiguous logical address range can be determined. Then, the destination address is determined based on the initial address and memory segment length. The memory segment corresponding to the namespace to be processed is added to the free segment after the destination address. Thus, when there is only one namespace to be processed, data processing is completed directly, improving the disk drive's storage space utilization. When there are multiple namespaces to be processed, the processing can be repeated. Once the logical address ranges of the namespaces have been processed, the modification of the current logical address is considered complete.

[0084] The namespace to be reorganized can be a single namespace or multiple namespaces. When the namespace to be reorganized is a single namespace, after adding it to the garbage collection buffer, the fragments of this namespace are contiguous. After placing it back into the target namespace, the corresponding fragments remain contiguous. As another optional implementation, after sequentially reorganizing the memory fragments corresponding to the namespace to be reorganized to the end of the target namespace, it is necessary to update the address information in the memory pool and obtain the number of namespaces to be reorganized. If there are multiple namespaces, it indicates that there are namespaces in the disk drive that are not contiguous. In this case, it is necessary to continue executing the steps of selecting the target namespace and the namespace to be reorganized based on the updated address information in the memory pool. Based on this, non-contiguous namespaces can continue to be reorganized, improving the storage space utilization of the disk drive. When there is only one namespace, it is necessary to execute the steps of obtaining the number of namespaces and fragments in the memory pool to determine whether the number of namespaces and fragments are the same. If they are the same, no data processing is required. When the number of namespaces differs from the number of fragments, further processing is required to improve the utilization rate of the disk drive's storage space.

[0085] In this embodiment, multiple discontinuous memory segments are modified into segments with contiguous logical addresses, thereby enabling the use of free segments interspersed among the multiple discontinuous memory segments and improving the storage space utilization of the disk drive.

[0086] According to embodiments of this application, a controller memory buffer management system is provided, such as... Figure 3 As shown, the system includes: a memory scanning module and a memory conversion module; The memory scanning module is used to obtain the status information of the first preset number of memory blocks in the controller's memory buffer; The memory scanning module is used to determine the first memory block to be processed based on the status information, wherein the first memory block to be processed is a memory block containing fragments; The memory conversion module is configured to determine, according to the state information, a second to-be-processed memory block, wherein the second to-be-processed memory block is a free memory block and the second to-be-processed memory block is not adjacent to other free memory blocks. The memory scanning module is configured to recycle the fragments in the first to-be-processed memory block when the size of the fragments in the first to-be-processed memory block is greater than a first preset threshold. The memory conversion module is configured to generate a virtual address according to the physical address of the second to-be-processed memory block, wherein the virtual address is used to map the second to-be-processed memory block as a continuous memory space.

[0087] Specifically, as shown in Figure 3 The controller memory buffer management system includes a memory scanning module and a memory conversion module. The memory conversion module is configured to provide memory for a host controller memory buffer mapping area, and the host can access the host controller memory buffer mapping area. The memory scanning module acquires state information of a first preset number of memory blocks in the controller memory buffer. For example, the memory scanning module first acquires the state of each memory block in real time by scanning the SSD memory area. Each memory block corresponds to a register entry to store the state. These memory blocks include free space, allocated areas, and historical usage information. The memory space of the SSD is divided into memory blocks of a fixed size, and each memory block is monitored as an independent object during the scanning process. The engine updates the state of the memory block periodically or in real time.

[0088] The memory scanning module identifies a memory block as having fragments by monitoring the free space, allocated areas, and historical usage data of the memory block, and takes the memory block having fragments as a first to-be-processed memory block.

[0089] The memory conversion module determines a physically discontinuous memory block according to the state information. For example, a memory block that is not occupied and whose connected memory blocks are all occupied is a discontinuous memory block, i.e., a second to-be-processed memory block.

[0090] The first preset threshold is, for example, 1 MB, 2 MB, or another value. The memory scanning module recycles the fragments in the first to-be-processed memory block when the size of the fragments in the first to-be-processed memory block is greater than the first preset threshold.

[0091] The memory conversion module is responsible for mapping the physically discontinuous memory block as a logically continuous space for the host to directly access, ensuring that the host can access the CMB area as needed. In the case of load fluctuations or fragmentation, the mapping relationship can be dynamically adjusted. A virtual address is generated according to the physical address of the second to-be-processed memory block, and the second to-be-processed memory block is mapped as a continuous memory space using the virtual address, ensuring that the host can always access continuous memory space when reading or writing data, thereby reducing access delay. The memory conversion module is as shown inFigure 4 As shown, the memory conversion module includes an address resolution unit and a mapping unit, and is configured to map a plurality of non-continuous memory units into a continuous memory unit.

[0092] The controller memory buffer management system provided by the embodiment can quickly detect and organize the fragments of the memory blocks, recycle the fragments, improve the space utilization of the CMB, map the second to-be-processed memory block into a continuous memory space through a dynamic mapping mechanism using a virtual address, ensure that the host can access the continuous memory space logically, reduce the number of addressing, and improve the data transmission speed. The storage efficiency and access performance of the SSD system can be significantly improved. The problems of the discontinuous memory blocks and the memory blocks containing fragments in the controller memory buffer area are solved, and the communication delay of the host accessing the SSD is reduced.

[0093] As an optional embodiment, the system further comprises an event monitoring and triggering module; the event monitoring and triggering module comprises a data acquisition unit, a threshold comparison unit, an interrupt generation unit, and an adjustment unit; The data acquisition unit is configured to acquire performance information of the storage device, and obtain a target parameter according to the performance information and the state information; The threshold comparison unit is configured to compare the target parameter with a corresponding preset interval; The interrupt generation unit is connected with the adjustment unit, and is configured to generate an interrupt signal containing a priority in a case where the target parameter is out of the corresponding preset interval, and transmit the interrupt signal to the adjustment unit, wherein the priority is determined according to the comparison result of the target parameter and the preset interval; The adjustment unit is configured to determine an adjustment strategy of the controller memory buffer area according to the priority of the interrupt signal and the target parameter in a case where the interrupt signal exists, and adjust the controller memory buffer area according to the adjustment strategy.

[0094] Specifically, as shown in Figure 3 The controller memory buffer management system further comprises an event monitoring and triggering module, the event monitoring and triggering module is configured to monitor the usage of the solid state disk and trigger the host to modify the controller memory buffer, and the event monitoring and triggering module can also notify the memory conversion module to adjust. The structure of the event monitoring and triggering module is as shown in Figure 5As shown, it includes a data acquisition unit, a threshold comparison unit, an interrupt generation unit, and an adjustment unit, also includes a hardware counter unit and a sensor interface unit, the hardware counter unit is used to obtain the number of read-write requests and cache hit rate, and the sensor interface unit is used to obtain temperature power consumption. The data acquisition unit includes a high-speed register and a transmission controller. The threshold comparison unit includes: delay judgment, hit rate judgment and throughput judgment. The interrupt generation unit is used to generate low-priority interrupts, medium-priority interrupts, and high-priority interrupts. The adjustment unit is used for cache allocation, read-write request scheduling, and adjustment of controller memory buffer. The data acquisition unit is provided with a counter and a sensor interface, and the event monitoring and triggering module obtains the performance information of the storage device, including: using the counter to collect I / O request related data inside the SSD. For example, record the number of I / O requests per second, the number of read-write requests, the number of cache hits and misses, request delay, etc. These counters can capture the workload and performance of the SSD in real time at a high frequency, helping the system accurately grasp the current performance state. In addition to I / O related data, environmental data closely related to SSD performance is collected using a sensor interface, such as temperature, power consumption, storage unit health status, etc. These sensors can monitor the temperature changes, power consumption fluctuations, and possible hardware failures or wear of the SSD in real time, providing more dimensional performance data. The target parameters are obtained according to the performance information and state information, such as cache hit rate, I / O request delay, throughput, etc.

[0095] The threshold comparison unit compares the target parameters with the corresponding preset intervals to determine whether the set preset threshold is exceeded. The core of the threshold judgment process is to ensure that the system can respond in time when the performance appears bottleneck.

[0096] The interrupt generation unit uses an interrupt signal to deliver to other modules of the system (such as a reconfiguration controller, a memory management module, etc.) through hardware, ensuring that the system can respond in time and make dynamic adjustments. Once the interrupt signal reaches the reconfiguration controller, the controller will automatically adjust the size of the CMB (Controller Memory Buffer) according to the current load and demand, increase the cache space or optimize the cache allocation. Through the interrupt mechanism, the system can quickly respond to changing load conditions and maintain high performance and high stability.

[0097] The adjustment unit determines the adjustment strategy of the controller memory buffer according to the priority of the interrupt signal and the target parameters when the interrupt signal exists, and adjusts the controller memory buffer according to the adjustment strategy.

[0098] In the embodiment, the event monitoring and triggering module ensures that the system can make quick adjustment when performance bottleneck occurs, maintains the overall stability and efficiency of the system through the multi-level interrupt mechanism. In addition, by monitoring the key performance indicators in real time, dynamically adjusting the size and allocation strategy of the CMB, the system can maintain stable performance under dynamic load, break through the limitations of the existing static configuration of CMB and software layer management, and improve the utilization efficiency and access performance of CMB under high load and dynamic environment.

[0099] In the embodiment, the event monitoring and triggering module ensures that the system can make quick adjustment when performance bottleneck occurs, maintains the overall stability and efficiency of the system through the multi-level interrupt mechanism. In addition, by monitoring the key performance indicators in real time, dynamically adjusting the size and allocation strategy of the CMB, the system can maintain stable performance under dynamic load, break through the limitations of the existing static configuration of CMB and software layer management, and improve the utilization efficiency and access performance of CMB under high load and dynamic environment.

[0100] As an optional embodiment, the memory scanning module includes a memory scanning unit, a fragment detection unit, and a state reporting unit. The memory scanning unit is configured to generate a second preset number of scanning tasks when the storage device performs a data modification operation, or generate a second preset number of scanning tasks according to a preset period, and execute the scanning tasks in parallel to obtain state information. The fragment detection unit is configured to determine the free space, the allocated space of the memory block, and the historical usage data of the memory block according to the state information, determine the fragments in the memory block according to the free space, the allocated space, and the historical usage data. The state reporting unit is configured to obtain the free space and the allocated space of the memory block, obtain the number, size, and location of the fragments, and generate a memory usage report according to the free space, the allocated space, the number, size, and location of the fragments.

[0101] Specifically, the structure of the memory scanning module is as shown in Figure 6 The memory scanning module includes a memory state register, a cache fast access unit, a memory scanning unit, a fragment detection unit, a fragment consolidation and merging unit, a memory recycling and priority management unit, a state reporting unit, and a statistical analysis module. The memory scanning unit includes N channels, including channel 1, channel 2, …, and channel N, where N can be 5, 6, 7, or other numbers that meet actual needs. Different channels are used to execute different scanning tasks.

[0102] In order to efficiently monitor the usage state of the memory, the memory scanning module adopts a combination of periodic scanning and dynamic scanning to track the state of the memory blocks. The memory scanning module will periodically scan the state of the memory blocks according to the set period (such as every second, every minute, etc.). Dynamic scanning will immediately respond and scan the state of the memory blocks in the case of data modification operation performed by the storage device. In the case of data modification operation performed by the storage device, a second preset number of scanning tasks are generated, or a second preset number of scanning tasks are generated according to the preset period, and the scanning tasks are executed in parallel to obtain the state information.

[0103] The fragment detection unit determines the free space, the allocated space, and the historical usage data of the memory blocks according to the state information, identifies these fragment regions according to the free space, the allocated space, and the historical usage data, and determines whether there are fragments in the memory blocks. The memory blocks containing fragments are taken as the first to-be-processed memory blocks.

[0104] The state reporting unit will count the usage, the number of fragments, the size of fragments, the free space, and other information of each memory block in each scanning process. The scanning results will generate detailed memory usage reports for subsequent memory management operations. The report content includes: the usage state of the memory blocks: whether each memory block is being used, whether it is free, whether it contains fragments, etc. The free space and the allocated space of the memory blocks: the free space and the allocated space of each memory block are counted to evaluate the memory utilization efficiency. The size and position of the fragment regions: the size, position, and classification information of each fragment region are included in the report to facilitate subsequent fragment recovery and arrangement operations. These reports will be delivered to the fragment identification module and the memory management module to further optimize the memory allocation strategy and perform fragment.

[0105] In the embodiment, a controller memory buffer management apparatus is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware is also possible and contemplated.

[0106] The embodiment provides a controller memory buffer management apparatus, as shown in the following Figure 7 The apparatus includes: An information acquisition module 701 is configured to acquire state information of a first preset number of memory blocks in a controller memory buffer. The memory block determination module 702 is used to determine a first memory block to be processed and a second memory block to be processed based on the status information. The first memory block to be processed is a memory block with fragmentation, and the second memory block to be processed is a free memory block and is not adjacent to other free memory blocks. The fragmentation recycling module 703 is used to recycle fragments in the first memory block to be processed when the fragment size in the first memory block to be processed is greater than a first preset threshold. Address generation module 704 is used to generate a virtual address based on the physical address of the second memory block to be processed, wherein the virtual address is used to map the second memory block to be processed into a contiguous memory space.

[0107] Further functional descriptions of the above modules are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0108] In this embodiment, the controller memory buffer management device is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0109] This application also provides a computer device having the above-described features. Figure 7 The controller memory buffer management device shown.

[0110] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of this application, such as... Figure 8 As shown, the computer device includes one or more processors 801, memory 802, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 8 Take the 801 processor as an example.

[0111] The processor 801 can be a central processing unit, a network processing unit, or a combination thereof. The processor 801 can further include an integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field-programmable gate array, a generic array logic, or any combination thereof.

[0112] The memory 802 stores instructions executable by the at least one processor 801 to cause the at least one processor 801 to perform the methods illustrated in the above embodiments.

[0113] The memory 802 can include a program storage area and a data storage area. The program storage area can store an operating system, application programs, and the like for the computer device. The data storage area can store application data, user data, and the like. The memory 802 can include a volatile memory, such as a random access memory (RAM), and can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid state disk. The memory 802 can also include a combination of the above-mentioned memories.

[0114] The memory 802 can include a volatile memory, such as a random access memory (RAM); the memory can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid state disk; and the memory 802 can also include a combination of the above-mentioned memories.

[0115] The computer device further includes a communication interface 803 for communication between the computer device and other devices or communication networks.

[0116] The embodiments of the present application also provide a computer readable storage medium. The above-mentioned methods according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded to a local storage medium through network downloading, so that the methods described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a memory that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods illustrated in the above embodiments are implemented.

[0117] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, can invoke or provide methods and / or technical solutions according to the present application. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source files, executable files, installation package files, etc., and accordingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0118] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the present application.

Claims

1. A method for managing a controller memory buffer, the method comprising: The method comprises: obtaining state information of a first preset number of memory blocks in a controller memory buffer area; determining a first to-be-processed memory block and a second to-be-processed memory block according to the state information, wherein the first to-be-processed memory block is a memory block with fragmentation, and the second to-be-processed memory block is an idle memory block and is not adjacent to other idle memory blocks; in the case where the size of the fragmentation in the first to-be-processed memory block is greater than a first preset threshold, recycling the fragmentation in the first to-be-processed memory block; generating a virtual address according to the physical address of the second to-be-processed memory block, wherein the virtual address is used to map the second to-be-processed memory block as a continuous memory space.

2. The method of claim 1, wherein, After the state information of the first preset number of memory blocks in the controller memory buffer area is obtained, the method further comprises: obtaining performance information of a storage device, and obtaining a target parameter according to the performance information and the state information; in the case where the target parameter is out of a corresponding preset interval, generating an interrupt signal containing a priority, wherein the priority is determined according to the comparison result of the target parameter and the preset interval; in the case where the interrupt signal exists, determining an adjustment strategy of the controller memory buffer area according to the priority of the interrupt signal and the target parameter, and adjusting the controller memory buffer area according to the adjustment strategy.

3. The method of claim 1, wherein, The generating of the virtual address according to the physical address of the second to-be-processed memory block comprises: obtaining a starting address and a virtual address base address of the second to-be-processed memory block according to the physical address; determining an intra-block offset of the second to-be-processed memory block according to the physical address and the starting address, and obtaining the virtual address of the second to-be-processed memory block according to the intra-block offset and the virtual address base address.

4. The method of claim 3, wherein, The obtaining of the starting address and the virtual address base address of the second to-be-processed memory block according to the physical address comprises: determining a memory block number of the second to-be-processed memory block in the physical address; determining a target entry containing the memory block number in a memory management table containing the state information; determining the starting address and the virtual address base address of the second to-be-processed memory block in the target entry.

5. The method of claim 1, wherein, Before the state information of the first preset number of memory blocks in the controller memory buffer area is obtained, the method further comprises: dividing the memory space of the controller memory buffer area into a first preset number of memory blocks according to a preset size; obtaining initial state information and position information of the memory blocks; generating a memory management table according to the initial state information and the position information.

6. The method of claim 5, wherein, The obtaining of the state information of the first preset number of memory blocks in the controller memory buffer area comprises: in the case where a storage device performs a data modification operation, generating a second preset number of scanning tasks, or generating a second preset number of scanning tasks according to a preset period; performing the scanning tasks in parallel to obtain the state information; writing the state information into the memory management table.

7. The method of claim 1, wherein, The determination of the first to-be-processed memory block according to the state information comprises: determine free space, allocated space and historical usage data of the memory block according to the state information; determine whether there is fragmentation in the memory block according to the free space, the allocated space and the historical usage data; the memory block containing the fragmentation is taken as the first memory block to be processed.

8. The method according to claim 1 or 7, characterized in that, the recycling of the fragmentation in the first memory block to be processed includes: when the proportion of the memory space occupied by the fragmentation in the first memory block to be processed is greater than a second preset threshold, or the size of the fragmentation in the first memory block to be processed is greater than the first preset threshold, contiguous third preset number of adjacent fragments in the fragmentation of the first memory block to be processed are obtained, and the adjacent fragments are merged; determine the idle time of the first memory block to be processed according to the state information; when the idle time is greater than a third preset threshold, the first memory block to be processed is released as a new memory block.

9. The method of claim 2, wherein, the adjusting of the controller memory buffer according to the adjustment strategy includes: when the load processing frequency of the storage device is greater than a fourth preset threshold according to the target parameter, the memory space of the controller memory buffer is increased, and the fragmentation of the memory block in the controller memory buffer is recycled; when the load processing frequency of the storage device is less than or equal to the fourth preset threshold according to the target parameter, the memory space of the controller memory buffer is reduced, and the frequency of obtaining the target parameter is reduced.

10. A controller memory buffer management system, comprising: the system includes a memory scanning module and a memory conversion module; the memory scanning module is configured to obtain state information of a first preset number of memory blocks in a controller memory buffer; the memory scanning module is configured to determine a first memory block to be processed according to the state information, wherein the first memory block to be processed is a memory block with fragmentation; the memory conversion module is configured to determine a second memory block to be processed according to the state information, wherein the second memory block to be processed is an idle memory block and the second memory block to be processed is not adjacent to other idle memory blocks; the memory scanning module is configured to recycle the fragmentation in the first memory block to be processed when the size of the fragmentation in the first memory block to be processed is greater than a first preset threshold; the memory conversion module is configured to generate a virtual address according to a physical address of the second memory block to be processed, wherein the virtual address is used to map the second memory block to be processed as contiguous memory space.

11. The system of claim 10, wherein, the system further includes an event monitoring and triggering module; the event monitoring and triggering module includes a data acquisition unit, a threshold comparison unit, an interrupt generation unit and an adjustment unit; the data acquisition unit is configured to obtain performance information of a storage device, and obtain a target parameter according to the performance information and the state information; the threshold comparison unit is configured to compare the target parameter with a corresponding preset interval; the threshold comparison unit is configured to compare the target parameter with a corresponding preset interval; The interrupt generation unit is connected with the adjustment unit, and is configured to generate an interrupt signal containing a priority when the target parameter is out of the corresponding preset interval, and transmit the interrupt signal to the adjustment unit, wherein the priority is determined according to a comparison result of the target parameter and the preset interval. The adjustment unit is configured to determine an adjustment strategy of a controller memory buffer according to the priority of the interrupt signal and the target parameter when the interrupt signal exists, and adjust the controller memory buffer according to the adjustment strategy.

12. The system of claim 10, wherein, The memory scanning module comprises a memory scanning unit, a fragment detection unit and a state reporting unit. The memory scanning unit is configured to generate a second preset number of scanning tasks when a data modification operation is performed on the storage device, or generate a second preset number of scanning tasks according to a preset period, execute the scanning tasks in parallel, and obtain the state information. The fragment detection unit is configured to determine free space, allocated space and historical use data of a memory block according to the state information, and determine fragments in the memory block according to the free space, the allocated space and the historical use data. The state reporting unit is configured to obtain the free space and the allocated space of the memory block, obtain the number, size and position of the fragments, and generate a memory use report according to the free space, the allocated space, the number, size and position of the fragments.

13. A computer device, comprising: Comprise: A memory and a processor, which are connected with each other and communicate with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the controller memory buffer management method in any one of claims 1 to 9.

14. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions, and the computer instructions are used to make the computer execute the controller memory buffer management method in any one of claims 1 to 9.

15. A computer program product, characterised in that, The computer instructions are used to make the computer execute the controller memory buffer management method in any one of claims 1 to 9.

Images