Memory dependency prediction method and device based on branch predictor and processor architecture

Abstract

The invention relates to the technical field of processors, and provides a memory dependency prediction method and device based on a branch predictor and a processor architecture, and the method comprises the steps: selecting a prediction block from an instruction fetching queue; determining a target load instruction in the prediction block; and predicting memory dependence information of the target load instruction according to global branch historical information of the branch direction predictor. According to the embodiment of the invention, the prediction precision of memory dependency prediction can be improved, the memory dependency prediction cost can be reduced, and the method is suitable for a modern processor which is high in performance, performs out-of-order execution and is provided with a decoupling front-end framework.

Description

Technical Field

[0001] This specification relates to the field of processor technology, and in particular to a memory dependency prediction method, apparatus and processor architecture based on a branch predictor. Background Technology

[0002] Memory dependency prediction is a technique in processor architecture used to optimize instruction execution efficiency. By predicting data dependencies between memory operation instructions (such as Load instructions for reading memory and Store instructions for writing memory), pipeline scheduling can be optimized. Currently, existing memory dependency prediction methods suffer from low accuracy and high cost. Summary of the Invention

[0003] The purpose of the embodiments in this specification is to provide a memory dependency prediction method, device and processor architecture based on a branch predictor, so as to improve the prediction accuracy of memory dependency prediction and reduce the cost of memory dependency prediction.

[0004] To achieve the above objectives, in one aspect, embodiments of this specification provide a memory dependency prediction method based on a branch predictor, including:

[0005] Select the prediction block from the instruction fetch queue;

[0006] Determine the target load instruction in the prediction block;

[0007] The memory dependency information of the target load instruction is predicted based on the global branch history information of the branch direction predictor.

[0008] In some embodiments of this application, determining the target load instruction in the prediction block includes:

[0009] Select a branch target buffer (BTB) entry from the prediction block;

[0010] Confirm that the instruction type corresponding to the selected BTB entry is a load instruction;

[0011] If it is a load instruction, then the MDP field identifier in the corresponding entry of the load instruction in the branch direction predictor is used to confirm whether the load instruction is an MDP load instruction; the MDP load instruction represents a load instruction that needs to perform memory dependency prediction.

[0012] If it is an MDP load instruction, then confirm whether the instruction address of the MDP load instruction is within the starting address of the prediction block;

[0013] If it is located within the starting address of the prediction block, then the MDP load instruction is determined as the target load instruction.

[0014] In some embodiments of this application, predicting the memory dependency information of the target load instruction based on the global branch history information of the branch direction predictor includes:

[0015] Based on the useful value of the entry corresponding to the target load instruction in the branch direction predictor, a storage distance is selected as the target storage distance from multiple storage distances of the BTB entry corresponding to the target load instruction. Each storage distance represents the number of store instructions that the target load instruction depends on on a specific branch history path.

[0016] Confirm whether the count value of the saturation counter corresponding to the target storage distance is greater than the threshold;

[0017] If the count value of the saturation counter corresponding to the target storage distance is greater than the threshold, it is confirmed that the target load instruction has a memory dependency, and the storage distance of its memory dependency is the target storage distance.

[0018] In some embodiments of this application, after predicting the memory dependency information of the target load instruction based on the global branch history information of the branch predictor, the method further includes:

[0019] Save the memory dependency information of the target load instruction.

[0020] In some embodiments of this application, saving the memory dependency information of the target load instruction includes:

[0021] If the target load instruction has a memory dependency, then determine whether the target storage distance is a boundary value; the boundary value includes zero and an upper limit value;

[0022] If the target storage distance is not a boundary value, then check whether the insertion conditions are met in MDDB;

[0023] If the insertion conditions are met, the memory dependency prediction result of the target load instruction is inserted into the MDDB.

[0024] In some embodiments of this application, the insertion conditions include at least one of the following:

[0025] There are free entries in MDDB;

[0026] The number of MDP load instructions processed together in the prediction block did not exceed the specified range.

[0027] In some embodiments of this application, saving the memory dependency information of the target load instruction further includes:

[0028] If the target load instruction has a memory dependency and the corresponding storage distance is the upper limit, then in the MDP bit value array corresponding to the prediction block, the MDP bit value corresponding to the target load instruction is modified to 1; the MDP bit value of 1 indicates that the target load instruction needs to wait for the store instruction it depends on according to a preset strategy.

[0029] If the target load instruction has no memory dependency, or if the target load instruction has a memory dependency and the corresponding storage distance is zero, or if the target load instruction has a memory dependency and the corresponding storage distance is not a boundary value, then in the MDP bit value array corresponding to the prediction block, the MDP bit value corresponding to the target load instruction is maintained at 0.

[0030] In some embodiments of this application, the method further includes:

[0031] After the memory dependency prediction processing of all MDP load instructions in the prediction block is completed, the MDP bit value array corresponding to the prediction block is written into the instruction fetch queue.

[0032] In some embodiments of this application, the method further includes:

[0033] When it is confirmed that the target load instruction has a memory dependency, in the prediction block, the MDP bit value corresponding to all bytes between the instruction address of the target load instruction and its previous branch instruction is modified to 1; the MDP bit value of 1 indicates that the target load instruction needs to wait for the store instruction it depends on according to a preset strategy.

[0034] In some embodiments of this application, the preset strategy includes any one of the following:

[0035] Launch after all store instructions preceding the target load instruction have completed address processing;

[0036] Launch after a fixed number of store instructions preceding the target load instruction have completed address processing;

[0037] Increase the waiting time window and launch after the waiting time window times out.

[0038] In some embodiments of this application, the method further includes:

[0039] When converting a load instruction in the fetch queue into a micro-operation at a specified stage, an MDP available flag and storage distance are added to the converted micro-operation based on the MDP bit array and MDDB corresponding to the load instruction; the specified stage includes any one of the following: decoding stage, fetch stage, issue stage, and renaming stage.

[0040] In some embodiments of this application, the method further includes:

[0041] Dynamically update the BTB and branch direction predictor.

[0042] In some embodiments of this application, the dynamic updating of the BTB includes:

[0043] When a nuke event occurs after a load instruction is executed, the BTB is searched using the instruction address of that load instruction;

[0044] If no corresponding BTB entry is found, a free BTB entry is selected from the BTBs or a non-free BTB entry is selected according to the first replacement strategy, and the memory dependency information is stored.

[0045] If the corresponding BTB entry is hit and the memory distance of the load instruction does not exist in the BTB entry, then the memory dependency information of the load instruction is sequentially inserted into the BTB entry.

[0046] If the corresponding BTB entry is hit and the storage distance of the load instruction exists in the BTB entry, then the BTB entry remains unchanged;

[0047] If the corresponding BTB entry is hit and there are no free BTB entries in the BTB, then clear all BTB entries in the BTB.

[0048] In some embodiments of this application, the dynamically updated branch direction predictor includes:

[0049] When a nuke event occurs after a load instruction is executed, a target prediction table whose historical length matches the memory distance of the load instruction is selected from multiple prediction tables of the branch direction predictor.

[0050] Based on the historical length of the target prediction table, the history is extracted from the global history register, and the extracted history is hashed with the instruction address of the load instruction to generate an index of the target prediction table. The target prediction table is then searched using the index.

[0051] If no corresponding entry is found, a free entry is selected from the target prediction table or a non-free entry is selected according to the second replacement strategy, and the memory dependency information is stored.

[0052] If a corresponding entry is hit, the value of the saturation counter corresponding to that entry is incremented by 1.

[0053] In some embodiments of this application, the dynamically updated branch direction predictor further includes:

[0054] During the instruction retirement phase, if no memory dependency is found between the micro-operation with the MDP available flag set to 1 and the store instruction at the corresponding memory distance, the number of branch instructions is deduced based on the memory distance to locate the corresponding entry in the prediction table, and the value of the saturation counter corresponding to the entry is decremented by 1.

[0055] During the instruction retirement phase, if a micro-operation with the MDP flag set to 1 finds a memory dependency relationship with the store instruction at the corresponding memory distance, the number of branch instructions is deduced based on the memory distance to locate the corresponding entry in the prediction table, and the value of the saturation counter corresponding to that entry is incremented by 1.

[0056] In some embodiments of this application, the first replacement strategy includes the PLRU algorithm.

[0057] In some embodiments of this application, the second replacement strategy includes:

[0058] If the MDP field of the load instruction is 0, then the memory dependency information in the entry corresponding to the smallest useful value in the target prediction table is replaced with the memory dependency information of the load instruction.

[0059] If the MDP field of the load instruction is 1, then the memory dependency information in the entry corresponding to the smallest saturation count value in the target prediction table is replaced with the memory dependency information of the load instruction.

[0060] In some embodiments of this application, the method further includes:

[0061] Confirm whether the most recent exit instruction is a branch instruction;

[0062] If it is a branch instruction, then modify the bit value corresponding to the branch instruction in the branch bit value array to 1;

[0063] If it is not a branch instruction, then the bit value corresponding to the branch instruction in the branch bit value array is kept at 0;

[0064] The length of the exit branch bit value array is the upper limit of the storage distance; the number of bits with a value of 1 in the nearest storage distance bit of the exit branch bit value array corresponds to the number of branch instructions between the load instruction and the dependent store instruction.

[0065] In some embodiments of this application, the BTB and the branch direction predictor adopt a group-connected mapping structure.

[0066] In some embodiments of this application, the branch direction predictor includes any one of the following:

[0067] Tag-based geometric history length branch predictor;

[0068] Hash-aware predictor;

[0069] Global historical branch predictor.

[0070] On the other hand, embodiments of this specification also provide a memory dependency prediction device based on a branch predictor, comprising:

[0071] The selection module is used to select a prediction block from the instruction fetch queue;

[0072] The determination module is used to determine the target load instruction in the prediction block;

[0073] The prediction module is used to predict the memory dependency information of the target load instruction based on the global branch history information of the branch direction predictor.

[0074] On the other hand, embodiments of this specification also provide a processor architecture in which the above-described memory dependency prediction device is configured.

[0075] On the other hand, embodiments of this specification also provide a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the computer program, when run by the processor, executes instructions for the above-described method.

[0076] As can be seen from the technical solutions provided in the embodiments of this specification above, the embodiments of this application implement memory dependency prediction by reusing the branch predictor. This allows the branch predictor to retain the original branch prediction function while also having the function of memory dependency prediction. That is, the two functions of branch prediction and memory dependency prediction are implemented with a single set of hardware, thereby reducing hardware resources and processor area, and lowering the cost of memory dependency prediction. Moreover, the embodiments of this application predict the memory dependency information of the load instruction by utilizing the global branch history information of the branch predictor, and also inherit the high-precision learning capability of the branch predictor, thereby improving the prediction accuracy of memory dependency prediction. This is suitable for modern high-performance, out-of-order execution processors with decoupled front-end architectures. Attached Figure Description

[0077] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0078] Figure 1 A partial structural schematic diagram of the processor architecture in some embodiments of this specification is shown;

[0079] Figure 2 Flowcharts of memory dependency prediction methods based on branch predictors in some embodiments of this specification are shown;

[0080] Figure 3 It shows Figure 2 The flowchart shown illustrates the method for determining the target load instruction in the prediction block.

[0081] Figure 4 It shows Figure 2 The flowchart shown illustrates the method of predicting the memory dependency information of the target load instruction based on the global branch history information of the branch direction predictor.

[0082] Figure 5 This specification shows a schematic diagram illustrating the contents of a BTB entry in an exemplary embodiment.

[0083] Figure 6 This specification shows a schematic diagram illustrating the contents of an MDDB entry in an exemplary embodiment.

[0084] Figure 7 This diagram illustrates the correspondence between the MDP bit array and the prediction block in the instruction fetch queue in an exemplary embodiment of this specification.

[0085] Figure 8 This specification shows a block diagram of a memory dependency prediction apparatus based on a branch predictor in some embodiments;

[0086] Figure 9 A structural block diagram of a computer device in some embodiments of this specification is shown.

[0087] [Explanation of Labels in the Attached Image]

[0088] 81. Select module;

[0089] 82. Determine the module;

[0090] 83. Prediction module;

[0091] 902. Computer equipment;

[0092] 904, Processor;

[0093] 906. Memory;

[0094] 908. Drive mechanism;

[0095] 910. Input / output interfaces;

[0096] 912. Input devices;

[0097] 914. Output devices;

[0098] 916. Presentation equipment;

[0099] 918. Graphical User Interface;

[0100] 920. Network interface;

[0101] 922. Communication link;

[0102] 924. Communication bus. Detailed Implementation

[0103] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this specification.

[0104] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in the embodiments of this specification are all information and data authorized and agreed upon by the user and fully authorized by all parties. That is, the acquisition, transmission, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations.

[0105] Memory operations in a processor can include load operations (load instructions) and store operations (store instructions). In a program, when a load instruction depends on data provided by a store instruction, the load instruction is said to have a memory dependency. In this scenario, if the load instruction executes before the store instruction it depends on completes its write operation, the load instruction will read incorrect data. Therefore, for processors using out-of-order execution, memory dependency prediction (MDP) is required before issuing the load instruction.

[0106] Processors typically resolve control dependency issues using branch predictors. For example, in predicting conditional branch instructions, the core of branch prediction is predicting the branch direction (jump or no jump) and the target address of the jump in the instruction stream. In traditional technologies, branch prediction and memory dependency prediction are implemented using separate predictors; this leads to problems such as high hardware resource consumption, large area overhead, and low prediction accuracy in processors.

[0107] In view of this, embodiments of this application provide a memory dependency prediction scheme based on a branch predictor to improve the prediction accuracy and reduce the cost of memory dependency prediction. Overall, embodiments of this application implement memory dependency prediction by reusing a branch predictor, allowing the branch predictor to retain its original branch prediction function while also possessing memory dependency prediction capabilities. This means that both branch prediction and memory dependency prediction functions are implemented using a single hardware setup, thereby reducing hardware resources and processor area, and lowering the cost of memory dependency prediction. Furthermore, embodiments of this application utilize the global branch history information of the branch predictor to predict the memory dependency information of load instructions, inheriting the high-precision learning capability of the branch predictor, thus further improving the prediction accuracy of memory dependency prediction. This approach is suitable for modern high-performance processors with out-of-order execution and decoupled front-end architectures.

[0108] The branch predictor reused in the embodiments of this application may include: a branch target buffer (BTB) and a branch direction predictor (i.e., a branch jump predictor) that can perform direct branch prediction based on global branch history information, and other branch prediction components. In some embodiments of this application, the branch direction predictor may include, but is not limited to: a tagged geometric history length branch predictor (TAGE), a hash-aware predictor, a global history branch predictor (Gshare), etc.

[0109] In some embodiments of this application, the reuse of TAGE and BTB will be used as examples for description and illustration. However, such description and illustration are merely exemplary and should not be construed as the sole limitation on the embodiments of this application. In other embodiments of this application, any suitable branch predictor that can achieve the purpose of this application can be reused as needed.

[0110] Figure 1 The diagram shows partial structural schematics of the processor architecture in some embodiments of this application. In these embodiments, memory dependency prediction functionality can be achieved by reusing some components of the branch predictor (e.g., BTB, TAGE, and main predictor) in the processor architecture. Figure 1 In the branch predictor shown, ITTAGE (Indirect Target Tagged GEometric length predictor) is used for branch prediction of indirect branch instructions. Unlike direct branch prediction which has only one target address, indirect branch prediction has multiple target addresses. Since ITTAGE is an original component of the branch predictor and this application does not involve reusing ITTAGE to achieve memory dependency prediction, there is no need to explain it in detail.

[0111] In addition, Figure 1 In the branch predictor shown, PC+4 represents the current value of the program counter (PC) incremented by 4, indicating a method of address calculation that skips the next instruction and directly executes the instruction after that, primarily used to implement program jumps. Furthermore, in... Figure 1In this context, "Flush PC" means to clear the PC (Program Counter). For example, when an interrupt, exception, branch instruction prediction error, or nuke event occurs, the PC needs to be cleared and the backend sends the Next PC value. "Next PC Mux for BP" means to introduce the next PC value for branch prediction. "Next PC Mux for Fetch" means to introduce the next PC value for instruction fetch.

[0112] I. Memory Dependency Prediction

[0113] (I) TAGE

[0114] The core idea of ​​TAGE is to use multiple prediction tables based on global historical records of different lengths, and automatically select the most suitable (longest and matching) historical length for branch direction prediction through a tag matching mechanism. The entries or items in the prediction tables of TAGE (hereinafter referred to as TAGE entries or TAGE items) can include the following:

[0115] Tag: Generated from the Global History Register (GHR) and the instruction PC hash (i.e., address hash); Tag is the index for querying TAGE entries. When viewing a TAGE, only TAGE entries with the same Tag are considered. The GHR is a shift register used to record recent branch jump results. Different prediction tables require different bit values ​​in the GHR to calculate the index of the corresponding TAGE table (i.e., TAGE prediction table or prediction table).

[0116] Useful: This value is typically 2 bits. It is incremented when a branch prediction is correct to indicate that the prediction result is useful. Therefore, the Useful value can be called a useful value. When a valid TAGE entry needs to be replaced, the TAGE entry with a Useful value of 0 is preferred for replacement, that is, the least useful TAGE entry is replaced first.

[0117] Confidence Counter: A saturation counter, typically 3 bits, used to predict whether a branch instruction will jump. When updating the TAGE entry, if the branch instruction jumps, the corresponding counter value is increased by 1; otherwise, it is decreased by 1. During prediction, if the counter value is greater than a branch jump threshold (e.g., 3), a jump is predicted; otherwise, no jump is predicted.

[0118] To achieve MDP prediction, in some embodiments of this application, the TAGE entry has been expanded, and the expanded TAGE entry may include:

[0119] Tag: No change, generated by the PC hash of GHR and load instructions.

[0120] Useful: In the newly added MDP prediction domain, it is used to specify which store distance in the corresponding BTB item is used; where store distance represents the number of store instructions that a load instruction depends on. The larger the store distance, the more store instructions the load instruction depends on.

[0121] Confidence Counter: This remains a saturation counter, used for MDP prediction in the newly added MDP prediction domain. During updates, if a nuke event occurs for the corresponding load, the counter value is incremented by 1; otherwise, it is decremented by 1. During prediction, if the counter value is greater than the MDP threshold, it is predicted as having a memory dependency; otherwise, it is predicted as having no memory dependency. In some embodiments of this application, the MDP threshold can reuse the threshold for the aforementioned branch jump prediction, or it can be customized. A nuke event refers to: a load instruction that requires memory dependency prediction receiving erroneous data before waiting for the dependent store instruction to execute, resulting in the data loaded by the load instruction being flushed.

[0122] MDP: This is a newly added field, consisting of 1 bit (or more bits), used to identify whether this TAGE entry is used in the MDP. When the MDP field value is 1, it indicates that this TAGE entry is used in the MDP; when the MDP field value is 0, it indicates that this TAGE entry is not used in the MDP. When it is necessary to select a TAGE entry for replacement, for a TAGE entry used in the MDP, its count value can be viewed, and the TAGE entry with a value of 0 can be selected for replacement first.

[0123] (II) BTB

[0124] The Branch Predictor (BTB) stores information such as the instruction type, address, and target address of known branch instructions. The branch predictor combines the BTB with the branch direction predictor to predict which branch instruction will be taken (taken) or not taken (not taken), and its target address. In summary, the Branch Predictor (TAGE) predicts whether a branch instruction will jump, and the BTB determines the target address. A BTB entry can include the following:

[0125] Offset: The offset value identifies the relative position of the branch instruction to the instruction block header, that is, the offset of the branch instruction's address within the instruction block. The branch predictor typically predicts all known branch instructions within an instruction block, and different processors define this instruction block differently. For example, for a 32b / 64b instruction block, offset requires 5 / 6 bits to specify any one of these bytes.

[0126] Type: Represents the type of branch instruction, such as conditional, direct, indirect, call / return, etc. For example, a 3-bit type field can represent 8 different types of instructions.

[0127] Target_addr: Represents the target address for the jump. Modern high-performance processors often use 32-bit / 64-bit virtual addresses, so the size of this field can be between 32-bit and 64-bit.

[0128] To achieve MDP prediction, in some embodiments of this application, the BTB entries (or BTB terms) are expanded, and the expanded BTB entries may include:

[0129] Offset: Still represents the offset of the instruction address of a branch instruction (such as a load instruction) within the instruction block.

[0130] Type: Indicates the type of branch instruction. If there are unused values ​​in the current Type, there is no need to increase its bit width; redefine the value to represent the load type, that is, add the load type to the original instruction type. If all values ​​in the current Type are already used, one bit can be added to Type to represent the load type.

[0131] Target_addr: Since the load instruction does not have a jump address, in the MDP field, the target_addr field can be defined as the number of store instructions that the load instruction depends on; that is, in the MDP field, target_addr is defined as storedistance. Furthermore, due to different runtime instruction branch paths, the same load instruction depends on different store instructions on different branch paths, and has different store distances. In this embodiment, the target_addr field is allowed to support multiple store distances of different lengths under the load type, as well as a 1-bit validity bit to indicate whether the corresponding store distance is used. Additionally, the useful field of the TAGE entry is used to specify whether using a certain store distance from the corresponding BTB entry is useful.

[0132] In some embodiments of this application, the store instruction upon which the load instruction depends can be retrieved from the store queue of the memory sequential buffer (MOB). Specifically, in the value of store distance, storedistance = 2. d-1 The term 'd' has a special meaning (representing the number of bits allocated for the store distance), indicating that a load instruction needs to wait for the store instructions it depends on according to a preset strategy. In one embodiment of this application, the preset strategy may be: the load instruction waits for all the store instructions it depends on to complete address processing before being issued; in another embodiment of this application, the preset strategy may be: the load instruction waits for a fixed number of store instructions preceding the target load instruction to complete address processing before being issued; in yet another embodiment of this application, the preset strategy may be: adding a waiting time window and issuing the load instruction after the waiting time window expires.

[0133] In some embodiments of this application, if a load instruction has more than the number of store distances allowed by the BTB term, then the subsequent prediction of that load is forced to have a store distance of 2. d-1 This is to prevent a nuke event from occurring after the load is executed. In some embodiments of this application, this forced operation can be implemented as follows: when updating the BTB item, if all distance fields are used and all are different from the new distance, then all distances of the BTB item are set to 2. d-1 The saturation counter (ctr) of the TAGE item to be updated can be set to 0, that is, pointing to the first distance field (e.g. Figure 5 dist_1 in the middle.

[0134] (III) Fetch Queue

[0135] like Figure 1As shown in some embodiments of this application, in order to enable the MDP prediction to support the front-end decoupled architecture of the processor, a fetch queue located between the branch predictor and the fetch unit can also be used in some embodiments of this application. The fetch queue is a first-in-first-out (FIFO) queue used to store prediction blocks (PBs) of the branch predictor's prediction results. The latter will be fetched by the fetch pipeline, and the fetch unit can obtain the corresponding instruction data from the instruction cache according to the starting address provided by the prediction block. A PB can contain multiple branch instructions and their branch prediction results; the branch prediction result can start from the target address of the previous branch prediction jump, or a non-jump sequential address, and end with the jump branch instruction predicted in this cycle or the boundary conditions defined by the processor (such as PB length, 32B / 64B alignment, etc.). The address of the next sequential instruction of the PB or the jump address of the predicted jump branch instruction will become the starting address of the PB in the next clock cycle.

[0136] The advantages of using a Fetch Queue are:

[0137] (1) The branch predictor can provide the initial address for the next prediction on its own, without relying on the instruction fetch unit or the decoding unit. Therefore, it can perform a branch prediction once every clock cycle, instead of only once every N clock cycles.

[0138] (2) Implement instruction prefetching: For multiple prediction blocks cached in the Fetch Queue, when the oldest prediction block stalls for some reason, such as a cache miss or a backend stall, the instruction fetch unit can detect whether other prediction blocks in the Fetch Queue are in the instruction cache (IC). If not, it can send an instruction prefetch request to the lower-level cache in advance. In this way, the number of IC misses can be greatly reduced and processor performance can be improved.

[0139] In some embodiments of this application, in order to support MDP, each Fetch queue item may be added with an MDP bit array, the number of bits of which is the maximum number of instructions in a prediction block, and each bit corresponds to one or more bytes (determined by the instruction set; for example, x86 is a complex instruction set, and each byte may be the start address of an instruction, so the MDP bit needs to correspond to one byte; while ARMv8 / v9 instructions are fixed at 4 bytes, so each MDP bit corresponds to 4 bytes).

[0140] For example, such as Figure 7 As shown, a prediction block (such as...) Figure 7 PB1, PB2, etc. in the MDP bit array correspond to one MDP bit array (e.g. Figure 7 (e.g., a1, a2, etc.). In an MDP bit array, if a bit is 1, it means that the load instruction starting at that position must wait for all its dependent store instructions (e.g., store distance = 2). d-1 If one bit is 0, it could be one of the following situations:

[0141] 1) The instruction at this location is not a load instruction;

[0142] 2) The instruction at this location is a load instruction, but it has no memory dependency;

[0143] 3) This load instruction has a memory dependency, but its store distance is not equal to 2. d-1 At this point, the memory dependency information for the load instruction needs to be provided through the Memory Dependence Distance Buffer (MDDB).

[0144] Furthermore, in some embodiments of this application, the MDP bit array may be passed to the instruction decoding stage and used by the decoder to set the correct memory dependency state for the load instruction.

[0145] In some embodiments of this specification, when a memory dependency is confirmed for a load instruction, the MDP bit value corresponding to all bytes between the instruction address of the load instruction and its preceding branch instruction can be modified to 1 in the prediction block. This maps the MDP bit value to the address range, enabling a single prediction to mark the dependency relationship of multiple load instructions within the Prediction Block. In this way, MDP prediction for multiple load instructions can be performed in the same clock cycle, thereby improving the prediction bandwidth for memory dependencies and resulting in a greater improvement in processor performance. Of course, to assist in achieving this objective, among the multiple branch instructions contained in the prediction block, only the last branch instruction uses the actual branch prediction direction, while the remaining branch instructions are forced to predict no jumps.

[0146] (iv) MDDB

[0147] like Figure 1 As shown in some embodiments of this application, in order to save the MD prediction results, an MDDB can also be added. The MDDB is also a FIFO queue used to store the store distance corresponding to the load with memory dependency (store distance ≠ 2). d-1 (Store distance). Its lifecycle consists of inserting one or more new MDDB entries after branch prediction ends, and deleting them during decoding after they are queried and matched with the corresponding load instruction. Figure 6 As shown, an MDDB entry can include an address hash (PC hash) and its corresponding distance (i.e., store distance). Because MDDB entries have a short lifespan, to save space, the full PC of the MDP load instruction is not used; instead, its hash value can be used. The length of the hash value is determined by the specific implementation.

[0148] In some embodiments of this application, the number of items in the MDDB can also be determined by the specific implementation to ensure that there are always free MDDB items available for the branch predictor in most cases. If the MDDB is full when a branch predictor needs to insert a new MDDB item, either of the following two processing methods can be selected:

[0149] (1) Pause the branch prediction pipeline and continue when there are available MDDB items.

[0150] (2) Instead of interrupting the branch prediction pipeline, assume that the store distance of the load is 0 and set the corresponding value of the MDPbit array.

[0151] Furthermore, some processors may encounter situations where multiple MDP loads within a prediction block need to be inserted into the MDDB within the same clock cycle. If the MDDB is constructed using flip-flops, it allows for simultaneous modification of multiple data items. If the MDDB is composed of SRAM, in an architecture with selectable bank interleaving, each SRAM bank allows for simultaneous read and write operations. In this case, the maximum number of reads / writes allowed for the MDDB is the number of banks. If the number of MDP loads in a prediction block exceeds the number of MDDB banks, the storedistance of subsequent MDP loads can be forced to 0, and their corresponding MDP bit arrays can be configured. Here, "bank" refers to the number of memory banks in memory.

[0152] In other embodiments of this application, the predicted memory dependency information may also be stored in the BTB; in this scenario, it is not necessary to add a new MDDB.

[0153] (V) Main Predictor

[0154] like Figure 1 As shown, the Main Predictor integrates information from various sub-modules, such as BTB and TAGE, to predict whether to jump, which branch instruction needs to jump, and what the jump address is. Based on the above information, it determines the end address of the current prediction block and the start address of the next prediction block.

[0155] In some embodiments of this application, the Main predictor may add the following functional logic for MDP:

[0156] 1. Initialize the MDP bitarray of the current prediction block (i.e., the currently selected prediction block) to all zeros.

[0157] 2. Filter out BTB items of type Load from BTB type and match them with TAGE items whose MDP field is 1.

[0158] 3. For the load instruction matched in step 2, check if its PC is within the starting address of the current prediction block. If it is not within the range, ignore it; otherwise, proceed to the next step.

[0159] 4. If the store distance value of the selected BTB item in TAGE is not 0, and MDDB can be inserted, then allocate an MDDB item for this MDPload and update its content; otherwise, set the bit corresponding to the PC of this MDP load in the MDP bit array. The conditions for inserting an MDDB are as follows:

[0160] 1) There are free entries in MDDB.

[0161] 2) The number of MDP loads being processed together in the current prediction block is within the allowable range.

[0162] 5. After completing the processing of all MDP loads in the current prediction block, write the MDP bit array into the corresponding item of the current prediction block in the Fetch Queue.

[0163] (vi) Instruction Decoding

[0164] The instruction decoding stage transforms an instruction into a micro-operation (Uop) that contains more microarchitectural information. To support MDP, a Uop can have the following fields added:

[0165] MDP valid: 1 bit, when it is 1, it means that the corresponding Uop (must be load) requires MDP.

[0166] Store distance: Same as store distance in BTB item. When it is 0, it means that the uop must wait for all the store instructions it depends on to obtain the address before it can be issued; otherwise, the uop must wait for the store instruction with the specified distance to obtain the address before it can be issued.

[0167] After the decoding module recognizes the load instruction, it can simultaneously view the corresponding MDP bit array and MDDB, including the following cases:

[0168] (1) The corresponding MDP bit = 0 and the oldest MDDB item PC hash is equal to the load PC has: This load does not need an MDP, so set its MDP valid to 0;

[0169] (2) Corresponding MDP bit=1: This Load requires MDP, set its MDP_valid to 1, store distance=0;

[0170] (3) The corresponding MDP bit = 0, and the PC hash of the oldest MDDB item is equal to the load PC hash: the load needs MDP, set its MDP valid to 1, store distance to the value of the MDDB item, and release the MDDB item.

[0171] Zero-latency dynamic dependency injection can be achieved by dynamically marking load uops during the decoding phase. In other embodiments, injection can be performed at other CPU pipeline stages, such as instruction fetch, renaming, or instruction issue stages.

[0172] II. Memory Dependency Updates

[0173] (I) BTB and TAGE Updates

[0174] BTB and TAGE, which support memory dependency prediction, need to be continuously updated to maintain their high prediction accuracy. In some embodiments of this application, memory dependency updates take the following forms:

[0175] 1. Updates when Nuke occurs

[0176] A Nuke load may occur if MDP is present or absent: BTB / TAGE needs to be updated.

[0177] (1) BTB: Use load PC to search for BTB.

[0178] If a BTB (Best-Trust Item) is not hit, a free item is selected or a replacement strategy is used to select a BTB item to store the memory dependency information, and this item is set to v1 = 1, where dist_1 is the current store distance. The replacement strategy could include, for example, the Least Recently Used (PLRU) algorithm.

[0179] If a BTB item is hit, and the current store distance already exists in that item, then save the index A of that field (e.g., ...). Figure 5 If all distance fields are used, the BTB item (e.g., V1, V2, etc.) is not modified; otherwise, an additional distance field is added and its position A is recorded. If all distance fields are used, all field values ​​of the BTB item are set to 0 (i.e., the load instruction depends on all previous store instructions), and A is set to 0.

[0180] (2) TAGE table:

[0181] First, select a TAGE table with the same or similar history length (i.e., history length less than or equal to B) based on the number of branch instructions B between the load and the corresponding store.

[0182] Using the corresponding historical length of this table, extract the current GHR (i.e., extract the branch history) and combine it with load PC to generate an index to index this table.

[0183] If the table is not hit, a free item is selected or a replacement strategy such as PLRU is used to select an item to store memory dependency information. The item's MDP field is initialized to 1, ctr is set to the default initial value (e.g., MDP threshold + 1), and Useful is set to A (i.e., the BTB item's store distance field index).

[0184] If the table is hit, the ctr value of that item is incremented by 1. Here, ctr is the count value of the saturation counter.

[0185] 2. Updates during the Retire phase of the instruction.

[0186] (1) When retiring, the load uop with MDP valid=1 does not find any memory dependency relationship with the store instruction at the store distance. Based on the store distance length, the number of branch instructions is deduced, thereby indexing the TAGE table item that makes the MDP prediction. If the item ctr>0, the ctr value of the item is reduced by 1.

[0187] (2) When retiring, the load uop with MDP valid=1 finds that there is a memory dependency relationship with the store instruction at the store distance. Based on the length of the store distance, the number of branch instructions is deduced, thereby indexing the TAGE table item that makes the MDP prediction. If the ctr of the item is less than the maximum value, the ctr value of the item is incremented by 1.

[0188] (II) TAGE Replacement Strategy

[0189] In some embodiments of this application, the replacement strategy for TAGE changes when MDP is supported:

[0190] 1. When the MDP field of the TAGE item is 0, the same as the original TAGE scheme is used to select the replacement item using the useful field of the TAGE item, that is, the item with the smaller usefulness is selected for replacement.

[0191] 2. When the MDP field of the TAGE item is 1, since the useful field is used to select store_distance, the item with the smaller ctr is preferred to be used instead.

[0192] 3. Since the useful and ctr fields often have different lengths, when choosing from multiple TAGE items with both MDP=0 and MDP=1, you can first select the item with the lowest value from each group, and then decide whether to replace it with the item with the lowest useful or ctr value based on certain rules. For example, a simple rule could favor branch instructions, meaning that branch instructions always prioritize replacing MDP TAGE items.

[0193] (III) RBBA

[0194] In some embodiments of this application, the MDP information is updated upon load retirement. This update requires knowing the number of branch instructions between the load instruction and the dependent store instruction. To achieve this, a Retire Branch Bit Array (RBBA) can be maintained. It is a FIFO queue where each most recently retired instruction has a corresponding bit; if the corresponding instruction is a branch instruction, its value is 1, otherwise it is 0. The number of bits in the RBBA is the maximum store distance value supported by an implementation. Therefore, the number of 1s in the most recent store distance bit in the RBBA is the number of branch instructions between the load instruction and the dependent store instruction.

[0195] III. Optimized Design

[0196] Reusing BTB and TAGE for MDP can improve the utilization efficiency of hardware resources, but in some cases, it can also increase the probability of conflict misses between these two components. Therefore, one implementation scheme can adopt a set associative mapping structure for BTB and each TAGE table; and use the maximum set associativity as timing permits to minimize their conflict misses.

[0197] Based on the processor architecture described above, this specification provides a memory dependency prediction method based on a branch predictor, which can be applied to the branch predictor (main predictor) side. (Refer to...) Figure 2 As shown in some embodiments of this specification, the memory dependency prediction method based on the branch predictor may include the following steps:

[0198] Step 201: Select a prediction block from the instruction fetch queue.

[0199] Step 202: Determine the target load instruction in the prediction block.

[0200] Step 203: Predict the memory dependency information of the target load instruction based on the global branch history information of the branch direction predictor.

[0201] This application embodiment achieves memory dependency prediction by reusing the branch predictor. This allows the branch predictor to retain its original branch prediction function while also possessing memory dependency prediction capabilities. In other words, a single hardware implementation achieves both branch prediction and memory dependency prediction, thereby reducing hardware resources and processor area, and lowering the cost of memory dependency prediction. Furthermore, this application embodiment utilizes the global branch history information of the branch predictor to predict the memory dependency information of the load instruction, inheriting the high-precision learning capability of the branch predictor, thus further improving the prediction accuracy of memory dependency prediction. This makes it suitable for modern high-performance, out-of-order execution processors with decoupled front-end architectures.

[0202] In some embodiments of this application, since the fetch queue is a FIFO queue, a prediction block can be selected from the head of the fetch queue each time.

[0203] refer to Figure 3 As shown, in some embodiments of this application, determining the target load instruction in the prediction block based on the branch target buffer may include the following steps:

[0204] Step 301: Select a Branch Target Buffer (BTB) entry from the prediction block.

[0205] Step 302: Confirm whether the instruction type corresponding to the selected BTB entry is a load instruction. If it is a load instruction, proceed to step 303; otherwise, jump to step 301, ignore the BTB entry, and select the next BTB entry from the prediction block. Since memory dependency prediction is for load instructions, there is no need to perform memory dependency prediction when the instruction is not a load instruction.

[0206] Step 303: Confirm whether the load instruction is an MDP load instruction. If the load instruction is an MDP load instruction, proceed to step 304; otherwise, proceed to step 301.

[0207] Among them, the MDP load instruction represents a load instruction that requires memory dependency prediction.

[0208] In some embodiments of this application, the memory dependency prediction MDP field identifier in the entry corresponding to the load instruction in the branch direction predictor is used to determine whether the load instruction is an MDP load instruction; when the value of the MDP field identifier is 1, it indicates that the load instruction needs to perform memory dependency prediction; when the value of the MDP field identifier is 0, it indicates that the load instruction does not need to perform memory dependency prediction.

[0209] Step 304: Confirm whether the instruction address of the MDP load instruction is within the starting address of the prediction block. If it is within the starting address of the prediction block, proceed to step 305; otherwise, jump to step 301.

[0210] Step 305: Determine the MDP load instruction as the target load instruction.

[0211] refer to Figure 4 As shown, in some embodiments of this application, predicting the memory dependency information of the target load instruction based on the global branch history information of the branch direction predictor may include the following steps:

[0212] Step 401: Based on the useful value of the entry corresponding to the target load instruction in the branch direction predictor, select a storage distance as the target storage distance from multiple storage distances of the BTB entry corresponding to the target load instruction.

[0213] In some embodiments of this application, each of the store distances represents the number of store instructions that the target load instruction depends on on a specific branch history path.

[0214] Step 402: Confirm whether the count value of the saturation counter corresponding to the target storage distance is greater than the threshold. If the count value of the saturation counter corresponding to the target storage distance is greater than the threshold, proceed to step 403; otherwise, proceed to step 404.

[0215] Step 403: Confirm that the target load instruction has a memory dependency, and that the storage distance of its memory dependency is the target storage distance.

[0216] Step 404: Confirm that the target load instruction has no memory dependency.

[0217] In some embodiments of the memory dependency prediction method of this application, after predicting the memory dependency information of the target load instruction based on the global branch history information of the branch predictor, the method further includes: saving the memory dependency information of the target load instruction.

[0218] In some embodiments of the memory dependency prediction method of this application, storing the memory dependency information of the target load instruction includes:

[0219] (1) If the target load instruction has a memory dependency, then determine whether the target storage distance is a boundary value; the boundary value includes 0 and an upper limit value (e.g., 2). d-1 ).

[0220] (2) If the target storage distance is not a boundary value, check whether the insertion conditions are met in the memory-dependent distance buffer (MDDB).

[0221] (3) If the insertion condition is met, the memory dependency prediction result of the target load instruction is inserted into the MDDB. The insertion condition includes at least one of the following:

[0222] a. There are idle entries in MDDB;

[0223] b. The number of MDP load instructions processed together in the prediction block does not exceed the specified range.

[0224] (4) If the target load instruction has a memory dependency and the corresponding storage distance is the upper limit, then in the MDP bit array corresponding to the prediction block, the MDP bit value corresponding to the target load instruction is modified to 1; the MDP bit value of 1 indicates that the target load instruction needs to wait for the store instruction it depends on according to the preset strategy.

[0225] (5) If the target load instruction has no memory dependency, or if the target load instruction has a memory dependency and the corresponding storage distance is zero, or if the target load instruction has a memory dependency and the corresponding storage distance is not a boundary value, then in the MDP bit array corresponding to the prediction block, the MDP bit value corresponding to the target load instruction is maintained at 0 (since the MDP bit array is set to 0 during initialization, maintaining it here means no modification is required).

[0226] In some embodiments of this application, the memory dependency prediction method may further include:

[0227] After the memory dependency prediction processing of all MDP load instructions in the same prediction block is completed, the MDP bit value array corresponding to the prediction block is written into the instruction fetch queue.

[0228] In some embodiments of this application, the memory dependency prediction method may further include:

[0229] When a memory dependency is confirmed for a load instruction, the MDP bit value corresponding to all bytes between the instruction address of that load instruction and its preceding branch instruction can be modified to 1 in the prediction block. This maps the MDP bit value to the address range, allowing a single prediction to mark the dependencies of multiple load instructions within the prediction block. In this way, the MDP of multiple load instructions can be predicted in the same clock cycle, thereby increasing prediction bandwidth and resulting in a greater improvement in processor performance. Of course, to facilitate this, the prediction block contains multiple branch instructions, with only the last branch instruction using the actual branch prediction direction, while the remaining branch instructions are forced to predict no jumps.

[0230] In some embodiments of the memory dependency prediction method of this application, the preset strategy includes any one of the following:

[0231] Launch after all store instructions preceding the target load instruction have completed address processing;

[0232] Launch after a fixed number of store instructions preceding the target load instruction have completed address processing;

[0233] Increase the waiting time window and launch after the waiting time window times out.

[0234] In some embodiments of this application, the memory dependency prediction method may further include:

[0235] When converting a load instruction in the fetch queue into a micro-operation at a specified stage, an MDP available flag and storage distance are added to the converted micro-operation based on the MDP bit array and MDDB corresponding to the load instruction; the specified stage includes any one of the following: decoding stage, fetch stage, issue stage, and renaming stage.

[0236] In some embodiments of this application, the memory dependency prediction method may further include:

[0237] Dynamically update the BTB and branch direction predictor.

[0238] In the memory dependency prediction method of some embodiments of this application, the dynamic updating of BTB includes:

[0239] When a nuke event occurs after a load instruction is executed, the BTB is searched using the instruction address of that load instruction;

[0240] If no corresponding BTB entry is found, a free BTB entry is selected from the BTBs or a non-free BTB entry is selected according to the first replacement strategy, and the memory dependency information is stored.

[0241] If the corresponding BTB entry is hit and the memory distance of the load instruction does not exist in the BTB entry, then the memory dependency information of the load instruction is sequentially inserted into the BTB entry.

[0242] If the corresponding BTB entry is hit and the storage distance of the load instruction exists in the BTB entry, then the BTB entry remains unchanged;

[0243] If the corresponding BTB entry is hit and there are no free BTB entries in the BTB, then clear all BTB entries in the BTB.

[0244] In some embodiments of the memory dependency prediction method of this application, the dynamically updated branch direction predictor includes:

[0245] When a nuke event occurs after a load instruction is executed, a target prediction table whose historical length matches the memory distance of the load instruction is selected from multiple prediction tables of the branch direction predictor.

[0246] Based on the historical length of the target prediction table, the history is extracted from the global history register, and the extracted history is hashed with the instruction address of the load instruction to generate an index of the target prediction table. The target prediction table is then searched using the index.

[0247] If no corresponding entry is found, a free entry is selected from the target prediction table or a non-free entry is selected according to the second replacement strategy, and the memory dependency information is stored.

[0248] If a corresponding entry is hit, the value of the saturation counter corresponding to that entry is incremented by 1.

[0249] In some embodiments of the memory dependency prediction method of this application, the dynamically updated branch direction predictor further includes:

[0250] During the instruction retirement phase, if no memory dependency is found between the micro-operation with the MDP available flag set to 1 and the store instruction at the corresponding memory distance, the number of branch instructions is deduced based on the memory distance to locate the corresponding entry in the prediction table, and the value of the saturation counter corresponding to the entry is decremented by 1.

[0251] During the instruction retirement phase, if a micro-operation with the MDP flag set to 1 finds a memory dependency relationship with the store instruction at the corresponding memory distance, the number of branch instructions is deduced based on the memory distance to locate the corresponding entry in the prediction table, and the value of the saturation counter corresponding to that entry is incremented by 1.

[0252] In some embodiments of the memory dependency prediction method of this application, the first replacement strategy includes: the least recently used algorithm.

[0253] In the memory dependency prediction method of some embodiments of this application, the second replacement strategy includes:

[0254] If the MDP field of the load instruction is 0, then the memory dependency information in the entry corresponding to the smallest useful value in the target prediction table is replaced with the memory dependency information of the load instruction.

[0255] If the MDP field of the load instruction is 1, then the memory dependency information in the entry corresponding to the smallest saturation count value in the target prediction table is replaced with the memory dependency information of the load instruction.

[0256] In some embodiments of this application, the memory dependency prediction method may further include:

[0257] Confirm whether the most recent exit instruction is a branch instruction;

[0258] If it is a branch instruction, then modify the bit value corresponding to the branch instruction in the branch bit value array to 1;

[0259] If it is not a branch instruction, then the bit value corresponding to the branch instruction in the branch bit value array is kept at 0;

[0260] The length of the exit branch bit value array is the upper limit of the storage distance; the number of bits with a value of 1 in the nearest storage distance bit of the exit branch bit value array corresponds to the number of branch instructions between the load instruction and the dependent store instruction.

[0261] In some embodiments of this application, the memory dependency prediction method may further include:

[0262] The BTB and the branch direction predictor adopt a group-connected mapping structure.

[0263] In some embodiments of this application, the branch direction predictor includes any one of the following:

[0264] Tag-based geometric history length branch predictor (TAGE);

[0265] Hashed Perceptron;

[0266] Global Historical Branch Predictor (Gshare).

[0267] Although the process described above includes multiple operations that occur in a specific order, it should be clearly understood that these processes may include more or fewer operations, which may be executed sequentially or in parallel (e.g., using parallel processors or a multithreaded environment).

[0268] Corresponding to the above-described memory dependency prediction method based on branch predictors, this specification also provides a memory dependency prediction device based on branch predictors, which can be configured on the main predictor of the aforementioned branch predictors. (Refer to...) Figure 8 As shown in some embodiments of this specification, a memory dependency prediction apparatus based on a branch predictor may include:

[0269] Selection module 81 is used to select a prediction block from the instruction fetch queue;

[0270] Determining module 82 is used to determine the target load instruction in the prediction block;

[0271] The prediction module 83 is used to predict the memory dependency information of the target load instruction based on the global branch history information of the branch direction predictor.

[0272] This specification also provides another processor architecture in which the above-described memory dependency prediction device is configured.

[0273] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware.

[0274] Embodiments of this specification also provide a computer device. For example... Figure 9As shown, in some embodiments of this specification, the computer device 902 may include one or more processors 904, such as one or more central processing units (CPUs) or graphics processing units (GPUs), each of which may implement one or more hardware threads. The computer device 902 may also include any memory 906 for storing information of any kind, such as code, settings, data, etc. In one specific embodiment, a computer program is stored on the memory 906 and can run on the processor 904. When the computer program is run by the processor 904, it can execute instructions of the memory dependency prediction method based on a branch predictor as described in any of the above embodiments. Without limitation, for example, the memory 906 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory may represent a fixed or removable component of the computer device 902. In one case, when the processor 904 executes associated instructions stored in any memory or combination of memories, the computer device 902 can perform any operation of the associated instructions. The computer device 902 also includes one or more drive mechanisms 908 for interacting with any memory, such as a hard disk drive mechanism, an optical disk drive mechanism, etc.

[0275] Computer device 902 may also include an input / output interface 910 (I / O) for receiving various inputs (via input device 912) and providing various outputs (via output device 914). A specific output mechanism may include a presentation device 916 and an associated graphical user interface 918 (GUI). In other embodiments, the input / output interface 910 (I / O), input device 912, and output device 914 may be omitted, and the device may function solely as a computer device within a network. Computer device 902 may also include one or more network interfaces 920 for exchanging data with other devices via one or more communication links 922. One or more communication buses 924 couple the components described above together.

[0276] Communication link 922 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 922 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0277] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), computer-readable storage media, and computer program products according to some embodiments of this specification. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processor to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processor, create a mechanism for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0278] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processor to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0279] These computer program instructions may also be loaded onto a computer or other programmable data processor, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0280] In a typical configuration, a computer device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0281] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0282] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by computer equipment. As defined in this specification, computer-readable media does not include transient media, such as modulated data signals and carrier waves.

[0283] Those skilled in the art will understand that the embodiments of this specification can be provided as methods, systems, or computer program products. Therefore, the embodiments of this specification can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, the embodiments of this specification can take the form of computer program products implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0284] The embodiments described in this specification can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. The embodiments of this specification can also be practiced in distributed computing environments where tasks are performed by remote processors connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0285] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0286] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0287] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this specification. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0288] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A memory dependency prediction method based on a branch predictor, characterized in that, include: Select the prediction block from the instruction fetch queue; Determine the target load instruction in the prediction block; The memory dependency information of the target load instruction is predicted based on the global branch history information of the branch direction predictor.

2. The memory dependency prediction method as described in claim 1, characterized in that, Determining the target load instruction in the prediction block includes: Select a branch target buffer (BTB) entry from the prediction block; Confirm that the instruction type corresponding to the selected BTB entry is a load instruction; If it is a load instruction, then the memory dependency prediction MDP field identifier in the corresponding entry of the load instruction in the branch direction predictor is used to confirm whether the load instruction is an MDP load instruction; the MDP load instruction represents a load instruction that needs to perform memory dependency prediction. If it is an MDP load instruction, then confirm whether the instruction address of the MDP load instruction is within the starting address of the prediction block; If it is located within the starting address of the prediction block, then the MDP load instruction is determined as the target load instruction.

3. The memory dependency prediction method as described in claim 1, characterized in that, The step of predicting the memory dependency information of the target load instruction based on the global branch history information of the branch direction predictor includes: Based on the useful value of the entry corresponding to the target load instruction in the branch direction predictor, a storage distance is selected as the target storage distance from multiple storage distances of the BTB entry corresponding to the target load instruction. Each storage distance represents the number of store instructions that the target load instruction depends on on a specific branch history path. Confirm whether the count value of the saturation counter corresponding to the target storage distance is greater than the threshold; If the count value of the saturation counter corresponding to the target storage distance is greater than the threshold, it is confirmed that the target load instruction has a memory dependency, and the storage distance of its memory dependency is the target storage distance.

4. The memory dependency prediction method as described in claim 3, characterized in that, After predicting the memory dependency information of the target load instruction based on the global branch history information of the branch predictor, the method further includes: Save the memory dependency information of the target load instruction.

5. The memory dependency prediction method as described in claim 4, characterized in that, The process of saving the memory dependency information of the target load instruction includes: If the target load instruction has a memory dependency, then determine whether the target storage distance is a boundary value; the boundary value includes zero and an upper limit value; If the target storage distance is not a boundary value, then check whether the insertion conditions are met in the memory-dependent distance buffer MDDB. If the insertion conditions are met, the memory dependency prediction result of the target load instruction is inserted into the MDDB.

6. The memory dependency prediction method as described in claim 5, characterized in that, The insertion conditions include at least one of the following: There are free entries in MDDB; The number of MDP load instructions processed together in the prediction block did not exceed the specified range.

7. The memory dependency prediction method as described in claim 5, characterized in that, The method of saving the memory dependency information of the target load instruction also includes: If the target load instruction has a memory dependency and the corresponding storage distance is the upper limit, then in the MDP bit value array corresponding to the prediction block, the MDP bit value corresponding to the target load instruction is modified to 1; the MDP bit value of 1 indicates that the target load instruction needs to wait for the store instruction it depends on according to a preset strategy. If the target load instruction has no memory dependency, or if the target load instruction has a memory dependency and the corresponding storage distance is zero, or if the target load instruction has a memory dependency and the corresponding storage distance is not a boundary value, then in the MDP bit value array corresponding to the prediction block, the MDP bit value corresponding to the target load instruction is maintained at 0.

8. The memory dependency prediction method as described in claim 7, characterized in that, The method further includes: After the memory dependency prediction processing of all MDP load instructions in the prediction block is completed, the MDP bit value array corresponding to the prediction block is written into the instruction fetch queue.

9. The memory dependency prediction method as described in claim 3, characterized in that, The method further includes: When it is confirmed that the target load instruction has a memory dependency, in the prediction block, the MDP bit value corresponding to all bytes between the instruction address of the target load instruction and its previous branch instruction is modified to 1; the MDP bit value of 1 indicates that the target load instruction needs to wait for the store instruction it depends on according to a preset strategy.

10. The memory dependency prediction method as described in claim 7 or 9, characterized in that, The preset strategy includes any one of the following: Launch after all store instructions preceding the target load instruction have completed address processing; Launch after a fixed number of store instructions preceding the target load instruction have completed address processing; Increase the waiting time window and launch after the waiting time window times out.

11. The memory dependency prediction method as described in claim 8, characterized in that, The method further includes: When converting a load instruction in the fetch queue into a micro-operation at a specified stage, an MDP available flag and storage distance are added to the converted micro-operation based on the MDP bit array and MDDB corresponding to the load instruction; the specified stage includes any one of the following: decoding stage, fetch stage, issue stage, and renaming stage.

12. The memory dependency prediction method as described in claim 1, characterized in that, The method further includes: Dynamically update the BTB and branch direction predictor.

13. The memory dependency prediction method as described in claim 12, characterized in that, The dynamic updating of BTB includes: When a nuke event occurs after a load instruction is executed, the BTB is searched using the instruction address of that load instruction; If no corresponding BTB entry is found, a free BTB entry is selected from the BTBs or a non-free BTB entry is selected according to the first replacement strategy, and the memory dependency information is stored. If the corresponding BTB entry is hit and the memory distance of the load instruction does not exist in the BTB entry, then the memory dependency information of the load instruction is sequentially inserted into the BTB entry. If the corresponding BTB entry is hit and the storage distance of the load instruction exists in the BTB entry, then the BTB entry remains unchanged; If the corresponding BTB entry is hit and there are no free BTB entries in the BTB, then clear all BTB entries in the BTB.

14. The memory dependency prediction method as described in claim 12, characterized in that, The dynamically updated branch direction predictor includes: When a nuke event occurs after a load instruction is executed, a target prediction table whose historical length matches the memory distance of the load instruction is selected from multiple prediction tables of the branch direction predictor. Based on the historical length of the target prediction table, the history is extracted from the global history register, and the extracted history is hashed with the instruction address of the load instruction to generate an index of the target prediction table. The target prediction table is then searched using the index. If no corresponding entry is found, a free entry is selected from the target prediction table or a non-free entry is selected according to the second replacement strategy, and the memory dependency information is stored. If a corresponding entry is hit, the value of the saturation counter corresponding to that entry is incremented by 1.

15. The memory dependency prediction method as described in claim 12, characterized in that, The dynamically updated branch direction predictor further includes: During the instruction retirement phase, if no memory dependency is found between the micro-operation with the MDP available flag set to 1 and the store instruction at the corresponding memory distance, the number of branch instructions is deduced based on the memory distance to locate the corresponding entry in the prediction table, and the value of the saturation counter corresponding to the entry is decremented by 1. During the instruction retirement phase, if a micro-operation with the MDP flag set to 1 finds a memory dependency relationship with the store instruction at the corresponding memory distance, the number of branch instructions is deduced based on the memory distance to locate the corresponding entry in the prediction table, and the value of the saturation counter corresponding to that entry is incremented by 1.

16. The memory dependency prediction method as described in claim 13, characterized in that, The first replacement strategy includes: the least recently used algorithm.

17. The memory dependency prediction method as described in claim 14, characterized in that, The second replacement strategy includes: If the MDP field of the load instruction is 0, then the memory dependency information in the entry corresponding to the smallest useful value in the target prediction table is replaced with the memory dependency information of the load instruction. If the MDP field of the load instruction is 1, then the memory dependency information in the entry corresponding to the smallest saturation count value in the target prediction table is replaced with the memory dependency information of the load instruction.

18. The memory dependency prediction method as described in claim 15, characterized in that, The method further includes: Confirm whether the most recent exit instruction is a branch instruction; If it is a branch instruction, then modify the bit value corresponding to the branch instruction in the branch bit value array to 1; If it is not a branch instruction, then the bit value corresponding to the branch instruction in the branch bit value array is kept at 0; The length of the exit branch bit value array is the upper limit of the storage distance; the number of bits with a value of 1 in the nearest storage distance bit of the exit branch bit value array corresponds to the number of branch instructions between the load instruction and the dependent store instruction.

19. The memory dependency prediction method as described in claim 12, characterized in that, The BTB and the branch direction predictor adopt a group-connected mapping structure.

20. The memory dependency prediction method as described in claim 1, characterized in that, The branch direction predictor includes any one of the following: Tag-based geometric history length branch predictor; Hash-aware predictor; Global historical branch predictor.

21. A memory dependency prediction device based on a branch predictor, characterized in that, include: The selection module is used to select a prediction block from the instruction fetch queue; The determination module is used to determine the target load instruction in the prediction block; The prediction module is used to predict the memory dependency information of the target load instruction based on the global branch history information of the branch direction predictor.

22. A processor architecture, characterized in that, The processor architecture is configured with the memory dependency prediction device as described in claim 21.

23. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, When the computer program is run by the processor, it executes the instructions of the method according to any one of claims 1-20.

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