Chip, chip testing system, method, and electronic device

Abstract

The application discloses a chip, a chip test system and method and electronic equipment, and relates to the technical field of chips. The chip comprises an input port, a deserializer circuit, a scan input circuit and a scan chain circuit. In the chip, each input end of the scan input circuit supports input of data through the same input port (after conversion by the deserializer circuit) to supply data required by testing to the scan chain circuit. Therefore, the chip only needs to provide one input port to support testing of any scan chain in the scan chain circuit, and the cost is low.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip, a chip testing system, a method, and an electronic device. Background Technology

[0002] In related technologies, chip tests are often performed through the chip's GPIO (General Purpose Input Output) ports.

[0003] Specifically, to perform testing on a specific scan chain within a chip's scan chain circuit, a pair of GPIO ports is required. One GPIO port serves as the chip's input port, directly connected to an input terminal of the chip's scan input circuit. The other GPIO port serves as the chip's output port, directly connected to an output terminal of the chip's scan output circuit. Correspondingly, the scan input circuit inputs data from the GPIO port into the scan chain, and the scan output circuit sends the data generated by this scan chain to the other GPIO port for output. This data can then be used to confirm whether the scan chain has any defects.

[0004] However, due to the complexity of the logic circuits within the chip, data input from one input terminal of the scan input circuit typically only supports transmission to a portion of the scan chain circuit. To enable testing of each scan chain within the scan chain circuit, each input terminal of the scan input circuit needs to be connected to a separate GPIO port. Correspondingly, each output terminal of the scan output circuit also needs to be connected to a separate GPIO port, resulting in high implementation costs. Summary of the Invention

[0005] This application provides a chip, a chip testing system, a method, and an electronic device. The technical solutions provided by this application are as follows:

[0006] According to one aspect of the embodiments of this application, a chip is provided, the chip comprising: an input port, a deserializer circuit, a scan input circuit, and a scan chain circuit;

[0007] The deserializer circuit has M first output terminals, and the scanning input circuit has M first input terminals, where M is an integer greater than 1;

[0008] The input port is connected to the input terminal of the deserializer circuit, and the i-th first output terminal among the M first output terminals is connected to the i-th first input terminal among the M first input terminals, where i is a positive integer less than or equal to M;

[0009] The scan chain circuit includes multiple scan chains, and the input end of the scan chain is connected to the output end of the scan input circuit.

[0010] According to one aspect of the embodiments of this application, a chip is provided, the chip including: a scan chain circuit, a scan output circuit, a serializer circuit, and an output port;

[0011] The scan output circuit has M second output terminals, and the serializer circuit has M second input terminals, where M is an integer greater than 1.

[0012] The scan chain circuit includes multiple scan chains, and the output end of the scan chain is connected to the input end of the scan output circuit;

[0013] The i-th second output terminal among the M second output terminals is connected to the i-th second input terminal among the M second input terminals, and the output terminal of the serializer circuit is connected to the output port, where i is a positive integer less than or equal to M.

[0014] According to one aspect of the embodiments of this application, a chip testing system is provided, the chip testing system including a chip and external logic circuitry, the chip including: an input port, a deserializer circuit, a scan input circuit, and a scan chain circuitry; the external logic circuitry is connected to the input port.

[0015] The deserializer circuit has M first output terminals, and the scanning input circuit has M first input terminals, where M is an integer greater than 1;

[0016] The input port is connected to the input terminal of the deserializer circuit, and the i-th first output terminal among the M first output terminals is connected to the i-th first input terminal among the M first input terminals, where i is a positive integer less than or equal to M;

[0017] The scan chain circuit includes multiple scan chains, and the input end of the scan chain is connected to the output end of the scan input circuit.

[0018] According to one aspect of the embodiments of this application, a chip testing system is provided, the chip testing system including a chip and an external logic circuit, the chip including: a scan chain circuit, a scan output circuit, a serializer circuit and an output port; the external logic circuit is connected to the output port;

[0019] The scan output circuit has M second output terminals, and the serializer circuit has M second input terminals, where M is an integer greater than 1.

[0020] The scan chain circuit includes multiple scan chains, and the output end of the scan chain is connected to the input end of the scan output circuit;

[0021] The i-th second output terminal among the M second output terminals is connected to the i-th second input terminal among the M second input terminals, and the output terminal of the serializer circuit is connected to the output port, where i is a positive integer less than or equal to M.

[0022] According to one aspect of the embodiments of this application, a chip testing method is provided. The chip includes: an input port, a deserializer circuit, a scan input circuit, and a scan chain circuit; the deserializer circuit has M first output terminals, and the scan input circuit has M first input terminals, where M is an integer greater than 1; the input port is connected to the input terminal of the deserializer circuit, and the i-th first output terminal of the M first output terminals is connected to the i-th first input terminal of the M first input terminals, where i is a positive integer less than or equal to M; the scan chain circuit includes multiple scan chains, and the input terminals of the scan chains are connected to the output terminals of the scan input circuit; the method includes:

[0023] The input port receives serial input signals;

[0024] The deserializer circuit outputs M first data in parallel according to the serial input signal;

[0025] The scan input circuit inputs the M first data to the scan chain circuit, wherein different first data among the M first data are input to different scan chains;

[0026] The scan chain circuit generates M second data based on the M first data, and the M second data are used to determine the test results for the chip.

[0027] According to one aspect of the embodiments of this application, a method for testing a chip is provided. The chip includes: a scan chain circuit, a scan output circuit, a serializer circuit, and an output port; the scan output circuit has M second output terminals, and the serializer circuit has M second input terminals, where M is an integer greater than 1; the scan chain circuit includes multiple scan chains, and the output terminals of the scan chains are connected to the input terminals of the scan output circuit; the i-th second output terminal of the M second output terminals is connected to the i-th second input terminal of the M second input terminals, and the output terminal of the serializer circuit is connected to the output port, where i is a positive integer less than or equal to M; the method includes:

[0028] The scan chain circuit generates M second data based on M first data;

[0029] The scan output circuit outputs the M second data in parallel;

[0030] The serializer circuit generates a serial output signal based on the M second data, and the serial output signal is used to determine the test result for the chip;

[0031] The output port outputs the serial output signal.

[0032] According to one aspect of the embodiments of this application, an electronic device is provided, the electronic device including the above-described chip.

[0033] The technical solutions provided in this application have at least the following beneficial effects:

[0034] The chip's input port is connected to each of the M (first) input terminals of the scan input circuit via a deserializer circuit. This allows each input terminal of the scan input circuit to receive data through the same input port of the chip (after conversion by the deserializer circuit), thus providing the required test data to the scan chain circuit. Therefore, the chip only needs to provide one input port to support data input to any scan chain in the scan chain circuit, resulting in low implementation cost. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of a chip with a testable design structure and a chip testing system including the chip, provided in one possible implementation of this application.

[0036] Figure 2 This is a schematic diagram of the chip structure provided in one possible implementation of this application;

[0037] Figure 3 This is a schematic diagram of the chip structure provided in another possible implementation of this application;

[0038] Figure 4 This is a schematic diagram of the chip structure provided in another possible implementation of this application;

[0039] Figure 5 This is a schematic diagram of the chip structure provided in another possible implementation of this application;

[0040] Figure 6 This is a schematic diagram of a chip provided in one possible implementation of this application;

[0041] Figure 7 This is a schematic diagram of a chip provided in another possible implementation of this application;

[0042] Figure 8 This is a schematic diagram of a chip testing system provided in one possible implementation of this application;

[0043] Figure 9This is a schematic diagram of the external logic circuitry included in a possible implementation of the chip testing system provided in this application;

[0044] Figure 10 This is a schematic diagram of a chip testing scenario provided in one possible implementation of this application;

[0045] Figure 11 This is a schematic diagram of the chip testing situation provided in another possible implementation of this application;

[0046] Figure 12 This is a flowchart of a chip testing method provided in one possible implementation of this application;

[0047] Figure 13 This is a flowchart of a chip testing method provided in another possible implementation of this application. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0049] Before introducing the technical solution of this application, some terms involved in this application will be explained. The following related explanations are optional and can be combined with the technical solutions of the embodiments of this application in any way, all of which fall within the protection scope of this application. The embodiments of this application include at least some of the following contents.

[0050] Design for Testability (DFT): DFT is an integrated circuit design technique that incorporates test logic during the chip design phase to improve chip test coverage and reliability, thereby ensuring the quality of mass-produced chips.

[0051] Scan Chain: In DFT, when the chip is in test mode, its internal components (such as flip-flops) are connected into a chain structure to form a scan chain. By inputting data into the scan chain, it is possible to determine whether the components in the scan chain are working properly based on the data generated by the scan chain.

[0052] General Purpose Input / Output Port: GPIO port, a type of port whose function and status can be controlled by software programming. It can be used to input data to the chip or output data from the chip.

[0053] Serializer / Deserializer: Essential devices in serial communication. The serializer converts parallel data into a serial signal for transmission over a serial channel, while the deserializer converts the serial signal back into parallel data for processing at the receiving end. When the serializer / deserializer is integrated into a chip as a circuit, the deserializer circuit converts the serial signal received at the chip's input port into parallel data for transmission within the chip. Conversely, the serializer circuit converts the parallel data generated internally into a serial signal for output from the chip's output port.

[0054] Serdes: A high-speed interface in a chip, comprising a TX (Transmit) interface and an RX (Receive) interface. The RX interface can be used as an input port of the chip, and the TX interface can be used as an output port. Its advantage is that it can perform high-speed data transmission, such as transmitting high-speed serial signals.

[0055] The design process of a chip must include a testability design phase, which is used to verify physical and manufacturing defects that may exist during the chip manufacturing process after the chip is manufactured.

[0056] Please refer to Figure 1 This illustration shows a schematic diagram of a chip with a DFT structure provided in one possible implementation of this application, as well as a chip testing system including the chip. The chip testing system includes a chip 20, a testing platform 50, and a host computer 60.

[0057] The following describes the testing procedure for the scan chains in the chip, taking the first scan chain 11 as an example. The procedure includes the following steps:

[0058] 1. Test data is input from test machine 50 to GPIO port 1.

[0059] 2. Scan input module A, connected to GPIO port 1, inputs test data into the first scan chain 11. The first scan chain 11 can be connected to... Figure 1 The scan input module A and scan input module B shown are connected to any scan chain.

[0060] 3. The scan output module B, which is connected to the first scan chain 11, outputs the data generated by the first scan chain 11 to the chip through GPIO port 2.

[0061] 4. The test machine 50 compares the data output from GPIO port 2 with the expected data and sends the comparison result to the host computer 60.

[0062] 5. The host computer 60 determines the test result for the first scan chain 11 based on the comparison result.

[0063] As can be seen, by adopting the above testing procedure, if we want to target the second scan chain 12 in the chip (the second scan chain 12 can be...) Figure 1 To perform a test (where scan input module C and scan input module D are connected in any scan chain), test data needs to be input from GPIO port 5 or 7, and data needs to be received from GPIO port 6 or 8. Similarly, the more complex the logic circuitry in the chip, and the more scan input and output modules there are, the more GPIO ports are needed to support the test execution, which obviously incurs higher costs.

[0064] To address the aforementioned issues, this application provides a solution for adding a serializer / deserializer circuit to the DFT structure of a chip. This solution supports the execution testing of each scan chain in the chip via a pair of input / output ports, which will be described in more detail in the following embodiments.

[0065] Please refer to Figure 2 The diagram illustrates a schematic of the chip provided in one possible implementation of this application. The chip 20 includes: an input port 21, a deserializer circuit 22, a scan input circuit 23, and a scan chain circuit 24.

[0066] First, it should be noted that the accompanying drawings are merely illustrative examples of the chip structure provided in this application. The actual chip structure may include more or fewer components or ports than shown in the drawings, or combine certain components other than those shown in the drawings. This application does not limit the scope of the chip structure.

[0067] The deserializer circuit 22 has M first output terminals, and the scanning input circuit 23 has M first input terminals, where M is an integer greater than 1.

[0068] The aforementioned input port 21 is used to input data to chip 20, such as the RX interface included in the Serdes of chip 20.

[0069] In some embodiments, the input port 21 is integrated with a series of enabling circuits (such as Serdes-related enabling circuits) to support its signal receiving function. This application does not limit the specific structure of the input port 21.

[0070] The first output terminal refers to the output terminal of the deserializer circuit 22. For example, please refer to... Figure 2 The deserializer circuit 22 has four first output terminals: a1, a2, a3, and a4.

[0071] The first input terminal refers to the input terminal of the scanning input circuit 23. For example, please refer to... Figure 2 The scanning input circuit 23 has four first input terminals: b1, b2, b3, and b4.

[0072] Input port 21 is connected to the input terminal of deserializer circuit 22, and the i-th first output terminal among the M first output terminals is connected to the i-th first input terminal among the M first input terminals, where i is a positive integer less than or equal to M.

[0073] For example, please refer to Figure 2 Input port 21 is connected to the only input terminal of deserializer circuit 22. The four first output terminals (a1, a2, a3, a4) of deserializer circuit 22 are connected one-to-one with the four first input terminals (b1, b2, b3, b4) of scanning input circuit 23.

[0074] The scan chain circuit 24 includes multiple scan chains, and the input end of the scan chain is connected to the output end of the scan input circuit 23.

[0075] The technical solution provided in this application embodiment configures the chip's input port to be connected to M (first) input terminals of the scan input circuit via a deserializer circuit. This allows each input terminal of the scan input circuit to support data input through the same input port of the chip (after conversion by the deserializer circuit), thus providing the required test data to the scan chain circuit. Therefore, the chip only needs to provide one input port to support data input to any scan chain in the scan chain circuit, resulting in lower implementation costs.

[0076] The following examples will illustrate the specific functions of the various circuit structures described above.

[0077] In some embodiments, input port 21 is used to receive serial input signals. Serial input signals refer to the signal form in which data is input to the chip bit by bit.

[0078] The deserializer circuit 22 is used to output M first data in parallel based on the serial input signal.

[0079] The first data is used to test the scan chain and can be configured by technicians as needed. For any two of the M first data sets, their specific data content can be the same or different, depending on the testing requirements; this application does not impose any restrictions on this.

[0080] In some embodiments, the deserializer circuit 22 is used to output M first data in parallel from the M first output terminals according to the serial input signal, wherein the i-th first output terminal among the M first output terminals is used to output the i-th first data among the M first data.

[0081] For example, please refer to Figure 2 The deserializer circuit 22 has four first output terminals (a1, a2, a3, a4), each of which outputs a first data, enabling the parallel transmission of four first data.

[0082] The scan input circuit 23 is used to input M first data into the scan chain circuit 24, wherein different first data among the M first data are input into different scan chains.

[0083] In some embodiments, for any one of the M first data items, the scan input circuit 23 is configured to input the first data item to the scan chain indicated by the scan chain address according to the scan chain address carried in the first data item. In other embodiments, the scan input circuit 23 is configured to input the first data item received from the i-th first input terminal to the scan chain corresponding to the i-th first input terminal in the scan chain circuit according to a pre-configured correspondence, wherein the pre-configured correspondence includes the correspondence between the M first input terminals and a portion of the scan chains in the scan chain circuit.

[0084] In some embodiments, each first data is input to at least one scan chain in the scan chain circuit 24, and the scan chains to which different first data are input do not overlap.

[0085] The scan chain circuit 24 is used to generate M second data based on M first data, and the M second data are used to determine the test results for the chip.

[0086] The second data is generated based on the first data, meaning that each second data corresponds to a first data.

[0087] In some embodiments, the i-th second data among M second data is generated based on the i-th first data among M first data.

[0088] In some embodiments, the i-th second data among the M second data includes: data generated by at least one scan chain that receives the i-th first data based on the i-th first data.

[0089] For details on how to determine the test results for the chip based on the M second data points, please refer to the embodiments below, which will not be repeated here.

[0090] In the above embodiment, the serial input signal input from a single input port 21 is converted into M first data points by the deserializer circuit 22 and output in parallel. Different scan chains in the scan chain circuit 24 can generate M second data points based on the M first data points. Therefore, the above scheme achieves simultaneous input of individual test data (first data points) to scan chains at different locations in the chip using a single input port, thereby improving the testing efficiency of the chip and reducing the testing time.

[0091] In some embodiments, please refer to Figure 2The deserializer circuit 22 includes a serial-to-parallel conversion module 221, an input buffer queue 222, and a clock alignment circuit 223. All M first output terminals are output terminals of the clock alignment circuit 223.

[0092] The serial-to-parallel conversion module 221 is used to convert the serial input signal into M first data.

[0093] Input buffer queue 222 is used to store M first data.

[0094] In some embodiments, the input buffer queue 222 is a FIFO (First In First Out) queue, that is, when M first data are initially added to the input buffer queue 222, the M first data are located at the tail of the input buffer queue 222. The M first data will only be retrieved when all the data that were stored in the input buffer queue 222 before the M first data have been retrieved.

[0095] The clock alignment circuit 223 is used to output M first data stored in the input buffer queue 222 in parallel according to the clock data. The clock data is used to determine the timing reference for the data received by the scan input circuit 23.

[0096] In some embodiments, the clock alignment circuit 223 is used to transmit M first data in parallel when the timing of transmitting M first data is determined according to clock data and the timing reference of the data received by the scan input circuit is aligned.

[0097] In the above embodiment, the deserializer circuit 22 includes, in addition to the module for converting between serial signals and parallel data (serial-to-parallel conversion module 221), a corresponding buffer queue (input buffer queue 222). This allows for the reservation of a buffer space within the chip for the next step of parallel data transmission (input to clock alignment circuit 223) in scenarios where a serial signal is continuously input through input port 21 for continuous testing, thus preventing data loss. Furthermore, by designing the clock alignment circuit 223, the parallel data converted from the serial signal can be sent according to the timing required by the scanning input circuit 23, ensuring that this parallel data is correctly identified by the scanning input circuit 23.

[0098] In some embodiments, please refer to Figure 2 The scanning input circuit 23 includes N scanning input modules 231, each having at least one of M first input terminals. The scanning chain circuit 24 includes N scanning chain modules 241, each including at least two scanning chains, where N is an integer greater than 1.

[0099] For example, please refer to Figure 2The scan input circuit 23 includes two scan input modules 231, each scan input module 231 having two of the four first input terminals (b1 and b2 / b3 and b4), and the scan chain circuit 24 includes two scan chain modules 241.

[0100] For the k-th scan chain module among N scan chain modules, the input end of the scan chain in the k-th scan chain module is connected to the output end of the k-th scan input module among N scan input modules, where k is a positive integer less than or equal to N.

[0101] For example, please refer to Figure 2 The scan chains in different scan chain modules 241 are connected to different scan input modules 231.

[0102] The k-th scan input module is used to receive at least one of the M first data.

[0103] For example, please refer to Figure 2 Each of the two scanning input modules 231 is used to receive two of the four first data (through two first input ports).

[0104] In the above embodiment, the input port 21 of the chip 20 is connected to each input terminal of N scan input modules 231 through the deserializer circuit 22. Each scan input module 231 is connected to a scan chain module 241. Therefore, the above chip structure supports inputting data to each scan chain module 241 in the chip 20 through one input port. It is not necessary to increase the number of input ports used for chip testing due to the modularization and complexity of the scan chain (reflected in the increase in the number of scan chain modules 241).

[0105] In some embodiments, the kth scan input module is used to input at least one received first data into the kth scan chain module, wherein, in the case that the kth scan input module receives multiple first data, the multiple first data are input into different scan chains in the kth scan chain module.

[0106] In some embodiments, for any first data received by the kth scan input module, the kth scan input module is configured to input the first data into the kth scan chain module according to the scan chain address carried in the first data, wherein the scan chain address indicates the scan chain. In other embodiments, the kth scan input module is configured to input the first data received from its own first input terminal into the kth scan chain module according to a pre-configured correspondence, wherein the pre-configured correspondence includes the correspondence between at least one first input terminal of the kth scan input module and a portion of the scan chains in the kth scan chain module.

[0107] In some embodiments, each first data received by the kth scan input module is input to at least one scan chain in the kth scan chain module, and in the case that the kth scan input module receives multiple first data, the scan chains to which the different first data are input do not overlap.

[0108] The k-th scan chain module is used to generate at least one second data from M second data based on at least one first data.

[0109] In some embodiments, for any one of the above-mentioned at least one second data, it includes: data generated by at least one scan chain in the k-th scan chain module that receives the corresponding first data. The second data is generated based on the corresponding first data.

[0110] In the above embodiment, the serial input signal input from a single input port 21 is converted into M first data points by the deserializer circuit 22 and output in parallel. The M first data points are then distributed to N scan chain modules 241 through the corresponding scan input module 231. Therefore, the above scheme achieves simultaneous input of individual test data (first data points) to the scan chains of different scan chain modules 241 in the chip using a single input port, thereby improving the testing efficiency of the chip and reducing the testing time.

[0111] In some embodiments, please refer to Figure 3 The chip 20 also includes M first ports 31 and M multiplexers 32.

[0112] The first port 31 is used to input data to the chip. In some embodiments, the first port 31 is the GPIO port described above.

[0113] Each multiplexer 32 has two input ports (a first input port and a second input port) and one output port.

[0114] The i-th first output of the M first output terminals is connected to the first input port of the i-th multiplexer among the M multiplexers 32, and the i-th first port of the M first ports 31 is connected to the second input port of the i-th multiplexer.

[0115] For example, please refer to Figure 3 The four first output terminals (a1, a2, a3, a4) of the deserializer circuit 22 are connected one-to-one with the first input ports (0 input ports) of the four multiplexers, and the four first ports 31 are connected one-to-one with the second input ports (1 input ports) of the four multiplexers 32.

[0116] The output port of the i-th multiplexer is connected to the i-th first input port among the M first input ports.

[0117] For example, please refer to Figure 3 Each of the four multiplexers 32 output ports is connected to one of the four first input terminals (b1, b2, b3, b4) of the scanning input circuit 23.

[0118] In the above embodiment, each input terminal (first input terminal) of the scanning input circuit 23 is connected to the output port of a multiplexer 32. The two input ports of the multiplexer 32 are respectively connected to an output terminal (first output terminal) and a first port 31 of the deserializer circuit 22, thereby providing a chip structure that can flexibly adjust the input mode (serial input or parallel input) of test data (data used to test the chip).

[0119] In some embodiments, the i-th multiplexer is configured to, upon receiving a first control signal, output the data received at the first input port of the i-th multiplexer from the output port of the i-th multiplexer; and upon receiving a second control signal, output the data received at the second input port of the i-th multiplexer from the output port of the i-th multiplexer.

[0120] The first control signal and the second control signal are different control signals. For example, the first control signal is 0 and the second control signal is 1.

[0121] In other words, the i-th multiplexer is used to output the data (first data) output from the i-th first output terminal of the deserializer circuit 22 from the output port of the i-th multiplexer when the first control signal is received; and to output the data input from the i-th first port 31 from the output port of the i-th multiplexer when the second control signal is received.

[0122] As can be seen, by using the above M multiplexers 32, the data source of each first input terminal of the scanning input circuit 23 (converted from the serial input signal input from the input port 21 / directly input from the first port 31) can be flexibly controlled, which improves the flexibility of performing tests on the chip.

[0123] In some embodiments, chip 20 further includes a scan output circuit, a serializer circuit, and an output port.

[0124] The scan output circuit has M second output terminals, and the serializer circuit has M second input terminals, where M is an integer greater than 1.

[0125] The output of the scan chain is connected to the input of the scan output circuit.

[0126] The i-th second output terminal among the M second output terminals is connected to the i-th second input terminal among the M second input terminals, and the output terminal of the serializer circuit is connected to the output port.

[0127] Please refer to Figure 4 The diagram illustrates a schematic of the chip provided in another possible implementation of this application. The chip 20 includes: a scan chain circuit 24, a scan output circuit 25, a serializer circuit 26, and an output port 27.

[0128] The scan output circuit 25 has M second output terminals, and the serializer circuit 26 has M second input terminals, where M is an integer greater than 1.

[0129] The aforementioned output port 27 is used to send the data generated by chip 20 to the outside of the chip, such as the TX interface included in the Serdes of chip 20.

[0130] In some embodiments, the output port 27 is integrated with a series of enable circuits (such as Serdes-related enable circuits) to support its signal transmission function. This application does not limit the specific structure of the output port 27.

[0131] The second output terminal refers to the output terminal of the scan output circuit 25. For example, please refer to [reference needed]. Figure 4 The scanning output circuit 25 has four second output terminals: C1, C2, C3, and C4.

[0132] The second input terminal refers to the input terminal of the serializer circuit 26. For example, please refer to... Figure 4 The serializer circuit 26 has four second input terminals: d1, d2, d3, and d4.

[0133] The scan chain circuit 24 includes multiple scan chains, and the output of the scan chain is connected to the input of the scan output circuit 25.

[0134] The i-th second output terminal among the M second output terminals is connected to the i-th second input terminal among the M second input terminals, and the output terminal of the serializer circuit 26 is connected to the output port 27, where i is a positive integer less than or equal to M.

[0135] For example, please refer to Figure 4 The four second output terminals (c1, c2, c3, c4) of the scanning output circuit 25 and the four second input terminals (d1, d2, d3, d4) of the serializer circuit 26 are connected one-to-one. The only output terminal of the serializer circuit 26 is connected to the output port 27.

[0136] The technical solution provided in this application embodiment configures the chip's output port to be connected to M (second) output terminals of the scan chain circuit via a serializer circuit. This ensures that each output terminal of the scan output circuit supports outputting data generated by the scan chain circuit (after integration by the serializer circuit) from the same output port. Therefore, the chip only needs to provide one output port to support outputting data generated by any scan chain in the scan chain circuit, resulting in lower implementation costs.

[0137] The following examples will illustrate the specific functions of the various circuit structures described above.

[0138] In some embodiments, the scan chain circuit 24 is used to generate M second data based on M first data.

[0139] The scan output circuit 25 is used to output M second data in parallel.

[0140] In some embodiments, the scan output circuit 25 is used to output M second data in parallel from the M second output terminals, wherein the i-th second output terminal among the M second output terminals is used to output the i-th second data among the M second data.

[0141] For example, please refer to Figure 4 The scan output circuit 25 has four second output terminals (c1, c2, c3, c4), each of which outputs one second data, thus enabling the parallel transmission of four second data.

[0142] The serializer circuit 26 is used to generate a serial output signal based on M second data, and the serial output signal is used to determine the test results for the chip.

[0143] Serial output signal refers to the signal form in which data is output to the chip bit by bit.

[0144] Output port 27 is used to output serial output signals.

[0145] For details on how to determine the test results for the chip based on the serial output signal, please refer to the examples below, which will not be repeated here.

[0146] In the above embodiment, the serializer circuit 26 converts the M second data output in parallel by the scan output circuit 25 into a serial output signal that supports serial output from the output port. Therefore, the above solution can output data generated in parallel by scan chains at different locations in the chip through a single output port, resulting in lower implementation cost.

[0147] In some embodiments, please refer to Figure 4 The serializer circuit 26 includes an output buffer queue 261 and a parallel-to-serial conversion module 262, and the M second input terminals are all input terminals of the output buffer queue 261.

[0148] Output buffer queue 261 is used to store M second data items.

[0149] In some embodiments, the output buffer queue 261 is a FIFO (First In First Out) queue. That is to say, when M second data are initially added to the output buffer queue 261, the M first data are located at the tail of the output buffer queue 261. The M second data will only be retrieved when all the data that were stored in the output buffer queue 261 before the M second data have been retrieved.

[0150] The parallel-to-serial conversion module 262 is used to convert the M second data stored in the output buffer queue 261 into a serial output signal.

[0151] In the above embodiment, the serializer circuit 26 includes not only a module for converting serial signals and parallel data (parallel-to-serial conversion module 262), but also a corresponding buffer queue (output buffer queue 261). This allows for the reservation of a certain buffer space within the chip for the next step of parallel data transmission (input to parallel-to-serial conversion module 262) in the scenario where the scanning output circuit 25 continuously outputs parallel data for continuous testing, thus avoiding data loss.

[0152] In some embodiments, the scan chain circuit 24 includes N scan chain modules 241, each scan chain module 241 including at least two scan chains, and the scan output circuit 25 includes N scan output modules 251, each scan output module 251 having at least one of M second output terminals, where N is an integer greater than 1.

[0153] For example, please refer to Figure 4 The scan chain circuit 24 includes two scan chain modules 241, and the scan output circuit 25 includes two scan output modules 251. The scan output module 251 has two of the four second output terminals (c1 and c2 / c3 and c4).

[0154] For the k-th scan chain module among N scan chain modules, the output of the scan chain in the k-th scan chain module is connected to the input of the k-th scan output module among N scan output modules, where k is a positive integer less than or equal to N.

[0155] For example, please refer to Figure 4 The scan chains in different scan chain modules 241 are connected to different scan output modules 251.

[0156] The k-th scan output module is used to output at least one of the M second data.

[0157] For example, please refer to Figure 4 Each of the two scan output modules 251 is used to output two of the four second data (through two second output ports).

[0158] In the above embodiment, the output port 27 of the chip 20 is connected to the output terminals of N scan output modules 251 through the serializer circuit 26, and each scan output module 251 is connected to a scan chain module 241. Therefore, the above chip structure supports outputting the data generated by each scan chain module 241 in the chip 20 with one output port, without increasing the number of output ports used for chip testing due to the modularization and complexity of the scan chain (reflected in the increase in the number of scan chain modules 241).

[0159] In some embodiments, the k-th scan chain module is used to generate at least one second data based on at least one of the M first data.

[0160] The k-th scan output module is used to output at least one second data, wherein, in the case that the k-th scan chain module generates multiple second data, the multiple second data are output in parallel.

[0161] For example, please refer to Figure 4 Since each scan output module 251 has two second output terminals, each scan output module 251 can output two second data in parallel.

[0162] In the above embodiment, the data (M second data) generated by the scan chain module 241 is output in parallel to the serializer circuit 26 through the corresponding scan output module 251. The serializer circuit 26 can then convert the parallel output M second data into a serial output signal that supports serial output from the output port 27. Therefore, the above solution supports outputting data generated by scan chains in different scan chain modules 241 in the chip through a single output port, resulting in lower implementation costs.

[0163] In some embodiments, please refer to Figure 5 The chip 20 also includes M demultiplexers 33 and M second ports 34.

[0164] The second port 34 is used to output data from the chip. In some embodiments, the second port 34 is the GPIO port described above.

[0165] Each demultiplexer 33 has one input port and two output ports (first output port and second output port).

[0166] The i-th second output of the M second output terminals is connected to the input port of the i-th demultiplexer of the M demultiplexers.

[0167] For example, please refer to Figure 5 The scanning output circuit has four second output terminals (c1, c2, c3, c4) and four demultiplexers 33, each of which is connected to the input port of the demultiplexer 33 in a one-to-one correspondence.

[0168] The first output port of the i-th demultiplexer is connected to the i-th second input port among the M second input ports, and the second output port of the i-th demultiplexer is connected to the i-th second port among the M second ports.

[0169] For example, please refer to Figure 5 Each of the four demultiplexers 33 has its first output port connected to one of the four second input terminals (d1, d2, d3, d4) of the serializer circuit 26; and each of the four demultiplexers 33 has its second output port connected to one of the four second ports 34.

[0170] In the above embodiment, each output terminal of the scan output circuit 25 is connected to the input port of a demultiplexer 33, and the two output ports of the demultiplexer 33 are respectively connected to one output terminal of the serializer circuit 26 and a second port 34, thereby providing a chip structure that can flexibly adjust the output mode (serial output or parallel output) of the data generated based on the test data.

[0171] In some embodiments, the i-th demultiplexer is configured to output the data received at the input port of the i-th demultiplexer from the first output port of the i-th demultiplexer when a third control signal is received; and to output the data received at the input port of the i-th demultiplexer from the second output port of the i-th demultiplexer when a fourth control signal is received.

[0172] The third control signal and the fourth control signal are different control signals. For example, the third control signal is 0 and the fourth control signal is 1.

[0173] In other words, the i-th demultiplexer is used to output the data output from the i-th second output terminal of the scan output circuit 25 to the i-th second input terminal of the serializer circuit 26 when the third control signal is received; and to output the data output from the i-th second output terminal of the scan output circuit 25 to the i-th second port when the fourth control signal is received.

[0174] As can be seen, by using the above M demultiplexers 33, the destination of the output data of each second output terminal of the scan output circuit 25 can be flexibly controlled (to be given to the serializer circuit 26 so as to be output from the output port 27 in the form of a serial output signal / directly output from the second port 34), which improves the flexibility when performing tests on the chip.

[0175] In some embodiments, chip 20 further includes: an input port, a deserializer circuit, and a scan input circuit;

[0176] The deserializer circuit has M first output terminals, and the scanning input circuit has M first input terminals, where M is an integer greater than 1.

[0177] The input port is connected to the input terminal of the deserializer circuit. The i-th first output terminal among the M first output terminals is connected to the i-th first input terminal among the M first input terminals, where i is a positive integer less than or equal to M.

[0178] The input terminal of the scan chain is connected to the output terminal of the scan input circuit.

[0179] It should be noted that the chip structure described above can be arbitrarily combined according to the design requirements of technicians. The following embodiments will describe this. For any details not described in detail in the above chip structure embodiments, please refer to the following chip embodiments.

[0180] Please refer to Figure 6 The diagram illustrates a schematic of a chip provided in one possible implementation of this application. The chip 20 includes: an input port 21, a deserializer circuit 22, a scan input circuit 23, a scan chain circuit 24, a scan output circuit 25, a serializer circuit 26, and an output port 27.

[0181] The deserializer circuit 22 has M first output terminals, the scan input circuit 23 has M first input terminals, the scan output circuit 25 has M second output terminals, and the serializer circuit 26 has M second input terminals, where M is an integer greater than 1.

[0182] The aforementioned input port 21 is used to input data to chip 20, such as the RX interface included in the Serdes of chip 20.

[0183] The aforementioned output port 27 is used to send the data generated by chip 20 to the outside of the chip, such as the TX interface included in the Serdes of chip 20.

[0184] In addition, it should be noted that the above-mentioned input port 21 and output port 27 may also integrate a series of enable circuits (such as Serdes-related enable circuits) to support their signal transmission / reception functions. This application does not limit the specific structure of input port 21 and output port 27.

[0185] The first output terminal refers to the output terminal of the deserializer circuit 22. For example, please refer to... Figure 6 The deserializer circuit 22 has four first output terminals: a1, a2, a3, and a4.

[0186] The first input terminal refers to the input terminal of the scanning input circuit 23. For example, please refer to... Figure 6 The scanning input circuit 23 has four first input terminals: b1, b2, b3, and b4.

[0187] The second output terminal refers to the output terminal of the scan output circuit 25. For example, please refer to [reference needed]. Figure 6 The scanning output circuit 25 has four second output terminals: C1, C2, C3, and C4.

[0188] The second input terminal refers to the input terminal of the serializer circuit 26. For example, please refer to... Figure 6 The serializer circuit 26 has four second input terminals: d1, d2, d3, and d4.

[0189] Input port 21 is connected to the input terminal of deserializer circuit 22. The i-th first output terminal among the M first output terminals is connected to the i-th first input terminal among the M first input terminals, where i is a positive integer less than or equal to M.

[0190] For example, please refer to Figure 6 Input port 21 is connected to the only input terminal of deserializer circuit 22. The four first output terminals (a1, a2, a3, a4) of deserializer circuit 22 are connected one-to-one with the four first input terminals (b1, b2, b3, b4) of scanning input circuit 23.

[0191] The scan chain circuit 24 includes multiple scan chains. The input end of the scan chain is connected to the output end of the scan input circuit 23, and the output end of the scan chain is connected to the input end of the scan output circuit 25.

[0192] The i-th second output terminal among the M second output terminals is connected to the i-th second input terminal among the M second input terminals, and the output terminal of the serializer circuit is connected to the output port.

[0193] For example, please refer to Figure 6 The four second output terminals (c1, c2, c3, c4) of the scanning output circuit 25 and the four second input terminals (d1, d2, d3, d4) of the serializer circuit 26 are connected one-to-one. The only output terminal of the serializer circuit 26 is connected to the output port 27.

[0194] The technical solution provided in this application embodiment configures the chip's input ports to be connected to M (first) input terminals of the scan chain circuit via deserializer circuits, and configures the chip's output ports to be connected to M (second) output terminals of the scan chain circuit via serializer circuits. This allows each input terminal of the scan input circuit to support data input through the same input port of the chip (after conversion by the deserializer circuit), thus providing the required test data to the scan chain circuit. Similarly, each output terminal of the scan chain output circuit supports outputting the data generated by the scan chain circuit (after integration by the serializer circuit) from the same output port of the chip. Therefore, the chip only needs to provide one pair of input / output ports to support testing any scan chain in the scan chain circuit, resulting in lower implementation costs.

[0195] The following embodiments will describe the specific functions of the various circuit structures described above, as well as the specific procedures for performing tests on the chip 20 based on these circuit structures.

[0196] In some embodiments, input port 21 is used to receive serial input signals. Serial input signals refer to the signal form in which data is input to the chip bit by bit.

[0197] The deserializer circuit 22 is used to output M first data in parallel based on the serial input signal.

[0198] The first data is used to test the scan chain and can be configured by technicians as needed. For any two of the M first data sets, their specific data content can be the same or different, depending on the testing requirements; this application does not impose any restrictions on this.

[0199] In some embodiments, the deserializer circuit 22 is used to output M first data in parallel from the M first output terminals according to the serial input signal, wherein the i-th first output terminal among the M first output terminals is used to output the i-th first data among the M first data.

[0200] For example, please refer to Figure 6 The deserializer circuit 22 has four first output terminals (a1, a2, a3, a4). Each first output terminal outputs one first data, which can transmit four first data in parallel.

[0201] The scan input circuit 23 is used to input M first data into the scan chain circuit 24, wherein different first data among the M first data are input into different scan chains.

[0202] In some embodiments, for any one of the M first data items, the scan input circuit 23 is configured to input the first data item to the scan chain indicated by the scan chain address according to the scan chain address carried in the first data item. In other embodiments, the scan input circuit 23 is configured to input the first data item received from the i-th first input terminal to the scan chain corresponding to the i-th first input terminal in the scan chain circuit according to a pre-configured correspondence, wherein the pre-configured correspondence includes the correspondence between the M first input terminals and a portion of the scan chains in the scan chain circuit.

[0203] In some embodiments, each first data is input to at least one scan chain in the scan chain circuit 24, and the scan chains to which different first data are input do not overlap.

[0204] The scan chain circuit 24 is used to generate M second data based on M first data.

[0205] The second data is generated based on the first data, meaning that each second data corresponds to a first data.

[0206] In some embodiments, the i-th second data among M second data is generated based on the i-th first data among M first data.

[0207] In some embodiments, the i-th second data among the M second data includes: data generated by at least one scan chain that receives the i-th first data based on the i-th first data.

[0208] The scan output circuit 25 is used to output M second data in parallel.

[0209] In some embodiments, the scan output circuit 25 is used to output M second data in parallel from the M second output terminals, wherein the i-th second output terminal among the M second output terminals is used to output the i-th second data among the M second data.

[0210] For example, please refer to Figure 6 The scan output circuit 25 has four second output terminals (c1, c2, c3, c4), each of which outputs one second data, thus enabling the parallel transmission of four second data.

[0211] The serializer circuit 26 is used to generate a serial output signal based on M second data.

[0212] Serial output signal refers to the signal form in which data is output to the chip bit by bit.

[0213] Output port 27 is used to output a serial output signal, which is used to determine the test results for the chip.

[0214] For details on how to determine the test results for the chip based on the serial output signal, please refer to the examples below, which will not be repeated here.

[0215] In the above embodiment, the serial input signal input from a single input port 21 is converted into M first data signals output in parallel by the deserializer circuit 22. Different scan chains in the scan chain circuit 24 can generate M second data signals based on the M first data signals. Correspondingly, the serializer circuit 26 converts the M second data signals output in parallel by the scan output circuit 25 into serial output signals that support serial output from the output port. Therefore, the above scheme enables simultaneous testing of scan chains at different locations in the chip using separate test data (first data signals) with a pair of input-output ports, thereby improving the testing efficiency of the chip and reducing the testing time.

[0216] In some embodiments, please refer to Figure 6 The deserializer circuit 22 includes a serial-to-parallel conversion module 221, an input buffer queue 222, and a clock alignment circuit 223. All M first output terminals are output terminals of the clock alignment circuit 223. The serializer circuit 26 includes an output buffer queue 261 and a parallel-to-serial conversion module 262. All M second input terminals are input terminals of the output buffer queue 261.

[0217] The serial-to-parallel conversion module 221 is used to convert the serial input signal into M first data.

[0218] Input buffer queue 222 is used to store M first data.

[0219] In some embodiments, the input buffer queue 222 is a FIFO queue. That is, when M first data are initially added to the input buffer queue 222, the M first data are located at the tail of the input buffer queue 222. The M first data will only be retrieved when all the data that were stored in the input buffer queue 222 before the M first data have been retrieved.

[0220] The clock alignment circuit 223 is used to output M first data stored in the input buffer queue 222 in parallel according to the clock data. The clock data is used to determine the timing reference for the data received by the scan input circuit.

[0221] In some embodiments, the clock alignment circuit 223 is used to transmit M first data in parallel when the timing of transmitting M first data is determined according to clock data and the timing reference of the data received by the scan input circuit is aligned.

[0222] Output buffer queue 261 is used to store M second data items.

[0223] In some embodiments, the output buffer queue 261 is a FIFO queue. That is, when M second data are initially added to the output buffer queue 261, the M first data are located at the tail of the output buffer queue 261. The M second data will only be retrieved when all the data that were stored in the output buffer queue 261 before the M second data have been retrieved.

[0224] The parallel-to-serial conversion module 262 is used to convert the M second data stored in the output buffer queue 261 into a serial output signal.

[0225] In the above embodiment, the deserializer circuit 22 and the serializer circuit 26, in addition to modules for converting between serial signals and parallel data (serial-to-parallel conversion module 221 and parallel-to-serial conversion module 262), also include corresponding buffer queues (input buffer queue 222 and output buffer queue 261). This allows for the provision of buffer space within the chip for the next step of parallel data transmission (input to clock alignment circuit 223 or parallel-to-serial conversion module 262) in scenarios where a serial signal is continuously input through input port 21 for continuous testing, thus preventing data loss. Furthermore, by designing the clock alignment circuit 223, the parallel data converted from the serial signal can be sent according to the timing required by the scanning input circuit 23, ensuring that this parallel data is correctly identified by the scanning input circuit 23.

[0226] In addition, the above solution only requires connecting the above-mentioned deserializer circuit 22 and serializer circuit 26 to the general DFT structure of the chip (scan input circuit 23, scan chain circuit 24 and scan output circuit 25) to perform coverage testing on the chip, which has low implementation complexity.

[0227] In some embodiments, the scan input circuit 23 includes N scan input modules 231, each scan input module 231 having at least one first input terminal from among M first input terminals; the scan chain circuit 24 includes N scan chain modules 241, each scan chain module 241 including at least two scan chains; and the scan output circuit 25 includes N scan output modules 251, each scan output module 251 having at least one second output terminal from among M second output terminals, where N is an integer greater than 1.

[0228] For example, please refer to Figure 6 The scan input circuit 23 includes two scan input modules 231, each scan input module 231 having two of the four first input terminals (b1 and b2 / b3 and b4). The scan chain circuit 24 includes two scan chain modules 241. The scan output circuit 25 includes two scan output modules 251, each scan output module 251 having two of the four second output terminals (c1 and c2 / c3 and c4).

[0229] For the k-th scan chain module among N scan chain modules, one end of the scan chain in the k-th scan chain module is connected to the output of the k-th scan input module among N scan input modules, and the other end of the scan chain in the k-th scan chain module is connected to the input of the k-th scan output module among N scan output modules, where k is a positive integer less than or equal to N.

[0230] For example, please refer to Figure 6 The scan chains in different scan chain modules 241 are connected to different scan input modules 231 (and different scan output modules 251).

[0231] The k-th scan input module is used to receive at least one of the M first data, and the k-th scan output module is used to output at least one of the M second data.

[0232] For example, please refer to Figure 6 Each of the two scanning input modules 231 is used to receive two of the four first data (through two first input ports), and each of the two scanning output modules 251 is used to output two of the four second data (through two second output ports).

[0233] In the above embodiment, the input port 21 of chip 20 is connected to the input terminals of each of the N scan input modules 231 through the deserializer circuit 22, and the output port 27 of chip is connected to the output terminals of each of the N scan output modules 251 through the serializer circuit 26. Each scan input module 231 and scan output module 251 is connected to a scan chain module 241. Therefore, the above chip structure supports testing each scan chain module 241 in chip 20 with a pair of input and output ports, without increasing the number of chip ports used for chip testing due to the modularization and complexity of the scan chain (reflected in the increase in the number of scan chain modules 241).

[0234] In some embodiments, the kth scan input module is used to input at least one received first data into the kth scan chain module, wherein, in the case that the kth scan input module receives multiple first data, the multiple first data are input into different scan chains in the kth scan chain module.

[0235] In some embodiments, for any first data received by the kth scan input module, the kth scan input module is configured to input the first data into the kth scan chain module according to the scan chain address carried in the first data, wherein the scan chain address indicates the scan chain. In other embodiments, the kth scan input module is configured to input the first data received from its own first input terminal into the kth scan chain module according to a pre-configured correspondence, wherein the pre-configured correspondence includes the correspondence between at least one first input terminal of the kth scan input module and a portion of the scan chains in the kth scan chain module.

[0236] In some embodiments, each first data received by the kth scan input module is input to at least one scan chain in the kth scan chain module, and in the case that the kth scan input module receives multiple first data, the scan chains to which the different first data are input do not overlap.

[0237] The k-th scan chain module is used to generate at least one second data based on at least one first data.

[0238] In some embodiments, for any one of the above-mentioned at least one second data, it includes: data generated by at least one scan chain in the k-th scan chain module that receives the corresponding first data. The second data is generated based on the corresponding first data.

[0239] The k-th scan output module is used to output at least one second data, wherein, in the case that the k-th scan chain module generates multiple second data, the multiple second data are output in parallel.

[0240] For example, please refer to Figure 6 Since each scan output module 251 has two second output terminals, each scan output module 251 can output two second data in parallel.

[0241] In the above embodiment, the serial input signal input from a single input port 21 is converted into M first data points in parallel by the deserializer circuit 22. These M first data points are then distributed to N scan chain modules 241 via corresponding scan input modules 231. The data generated by these scan chain modules 241 (M second data points) are then output in parallel to the serializer circuit 26 via corresponding scan output modules 251. The serializer circuit 26 can thus convert the parallel output M second data points into a serial output signal that supports serial output from the output port. Therefore, the above scheme uses a pair of input-output ports to simultaneously test the scan chains in different scan chain modules 241 within the chip using separate test data (first data points), thereby improving the testing efficiency of the chip and reducing testing time.

[0242] In some embodiments, please refer to Figure 7 The chip 20 also includes M first ports 31, M multiplexers 32, M demultiplexers 33 and M second ports 34.

[0243] The first port 31 is used to input data into the chip, and the second port 34 is used to output data from the chip.

[0244] In some embodiments, the first port 31 and the second port 34 are both GPIO ports as described above.

[0245] Each multiplexer 32 has two input ports (first input port and second input port) and one output port, and each demultiplexer 33 has one input port and two output ports (first output port and second output port).

[0246] The i-th first output of the M first output terminals is connected to the first input port of the i-th multiplexer among the M multiplexers, and the i-th first port of the M first ports is connected to the second input port of the i-th multiplexer, where i is an integer less than or equal to M.

[0247] For example, please refer to Figure 7 The four first output terminals (a1, a2, a3, a4) of the deserializer circuit 22 are connected one-to-one with the first input ports (0 input ports) of the four multiplexers, and the four first ports 31 are connected one-to-one with the second input ports (1 input ports) of the four multiplexers 32.

[0248] The output port of the i-th multiplexer is connected to the i-th first input port among the M first input ports, and the i-th second output port among the M second output ports is connected to the input port of the i-th demultiplexer among the M demultiplexers.

[0249] For example, please refer to Figure 7 Each of the four multiplexers 32 has its output port connected to one of the four first input terminals (b1, b2, b3, b4) of the scan input circuit 23. The four second output terminals (c1, c2, c3, c4) of the scan output circuit are also connected to the input ports of the four demultiplexers 33.

[0250] The first output port of the i-th demultiplexer is connected to the i-th second input port among the M second input ports, and the second output port of the i-th demultiplexer is connected to the i-th second port among the M second ports 34.

[0251] For example, please refer to Figure 7Each of the four demultiplexers 33 has its first output port connected to one of the four second input terminals (d1, d2, d3, d4) of the serializer circuit 26; and each of the four demultiplexers 33 has its second output port connected to one of the four second ports 34.

[0252] In the above embodiment, each input terminal (first input terminal) of the scan input circuit 23 is connected to the output port of a multiplexer 32. The two input ports of the multiplexer 32 are respectively connected to one output terminal (first output terminal) and one first port 31 of the deserializer circuit 22. Each output terminal of the scan output circuit 25 is connected to the input port of a demultiplexer 33. The two output ports of the demultiplexer 33 are respectively connected to one output terminal and one second port 34 of the serializer circuit 26. This provides a chip structure that can flexibly adjust the input mode (serial input or parallel input) of test data (data used to test the chip) and the output mode (serial output or parallel output) of the data generated based on the test data. This will be described in more detail in the following embodiments.

[0253] In some embodiments, the i-th multiplexer is configured to, upon receiving a first control signal, output the data received at the first input port of the i-th multiplexer from the output port of the i-th multiplexer; and upon receiving a second control signal, output the data received at the second input port of the i-th multiplexer from the output port of the i-th multiplexer.

[0254] The first control signal and the second control signal are different control signals. For example, the first control signal is 0 and the second control signal is 1.

[0255] In other words, the i-th multiplexer is used to output the data (first data) output from the i-th first output terminal of the deserializer circuit 22 from the output port of the i-th multiplexer when the first control signal is received; and to output the data input from the i-th first port 31 from the output port of the i-th multiplexer when the second control signal is received.

[0256] The i-th demultiplexer is used to output the data received at the input port of the i-th demultiplexer from the first output port of the i-th demultiplexer when the third control signal is received; and to output the data received at the input port of the i-th demultiplexer from the second output port of the i-th demultiplexer when the fourth control signal is received.

[0257] The third control signal and the fourth control signal are different control signals. For example, the third control signal is 0 and the fourth control signal is 1.

[0258] In other words, the i-th demultiplexer is used to output the data output from the i-th second output terminal of the scan output circuit 25 to the i-th second input terminal of the serializer circuit 26 when the third control signal is received; and to output the data output from the i-th second output terminal of the scan output circuit 25 to the i-th second port when the fourth control signal is received.

[0259] As can be seen, the data source of each first input terminal of the scanning input circuit 23 can be flexibly controlled by the above M multiplexers 32 (converted from the serial input signal input from input port 21 / directly input from first port 31). The destination of the output data of each second output terminal of the scanning output circuit 25 can be flexibly controlled by the above M demultiplexers 33 (given to the serializer circuit 26 so as to be output from output port 27 in the form of a serial output signal / directly output from second port 34), which improves the flexibility when performing tests on the chip.

[0260] For example, please refer to Figure 7 If the first control signal is applied to all four multiplexers 32 and the third control signal is applied to all four demultiplexers, then Figure 7 The chip 20 shown can be equivalent to Figure 6 The data transmission of chip 20 shown in this case is described in the above embodiment and will not be repeated here.

[0261] For example, please refer to Figure 7 If the second control signal is applied to all four multiplexers 32 and the fourth control signal is applied to all four demultiplexers, then Figure 7 The chip 20 shown can be equivalent to Figure 1 If the data input from the second port 34 of the chip 20 shown is called the third data, and the data generated by the scan chain circuit 24 based on the third data is called the fourth data (for how to generate the fourth data based on the third data, please refer to the process of generating the second data based on the first data described above, which will not be repeated here), then in this case, M first ports 31 are used to input M third data in parallel, the scan chain circuit 24 is used to generate M fourth data based on the M third data, the scan output circuit 25 is used to output M fourth data in parallel, and M second ports 34 are used to output M fourth data from the chip in parallel.

[0262] For example, please refer to Figure 7If a first control signal is applied to all four multiplexers 32 and a fourth control signal is applied to all four demultiplexers 33, then in this case, input port 21 is used to receive a serial input signal; deserializer circuit 22 is used to output M first data in parallel based on the serial input signal; scan input circuit 23 is used to input the M first data to scan chain circuit 24; scan chain circuit 24 is used to generate M second data based on the M first data; scan output circuit 25 is used to output the M second data in parallel; and M second ports 34 are used to output the M second data from the chip in parallel.

[0263] For example, please refer to Figure 7 If a second control signal is applied to all four multiplexers 32 and a third control signal is applied to all four demultiplexers 33, then in this case, M first ports 31 are used to input M third data in parallel, the scan chain circuit 24 is used to generate M fourth data based on the M third data, the scan output circuit 25 is used to output M fourth data in parallel, and the serializer circuit 26 is used to generate another serial output signal different from the serial output signal mentioned above based on the M fourth data; the output port 27 is used to output this other serial output signal.

[0264] This application also provides a chip testing system, which includes a chip and external logic circuitry. The chip includes an input port, a deserializer circuit, a scan input circuit, and a scan chain circuit. The external logic circuitry is connected to the input port.

[0265] The deserializer circuit has M first output terminals, and the scanning input circuit has M first input terminals, where M is an integer greater than 1.

[0266] The input port is connected to the input terminal of the deserializer circuit. The i-th first output terminal among the M first output terminals is connected to the i-th first input terminal among the M first input terminals, where i is a positive integer less than or equal to M.

[0267] The scan chain circuit consists of multiple scan chains, and the input of each scan chain is connected to the output of the scan input circuit.

[0268] The technical solution provided in this application embodiment configures the chip's input port to be connected to M (first) input terminals of the scan input circuit via a deserializer circuit. This allows each input terminal of the scan input circuit to support data input through the same input port of the chip (after conversion by the deserializer circuit), thus providing the required test data to the scan chain circuit. Therefore, the chip only needs to provide one input port to the external logic circuit to support data input to any scan chain in the scan chain circuit, resulting in lower implementation costs.

[0269] In some embodiments, the external logic circuitry is used to send serial input signals to the input port.

[0270] The deserializer circuit is used to output M first data in parallel based on the serial input signal.

[0271] The scan input circuit is used to input M first data into the scan chain circuit, wherein different first data among the M first data are input into different scan chains.

[0272] The scan chain circuit is used to generate M second data points based on M first data points. The M second data points are used to determine the test results for the chip.

[0273] In the above embodiment, the serial input signal from a single input port of the external logic circuit is converted into M first data points by the deserializer circuit in parallel output. Different scan chains in the scan chain circuit can generate M second data points based on the M first data points. Therefore, the above scheme achieves simultaneous input of individual test data (first data points) to scan chains at different locations in the chip using a single input port, thereby improving the testing efficiency of the chip and reducing testing time.

[0274] In some embodiments, the external logic circuit has a test data input port.

[0275] The test data input port is used to receive M initial data points.

[0276] The external logic circuit is also used to convert the M first data into serial input signals.

[0277] In the above embodiment, the external logic circuit converts the test data (M first data points) into serial input signals outside the chip, and supports inputting the converted binary format test data from external devices. Therefore, this solution supports the use of traditional DFT test procedures without the need for special EDA (Electronic Design Automation) programs to generate test data.

[0278] In some embodiments, the chip further includes: M first ports and M multiplexers; the system further includes a test bench, which is connected to the M first ports respectively, and the test bench is used to input data to the first ports.

[0279] The i-th first output of the M first output terminals is connected to the first input port of the i-th multiplexer among the M multiplexers, and the i-th first port of the M first ports is connected to the second input port of the i-th multiplexer.

[0280] The output of the i-th multiplexer is connected to the i-th first input of the M first inputs.

[0281] In the above embodiments, on the one hand, in addition to connecting to the chip's input port via external logic circuitry, the test equipment can also be directly connected to the chip's first port. Therefore, the test equipment can also perform tests by inputting data to M first ports in parallel, according to actual needs. For example, during the chip's debugging and analysis phase, the test equipment can directly input data to the first port to eliminate the dependence on the port in the chip used for transmitting serial data (input port dependence).

[0282] This application also provides another chip testing system, which includes a chip and external logic circuitry. The chip includes a scan chain circuit, a scan output circuit, a serializer circuit, and an output port; the external logic circuitry is connected to the output port.

[0283] The scan output circuit has M second output terminals, and the serializer circuit has M second input terminals, where M is an integer greater than 1.

[0284] The scan chain circuit consists of multiple scan chains, and the output of each scan chain is connected to the input of the scan output circuit.

[0285] The i-th second output terminal among the M second output terminals is connected to the i-th second input terminal among the M second input terminals. The output terminal of the serializer circuit is connected to the output port, where i is a positive integer less than or equal to M.

[0286] The technical solution provided in this application embodiment configures the chip's output port to be connected to M (second) output terminals of the scan chain circuit via a serializer circuit. This ensures that each output terminal of the scan output circuit supports outputting data generated by the scan chain circuit (after integration by the serializer circuit) from the same output port. Therefore, the chip only needs to provide one output port to the external logic circuit to support outputting data generated by any scan chain in the scan chain circuit, resulting in lower implementation costs.

[0287] In some embodiments, the scan chain circuit is used to generate M second data based on M first data.

[0288] The scan output circuit is used to output M second data in parallel.

[0289] The serializer circuit is used to generate a serial output signal based on M second data.

[0290] An external logic circuit is used to generate a first discrimination signal based on the serial output signal output from the output port. The first discrimination signal is used to indicate the test result of the first test item for the chip.

[0291] The first test item refers to the test item that performs the test on the scan chains that are input with M first data respectively (testing whether these scan chains have defects).

[0292] In the above embodiment, different scan chains in the scan chain circuit can generate M second data based on M first data. Correspondingly, the serializer circuit converts the M second data output in parallel by the scan output circuit into a serial output signal that supports serial output from the output port. The external logic circuit can then generate a first discrimination signal indicating the test result of the first test item for the chip based on the serial output signal. Therefore, the above solution can output data generated in parallel by scan chains at different locations in the chip through a single output port, resulting in lower implementation costs.

[0293] In some embodiments, the external logic circuit has a test data input port.

[0294] The test data input port is used to receive the expected data corresponding to M second data points.

[0295] External logic circuitry is used to convert the serial output signal into M second data.

[0296] The external logic circuit is used to compare the M second data with the corresponding expected data to obtain the first discrimination signal.

[0297] The expected data corresponding to the second data refers to the data that the scan chain inputting the corresponding first data is expected to generate if the test passes. The second data is generated based on the corresponding first data.

[0298] In some embodiments, the first discrimination signal includes discrimination signals corresponding to M second data respectively. The discrimination signal corresponding to the second data is used to reflect whether it is consistent with the corresponding expected data. When the second data is consistent with the corresponding expected data, the discrimination signal corresponding to the second data indicates that the scan chain test that generated the second data has passed. When the second data is inconsistent with the corresponding expected data, the discrimination signal corresponding to the second data indicates that the scan chain test that generated the second data has failed.

[0299] In the above embodiment, the external logic circuit converts the serial output signal into M second data points for test analysis outside the chip. When the external logic circuit is connected to the test bench, since this solution realizes the reception of the serial signal by the external logic circuit as an additional hardware, the test bench only needs to receive the first discrimination signal generated by the external logic circuit, which reduces the accuracy requirements of the test bench and the complexity of the test bench's software program development.

[0300] In some embodiments, the chip further includes M demultiplexers and M second ports. The system also includes a test bench, which is connected to the M second ports and external logic circuitry, respectively.

[0301] The i-th second output of the M second output terminals is connected to the input port of the i-th demultiplexer of the M demultiplexers.

[0302] The first output port of the i-th demultiplexer is connected to the i-th second input port among the M second input ports, and the second output port of the i-th demultiplexer is connected to the i-th second port among the M second ports.

[0303] In the above embodiment, in addition to being connected to the external logic circuit, the test equipment is also connected to M second ports. Therefore, the test equipment can not only receive the signals generated by the external logic circuit based on the serial output signal, but also directly receive the data output by the scan output circuit, which further improves the test flexibility and helps to eliminate the dependence on the port in the chip used to transmit serial data (the dependence on the output port).

[0304] In some embodiments, the test equipment is configured to receive a first discrimination signal sent by an external logic circuit, the first discrimination signal being used to indicate the test result for a first test item of the chip; or...

[0305] The test equipment is used to generate a second discrimination signal based on the data output from the second port. The second discrimination signal is used to indicate the test result of the second test item for the chip.

[0306] The second test item may be the same as or different from the first test item; this application does not impose any restrictions on this.

[0307] In the above embodiment, the test equipment can obtain chip test results by analyzing the data output from the second port or directly obtain chip test results from the external logic circuit. Therefore, this solution can arbitrarily select the method of obtaining chip test results by the test equipment according to the requirements, making chip testing more flexible and convenient, and enabling the test equipment to flexibly process a large number of chips.

[0308] The structure of the chip testing system described in the above embodiments can be arbitrarily combined according to the design requirements of technicians. The following embodiments will describe this. For any details not described in detail in the above chip testing system embodiments, please refer to the following embodiments.

[0309] Please refer to Figure 8 The diagram illustrates a chip testing system provided in one possible implementation of this application. The system includes a chip 20 and external logic circuitry 40. The chip 20 includes: an input port 21, a deserializer circuit, a scan input circuit, a scan chain circuit, a scan output circuit, and a serializer circuit (circuits not explicitly labeled above). Figure 8 (not shown in the diagram) and output port 27; external logic circuit 40 is connected to input port 21 and output port 27 respectively.

[0310] In some embodiments, the external logic circuit 40 is an FPGA (Field Programmable Gate Array).

[0311] The deserializer circuit has M first output terminals, the scan input circuit has M first input terminals, the scan output circuit has M second output terminals, and the serializer circuit has M second input terminals, where M is an integer greater than 1.

[0312] The input port is connected to the input terminal of the deserializer circuit. The i-th first output terminal among the M first output terminals is connected to the i-th first input terminal among the M first input terminals, where i is a positive integer less than or equal to M.

[0313] The scan chain circuit includes multiple scan chains. One end of the scan chain is connected to the output of the scan input circuit, and the other end of the scan chain is connected to the input of the scan output circuit.

[0314] The i-th second output terminal among the M second output terminals is connected to the i-th second input terminal among the M second input terminals, and the output terminal of the serializer circuit is connected to the output port.

[0315] The technical solution provided in this application embodiment configures the chip's input ports to be connected to M (first) input terminals of the scan input circuit via a deserializer circuit, and configures the chip's output ports to be connected to M (second) output terminals of the scan output circuit via a serializer circuit. This allows each input terminal of the scan input circuit to support data input through the same input port of the chip (after conversion by the deserializer circuit), providing the required test data to the scan chain circuit. Similarly, each output terminal of the scan output circuit supports outputting data generated by the scan chain circuit (after integration by the serializer circuit) from the same output port of the chip. Therefore, the chip only needs to provide a pair of input / output ports to the external logic circuit to support testing any scan chain in the scan chain circuit, resulting in lower implementation costs.

[0316] In some embodiments, the external logic circuit 40 is used to send a serial input signal to the input port.

[0317] The deserializer circuit is used to output M first data in parallel based on the serial input signal.

[0318] The scan input circuit is used to input M first data into the scan chain circuit, wherein different first data among the M first data are input into different scan chains.

[0319] The scan chain circuit is used to generate M second data based on M first data.

[0320] The scan output circuit is used to output M second data in parallel.

[0321] The serializer circuit is used to generate a serial output signal based on M second data.

[0322] The external logic circuit is also used to generate a first discrimination signal based on the serial output signal output from the output port. The first discrimination signal is used to indicate the test result of the first test item for the chip.

[0323] The first test item refers to the test item that performs the test on the scan chains that are input with M first data respectively (testing whether these scan chains have defects).

[0324] In the above embodiment, the serial input signal input to the external logic circuit 40 from a single input port 21 is converted into M first data points by the deserializer circuit in parallel output. Different scan chains in the scan chain circuit can generate M second data points based on the M first data points. Correspondingly, the serializer circuit converts the M second data points output in parallel by the scan output circuit into a serial output signal that supports serial output from the output port. The external logic circuit 40 can then generate a first discrimination signal indicating the test result of the first test item for the chip based on the serial output signal. Therefore, the above scheme enables simultaneous testing of scan chains at different locations in the chip using separate test data (first data points) with a pair of input-output ports, thereby improving the testing efficiency of the chip and reducing the testing time.

[0325] In some embodiments, the external logic circuit 40 has a test data input port.

[0326] The test data input port is used to receive M first data points, and to receive the expected data corresponding to M second data points respectively.

[0327] In some embodiments, please refer to Figure 9 The external logic circuit 40 includes a memory 41.

[0328] The memory 41 is used to store M first data and to store the expected data corresponding to M second data respectively.

[0329] In some embodiments, on the host side (such as a tester's terminal device), a test file in a first format (which may be any data or code format that supports manual reading and editing) (including M first data in the first format and expected data corresponding to M second data in the first format) is converted into a binary format. The M first data in the binary format and the expected data (corresponding to M second data in the binary format) are written into the memory 41 included in the external logic circuit through the test data input port.

[0330] The external logic circuit 40 is also used to convert the M first data into serial input signals.

[0331] In some embodiments, please refer to Figure 9 The external logic circuit 40 includes a format conversion and transmission module 42, which is connected to the input ports of the memory 41 and the chip 20 respectively. It is used to convert the M first data stored in the memory 41 into serial input signals and input the serial input signals into the chip 20 from the input port.

[0332] The external logic circuit 40 is also used to convert the serial output signal into M second data.

[0333] In some embodiments, please refer to Figure 9 The external logic circuit 40 includes a format conversion receiving module 43, which is connected to the output port of the chip 20. It is used to receive the serial output signal output from the output port and convert the serial output signal into M second data.

[0334] The external logic circuit is used to compare the M second data with the corresponding expected data to obtain the first discrimination signal.

[0335] The expected data corresponding to the second data refers to the data that the scan chain inputting the corresponding first data is expected to generate if the test passes. The second data is generated based on the corresponding first data.

[0336] In some embodiments, please refer to Figure 9 The external logic circuit includes a comparator 44, which is connected to the format conversion receiving module 43 and the memory 41 respectively. The comparator 44 is used to compare the M second data with the corresponding expected data to obtain the first discrimination signal.

[0337] In some embodiments, the first discrimination signal includes discrimination signals corresponding to M second data respectively. The discrimination signal corresponding to the second data is used to reflect whether it is consistent with the corresponding expected data. When the second data is consistent with the corresponding expected data, the discrimination signal corresponding to the second data indicates that the scan chain test that generated the second data has passed. When the second data is inconsistent with the corresponding expected data, the discrimination signal corresponding to the second data indicates that the scan chain test that generated the second data has failed.

[0338] In the above embodiment, the external logic circuit 40 converts the test data (M first data points) into a serial input signal and the serial output signal into M second data points for test analysis outside the chip 20. It also supports inputting the converted binary format test data from external devices. Therefore, this solution supports the use of traditional DFT test procedures without requiring a special EDA (Electronic Design Automation) program to generate test data. Furthermore, when the external logic circuit 40 is connected to the test bench 50, since this solution implements the sending and receiving of serial signals using the external logic circuit 40 as additional hardware, the test bench 50 only needs to receive the first discrimination signal generated by the external logic circuit 40, reducing the accuracy requirements of the test bench and the complexity of its software development.

[0339] In some embodiments, please refer to Figure 8 The aforementioned chip 20 also includes: M first ports 31, M multiplexers, and M demultiplexers (unidentified components). Figure 8 (not shown in the diagram) and M second ports 34; the system also includes a test bench 50, which is connected to M first ports 31, M second ports 34 and external logic circuit 40 respectively.

[0340] The i-th first output of the M first output terminals is connected to the first input port of the i-th multiplexer among the M multiplexers, and the i-th first port of the M first ports is connected to the second input port of the i-th multiplexer.

[0341] The output port of the i-th multiplexer is connected to the i-th first input port among the M first input ports, and the i-th second output port among the M second output ports is connected to the input port of the i-th demultiplexer among the M demultiplexers.

[0342] The first output port of the i-th demultiplexer is connected to the i-th second input port among the M second input ports, and the second output port of the i-th demultiplexer is connected to the i-th second port among the M second ports.

[0343] In the above embodiment, on the one hand, in addition to being connected to the input / output ports of the chip 20 via the external logic circuit 40, the test equipment 50 can also be directly connected to the first port 31 and the second port 34 of the chip 20. Therefore, the test equipment 50 can also perform tests by inputting data in parallel to M first ports 31 according to actual needs. For example, during the debugging and analysis phase of the chip 20, the test equipment 50 can directly input data to the first port 31 and receive data from the second port 34 to eliminate the dependence on the ports in the chip 20 used for transmitting serial data (the dependence on the input port 21 and the output port 27).

[0344] In some embodiments, the test equipment 50 is used to receive a first discrimination signal sent by the external logic circuit 40.

[0345] In some embodiments, please refer to Figure 9 The external logic circuit 40 also includes a discrimination signal output module 45, which is used to send the first discrimination signal to the test machine 50.

[0346] In some embodiments, the test equipment 50 is used to input data to the first port and generate a second discrimination signal based on the data output from the second port. The second discrimination signal is used to indicate the test result of a second test item for the chip.

[0347] In some embodiments, the test equipment 50 is used to input third data to the first port and generate a second discrimination signal based on the fourth data output from the second port. The second discrimination signal is used to indicate the test result of a second test item for the chip.

[0348] In some embodiments, the test equipment 50 is used to compare the fourth data with the corresponding expected data to obtain a second discrimination signal.

[0349] The expected data corresponding to the fourth data refers to the data that the scan chain inputting the corresponding third data is expected to generate if the test passes. The fourth data is generated based on the corresponding third data.

[0350] In some embodiments, the second test item refers to a test item that performs a test on a scan chain for a third data input.

[0351] In some embodiments, the first discrimination signal includes a discrimination signal corresponding to the fourth data, which is used to reflect whether it is consistent with the corresponding expected data. In the case that the fourth data and the corresponding expected data are consistent, the discrimination signal corresponding to the fourth data indicates that the scan chain test that generated the fourth data has passed. In the case that the fourth data and the corresponding expected data are inconsistent, the discrimination signal corresponding to the fourth data indicates that the scan chain test that generated the fourth data has failed.

[0352] In some embodiments, the test equipment 50 is used to input third data in parallel to M first ports and generate a second discrimination signal based on M fourth data output in parallel from M second ports.

[0353] In some embodiments, the test equipment 50 is used to compare the M fourth data with the corresponding expected data to obtain a second discrimination signal.

[0354] In some embodiments, the second test item refers to a test item that performs a test on a scan chain that is input to M third data respectively.

[0355] In some embodiments, the second discrimination signal includes discrimination signals corresponding to M fourth data.

[0356] In some embodiments, please refer to Figure 8 The chip testing system also includes a host computer 60, and the testing platform 50 is also used to send the aforementioned first discrimination signal or second discrimination signal to the host computer 60. The host computer 60 is a device used to record and analyze chip test results, such as a terminal for chip testers.

[0357] In the above embodiment, the test station 50 can either input data to the first port 31 and analyze the data output from the second port 34 to obtain the chip test results, or it can directly obtain the chip test results from the external logic circuit 40. Therefore, this solution can arbitrarily select the method of inputting test data and obtaining chip test results for the test station 50 according to the requirements, making chip testing more flexible and convenient, and enabling the test station 50 to flexibly process a large number of chips.

[0358] For example, please refer to Figure 10 In scenario 1, the external logic circuit 40 is used to input a serial input signal to the input port 21 of the chip 20, and the output port 27 of the chip 20 is used to output a serial output signal. The external logic circuit 40 is used to convert the serial output signal into M second data, and compare the M second data with the corresponding expected data to obtain the first discrimination signal.

[0359] For example, please refer to Figure 10 In scenario 2, the test equipment 50 is used to input M third data in parallel to the M first ports 31 of the chip. The test equipment 50 is also used to receive M fourth data output in parallel from the M second ports 34 of the chip. The test equipment 50 is also used to compare the M fourth data with the corresponding expected data to obtain the second discrimination signal.

[0360] Of course, due to the presence of the multiplexer and demultiplexer, the first discrimination signal can also be generated by the test equipment 50, and the second discrimination signal can also be generated by the external test logic circuit 40.

[0361] For example, please refer to Figure 11 In scenario 3, the test equipment 50 is used to input M third data in parallel to M first ports, the chip's output port 27 is used to output another serial output signal as described above, and the external logic circuit 40 is used to convert the other serial output signal into M fourth data. The M fourth data are compared with the corresponding expected data to obtain the second discrimination signal.

[0362] For example, please refer to Figure 11In scenario 4, the external logic circuit 40 is used to input a serial input signal to the input port 21 of the chip, and the test equipment 50 is used to receive M second data output in parallel from the M second ports 34 of the chip. The test equipment 50 is also used to compare the M second data with the corresponding expected data to obtain the first discrimination signal.

[0363] Of course, the chip structure provided in this application also supports performing tests on the chip using only a single test data (first data / third data). This single test data can be input to the chip from the input port in the form of a serial signal, or it can be input directly from the first port. The above example is only used to illustrate the test process based on M test data.

[0364] Please refer to Figure 12 The diagram illustrates a flowchart of a testing method for a chip provided in one possible implementation of this application. The chip includes: an input port, a deserializer circuit, a scan input circuit, and a scan chain circuit; the deserializer circuit has M first output terminals, and the scan input circuit has M first input terminals, where M is an integer greater than 1; the input port is connected to the input terminal of the deserializer circuit, and the i-th first output terminal among the M first output terminals is connected to the i-th first input terminal among the M first input terminals, where i is a positive integer less than or equal to M; the scan chain circuit includes multiple scan chains, and the input terminals of the scan chains are connected to the output terminals of the scan input circuit; the method includes at least one of the following steps 1210 to 1240.

[0365] Step 1210: The input port receives the serial input signal.

[0366] Step 1220: The deserializer circuit outputs M first data in parallel based on the serial input signal.

[0367] Step 1230: The scan input circuit inputs M first data into the scan chain circuit, wherein different first data among the M first data are input into different scan chains.

[0368] Step 1240: The scan chain circuit generates M second data based on M first data. The M second data are used to determine the test results for the chip.

[0369] In some embodiments, the above-mentioned deserializer circuit includes a serial-to-parallel conversion module, an input buffer queue, and a clock alignment circuit, wherein the M first output terminals are all output terminals of the clock alignment circuit.

[0370] Step 1220 above includes the following steps: the serial-to-parallel conversion module converts the serial input signal into M first data; the input buffer queue stores the M first data; the clock alignment circuit outputs the M first data stored in the input buffer queue in parallel according to the clock data, and the clock data is used to determine the timing reference for the data received by the scanning input circuit.

[0371] In some embodiments, the scan input circuit includes N scan input modules, each scan input module having at least one of M first input terminals; the scan chain circuit includes N scan chain modules, each scan chain module including at least two scan chains, where N is an integer greater than 1; for the k-th scan chain module among the N scan chain modules, the input terminal of the scan chain in the k-th scan chain module is connected to the output terminal of the k-th scan input module among the N scan input modules, where k is a positive integer less than or equal to N.

[0372] Step 1230 includes the following steps: the k-th scan input module receives at least one first data from M first data; the k-th scan input module inputs the received at least one first data to the k-th scan chain module, wherein, in the case that the k-th scan input module receives multiple first data, the multiple first data are input to different scan chains in the k-th scan chain module.

[0373] Step 1240 includes the following steps: The k-th scan chain module generates at least one second data from M second data based on at least one first data.

[0374] Please refer to Figure 13 The diagram illustrates a flowchart of a testing method for a chip provided in another possible implementation of this application. The chip includes: a scan chain circuit, a scan output circuit, a serializer circuit, and an output port; the scan output circuit has M second output terminals, and the serializer circuit has M second input terminals, where M is an integer greater than 1; the scan chain circuit includes multiple scan chains, with the output terminals of the scan chains connected to the input terminals of the scan output circuit; the i-th second output terminal among the M second output terminals is connected to the i-th second input terminal among the M second input terminals, and the output terminal of the serializer circuit is connected to the output port, where i is a positive integer less than or equal to M; the method includes at least one of the following steps 1310 to 1340.

[0375] Step 1310: The scan chain circuit generates M second data based on M first data.

[0376] Step 1320: The scan output circuit outputs M second data in parallel.

[0377] Step 1330: The serializer circuit generates a serial output signal based on M second data points. The serial output signal is used to determine the test results for the chip.

[0378] Step 1340: Output a serial output signal from the output port.

[0379] In some embodiments, the serializer circuit includes an output buffer queue and a parallel-to-serial conversion module, and the M second input terminals are all input terminals of the output buffer queue.

[0380] Step 1330 above includes the following steps: the output buffer queue stores M second data; the parallel-to-serial conversion module converts the M second data stored in the output buffer queue into a serial output signal.

[0381] In some embodiments, the scan chain circuit includes N scan chain modules, each scan chain module including at least two scan chains. The scan output circuit includes N scan output modules, each scan output module having at least one of M second output terminals, where N is an integer greater than 1. For the k-th scan chain module among the N scan chain modules, the output terminal of the scan chain in the k-th scan chain module is connected to the input terminal of the k-th scan output module among the N scan output modules, where k is a positive integer less than or equal to N.

[0382] Step 1320 includes the following steps: The k-th scan output module outputs at least one of the M second data.

[0383] In some embodiments, step 1310 includes: the k-th scan chain module generating at least one second data based on at least one of the M first data.

[0384] Step 1320 includes: the k-th scan output module outputs at least one second data, wherein, in the case that the k-th scan chain module generates multiple second data, the multiple second data are output in parallel.

[0385] Another possible implementation of this application provides a chip testing method. The chip includes: an input port, a deserializer circuit, a scan input circuit, a scan chain circuit, a scan output circuit, a serializer circuit, and an output port. For details regarding the connection relationships of the structures in the chip described above, please refer to the embodiments above; they will not be repeated here. The method includes the following steps:

[0386] 1. The input port receives serial input signals.

[0387] 2. The deserializer circuit is used to output M first data in parallel based on the serial input signal.

[0388] 3. The scan input circuit inputs M first data into the scan chain circuit, wherein different first data among the M first data are input into different scan chains.

[0389] 4. The scan chain circuit generates M second data based on M first data.

[0390] 5. The scanning output circuit outputs M second data in parallel.

[0391] 6. The serializer circuit generates a serial output signal based on M second data points. The serial output signal is used to determine the test results for the chip.

[0392] 7. The output port outputs a serial output signal.

[0393] It should be noted that for details not described in the above method embodiments, please refer to the above chip embodiments.

[0394] An exemplary embodiment of this application also provides an electronic device including the aforementioned chip. This electronic device may be such as a mobile phone, tablet computer, multimedia playback device, PC (Personal Computer), wearable device, in-vehicle terminal device, VR (Virtual Reality) device, AR (Augmented Reality) device, MR (Mixed Reality) device, etc., and this application does not limit it to any particular type.

[0395] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0396] The above are merely exemplary embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims

1. A chip, characterized in that, The chip is in test mode. The chip includes: an input port, a deserializer circuit, a scan input circuit, and a scan chain circuit. The scan input circuit includes N scan input modules, the scan chain circuit includes N scan chain modules, and each scan chain module includes at least two scan chains, where N is an integer greater than 1. The deserializer circuit has M first output terminals, the scanning input circuit has M first input terminals, and each scanning input module has at least one of the M first input terminals, where M is an integer greater than 1. The input port is connected to the input terminal of the deserializer circuit, and the i-th first output terminal among the M first output terminals is connected to the i-th first input terminal among the M first input terminals, where i is a positive integer less than or equal to M; For the kth scan chain module among the N scan chain modules, the input end of the scan chain in the kth scan chain module is connected to the output end of the kth scan input module among the N scan input modules, where k is a positive integer less than or equal to N; The input port is used to receive serial input signals; The deserializer circuit is used to output M first data in parallel according to the serial input signal, and the first data is used to test the scan chain; The k-th scan input module is used to receive at least one of the M first data, and for any received first data, input the first data to the scan chain indicated by the scan chain address in the k-th scan chain module according to the scan chain address carried in the first data, wherein, when the k-th scan input module receives multiple first data, the multiple first data are input to different scan chains in the k-th scan chain module.

2. The chip according to claim 1, characterized in that, The scan chain circuit is used to generate M second data based on the M first data, and the M second data are used to determine the test results for the chip.

3. The chip according to claim 1, characterized in that, The deserializer circuit includes a serial-to-parallel conversion module, an input buffer queue, and a clock alignment circuit, and the M first output terminals are all output terminals of the clock alignment circuit. The serial-to-parallel conversion module is used to convert the serial input signal into the M first data; The input buffer queue is used to store the M first data; The clock alignment circuit is used to output the M first data stored in the input buffer queue in parallel according to the clock data, and the clock data is used to determine the timing reference for the data received by the scanning input circuit.

4. The chip according to claim 1, characterized in that, The k-th scan chain module is used to generate at least one second data among the M second data based on the at least one first data.

5. The chip according to any one of claims 1 to 4, characterized in that, The chip also includes M first ports and M multiplexers; The i-th first output terminal of the M first output terminals is connected to the first input port of the i-th multiplexer of the M multiplexers, and the i-th first port of the M first ports is connected to the second input port of the i-th multiplexer. The output port of the i-th multiplexer is connected to the i-th first input port among the M first input ports.

6. The chip according to claim 5, characterized in that, The i-th multiplexer is used to output the data received at the first input port of the i-th multiplexer from the output port of the i-th multiplexer when a first control signal is received. Upon receiving the second control signal, the data received at the second input port of the i-th multiplexer is output from the output port of the i-th multiplexer.

7. The chip according to claim 1, characterized in that, The chip also includes: a scan output circuit, a serializer circuit, and an output port; The scan output circuit has M second output terminals, and the serializer circuit has M second input terminals, where M is an integer greater than 1. The output terminal of the scan chain is connected to the input terminal of the scan output circuit; The i-th second output terminal of the M second output terminals is connected to the i-th second input terminal of the M second input terminals, and the output terminal of the serializer circuit is connected to the output port.

8. A chip, characterized in that, The chip is in test mode. The chip includes: a scan input circuit, a scan chain circuit, a scan output circuit, a serializer circuit, and an output port. The scan input circuit includes N scan input modules, the scan chain circuit includes N scan chain modules, and each scan chain module includes at least two scan chains, where N is an integer greater than 1. For the kth scan chain module among the N scan chain modules, the input end of the scan chain in the kth scan chain module is connected to the output end of the kth scan input module among the N scan input modules, where k is a positive integer less than or equal to N; The scan output circuit has M second output terminals, and the serializer circuit has M second input terminals, where M is an integer greater than 1. The scan chain circuit includes multiple scan chains, and the output end of the scan chain is connected to the input end of the scan output circuit; The i-th second output terminal among the M second output terminals is connected to the i-th second input terminal among the M second input terminals, and the output terminal of the serializer circuit is connected to the output port, where i is a positive integer less than or equal to M; The k-th scan input module is used to receive at least one first data from M first data, and, for any received first data, input the first data to the scan chain indicated by the scan chain address in the k-th scan chain module according to the scan chain address carried in the first data, wherein, when the k-th scan input module receives multiple first data, the multiple first data are input to different scan chains in the k-th scan chain module, and the first data is used to test the scan chain; The scan output circuit is used to output M second data in parallel, and the different second data among the M second data are generated by different scan chains; The serializer circuit is used to generate a serial output signal based on the M second data, and the serial output signal is used to determine the test result for the chip; The output port is used to output the serial output signal.

9. The chip according to claim 8, characterized in that, The serializer circuit includes an output buffer queue and a parallel-to-serial conversion module, and the M second input terminals are all input terminals of the output buffer queue; The output buffer queue is used to store the M second data; The parallel-to-serial conversion module is used to convert the M second data stored in the output buffer queue into the serial output signal.

10. The chip according to claim 8, characterized in that, The scanning output circuit includes N scanning output modules, each scanning output module having at least one of the M second output terminals, where N is an integer greater than 1; For the kth scan chain module among the N scan chain modules, the output terminal of the scan chain in the kth scan chain module is connected to the input terminal of the kth scan output module among the N scan output modules, where k is a positive integer less than or equal to N; The k-th scan output module is used to output at least one of the M second data.

11. The chip according to claim 10, characterized in that, The k-th scan chain module is used to generate the at least one second data based on at least one of the M first data; The k-th scan output module is used to output the at least one second data, wherein, when the k-th scan chain module generates multiple second data, the multiple second data are output in parallel.

12. The chip according to any one of claims 8 to 11, characterized in that, The chip also includes M demultiplexers and M second ports; The i-th second output terminal of the M second output terminals is connected to the input port of the i-th demultiplexer of the M demultiplexers; The first output port of the i-th demultiplexer is connected to the i-th second input port among the M second input ports, and the second output port of the i-th demultiplexer is connected to the i-th second port among the M second ports.

13. The chip according to claim 12, characterized in that, The i-th demultiplexer is used to output the data received at the input port of the i-th demultiplexer from the first output port of the i-th demultiplexer when a third control signal is received. Upon receiving the fourth control signal, the data received at the input port of the i-th demultiplexer is output from the second output port of the i-th demultiplexer.

14. The chip according to claim 8, characterized in that, The chip also includes: input ports and deserializer circuitry; The deserializer circuit has M first output terminals, and the scanning input circuit has M first input terminals, where M is an integer greater than 1; The input port is connected to the input terminal of the deserializer circuit, and the i-th first output terminal among the M first output terminals is connected to the i-th first input terminal among the M first input terminals, where i is a positive integer less than or equal to M; The input terminal of the scan chain is connected to the output terminal of the scan input circuit.

15. A chip testing system, characterized in that, The chip testing system includes a chip and an external logic circuit. The chip is in test mode. The chip includes: an input port, a deserializer circuit, a scan input circuit, and a scan chain circuit. The scan input circuit includes N scan input modules, and the scan chain circuit includes N scan chain modules. Each scan chain module includes at least two scan chains, where N is an integer greater than 1. The external logic circuit is connected to the input port. The deserializer circuit has M first output terminals, the scanning input circuit has M first input terminals, and each scanning input module has at least one of the M first input terminals, where M is an integer greater than 1. The input port is connected to the input terminal of the deserializer circuit, and the i-th first output terminal among the M first output terminals is connected to the i-th first input terminal among the M first input terminals, where i is a positive integer less than or equal to M; For the kth scan chain module among the N scan chain modules, the input end of the scan chain in the kth scan chain module is connected to the output end of the kth scan input module among the N scan input modules, where k is a positive integer less than or equal to N; The input port is used to receive serial input signals; The deserializer circuit is used to output M first data in parallel according to the serial input signal, and the first data is used to test the scan chain; The k-th scan input module is used to receive at least one of the M first data, and for any received first data, input the first data to the scan chain indicated by the scan chain address in the k-th scan chain module according to the scan chain address carried in the first data, wherein, when the k-th scan input module receives multiple first data, the multiple first data are input to different scan chains in the k-th scan chain module.

16. The system according to claim 15, characterized in that, The external logic circuit has a test data input port; The test data input port is used to receive the M first data; The external logic circuit is used to convert the M first data into the serial input signal; The external logic circuit is used to send the serial input signal to the input port; The scan chain circuit is used to generate M second data based on the M first data, and the M second data are used to determine the test results for the chip.

17. The system according to claim 15 or 16, characterized in that, The chip further includes: M first ports and M multiplexers; the system further includes a test bench, which is connected to the M first ports respectively, and the test bench is used to input data to the first ports; The i-th first output terminal of the M first output terminals is connected to the first input port of the i-th multiplexer of the M multiplexers, and the i-th first port of the M first ports is connected to the second input port of the i-th multiplexer. The output port of the i-th multiplexer is connected to the i-th first input port among the M first input ports.

18. A chip testing system, characterized in that, The chip testing system includes a chip and an external logic circuit. The chip includes a scan input circuit, a scan chain circuit, a scan output circuit, a serializer circuit, and an output port. The external logic circuit is connected to the output port. The scan input circuit includes N scan input modules, the scan chain circuit includes N scan chain modules, and each scan chain module includes at least two scan chains, where N is an integer greater than 1. For the kth scan chain module among the N scan chain modules, the input end of the scan chain in the kth scan chain module is connected to the output end of the kth scan input module among the N scan input modules, where k is a positive integer less than or equal to N; The scan output circuit has M second output terminals, and the serializer circuit has M second input terminals, where M is an integer greater than 1. The scan chain circuit includes multiple scan chains, and the output end of the scan chain is connected to the input end of the scan output circuit; The i-th second output terminal among the M second output terminals is connected to the i-th second input terminal among the M second input terminals, and the output terminal of the serializer circuit is connected to the output port, where i is a positive integer less than or equal to M; The k-th scan input module is used to receive at least one first data from M first data, and, for any received first data, input the first data to the scan chain indicated by the scan chain address in the k-th scan chain module according to the scan chain address carried in the first data, wherein, when the k-th scan input module receives multiple first data, the multiple first data are input to different scan chains in the k-th scan chain module, and the first data is used to test the scan chain; The scan output circuit is used to output M second data in parallel, and the different second data among the M second data are generated by different scan chains; The serializer circuit is used to generate a serial output signal based on the M second data, and the serial output signal is used to determine the test result for the chip; The output port is used to output the serial output signal.

19. The system according to claim 18, characterized in that, The external logic circuit has a test data input port; The scan chain circuit is used to generate the M second data based on the M first data; The external logic circuit is used to convert the serial output signal into the M second data; The test data input port is used to receive the expected data corresponding to the M second data respectively; The external logic circuit is further configured to compare the M second data with the corresponding expected data to obtain a first discrimination signal, which is used to indicate the test result of the first test item for the chip.

20. The system according to claim 18 or 19, characterized in that, The chip further includes: M demultiplexers and M second ports; the system further includes a test bench, which is connected to the M second ports and the external logic circuit respectively; The i-th second output terminal of the M second output terminals is connected to the input port of the i-th demultiplexer of the M demultiplexers; The first output port of the i-th demultiplexer is connected to the i-th second input port among the M second input ports, and the second output port of the i-th demultiplexer is connected to the i-th second port among the M second ports; The test equipment is used to receive a first discrimination signal sent by the external logic circuit, the first discrimination signal being used to indicate the test result for a first test item of the chip; or... The test equipment is used to generate a second discrimination signal based on the data output from the second port. The second discrimination signal is used to indicate the test result of a second test item for the chip.

21. A method for testing a chip, characterized in that, The chip is in test mode. The chip includes: an input port, a deserializer circuit, a scan input circuit, and a scan chain circuit. The scan input circuit includes N scan input modules, and the scan chain circuit includes N scan chain modules. Each scan chain module includes at least two scan chains, where N is an integer greater than 1. The deserializer circuit has M first output terminals, and the scan input circuit has M first input terminals. Each scan input module has at least one of the M first input terminals, where M is an integer greater than 1. The input port is connected to the input terminal of the deserializer circuit. The i-th first output terminal of the M first output terminals is connected to the i-th first input terminal of the M first input terminals, where i is a positive integer less than or equal to M. For the k-th scan chain module among the N scan chain modules, the input terminal of the scan chain in the k-th scan chain module is connected to the output terminal of the k-th scan input module among the N scan input modules, where k is a positive integer less than or equal to N. The method includes: The input port receives serial input signals; The deserializer circuit outputs M first data in parallel according to the serial input signal, and the first data is used to test the scan chain; The k-th scan input module receives at least one of the M first data, and for any received first data, inputs the first data into the scan chain indicated by the scan chain address in the k-th scan chain module according to the scan chain address carried in the first data, wherein, when the k-th scan input module receives multiple first data, the multiple first data are input into different scan chains in the k-th scan chain module; The scan chain circuit generates M second data based on the M first data, and the M second data are used to determine the test results for the chip.

22. A method for testing a chip, characterized in that, The chip includes: a scan input circuit, a scan chain circuit, a scan output circuit, a serializer circuit, and an output port. The scan input circuit includes N scan input modules, the scan chain circuit includes N scan chain modules, each scan chain module includes at least two scan chains, and N is an integer greater than 1. The scan output circuit has M second output terminals, and the serializer circuit has M second input terminals, where M is an integer greater than 1. For the k-th scan chain module among the N scan chain modules, the input terminal of the scan chain in the k-th scan chain module is connected to the output terminal of the k-th scan input module among the N scan input modules, where k is a positive integer less than or equal to N. The ith second output terminal among the M second output terminals is connected to the ith second input terminal among the M second input terminals, and the output terminal of the serializer circuit is connected to the output port, where i is a positive integer less than or equal to M. The method includes: The k-th scan input module receives at least one first data from M first data, and for any received first data, inputs the first data into the scan chain indicated by the scan chain address in the k-th scan chain module according to the scan chain address carried in the first data, wherein, when the k-th scan input module receives multiple first data, the multiple first data are input into different scan chains in the k-th scan chain module, and the first data is used to test the scan chain; The scan chain circuit generates M second data based on the M first data, wherein different second data are generated by different scan chains; The scan output circuit outputs the M second data in parallel; The serializer circuit generates a serial output signal based on the M second data, and the serial output signal is used to determine the test result for the chip; The output port outputs the serial output signal.

23. An electronic device, characterized in that, The electronic device includes a chip as described in any one of claims 1 to 7, or a chip as described in any one of claims 8 to 14.

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