DDR (Double Data Rate) model system for SoC (System on Chip) verification and use method thereof

Abstract

The invention discloses a DDR model system for SoC chip verification and a use method thereof, and relates to the technical field of chip design verification, and the system comprises a plurality of protocol interface modules which can be connected with a verified circuit module on an SoC chip and are used for receiving command sequences of different bus interface protocols; the initialization data module is used for storing key time sequence information required by initialization of the DDR controller, converting command sequences of different bus interface protocols into command sequences conforming to JEDEC DDR specifications, supporting direct loading of the key time sequence information in a backdoor mode, and automatically loading the key time sequence information to a register after resetting; and the address mapping module is used for mapping a logic address in the command sequence into a physical address which can be identified by the storage module, and writing data corresponding to the logic address into a corresponding position of the storage module. According to the invention, the initialization time of the DDR controller can be greatly shortened, and the simulation verification process of the SoC chip is accelerated.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design verification, and in particular to a DDR model system for SoC chip verification and a use method thereof. BACKGROUND

[0002] With the rapid development of integrated circuit technology, the design scale of System on Chip (SoC) chips grows exponentially, and the number of logic gates integrated in large SoC chips has reached the level of hundreds of billions, and the functional modules are increasingly complex. This complexity makes the simulation verification of SoC chips before tape-out a key bottleneck in the entire design process, and the simulation verification is difficult, time-consuming and costly. Therefore, it is crucial to develop efficient SoC chip verification acceleration technology.

[0003] In the simulation verification process of SoC chips, the initialization process of high-speed peripheral interface circuits such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR) controllers is an indispensable link. The initialization process of the DDR controller usually needs to be completed by the processor core (CPU Core) through sending a series of commands to configure the registers under the management of the operating system. Taking the fifth generation DDR (DDR5) controller as an example, the number of registers to be configured is as high as tens of thousands, so the initialization process of the DDR controller is extremely time-consuming. At the same time, if the initialization process of the DDR controller includes training operations, a large number of circuit algorithm iterations are required to adjust the signal timing, which will result in the DDR controller initialization time accounting for more than 99% of the entire SoC chip simulation time, and the time proportion of the actual access of the SoC chip other functional modules to the DDR for functional verification is less than 1%.

[0004] In the existing simulation verification process of SoC chips, the DDR controller initialization process needs to be completed before effective simulation verification of other circuit modules can be started, and the initialization process of the DDR controller is extremely time-consuming, which greatly affects the efficiency of the SoC chip simulation verification, thereby limiting the convergence time of the SoC chip simulation verification.

[0005] Therefore, a DDR model system for SoC chip verification and a use method thereof are proposed, which can greatly shorten the DDR controller initialization time, significantly accelerate the simulation verification process of the SoC chip, shorten the SoC chip verification period, and reduce the SoC chip research and development time cost. SUMMARY

[0006] To solve the above problems in the prior art, the application provides a DDR model system for SoC chip verification and a use method thereof, which can greatly shorten the initialization time of a DDR controller, significantly accelerate the simulation verification process of an SoC chip, shorten the verification period of the SoC chip, and reduce the development time cost of the SoC chip.

[0007] The technical scheme of the application is as follows:

[0008] In a first aspect, a DDR model system for SoC chip verification is provided, comprising:

[0009] A plurality of protocol interface modules capable of connecting the circuit modules to be verified on the SoC chip, for receiving command sequences of different bus interface protocols;

[0010] An initialization data module connected with the plurality of protocol interface modules respectively and configured with registers and a backdoor operation interface, for storing the key timing information required for initialization of the DDR controller, converting the command sequences of different bus interface protocols into command sequences conforming to the JEDEC DDR specification, supporting direct loading of the key timing information required for initialization of the DDR controller through the backdoor mode, and automatically loading the key timing information to the registers after reset;

[0011] An address mapping module connected with the initialization data module and the storage module respectively, for mapping the logical addresses in the command sequences into physical addresses recognizable by the storage module, and writing the data corresponding to the logical addresses into the corresponding positions of the storage module;

[0012] The storage module is used for storing data.

[0013] Further, in some embodiments, the plurality of protocol interface modules comprises a plurality of CHI protocol interface modules, AXI4 protocol interface modules, AXI4-Lite protocol interface modules, AXI4-Stream protocol interface modules, APB protocol interface modules, and AHB protocol interface modules.

[0014] Further, in some embodiments, the APB protocol interface module can write and read data to and from the initialization data module to verify whether the APB function of other circuit modules on the SoC chip is correct.

[0015] Further, in some embodiments, the AHB protocol interface module can write and read data to and from the initialization data module to verify whether the AHB function of other circuit modules on the SoC chip is correct.

[0016] Further, in some embodiments, the DDR model system is configured by a multi-bit mode selection parameter and a compilation macro definition to select different protocol interface modules to be enabled;

[0017] wherein the highest bit of the mode selection parameter is used to select to use the DDR model system or a real DDR controller, and the lower bits of the mode selection parameter are used to further select the protocol interface modules to be enabled when the DDR model system is selected.

[0018] The second aspect also provides a use method of the DDR model system for SoC chip verification as described above, comprising:

[0019] In the simulation compilation phase, the working mode of the DDR model system and the required protocol interface modules are selected by the set multi-bit mode selection parameter and the configuration macro definition;

[0020] At the beginning of the simulation, the key timing information required for the initialization of the DDR controller is directly loaded to the initialization data module by a backdoor method to skip the real DDR controller initialization process;

[0021] The DDR model system is enabled to interact with the circuit module to be verified in the SoC chip through the selected protocol interface module to complete the functional verification of the circuit module.

[0022] Further, in some embodiments, the DDR model system is configured by a multi-bit mode selection parameter and a compilation macro definition to select different protocol interface modules to be enabled;

[0023] The value of ddr_model[3] is determined;

[0024] If the value of ddr_model[3] is 1’b0, the working mode of the DDR model system is selected to be not enabled, and the macro definition of the real DDR controller is used to use the real DDR controller to perform the functional verification of the circuit module in the SoC chip, and the DDR controller is normally initialized;

[0025] If the value of ddr_model[3] is 1’b1, the working mode of the DDR model system is selected to be enabled, and the value of ddr_model[2] is further determined;

[0026] If the value of ddr_model[2] is 1’b0, the macro definition of the APB protocol interface module is used to connect the DDR model system to the circuit module to be verified in the SoC chip through the APB protocol interface module;

[0027] If the value of ddr_model[2] is 1’b1, the macro definition of AHB protocol interface module is used to make the DDR model system connect the circuit module to be verified in the SoC chip through the AHB protocol interface module;

[0028] ddr_model[3] represents the 3rd bit of the mode selection parameter; ddr_model[2] represents the 2nd bit of the mode selection parameter; 1’b0 represents a 1-bit wide binary number with a value of 0; and 1’b1 represents a 1-bit wide binary number with a value of 1.

[0029] Further, in some embodiments, the mode selection parameter with the set multi-bit width and the configuration macro definition are used to select the working mode of the DDR model system and the required protocol interface module, and the method further comprises the following steps:

[0030] When the value of ddr_model[3] is 1’b1, the value of ddr_model[1:0] is further judged.

[0031] If the value of ddr_model[1:0] is 2’b00, the macro definition of CHI protocol interface module is used to make the DDR model system connect the circuit module to be verified in the SoC chip through the CHI protocol interface module;

[0032] If the value of ddr_model[1:0] is 2’b01, the macro definition of AXI4 protocol interface module is used to make the DDR model system connect the circuit module to be verified in the SoC chip through the AXI4 protocol interface module;

[0033] If the value of ddr_model[1:0] is 2’b10, the macro definition of AXI4-Lite protocol interface module is used to make the DDR model system connect the circuit module to be verified in the SoC chip through the AXI4-Lite protocol interface module;

[0034] If the value of ddr_model[1:0] is 2’b11, the macro definition of AXI4-Stream protocol interface module is used to make the DDR model system connect the circuit module to be verified in the SoC chip through the AXI4-Stream protocol interface module;

[0035] ddr_model[1:0] represents a bit field containing two binary bits from the 1st bit to the 0th bit in the mode selection parameter; 2’b00 represents a 2-bit wide binary number with a value of binary 00; 2’b01 represents a 2-bit wide binary number with a value of binary 01; 2’b10 represents a 2-bit wide binary number with a value of binary 10; and 2’b11 represents a 2-bit wide binary number with a value of binary 11.

[0036] The main advantages of the technical solution of the present application are as follows:

[0037] The SoC chip verification-oriented DDR model system of the present application can replace real DDR controllers, DDR physical interfaces and SDRAM modules in a simulation verification environment, can quickly adapt to different SoC chip architectures and verification requirements by setting a plurality of different protocol interface modules to receive and process command sequences of different types of bus interface protocols, and is suitable for various verification scenarios such as module level, subsystem level and system level; the initialization data module is set, and the initialization data module supports direct loading of key timing information required for DDR controller initialization through a backdoor mode, and can automatically load the key timing information to the register after reset, which can completely avoid the time-consuming and lengthy DDR controller initialization process, significantly accelerate the simulation verification process of the SoC chip, shorten the SoC chip verification period, and reduce the SoC chip research and development time cost; and the initialization data module supports dynamic reconfiguration, which is convenient for verification engineers to perform boundary condition testing, fault injection and debugging, and helps to more comprehensively cover test points and improve the completeness of verification. BRIEF DESCRIPTION OF DRAWINGS

[0038] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present application, constitute a part of the present application, and the illustrative embodiments of the present application and their descriptions serve to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0039] Figure 1 A structural schematic diagram of an existing SoC chip provided for illustration;

[0040] Figure 2 A structural schematic diagram of a SoC chip verification-oriented DDR model system provided for the embodiments of the present application;

[0041] Figure 3 A structural schematic diagram of another SoC chip verification-oriented DDR model system provided for the embodiments of the present application;

[0042] Figure 4 A flowchart of a use method of a SoC chip verification-oriented DDR model system provided for the embodiments of the present application. DETAILED DESCRIPTION

[0043] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described below in connection with the specific embodiments of the present application and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without any creative work fall within the protection scope of the present application.

[0044] The technical solutions provided by the embodiments of the present application will be described in detail below in connection with the drawings.

[0045] Reference Figure 1The SoC chip mainly includes a core module, a Level 3 Cache module, a PCIE (Peripheral Component Interconnect Express) module, a UCIE (Universal Chiplet Interconnect Express) module, a DDR module and an SDRAM (Synchronous Dynamic Random-Access Memory) module. The DDR module includes a DDR controller and a DDR physical interface. The core module is a processor core of the SoC chip, and its function is mainly to send a command of a configuration register to set a register of the DDR controller and to interact with the SDRAM module through read and write commands. The Level 3 Cache module is mainly responsible for cache operation of data to improve data access efficiency. The PCIE module is a high-speed serial computer expansion bus module, and is mainly responsible for connection with a computer peripheral device and provides high-speed data transmission. The UCIE module is a technical standard for inter-chip interconnection, and is mainly responsible for realizing high-speed and low-delay communication between chips. The DDR controller is connected with the Level 3 Cache module and interacts with the Level 3 Cache module. The DDR controller can convert a logical address of a bus interface protocol (for example, AXI (Advanced eXtensible Interface), CHI (Coherent Hub Interface), APB (Advanced Peripheral Bus), AHB (Advanced High-performance Bus) and the like) memory access command sent by the Level 3 Cache module into a corresponding physical address, and converts the memory access command into a read and write command conforming to a JEDEC (Joint Electron Device Engineering Council) DDR specification. The DDR physical interface is mainly used to convert a logical signal sent by the DDR controller into an electrical signal and send the electrical signal to the SDRAM module. In addition, the DDR physical interface is also used to perform ZQ calibration, Write Leveling, Read Leveling, VREF Leveling and the like to ensure accuracy and stability of the signal. The SDRAM module is a core part of data storage, and is responsible for storing data and providing data according to a read command of the DDR physical interface and writing data according to a write command of the DDR physical interface.

[0046] Reference Figure 2In the first aspect, the embodiment of the present application provides a DDR model system for SoC chip verification, which is used for replacing a real DDR controller, a DDR physical interface and an SDRAM module in a simulation verification environment, and comprises the following parts:

[0047] a plurality of protocol interface modules, which are capable of connecting the circuit modules to be verified on the SoC chip, and are used for receiving command sequences of different bus interface protocols;

[0048] an initialization data module, which is connected with the plurality of protocol interface modules respectively, and is configured with registers and a backdoor operation interface, and is used for storing key timing information required by the DDR controller initialization, converting the command sequences of different bus interface protocols into command sequences conforming to the JEDEC DDR specification, supporting direct loading of the key timing information required by the DDR controller initialization through the backdoor mode, and automatically loading the key timing information to the registers after reset;

[0049] an address mapping module, which is connected with the initialization data module and the storage module respectively, and is used for mapping logical addresses in the command sequences into physical addresses recognizable by the storage module, and writing data corresponding to the logical addresses into corresponding positions of the storage module;

[0050] a storage module, which is used for storing data.

[0051] In the embodiment of the present application, one protocol interface module corresponds to one type of bus interface protocol, each protocol interface module is responsible for receiving the command sequence of the bus interface protocol corresponding thereto, and sends the command sequence to the initialization data module, so that the initialization data module converts the received command sequence of the bus interface protocol into a command sequence conforming to the JEDEC DDR specification. By designing a plurality of protocol interface modules and making the plurality of protocol interface modules correspond to a plurality of different bus interface protocols respectively, the DDR model system can have high flexibility and scalability, and can be seamlessly connected into the SoC chip verification environment based on different bus architectures.

[0052] In the embodiment of the present application, the initialization data module is internally configured with a register and a backdoor operation interface, and can be connected with a device in a SoC chip verification environment through the backdoor operation interface. The initialization data module is used for storing key timing information required by a DDR controller initialization. The key timing information is an important parameter for ensuring normal operation of a system under different protocols. The initialization data module can convert a command sequence of different bus interface protocols sent by different protocol interface modules into a command sequence conforming to a JEDEC DDR specification according to the key timing information. Based on the above conversion processing, the DDR model system can support a plurality of complex AMBA (Advanced Microcontroller Bus Architecture) bus interface protocols, and ensure normal and efficient operation under different verification environments. The initialization data module supports direct loading of the key timing information required by the DDR controller initialization through a backdoor mode. After reset, the key timing information can be automatically loaded into the register, that is, the verification environment can directly write the key timing information into the internal register of the initialization data module through the backdoor operation interface, so as to quickly complete the initialization process and avoid a long real DDR controller initialization process.

[0053] In the embodiment of the present application, the backdoor mode can be implemented through force and deposit commands of SystemVerilog or a uvm_hdl_deposit() function of UVM (Universal Verification Methodology).

[0054] In the embodiment of the present application, the address mapping module receives the converted command sequence sent by the initialization data module, maps and converts a logical address corresponding to the command sequence into a physical address recognizable by the storage module according to a predefined address mapping rule, and writes data corresponding to the command sequence into a corresponding position of the storage module.

[0055] In the embodiment of the present application, the storage module performs read and write operations of data according to the address provided by the address mapping module, and stores the data to simulate the function of an SDRAM module in a SoC chip.

[0056] The SoC chip verification-oriented DDR model system provided by the embodiment of the application can replace a real DDR controller, a DDR physical interface and a SDRAM module in a simulation verification environment, can quickly adapt to different SoC chip architectures and verification requirements by setting a plurality of different protocol interface modules to receive and process command sequences of different types of bus interface protocols, and is suitable for various verification scenes such as a module level, a subsystem level and a system level; the initialization data module is set, the initialization data module supports direct loading of key timing information required for DDR controller initialization through a backdoor mode, and the key timing information can be automatically loaded into a register after reset, so that a time-consuming and lengthy DDR controller initialization process can be completely avoided, the simulation verification process of the SoC chip is significantly accelerated, the SoC chip verification period is shortened, and the SoC chip research and development time cost is reduced; and the initialization data module supports dynamic reconfiguration, which facilitates boundary condition testing, fault injection and debugging by verification engineers, helps to more comprehensively cover test points, and improves the completeness of verification.

[0057] Reference Figure 3 Further, in the embodiment of the application, the plurality of protocol interface modules include a plurality of CHI (Coherent Hub Interface) protocol interface modules, AXI4 (Advanced eXtensible Interface 4) protocol interface modules, AXI4-Lite (Advanced eXtensible Interface 4-Lite) protocol interface modules, AXI4-Stream (Advanced eXtensible Interface 4-Stream) protocol interface modules, APB (Advanced Peripheral Bus) protocol interface modules and AHB (Advanced High-performance Bus) protocol interface modules.

[0058] The CHI protocol interface module is used to connect an external device conforming to the CHI protocol and receive a command sequence of the CHI protocol; the AXI4 protocol interface module is used to connect an external device conforming to the AXI4 protocol and receive a command sequence of the AXI4 protocol; the AXI4-Lite protocol interface module is used to connect an external device conforming to the AXI4-Lite protocol and receive a command sequence of the AXI4-Lite protocol; the AXI4-Stream protocol interface module is used to connect an external device conforming to the AXI4-Stream protocol and receive a command sequence of the AXI4-Stream protocol; the APB protocol interface module is used to connect an external device conforming to the APB protocol and receive a command sequence of the APB protocol; and the AHB protocol interface module is used to connect an external device conforming to the AHB protocol and receive a command sequence of the AHB protocol.

[0059] In the embodiment of the present application, by setting the CHI protocol interface module, the AXI4 protocol interface module, the AXI4-Lite protocol interface module, the AXI4-Stream protocol interface module, the APB protocol interface module and the AHB protocol interface module, the DDR model system can be adapted to various bus interface protocols including CHI protocol, AXI protocol, APB protocol and AHB protocol, so as to meet different use scenarios and verification requirements.

[0060] Further, in the embodiment of the present application, the APB protocol interface module can write data to and read data from the initialization data module to verify whether the APB function of other circuit modules on the SoC chip is correct; and the AHB protocol interface module can write data to and read data from the initialization data module to verify whether the AHB function of other circuit modules on the SoC chip is correct.

[0061] Further, in the embodiment of the present application, the DDR model system is configured by a multi-bit mode selection parameter and a compilation macro definition to select different protocol interface modules to be enabled.

[0062] Specifically, in the embodiment of the present application, a multi-bit mode selection parameter is set to determine the protocol interface modules to be enabled by the DDR model system; wherein the highest bit of the mode selection parameter is used to select the DDR model system or the real DDR controller, and the lower bits of the mode selection parameter are used to further select the protocol interface modules to be enabled when the DDR model system is selected.

[0063] In the embodiment of the present application, a mode selection parameter with a bit width of 4 bits is set to determine the protocol interface modules to be enabled by the DDR model system.

[0064] Reference Figure 4 In a second aspect, the embodiment of the present application further provides a use method of the DDR model system for SoC chip verification as described above, and the method comprises the following steps:

[0065] Step 1, in the simulation compilation phase, the working mode of the DDR model system and the required protocol interface module are selected by setting a multi-bit mode selection parameter and a configuration macro definition;

[0066] Step 2, at the beginning of simulation, the key timing information required for initialization of the DDR controller is directly loaded to the initialization data module by a backdoor method to skip the real DDR controller initialization process;

[0067] Step 3, the DDR model system interacts with the circuit module to be verified in the SoC chip through the selected protocol interface module, and completes the function verification of the circuit module.

[0068] Specifically, in the embodiment of the application, when the working mode of the DDR model system is selected by setting the mode selection parameter of the multi-bit width and the configuration macro definition, the working mode of the DDR model system includes enabling and not enabling; when the working mode of the DDR model system is selected as enabling, the DDR model system is used for the function verification of the circuit module in the SoC chip; when the working mode of the DDR model system is selected as not enabling, the real DDR controller is used for the function verification of the circuit module in the SoC chip. When the DDR model system is used for the function verification of the circuit module in the SoC chip, the key timing information required for the initialization of the DDR controller is directly loaded to the initialization data module through a backdoor mode to skip the initialization process of the real DDR controller; when the real DDR controller is used for the function verification of the circuit module in the SoC chip, the DDR controller is normally initialized.

[0069] Further, based on the above-mentioned specific multiple protocol interface modules, in the embodiment of the application, the working mode of the DDR model system and the required protocol interface module are selected by setting the mode selection parameter of the multi-bit width and the configuration macro definition, including the following steps:

[0070] The value of ddr_model[3] is judged;

[0071] If the value of ddr_model[3] is 1’b0, the working mode of the DDR model system is selected as not enabling, and the macro definition of the real DDR controller is used to use the real DDR controller for the function verification of the circuit module in the SoC chip, and the DDR controller is normally initialized;

[0072] If the value of ddr_model[3] is 1’b1, the working mode of the DDR model system is selected as enabling, and the value of ddr_model[2] is further judged;

[0073] If the value of ddr_model[2] is 1’b0, the macro definition of the APB protocol interface module is used to make the DDR model system connect the circuit module to be verified in the SoC chip through the APB protocol interface module;

[0074] If the value of ddr_model[2] is 1’b1, the macro definition of the AHB protocol interface module is used to make the DDR model system connect the circuit module to be verified in the SoC chip through the AHB protocol interface module.

[0075] In the embodiment of the present application, ddr_model[3] represents the 3rd bit of the mode selection parameter; ddr_model[2] represents the 2nd bit of the mode selection parameter; 1’b0 represents a 1-bit binary number with a value of 0; and 1’b1 represents a 1-bit binary number with a value of 1.

[0076] Further, based on the above-mentioned plurality of protocol interface modules with specific settings, in the embodiment of the present application, the mode selection parameter with a plurality of bit widths and the configuration macro definition are used to select the working mode of the DDR model system and the required protocol interface module, and the following steps are further included:

[0077] When the value of ddr_model[3] is 1’b1, the value of ddr_model[1:0] is further determined.

[0078] If the value of ddr_model[1:0] is 2’b00, the macro definition of the CHI protocol interface module is used, so that the DDR model system is connected to the circuit module to be verified in the SoC chip through the CHI protocol interface module.

[0079] If the value of ddr_model[1:0] is 2’b01, the macro definition of the AXI4 protocol interface module is used, so that the DDR model system is connected to the circuit module to be verified in the SoC chip through the AXI4 protocol interface module.

[0080] If the value of ddr_model[1:0] is 2’b10, the macro definition of the AXI4-Lite protocol interface module is used, so that the DDR model system is connected to the circuit module to be verified in the SoC chip through the AXI4-Lite protocol interface module.

[0081] If the value of ddr_model[1:0] is 2’b11, the macro definition of the AXI4-Stream protocol interface module is used, so that the DDR model system is connected to the circuit module to be verified in the SoC chip through the AXI4-Stream protocol interface module.

[0082] In the embodiment of the present application, ddr_model[1:0] represents a bit field containing two binary bits from the 1st bit to the 0th bit in the mode selection parameter; 2’b00 represents a 2-bit binary number with a value of binary 00; 2’b01 represents a 2-bit binary number with a value of binary 01; 2’b10 represents a 2-bit binary number with a value of binary 10; and 2’b11 represents a 2-bit binary number with a value of binary 11.

[0083] In the embodiment of the present application, the working mode of the DDR model system and the required protocol interface module are selected by the above-mentioned manner, the interface of different bus protocols can be freely configured, thereby improving the flexibility and scalability of the DDR model system, so as to be suitable for different SoC chip function verification test scenes; the key timing information required for initialization of the DDR controller is directly loaded through the backdoor mode, which can reduce the initialization time of the DDR controller, accelerate the verification speed of other circuit modules on the SoC chip, thereby shortening the convergence period of the SoC chip simulation verification, and reducing the chip research and design cost.

[0084] It should be noted that, in this paper, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. In addition, "front", "back", "left", "right", "up", "down" in this paper are referred to the placement state shown in the drawings.

[0085] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A DDR model system for SoC chip verification, characterized in that, Comprise: A plurality of protocol interface modules capable of connecting the verified circuit modules on the SoC chip, for receiving command sequences of different bus interface protocols; An initialization data module connected with the plurality of protocol interface modules respectively, and configured with registers and a backdoor operation interface, for storing key timing information required by DDR controller initialization, converting command sequences of different bus interface protocols into command sequences conforming to JEDEC DDR specifications, supporting direct loading of key timing information required by DDR controller initialization through a backdoor mode, and automatically loading key timing information to registers after reset; An address mapping module connected with the initialization data module and a storage module respectively, for mapping logical addresses in the command sequences into physical addresses recognizable by the storage module, and writing data corresponding to the logical addresses into corresponding positions of the storage module; The storage module for storing data.

2. The SoC-chip verification oriented DDR model system of claim 1, wherein, The plurality of protocol interface modules comprise: a plurality of CHI protocol interface modules, AXI4 protocol interface modules, AXI4-Lite protocol interface modules, AXI4-Stream protocol interface modules, APB protocol interface modules, and AHB protocol interface modules.

3. The SoC-chip verification oriented DDR model system of claim 2, wherein, The APB protocol interface module can write and read data to and from the initialization data module to verify whether the APB function of other circuit modules on the SoC chip is correct.

4. The SoC-chip verification oriented DDR model system of claim 2, wherein, The AHB protocol interface module can write and read data to and from the initialization data module to verify whether the AHB function of other circuit modules on the SoC chip is correct.

5. The SoC-chip verification oriented DDR model system of claim 1, wherein, The DDR model system is configured through a multi-bit-width mode selection parameter and a compilation macro definition to select different protocol interface modules to be enabled; The highest bit of the mode selection parameter is used to select the DDR model system or the real DDR controller, and the lower bits of the mode selection parameter are used to further select the protocol interface modules to be enabled when the DDR model system is selected.

6. A method of using the SoC-chip verification oriented DDR model system according to any one of claims 1 to 5, characterized by, Comprise: In the simulation compilation phase, the working mode of the DDR model system and the required protocol interface modules are selected through the set multi-bit-width mode selection parameter and the configuration macro definition; At the beginning of simulation, the key timing information required by DDR controller initialization is directly loaded to the initialization data module through a backdoor mode to skip the real DDR controller initialization process; The DDR model system interacts with the verified circuit modules in the SoC chip through the selected protocol interface modules to complete the functional verification of the circuit modules.

7. The method of using a SoC-chip verification oriented DDR model system according to claim 6, wherein, The working mode of the DDR model system and the required protocol interface modules are selected through the set multi-bit-width mode selection parameter and the configuration macro definition, comprising the following steps: Judge the value of ddr_model[3]; If the value of ddr_model[3] is 1’b0, the working mode of the DDR model system is not enabled, and the macro definition of the real DDR controller is used to use the real DDR controller to perform the functional verification of the circuit modules in the SoC chip, and the DDR controller is normally initialized; If the value of ddr_model[3] is 1’b1, the working mode of the DDR model system is selected as enabled, and it is further determined whether the value of ddr_model[2] is 1’b0; If the value of ddr_model[2] is 1’b0, a macro definition of an APB protocol interface module is used, so that the DDR model system is connected to the circuit module to be verified in the SoC chip through the APB protocol interface module; If the value of ddr_model[2] is 1’b1, a macro definition of an AHB protocol interface module is used, so that the DDR model system is connected to the circuit module to be verified in the SoC chip through the AHB protocol interface module; Wherein, ddr_model[3] represents the 3rd bit of the mode selection parameter; ddr_model[2] represents the 2nd bit of the mode selection parameter; 1’b0 represents a 1-bit wide binary number with a value of 0; 1’b1 represents a 1-bit wide binary number with a value of 1. 8.The method of using the SoC-chip-verification-oriented DDR model system according to claim 7, wherein, The mode selection parameter with a set multi-bit width and the configuration macro definition for selecting the working mode of the DDR model system and the required protocol interface module further include the following steps: When the value of ddr_model[3] is 1’b1, it is further determined whether the value of ddr_model[1:0] is 2’b00; If the value of ddr_model[1:0] is 2’b00, a macro definition of a CHI protocol interface module is used, so that the DDR model system is connected to the circuit module to be verified in the SoC chip through the CHI protocol interface module; If the value of ddr_model[1:0] is 2’b01, a macro definition of an AXI4 protocol interface module is used, so that the DDR model system is connected to the circuit module to be verified in the SoC chip through the AXI4 protocol interface module; If the value of ddr_model[1:0] is 2’b10, a macro definition of an AXI4-Lite protocol interface module is used, so that the DDR model system is connected to the circuit module to be verified in the SoC chip through the AXI4-Lite protocol interface module; If the value of ddr_model[1:0] is 2’b11, a macro definition of an AXI4-Stream protocol interface module is used, so that the DDR model system is connected to the circuit module to be verified in the SoC chip through the AXI4-Stream protocol interface module; Wherein, ddr_model[1:0] represents a bit field containing two binary bits from the 1st bit to the 0th bit in the mode selection parameter; 2’b00 represents a 2-bit wide binary number with a value of binary 00; 2’b01 represents a 2-bit wide binary number with a value of binary 01; 2’b10 represents a 2-bit wide binary number with a value of binary 10; 2’b11 represents a 2-bit wide binary number with a value of binary 11.

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