System on chip, method and device supporting inter-core communication and storage medium

Abstract

Disclosed are a system-on-chip, method and device supporting inter-core communication, and a storage medium, the system-on-chip comprising: a communication controller for generating a first interrupt signal in response to receiving a first data frame; the first processor core is used for responding to the first interrupt signal, acquiring a first data frame and writing the first data frame into a special data buffer area corresponding to the communication controller; reading a plurality of data frames stored in the special data buffer area according to a preset period; forwarding the plurality of read data frames to a second processor core; and a second processor core for receiving the plurality of first data frames from the first processor core. According to the system on chip disclosed by the invention, the real-time performance of sensing the application by the second processor core can be improved to a certain extent, the frequent interaction between the cores can be reduced, the CPU resource overhead is reduced, and the real-time response capability of the first processor core and the reliability and safety of vehicle control are further improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of inter-core communication in intelligent driving chips, and particularly relates to an on-chip system supporting inter-core communication, a method, an apparatus and a storage medium. BACKGROUND

[0002] In an intelligent driving chip with a heterogeneous core architecture, a large computing core (for example, an Acore core) needs to obtain key information such as radar data and chassis control data from a microcontroller unit core (MCU core) in real time, for environment perception fusion and decision logic processing, to meet the requirements of the intelligent driving system for environment perception and computing performance.

[0003] However, the data transmission mechanism of the traditional CAN bus is that the CAN controller corresponding to the MCU core directly forwards a frame of CAN data to the Acore core through a network interface (such as Ethernet) or a serial peripheral interface (SPI) after receiving the frame of CAN data. In a high-frequency CAN data transmission scenario, not only can the real-time performance of the Acore core perception application not be truly improved, but also CPU resources will be excessively consumed, which seriously affects the real-time response capability of the MCU core, and further affects the reliability and safety of vehicle control. SUMMARY

[0004] In a high-frequency CAN data transmission scenario, the CAN data is forwarded from the MCU core to the Acore core frame by frame, which not only makes it difficult to improve the real-time performance of the Acore core perception application, but also excessively consumes CPU resources, seriously affects the real-time response capability of the MCU core, and further affects the reliability and safety of vehicle control.

[0005] To solve the above technical problems, the first aspect embodiment of the present disclosure provides an on-chip system supporting inter-core communication, which comprises:

[0006] At least one communication controller coupled to the first processor core, the communication controller being configured to generate a first interrupt signal in response to receiving a first data frame;

[0007] The first processor core is configured to obtain the first data frame and write the first data frame into a dedicated data buffer corresponding to the communication controller in response to the first interrupt signal; read a plurality of data frames stored in the dedicated data buffer according to a preset period; and forward the plurality of read data frames to the second processor core; wherein the plurality of data frames include the first data frame.

[0008] a second processor core configured to receive a plurality of first data frames from the first processor core.

[0009] In a second aspect, embodiments of the present disclosure provide a method for inter-core communication on a system-on-chip, the system-on-chip comprising a first processor core, a second processor core, and at least one communication controller coupled to the first processor core, the method comprising:

[0010] generating, by the communication controller, a first interrupt signal in response to receiving the first data frame;

[0011] acquiring, by the first processor core, the first data frame and writing the first data frame into a dedicated data buffer corresponding to the communication controller in response to the first interrupt signal; reading a plurality of data frames stored in the dedicated data buffer according to a preset period; and forwarding the plurality of read data frames to the second processor core, wherein the plurality of data frames comprises the first data frame.

[0012] receiving, by the second processor core, the plurality of first data frames from the first processor core.

[0013] In a third aspect, embodiments of the present disclosure provide an integrated circuit, comprising the system-on-chip supporting data communication and at least one dedicated data buffer according to the first aspect, the dedicated data buffer being configured to store the first data frame received by the communication controller.

[0014] In a fourth aspect, embodiments of the present disclosure provide an electronic device, comprising a processor and a memory storing processor-executable instructions; the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method for inter-core communication on a system-on-chip according to the second aspect.

[0015] In a fifth aspect, embodiments of the present disclosure provide a computer-readable storage medium storing a computer program for executing the method for inter-core communication on a system-on-chip according to the second aspect.

[0016] In a sixth aspect, embodiments of the present disclosure provide an apparatus for inter-core communication on a system-on-chip, the apparatus comprising:

[0017] a generating module configured to generate, by the communication controller, a first interrupt signal in response to receiving the first data frame;

[0018] a forwarding module configured to acquire, by the first processor core, the first data frame and write the first data frame into a dedicated data buffer corresponding to the communication controller in response to the first interrupt signal; read a plurality of data frames stored in the dedicated data buffer according to a preset period; and forward the plurality of read data frames to the second processor core, wherein the plurality of data frames comprises the first data frame.

[0019] receive, by the second processor core, the plurality of first data frames from the first processor core.

[0020] A seventh aspect of the present disclosure provides a computer program product, when instructions in the computer program product are executed by a processor, the instructions perform the method for inter-core communication on a system on chip provided in the second aspect.

[0021] The system on chip supporting inter-core communication provided by the embodiments of the present disclosure can avoid data loss by setting a dedicated data buffer and saving the received first data frames in the dedicated data buffer corresponding to the communication controller in a communication controller interrupt-driven manner. Then, the read data frames are transmitted to the second processor core through periodic reading and forwarding of the dedicated data buffer. In this way, the second processor core can read and forward the complete time window of data frames within a controllable delay, improve the real-time performance of the second processor core to a certain extent, reduce the frequent interaction between cores, reduce the CPU resource overhead, and further improve the real-time response capability of the first processor core and the reliability and safety of vehicle control. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a structural schematic diagram of a system on chip supporting inter-core communication provided by an example embodiment of the present disclosure.

[0023] Figure 2 is a flowchart of a method for inter-core communication on a system on chip provided by an example embodiment of the present disclosure.

[0024] Figure 3 is a flowchart of another method for inter-core communication on a system on chip provided by an example embodiment of the present disclosure.

[0025] Figure 4 is a flowchart of still another method for inter-core communication on a system on chip provided by an example embodiment of the present disclosure.

[0026] Figure 5 is a flowchart of still another method for inter-core communication on a system on chip provided by an example embodiment of the present disclosure.

[0027] Figure 6 is a structural schematic diagram of an apparatus for inter-core communication on a system on chip provided by an example embodiment of the present disclosure.

[0028] Figure 7 is a structural schematic diagram of another apparatus for inter-core communication on a system on chip provided by an example embodiment of the present disclosure.

[0029] Figure 8 is a structural schematic diagram of an integrated circuit provided by an example embodiment of the present disclosure.

[0030] Figure 9 is a structural schematic diagram of an electronic device provided by an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] For the purpose of interpreting the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, obviously, the described embodiments are only part of the embodiments of the present disclosure, not all the embodiments, it should be understood that the present disclosure is not limited by the example embodiments.

[0032] It should be noted that: unless otherwise specified, the relative arrangement, numerical expression and numerical value of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0033] SUMMARY

[0034] In the intelligent driving chip of the heterogeneous core architecture, the Controller Area Network (CAN) controller is usually integrated in the Microcontroller Unit Core (MCU core) with high real-time performance and high security level, to ensure the reliability and stability of vehicle operation. However, with the continuous improvement of the demand for environmental perception and computing performance of intelligent driving systems (including automatic driving systems and auxiliary driving systems), the Acore core needs to obtain key information such as radar data and chassis control data from the MCU core in real time, for environmental perception fusion and decision logic processing.

[0035] However, the data transmission mechanism of the traditional CAN bus is that the CAN controller corresponding to the MCU core directly forwards the frame of CAN data to the Acore core through a network interface (such as Ethernet) or a Serial Peripheral Interface (SPI) after receiving each frame of CAN data. This scheme of forwarding after receiving each frame of CAN data can only guarantee the minimum delay of data forwarding, and the essence of the real-time performance of the Acore core perception application is to read and forward the complete time window data within a controllable delay. Therefore, in the high-frequency CAN data transmission scenario, not only can the real-time performance of the Acore core perception application not be truly improved, but also the Central Processing Unit (CPU) resources will be excessively consumed, which seriously affects the real-time response capability of the MCU core, and further affects the reliability and safety of vehicle control.

[0036] To solve the above technical problems, the embodiment of the present application provides an on-chip system supporting inter-core communication. The on-chip system receives a first data frame through at least one communication controller coupled with a first processor core, and generates a first interrupt signal in response to receiving the first data frame. The first processor core acquires the first data frame and writes the first data frame into a dedicated data buffer corresponding to the communication controller in response to the first interrupt signal, so as to avoid data loss. The first processor core reads a plurality of data frames stored in the dedicated data buffer according to a preset period, and forwards the read data frames to a second processor core, so as to realize batch forwarding of data. In this way, the second processor core can read and forward the data frames of a complete time window within a controllable delay, which improves the real-time performance of the second processor core in perceiving the application to a certain extent, reduces the frequent interaction between cores, reduces the CPU resource overhead, and further improves the real-time response capability of the first processor core and the reliability and safety of vehicle control.

[0037] Exemplary system

[0038] Figure 1 FIG. 1 is a structural schematic diagram of an on-chip system supporting inter-core communication according to an example embodiment of the present disclosure. As shown in the figure, the on-chip system 10 supporting inter-core communication can include a first processor core 101, a second processor core 102, and at least one communication controller 103 coupled with the first processor core 101. Wherein, Figure 1

[0039] The communication controller 103 is configured to generate a first interrupt signal in response to receiving a first data frame.

[0040] The first processor core 101 is configured to acquire the first data frame and write the first data frame into a dedicated data buffer corresponding to the communication controller 103 in response to the first interrupt signal; read a plurality of data frames stored in the dedicated data buffer according to a preset period; and forward the read plurality of data frames to the second processor core 102; wherein the plurality of data frames include the first data frame.

[0041] The second processor core 102 is configured to receive the plurality of first data frames from the first processor core 101.

[0042] For example, the first processor core 101 can correspond to an MCU core, the second processor core 102 can correspond to an Acore core, and the communication controller 103 can correspond to a CAN controller.

[0043] ​In some examples, the number of communication controllers 103 in the system on chip 10 can be determined according to the sensor types and the automotive safety integrity level (ASIL) outside the system on chip 10. The number of communication controllers 103 in the system on chip 10 is not limited in the embodiments of the present disclosure, and the embodiments of the present disclosure are exemplarily described by taking an example that the system on chip 10 includes 10 communication controllers 103. For example, the system on chip 10 can include 10 CAN controllers, CAN0, CAN1, CAN2, …, and CAN9.

[0044] The first data frame can be a single frame of sensor data received by the CAN controller from the sensor outside the system on chip. If the sensor is a millimeter wave radar, the first data frame is a radar data frame; if the sensor is a chassis sensor, the first data frame is a chassis data frame. The type of the first data frame is not limited in the embodiments of the present disclosure.

[0045] The first interrupt signal can correspond to an interrupt request (IRQ) of the MCU core. Taking an example that the communication controller 103 is a CAN controller, when a receive first in first out (RX FIFO) buffer in the CAN controller receives the first data frame, a CPU interrupt is triggered, and an IRQ is sent to a general interrupt controller (GIC).

[0046] Exemplarily, the dedicated data buffer can be a memory region configured by the MCU core in an off-chip double data rate synchronous dynamic random access memory (DDR SDRAM, referred to as DDR for short) and used for storing data frames. The data buffer can be implemented in a ring structure to realize ring writing, and therefore, can also be referred to as a ring buffer. In some examples, the total capacity of the data buffer can be greater than or equal to a preset byte, and the total capacity of the data buffer is not limited in the embodiments of the present disclosure. The embodiments of the present disclosure are exemplarily described by taking an example that the total capacity of the data buffer is greater than or equal to 10,000 bytes.

[0047] It can be understood that if the system on chip 10 includes 10 CAN controllers, CAN0, CAN1, CAN2, …, and CAN9, 10 dedicated data buffers can be respectively configured in the DDR. For example, the DDR can include a CAN0 buffer corresponding to CAN0, a CAN1 buffer corresponding to CAN1, a CAN2 buffer corresponding to CAN2, …, and a CAN9 buffer corresponding to CAN9.

[0048] The preset period can be determined according to the delay time requirement of data transmission and the overall efficiency requirement of the system. The embodiment of the present disclosure does not limit the size of the preset period, and the embodiment of the present disclosure takes 3 ms (milliseconds) as an example for exemplary description.

[0049] Exemplarily, the MCU core can copy the first data frame in the interrupt processing program in response to the IRQ, and copy the copy of the first data frame into the special data buffer corresponding to the CAN controller. Then, the CAN forwarding service function is called by the application layer software according to the preset period, all CAN data frames to be forwarded are read from the special data buffer, and a plurality of CAN data frames are obtained. Finally, the plurality of CAN data frames read are forwarded to the Acore core through the inter-core communication protocol between the MCU core and the Acore core. The Acore core receives the plurality of CAN data frames.

[0050] Taking the CAN0 corresponding to the CAN0 buffer as an example, the MCU core can copy the copy of the first data frame into the CAN0 buffer, and read all CAN data frames received by the CAN0 from the CAN0 buffer.

[0051] The on-chip system supporting inter-core communication provided by the embodiment of the present disclosure can avoid data loss by setting a special data buffer and saving the received first data frame in the special data buffer corresponding to the communication controller in a real-time manner through the communication controller interrupt driving. Then, the read data frame is transmitted to the second processor core through periodic reading and forwarding of the special data buffer. In this way, not only can the second processor core read and forward the complete time window data frame within a controllable delay, but also can improve the real-time performance of the second processor core to a certain extent, and reduce the frequent interaction between the cores, reduce the CPU resource overhead, and further improve the real-time response ability of the first processor core and the reliability and safety of vehicle control.

[0052] In the related art, the MCU core needs to forward the CAN data frame to the Acore core through a network interface (such as Ethernet) or SPI, and the switch buffer delay and protocol stack scheduling delay caused by network traffic fluctuation in the forwarding process can significantly affect the real-time performance and stability of the system.

[0053] Based on the technical problem, continuing to refer to Figure 1 The first processor core 101 of the present disclosure for forwarding the plurality of read data frames to the second processor core 102 can include:

[0054] The first processor core 101 is specifically configured to encode a plurality of data frames according to a preset inter-core communication protocol to generate a data packet; write the data packet into a shared memory area of the first processor core 101 and the second processor core 102, and trigger a second interrupt signal to send the second interrupt signal to the second processor core 102;

[0055] The second processor core 102 is configured to receive a plurality of first data frames from the first processor core 101, and can include: the second processor core 102 is configured to read the data packet from the shared memory area in response to the second interrupt signal, and parse the data packet based on the inter-core communication protocol to obtain the plurality of first data frames.

[0056] Exemplarily, the inter-core communication protocol can be a protocol specification that ensures the reliability, real-time performance and consistency of data transmission between the MCU core and the Acore core. The inter-core communication protocol can include access rules, data interaction formats and synchronization mechanisms. In some examples, the data interaction format can refer to the custom data packet format shown in Table 1 below.

[0057] Table 1

[0058]

[0059]

[0060] In Table 1, startFlag0-startFlag4 are fixed packet header delimiters for identifying the start of the data packet.

[0061] frameType is the type of CAN data frame, which distinguishes between ordinary CAN data frames and Controller Area Network with Flexible Data-Rate (CAN FD) frames.

[0062] length is the total length of the CAN data.

[0063] crc is a Cyclic Redundancy Check (CRC) check on the data in the packet to ensure the correctness of data transmission.

[0064] endFlag0-endFlag3 are fixed packet trailer delimiters for identifying the end of the data packet.

[0065] And the frame format of the CAN data frame stored in the field data of N bytes can refer to Table 2 below.

[0066] Table 2

[0067]

[0068] In Table 2, the time stamp is used to record the accurate time when the CAN data frame is received by the MCU core, facilitating subsequent time synchronization and delay calculation.

[0069] The id is the identifier of the CAN data frame, used to distinguish different message types.

[0070] The count is used to detect whether there is a loss of CAN data frames within the data packet.

[0071] The frameType is used to distinguish the type of CAN data frame in detail, supporting multiple CAN protocol formats.

[0072] The channel is used to indicate which CAN controller the CAN data frame comes from, which is helpful for multi-channel parallel processing.

[0073] The length is the length of the actual CAN data, ensuring the integrity of the data.

[0074] The data is used to store the actual data content of the CAN data frame.

[0075] The shared memory area can be a special area pre-configured by the Acore core in the DDR, used to store CAN data frames to be transmitted between cores. In some examples, the Acore core also needs to configure the shared memory area as a dual-core shared access mode to support access by the MCU core and the Acore core.

[0076] The second interrupt signal can correspond to the IRQ of the Acore core. In some examples, the second interrupt signal can be a GIC interrupt signal, and can be triggered by the MCU core writing the GIC register to generate the GIC. In other examples, the second interrupt signal can be a Mailbox interrupt signal, and can be triggered by the MCU core writing the sending register of the Mailbox to generate the Mailbox. The type and generation method of the second interrupt signal are not limited in the embodiments of the present disclosure, and the embodiments of the present disclosure are exemplarily described taking the GIC interrupt signal generated by the MCU core writing the GIC register as an example.

[0077] The MCU core can encode and package multiple CAN data frames according to the data packet format as shown in Table 1 specified by the inter-core communication protocol to obtain a CAN data packet, and write the CAN data packet into the shared memory area between the MCU core and the Acore core, so that the Acore core can quickly access. Then, the second interrupt signal is generated through the GIC or the Mailbox, and is sent to the Acore core. Thus, the Acore core is informed that there is a new CAN data frame to be read, thereby realizing efficient inter-core communication.

[0078] The virtual CAN driver on the core can respond to the second interrupt signal, read the forwarded CAN data packet from the shared memory region in the interrupt handling program, and parse the CAN data packet based on an inter-core communication protocol to obtain a plurality of first data frames.

[0079] The system on chip provided by the embodiments of the present disclosure can forward a plurality of data frames from the first processor core to the second processor core through shared memory and inter-core interrupts, which can not only avoid the problem of high CPU resource consumption caused by forwarding data frames through a complex Ethernet protocol stack or a complex SPI protocol stack, but also reduce transmission delay by simplifying the transmission path of the data frames, ensure that the data transmission delay is within a controllable range, and meet the real-time requirements of the system. Furthermore, since only one scheduling point corresponding to the second interrupt signal is involved in the data frame forwarding process, the stability of the transmission delay is further ensured.

[0080] In some embodiments of the present disclosure, in a high-frequency CAN data transmission scenario, the data consistency and integrity of data transmission directly affect the reliability of the system. If data loss or errors occur in data transmission, it may cause control instruction delay, perception information distortion, and thus trigger vehicle control abnormalities, decision biases, and other risks, and even endanger driving safety in severe cases. Based on this, the embodiments of the present disclosure can introduce multi-level reliability guarantee measures in the data forwarding mechanism. For example, the second processor core can perform timeout detection, frame loss detection, and / or data consistency detection on the data packet after receiving the data packet, and when the detection is successful, parse the data packet to obtain a plurality of first data frames, and when the detection fails, report error information.

[0081] With reference to the foregoing Figure 1 As shown in the foregoing Figure 1 The second processor core 102 is specifically configured to respond to the second interrupt signal to perform timeout detection, frame loss detection, and / or data consistency detection on the data packet to obtain a data detection result; respond to the data detection result representing that the data detection is successful to parse the data packet based on an inter-core communication protocol to obtain a plurality of first data frames; and write the plurality of first data frames into a preset cache space in the second processor core 102.

[0082] The data detection result can be a result obtained by detecting the data packet, and can include data detection success and data detection failure. If the detection items include timeout detection, frame loss detection, and / or data consistency detection, the data detection result can include a timeout detection result corresponding to the timeout detection, a frame loss detection result corresponding to the frame loss detection, and / or a data consistency detection result corresponding to the data consistency detection.

[0083] The timeout detection result can include timeout detection success and timeout detection failure; the frame loss detection result can include frame loss detection success and frame loss detection failure; and the data consistency detection result can include data consistency detection success and data consistency detection failure.

[0084] For example, the detection items include timeout detection, frame loss detection and data consistency detection. If all of the timeout detection result, the frame loss detection result and the data consistency detection result are successful, it is determined that the data detection is successful. If at least one of the timeout detection result, the frame loss detection result and the data consistency detection result fails, it is determined that the data detection fails. For example, if the timeout detection result is timeout detection failure, it is determined that the data detection fails. For another example, if the timeout detection result is timeout detection failure and the data consistency detection result is data consistency detection failure, it is determined that the data detection fails.

[0085] In some examples, the second processor core 102 is specifically configured to: obtain, from the data packet, a first receiving time stamp of each first data frame, a cycle count value of each first data frame, and a cyclic redundancy check value of the data packet; perform timeout detection on the data packet based on the first receiving time stamp of each first data frame to obtain a timeout detection result; perform frame loss detection on the data packet based on the cycle count value of each first data frame to obtain a frame loss detection result; and / or perform data consistency detection on the data packet based on the cyclic redundancy check value of the data packet to obtain a data consistency detection result.

[0086] The first receiving time stamp can be a global system time when the CAN controller receives the first data frame, corresponding to the time stamp in Table 2. The cycle count value is a value of a cycle counter, corresponding to the count in Table 2, and the cycle count value is incremented by 1 for each transmitted data packet, and returns to 0 after reaching 255. The cyclic redundancy check value is a preset CRC check code, corresponding to the crc in Table 1.

[0087] For example, the detection items include timeout detection, frame loss detection and data consistency detection. The Acore core can read the value of the time stamp field, the value of the count field and the value of the crc field of the CAN data packet based on the application layer software, perform timeout detection on the CAN data packet based on the value of the time stamp field of each first data frame to obtain a timeout detection result, perform frame loss detection on the data packet based on the value of the count field of each first data frame to obtain a frame loss detection result, and perform data consistency detection on the data packet based on the value of the crc field of the CAN data packet to obtain a data consistency detection result.

[0088] The embodiments of the present disclosure do not limit the order of performing the timeout detection, the frame loss detection and the data consistency detection on the CAN data packet by the Acore core, and the embodiments of the present disclosure are exemplarily described by taking the example that the Acore core performs the timeout detection first, then performs the frame loss detection, and finally performs the data consistency detection.

[0089] Exemplarily, the Acore core can first determine the time of receiving each first data frame, and perform the timeout detection based on the time and the value of the time stamp field of the corresponding first data frame to obtain a timeout detection result. The time of receiving each first data frame by the Acore core can be the global system time at the time of receiving each first data frame by the Acore core. In some examples, the Acore core can read the global system time at the current time by calling an application programming interface (API). For example, the Acore core can call a system predefined interface to read the time value at the current time from a global clock source (for example, a system clock manager, a hardware timer, etc.) of the system as the global system time.

[0090] The Acore core can determine whether the value of the count field of each first data frame is the same as the expected sequence number. If the value of the count field of each first data frame is the same as the expected sequence number, it is determined that there is no loss and disorder of the CAN data frame, that is, the frame loss detection result is frame loss detection success; if the value of the count field of the first data frame is different from the expected sequence number, it is determined that there is loss and / or disorder of the CAN data frame, that is, the frame loss detection result is frame loss detection failure.

[0091] The expected sequence number can be a sequence number reference value determined by the Acore core, and can be determined according to the value of the first count field received by the Acore core. The embodiments of the present disclosure do not limit the determination manner of the expected sequence number.

[0092] The Acore core can calculate the CRC value of the CAN data packet, and compare the calculated CRC value with the value of the field crc in the CAN data packet. If the calculated CRC value is the same as the value of the field crc, it is determined that the data consistency detection result is data consistency detection success; if the calculated CRC value is different from the value of the field crc, it is determined that the data consistency detection result is data consistency detection failure.

[0093] In some embodiments of the present disclosure, the second processor core 103 is configured to perform timeout detection on the data packet based on the first receiving time stamp of each first data frame to obtain a timeout detection result, which can include: obtaining a second time stamp of the second processor core 103 receiving the data packet; calculating a transmission time based on the second time stamp and the first receiving time stamp of each first data frame; and determining that the timeout detection result is timeout detection success in response to the transmission time being less than or equal to a transmission time threshold.

[0094] The transmission time threshold is a preset maximum allowed data transmission time consumption.

[0095] For example, the second time stamp can be a global system time when the Acore core receives the CAN data packet (including the first data frame), and can be determined by the Acore core calling an API interface. The implementation of obtaining the second time stamp is similar to that of the Acore core determining the time of receiving each first data frame, which will not be described here in the embodiments of the present disclosure.

[0096] In some examples, the transmission time threshold can be between 4 ms and 6 ms. The embodiments of the present disclosure do not limit the size of the transmission time threshold, and the embodiments of the present disclosure will be exemplarily described with the transmission time threshold being 5 ms.

[0097] The Acore core can call an API interface to obtain the second time stamp of the CAN data packet, calculate the difference between the second time stamp and the first receiving time stamp to obtain the transmission time, and compare the size relationship between the transmission time and the transmission time threshold. In the case that the transmission time is less than or equal to the transmission time threshold, it is determined that the timeout detection result is timeout detection success, and in the case that the transmission time is greater than the transmission time threshold, it is determined that the timeout detection result is timeout detection failure. In this way, in the case that the transmission time threshold can accurately reflect the maximum allowed data transmission time consumption in the actual transmission scenario, the size relationship between the transmission time of the first data frame and the transmission time threshold can accurately determine the timeout detection result.

[0098] In some examples, the Acore core can further include a plurality of cache regions. If the system on chip 10 includes 10 CAN controllers CAN0, CAN1, CAN2, …, CAN9, the Acore core corresponds to 10 cache regions. After the Acore core reads the data packet from the shared memory region in response to the second interrupt signal, the data packet can be cached in the corresponding cache region. The cache region corresponds to the CAN controller receiving the plurality of first data frames of the data packet.

[0099] The plurality of first data frames obtained by parsing the data packet (different from the original CAN data frame received by the CAN controller) can be of the same format as the CAN data frame in the CAN data packet. In some examples, the plurality of first data frames obtained by parsing the data packet can refer to the data in the data field shown in Table 1 above, i.e., each first data frame can correspond to the CAN data frame shown in Table 2.

[0100] The core nucleus can call an API to parse the CAN data packet to obtain a plurality of first data frames, and write the plurality of first data frames to a preset cache space on the Acore core specified by the API.

[0101] In some examples, the API can be int canRecvMsgFrame(const char*target, CanFrame*frame, Pack_Info*pack), where target is the name of the CAN channel (corresponding to a CAN controller), frame is the preset cache space specified by the API, and pack is a structure specified by the API.

[0102] The Acore core can call int canRecvMsgFrame(const char*target, CanFrame*frame, Pack_Info*pack) to read the data packet from the storage area corresponding to target in the Acore core, parse the data packet to obtain a plurality of first data frames, and write the plurality of first data frames to the cache space frame.

[0103] The system on chip provided by the embodiments of the present disclosure can avoid resource waste caused by parsing data packets that have transmission timeout, frame loss, and / or data inconsistency, and ensure the integrity and reliability of CAN data frame transmission, by performing timeout detection, frame loss detection, and / or data consistency detection on the data packet, and only parsing and saving the data packet when the data detection result indicates that the timeout detection, frame loss detection, and / or data consistency detection are all successful.

[0104] In some other embodiments of the present disclosure, the second processor core 102 is further configured to, in response to the data detection result indicating that the data detection fails, save error information and continue to receive a new data packet.

[0105] The Acore core can record error information in the case of timeout detection failure, frame loss detection failure and / or data consistency detection failure, identify that the current CAN data packet is unavailable or discard the current CAN data packet, and continue to transmit a new CAN data packet. In this way, the Acore core can timely report diagnostic information when detecting data consistency errors, frame loss or transmission timeout, and continue to receive new data packets to restore data transmission capability and ensure continuous and stable operation of the system.

[0106] In some embodiments of the present disclosure, with continued reference to Figure 1 As shown, the second processor core 102 is further configured to, in response to the data detection result representing successful data detection, parse the data packet based on an inter-core communication protocol to obtain data length information, write the data length information to a preset interface, read the data length information from the preset interface based on a user program, read a preset number of data frames from a preset cache space based on the data length information, and wherein the preset number of data frames is not more than a total number of frames corresponding to the data length information.

[0107] The data length information can include a total length of the data packet (corresponding to the length field in Table 1) and a total length of the CAN data frame (corresponding to the length field in Table 2). The preset interface can be a structure body specified by an API.

[0108] The Acore core can call int canRecvMsgFrame(const char*target, CanFrame*frame, Pack_Info*pack) to read the data packet from the storage area corresponding to target in the Acore core, parse the data packet to obtain a plurality of first data frames and data length information, and write the plurality of first data frames to the cache space frame and write the data length information to the pack structure body specified by the API.

[0109] The definition of the pack structure body can be as follows:

[0110] struct CanFrame{

[0111] uint64_t time_stamp;

[0112] uint32_t canid;

[0113] uint8_t count;

[0114] uint8_t can_type;

[0115] uint8_t can_channel;

[0116] uint8_t len;

[0117] uint8_t data

[60] ;

[0118] };

[0119] In the definition, time_stamp is the time stamp of the CAN frame reception; canid is the identifier of the CAN frame; count is the cycle counter of the CAN frame in the data packet, used for frame loss detection; can_type is the type of the CAN data frame, supporting multiple protocol formats; and can_channel is used to indicate the CAN controller channel from which the CAN data frame originates.

[0120] After the Acore core calls int canRecvMsgFrame(const char*target, CanFrame*frame, Pack_Info*pack), the pack structure is read, the total number of CAN data frames buffered in the preset buffer space is determined according to the data length information, and no more than the preset number of data frames are read from the preset buffer space based on the user layer program of the Acore core, which can facilitate the Acore core application layer to process and manage data.

[0121] In some embodiments of the present disclosure, the first processor core 101 is further configured to, in response to the first interrupt signal, transmit the first data frame to an interface layer corresponding to the first processor core 101.

[0122] When the MCU core responds to the first interrupt signal, it can first call the CanIF_RxIndication API to report the first data frame to the CAN interface layer (CANIF module), so that the application layer service of the MCU core can use the first data frame, thereby not affecting the use of the first data frame by the MCU core.

[0123] It can be understood that the above embodiments are exemplarily described taking the CAN data frame inter-core forwarding mechanism received by the communication controller 103 as an example. Since all communication controllers 103 in the system on chip 10 adopt the same forwarding mechanism, the system on chip 10 can support data parallel forwarding of multiple CAN controllers corresponding to the MCU core, and the Acore core can respond to different interrupt numbers to read the CAN data corresponding to each CAN controller from the corresponding dedicated data buffer. This not only enhances the scalability of the system, but also adapts to the needs of multiple CAN buses and safety isolation in modern automotive electronic systems.

[0124] Exemplary method

[0125] Corresponding to the above-mentioned system on chip 10 supporting inter-core communication, Figure 2is a flowchart of a method for inter-core communication on a system-on-chip according to an example embodiment of the present disclosure. As shown in Figure 2 The method for inter-core communication on a system-on-chip can be applied to a system-on-chip 10 as shown in Figure 1 and can include the following steps 201 to 203.

[0126] Step 201, generating a first interrupt signal by the communication controller in response to receiving the first data frame.

[0127] Step 202, obtaining the first data frame by the first processor core in response to the first interrupt signal and writing the first data frame into a dedicated data buffer corresponding to the communication controller; reading a plurality of data frames stored in the dedicated data buffer according to a preset period; and forwarding the plurality of read data frames to the second processor core.

[0128] The plurality of data frames include the first data frame.

[0129] Step 203, receiving the plurality of first data frames from the first processor core by the second processor core.

[0130] In some embodiments, as shown in Figure 3 based on the above-described Figure 2 embodiment, the step 202 of forwarding the plurality of read data frames to the second processor core by the first processor core can include the following steps 2021 and 2022.

[0131] Step 2021, encoding the plurality of data frames by the first processor core according to a preset inter-core communication protocol to generate a data packet.

[0132] Step 2022, writing the data packet into a shared memory region of the first processor core and the second processor core, and triggering generation of a second interrupt signal and sending the second interrupt signal to the second processor core.

[0133] Continuing to refer to Figure 3 based on the above-described Figure 2 embodiment, the step 203 of receiving the plurality of first data frames from the first processor core by the second processor core can include the following step 2031.

[0134] Step 2031, reading the data packet from the shared memory region by the second processor core in response to the second interrupt signal, and parsing the data packet based on the inter-core communication protocol to obtain the plurality of first data frames.

[0135] In some embodiments, as shown in Figure 4 based on the above-described Figure 3On the basis of the embodiment shown, step 2031 comprises the following steps 401 to 403.

[0136] Step 401 comprises: performing, by the second processor core, timeout detection, frame loss detection, and / or data consistency detection on the data packet in response to the second interrupt signal, to obtain a data detection result.

[0137] Step 402 comprises: performing, by the second processor core, based on the inter-core communication protocol, parsing on the data packet to obtain a plurality of first data frames in response to the data detection result indicating that the data detection is successful.

[0138] Step 403 comprises: writing, by the second processor core, the plurality of first data frames into a preset cache space in the second processor core.

[0139] In some embodiments, the method for inter-core communication on a system on chip further comprises: in response to the data detection result indicating that the data detection fails, saving error information and continuing to receive a new data packet.

[0140] In some embodiments, step 401 comprises: in response to the second interrupt signal, obtaining, by the second processor core, a first reception timestamp of each first data frame, a cyclic count value of each first data frame, and a cyclic redundancy check value of the data packet from the data packet; performing, by the second processor core, based on the first reception timestamp of each first data frame, timeout detection on the data packet to obtain a timeout detection result; performing, by the second processor core, based on the cyclic count value of each first data frame, frame loss detection on the data packet to obtain a frame loss detection result; and / or performing, by the second processor core, based on the cyclic redundancy check value of the data packet, data consistency detection on the data packet to obtain a data consistency detection result; wherein the data detection result comprises the timeout detection result, the frame loss detection result, and the data consistency detection result.

[0141] In some embodiments, performing, by the second processor core, based on the first reception timestamp of each first data frame, timeout detection on the data packet to obtain a timeout detection result in response to the second interrupt signal comprises: obtaining, by the second processor core, a second timestamp of receiving the data packet in response to the second interrupt signal; calculating, by the second processor core, based on the second timestamp and the first reception timestamp of each first data frame, a transmission time; and determining, by the second processor core, that the timeout detection is successful in response to the transmission time being less than or equal to a transmission time threshold value; wherein the transmission time threshold value is a preset maximum allowed data transmission time consumption.

[0142] In some embodiments, the method for inter-core communication on a system on chip further comprises: in response to the data detection result representing that the data detection is successful, parsing the data packet based on the inter-core communication protocol to obtain data length information; writing the data length information to the preset interface; reading the data length information from the preset interface based on the user program; reading a preset number of data frames from the preset cache space based on the data length information; and wherein the preset number of data frames does not exceed the total number of frames corresponding to the data length information.

[0143] As shown in the above Figure 5 embodiments, based on the above Figure 2 embodiments, the method for inter-core communication on a system on chip further comprises: step 204, transmitting the first data frame to the interface layer corresponding to the first processor core through the first processor core in response to the first interrupt signal.

[0144] As for the method for inter-core communication on a system on chip in the above embodiments, the specific manner in which each step performs an operation and the corresponding beneficial effects have been described in detail in the corresponding embodiment part of the aforementioned system on chip supporting data communication part, and can be referred to the corresponding operation manner and beneficial technical effects of the above exemplary system part, which will not be described here again.

[0145] Exemplary apparatus

[0146] Figure 6 is a structural schematic diagram of an inter-core communication device for a system on chip provided by an exemplary embodiment of the present disclosure. As shown in the above Figure 6 embodiments, the inter-core communication device 60 for a system on chip can comprise an interrupt signal generation module 601, a forwarding module 602 and a receiving module 603.

[0147] The interrupt signal generation module 601 is configured to generate a first interrupt signal through a communication controller in response to receiving a first data frame;

[0148] The forwarding module 602 is configured to acquire the first data frame and write the first data frame into a dedicated data buffer corresponding to the communication controller through the first processor core in response to the first interrupt signal; read a plurality of data frames stored in the dedicated data buffer according to a preset period; and forward the plurality of read data frames to the second processor core; wherein the plurality of data frames comprise the first data frame.

[0149] The receiving module 603 is configured to receive the plurality of first data frames from the first processor core through the second processor core.

[0150] In some embodiments, in some embodiments, as shown in the above Figure 7 embodiments, based on the above Figure 6On the basis of the illustrated embodiment, the forwarding module 602 can include a generating unit 6021 and an interrupt triggering unit 6022.

[0151] The generating unit 6021 is configured to encode the plurality of data frames according to a preset inter-core communication protocol by the first processor core to generate a data packet.

[0152] The interrupt triggering unit 6022 is configured to write the data packet into a shared memory region of the first processor core and the second processor core, and trigger generation of a second interrupt signal and transmission of the second interrupt signal to the second processor core.

[0153] Continuing to refer to Figure 7 On the basis of the above Figure 6 On the basis of the illustrated embodiment, the receiving module 603 is specifically configured to read the data packet from the shared memory region by the second processor core in response to the second interrupt signal, and parse the data packet based on the inter-core communication protocol to obtain the plurality of first data frames.

[0154] In some embodiments, the receiving module 603 is specifically configured to perform timeout detection, frame loss detection, and / or data consistency detection on the data packet by the second processor core in response to the second interrupt signal to obtain a data detection result; perform parsing of the data packet based on the inter-core communication protocol to obtain the plurality of first data frames by the second processor core in response to the data detection result indicating that the data detection is successful; and write the plurality of first data frames into a preset cache space in the second processor core by the second processor core.

[0155] In some embodiments, the receiving module 603 is further configured to save error information in response to the data detection result indicating that the data detection fails, and continue to receive a new data packet.

[0156] In some embodiments, the receiving module 603 is specifically configured to obtain, by the second processor core in response to the second interrupt signal, a first reception timestamp of each first data frame, a cycle count value of each first data frame, and a cyclic redundancy check value of the data packet from the data packet; perform timeout detection on the data packet based on the first reception timestamp of each first data frame to obtain a timeout detection result; perform frame loss detection on the data packet based on the cycle count value of each first data frame to obtain a frame loss detection result; and / or perform data consistency detection on the data packet based on the cyclic redundancy check value of the data packet to obtain a data consistency detection result; wherein the data detection result includes the timeout detection result, the frame loss detection result, and the data consistency detection result.

[0157] In some embodiments, the receiving module 603 is specifically configured to acquire, by the second processor core, a second timestamp of receiving the data packet by the second processor core in response to the second interrupt signal; calculate a transmission time based on the second timestamp and the first receiving timestamp of each first data frame; and determine that the timeout detection result is timeout detection success in response to the transmission time being less than or equal to a transmission time threshold. The transmission time threshold is a preset maximum allowed data transmission time consumption.

[0158] In some embodiments, the receiving module 603 is further configured to, in response to the data detection result representing that the data detection is successful, parse the data packet based on an inter-core communication protocol to obtain data length information; write the data length information to a preset interface; read the data length information from the preset interface based on a user program; and read a preset number of data frames from the preset cache space based on the data length information. The preset number of data frames is less than or equal to a total number of frames corresponding to the data length information.

[0159] As to one of the above-mentioned embodiments, the specific manners in which each module performs operations and the corresponding beneficial effects have been described in detail in the corresponding embodiment part of the foregoing method for inter-core communication on a system on chip, and can be referred to the corresponding operation performing manners and beneficial technical effects of the above-mentioned exemplary method part, which will not be described herein again.

[0160] On the basis of the above-mentioned system on chip supporting inter-core communication, the embodiment of the present disclosure further provides an integrated circuit. Figure 8 is a structural schematic diagram of an integrated circuit provided by an exemplary embodiment of the present disclosure. As shown in Figure 8 , the integrated circuit 80 can include a system on chip 10 supporting inter-core communication and at least one special data buffer 801 as shown in Figure 1 . The special data buffer 801 is used to store the first data frame received by the communication controller 103.

[0161] Exemplary electronic device

[0162] Figure 9 is a structural schematic diagram of an electronic device provided by an exemplary embodiment of the present disclosure. As shown in Figure 9 , the electronic device 90 can include a processor 901 and a memory 902 for storing executable instructions of the processor 901; the processor 901 is used to read the executable instructions from the memory 902 and execute the instructions to implement the method for inter-core communication on a system on chip described in the above-mentioned embodiments.

[0163] The memory 902 can include one or more computer program products that can include various forms of computer-readable storage media, for example, volatile memory and / or non-volatile memory. The volatile memory, for example, can include random access memory (RAM), cache memory, and / or the like. The non-volatile memory, for example, can include read-only memory (ROM), hard disk drives, solid-state drives, and / or the like.

[0164] Of course, in order to simplify, Figure 9 Only some of the components in the electronic device 90 related to the present disclosure are shown in the middle, and components such as buses, input / output interfaces, and the like are omitted. In addition, the electronic device 90 can also include any other appropriate components according to specific application circumstances, for example, the electronic device 90 can also include the sensor module 1103.

[0165] Exemplary computer program product and computer readable storage medium

[0166] In addition to the above method and device, the embodiments of the present disclosure can also provide a computer program product comprising computer program instructions, which, when executed by a processor, cause the processor to perform the steps of the inter-core communication method on a system on chip described in the above “Exemplary Method” section.

[0167] The computer program product can be written in any combination of one or more programming languages, including object-oriented programming languages, such as Java, C++, and conventional procedural programming languages, such as the "C" programming language, or the like. The program code can execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device and partly on a remote computing device, or entirely on the remote computing device or server.

[0168] In addition, the embodiments of the present disclosure can also be a computer readable storage medium having stored thereon computer program instructions, which, when executed by a processor, cause the processor to perform the steps of the inter-core communication method on a system on chip described in the above “Exemplary Method” section.

[0169] The computer readable storage medium can be any combination of one or more computer readable medium(s). The computer readable medium can be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0170] The above describes the basic principles of the present disclosure in combination with specific embodiments, but the advantages, benefits, effects and the like mentioned in the present disclosure are only examples and are not limiting, and it cannot be considered that they are necessarily possessed by each embodiment of the present disclosure. In addition, the above specific details of the disclosure are only for the purpose of example and for the purpose of understanding, and are not limiting, and the above details do not limit the present disclosure to necessarily adopt the above specific details for implementation.

[0171] Those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A system-on-chip supporting inter-core communication, comprising: at least one communication controller coupled with a first processor core, the communication controller configured to generate a first interrupt signal in response to receiving a first data frame; the first processor core configured to, in response to the first interrupt signal, fetch the first data frame and write the first data frame into a dedicated data buffer corresponding to the communication controller, and read a plurality of data frames stored in the dedicated data buffer according to a preset period; forward the plurality of read data frames to a second processor core, wherein the plurality of data frames comprises the first data frame; the second processor core configured to receive the plurality of first data frames from the first processor core.

2. The system-on-chip of claim 1, wherein the first processor core configured to forward the plurality of read data frames to the second processor core comprises: the first processor core specifically configured to encode the plurality of data frames according to a preset inter-core communication protocol to generate a data packet, write the data packet into a shared memory region of the first processor core and the second processor core, and trigger generation of a second interrupt signal and sending of the second interrupt signal to the second processor core; the second processor core configured to receive the plurality of first data frames from the first processor core comprises: the second processor core configured to, in response to the second interrupt signal, read the data packet from the shared memory region and parse the data packet based on the inter-core communication protocol to obtain the plurality of first data frames.

3. The system on chip of claim 2, wherein, the second processor core specifically configured to: in response to the second interrupt signal, perform timeout detection, frame loss detection, and / or data consistency detection on the data packet to obtain a data detection result; in response to the data detection result indicating that the data detection is successful, parse the data packet based on the inter-core communication protocol to obtain the plurality of first data frames; write the plurality of first data frames into a preset cache space in the second processor core.

4. The system-on-chip of claim 3, the second processor core further configured to: in response to the data detection result indicating that the data detection is unsuccessful, save error information and continue to receive a new data packet.

5. The system on chip of claim 3, wherein, the second processor core specifically configured to: obtain, from the data packet, a first reception timestamp of each of the first data frames, a cycle count value of each of the first data frames, and a cyclic redundancy check value of the data packet; perform timeout detection on the data packet based on the first reception timestamp of each of the first data frames to obtain a timeout detection result, perform frame loss detection on the data packet based on the cycle count value of each of the first data frames to obtain a frame loss detection result, and / or perform data consistency detection on the data packet based on the cyclic redundancy check value of the data packet to obtain a data consistency detection result; wherein the data detection result comprises the timeout detection result, the frame loss detection result, and the data consistency detection result.

6. The system on chip of claim 5, wherein, the second processor core specifically configured to: acquire a second timestamp of the second processor core receiving the data packet; calculate a transmission time based on the second timestamp and the first receiving timestamp of each of the first data frames; determine that the timeout detection result is a timeout detection success in response to the transmission time being less than or equal to a transmission time threshold; wherein the transmission time threshold is a preset maximum allowed data transmission time consumption.

7. The system on chip according to claim 3, the second processor core, further specifically configured to: analyze the data packet based on the inter-core communication protocol to obtain data length information in response to the data detection result representing data detection success; write the data length information to a preset interface; read the data length information from the preset interface based on a user program; read a preset number of data frames from the preset cache space based on the data length information; wherein the preset number of data frames does not exceed a total number of frames corresponding to the data length information.

8. The system on chip of any one of claims 1-7, wherein, The first processor core is further configured to transmit the first data frames to an interface layer corresponding to the first processor core in response to the first interrupt signal.

9. An inter-core communication method for a system on chip, the system on chip comprising a first processor core, a second processor core, and at least one communication controller coupled to the first processor core, the method comprising: generating a first interrupt signal by the communication controller in response to receiving a first data frame; acquiring the first data frame by the first processor core in response to the first interrupt signal and writing the first data frame to a dedicated data buffer corresponding to the communication controller; reading a plurality of data frames stored in the dedicated data buffer according to a preset period; forwarding the plurality of read data frames to the second processor core; wherein the plurality of data frames comprises the first data frame; receiving the plurality of first data frames from the first processor core by the second processor core.

10. An integrated circuit comprising the system on chip according to any one of claims 1-8 and at least one dedicated data buffer; the dedicated data buffer is configured to store the first data frame received by the communication controller.

11. An electronic device comprising: a processor; a memory for storing executable instructions of the processor; the processor is configured to read the executable instructions from the memory and execute the instructions to implement the inter-core communication method for a system on chip according to claim 9.

12. A computer readable storage medium, the storage medium storing a computer program, the computer program being executed by a processor to implement the inter-core communication method for a system on chip according to claim 9.

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