Test pattern generation method for test rule inspection system and related product
By automatically generating test patterns and utilizing the stretching and moving operations of seed patterns, the problem of low test pattern generation efficiency in the mask manufacturability rule checking system is solved, achieving efficient and comprehensive testing results.
Patent Information
- Application Number
- CN202511095421.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-05
- Publication Date
- 2025-11-21
AI Technical Summary
In the existing technology, the test pattern generation efficiency of the mask manufacturability rule checking system is low, and manually drawing test patterns is time-consuming and prone to missing complex scenes, resulting in insufficient test coverage.
By automatically generating test patterns and utilizing the stretching and moving operations of seed patterns, various test patterns are generated on the test layout according to geometric inspection rules, including minimum spacing and minimum width rules. Random number algorithms are used to control pattern changes, thereby improving coverage.
It enables the rapid and efficient generation of a wide variety of test graphics, improving the testing effectiveness and coverage of the mask manufacturability rule checking system.
Smart Images
Figure CN120995975A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a method for generating test patterns for a test rule checking system, a computer-readable storage medium, a computer program product, and a computer device. Background Technology
[0002] Manufacturing Rule Check (MRC), also known as Mask Rule Check, is a technique used in chip design and manufacturing to verify the manufacturability of photomask designs. It is a crucial link between chip design and manufacturing. By using a mask manufacturability rule check system to inspect the mask layout, it can be ensured that the mask geometry in the layout meets the physical limits and manufacturing capabilities of the photolithography process, thereby avoiding yield reduction or chip failure caused by mask design defects.
[0003] Mask manufacturability checks involve numerous rules, some of which relate to geometric checks of the mask geometry. Generally, geometric rule checks include minimum spacing rules, minimum width rules, etc. Minimum spacing rules can include minimum edge spacing (min space egde to edge), minimum vertex spacing (min space corner to corner), etc. Minimum width rules can include minimum edge width (min width egde to edge), minimum vertex width (min width corner to corner), etc.
[0004] To ensure the mask manufacturability rule checking function functions properly, the mask manufacturability rule checking system needs to be thoroughly tested using a test layout. The test layout includes test patterns, which are typically drawn manually according to geometric checking rules.
[0005] With the continuous development of integrated circuit technology, mask design layouts are becoming increasingly complex, and the environment surrounding each geometric shape in the layout is also becoming more complex. To improve testing effectiveness, test patterns need to cover as many scenarios as possible when designing them. On the one hand, this requires a significant amount of human resources to draw the test patterns, and the efficiency is low; on the other hand, manually drawing test patterns can easily overlook some complex scenarios, resulting in insufficient test pattern coverage, which in turn can transfer potential problems to the production stage, causing huge economic losses. Summary of the Invention
[0006] One object of the present invention is to provide a test pattern generation method, computer-readable storage medium, computer program product and computer device for a test rule checking system, so as to realize the automatic generation of various test patterns for a test mask manufacturability rule checking system and improve the generation efficiency of test patterns.
[0007] A further objective of this invention is to generate a wide variety of test patterns to expand the coverage of the generated test patterns, thereby improving the testing effectiveness of the mask manufacturability rule checking system.
[0008] Specifically, according to one aspect of the present invention, the present invention provides a test pattern generation method for a test mask manufacturability rule checking system, comprising:
[0009] Obtain the geometric inspection rules for the system under test, which are used to check the manufacturability of the mask design layout based on the geometric inspection rules;
[0010] According to the geometric inspection rules, one or more seed graphics are generated on the test layout, wherein the seed graphics are polygons;
[0011] For each vertex of each seed graphic, obtain the first movement vector respectively;
[0012] Each vertex is stretched according to its respective first movement vector, and all graphics on the test layout are saved after each stretching for use in testing the system under test.
[0013] Optionally, multiple seed patterns are generated on the test layout and are spaced apart from each other.
[0014] Optionally, before the step of obtaining the first movement vector for each vertex of each of the seed graphics, the method further includes:
[0015] For each of the seed graphics, obtain the second movement vector respectively;
[0016] Move the corresponding seed graphic according to each of the second movement vectors, and save all graphics on the test board after each movement.
[0017] Optionally, the step of stretching the corresponding vertex according to each of the first movement vectors, and saving all the graphics on the test layout after each stretching, includes:
[0018] Each vertex of each seed graphic in the test layout obtained after moving the corresponding seed graphic according to the second movement vector is stretched according to the first movement vector, and all graphics on the test layout are saved after each stretching is completed.
[0019] Optionally, the geometric inspection rules include a minimum spacing rule, which is used to check the spacing between adjacent polygons in the mask design layout; the step of generating multiple seed graphics on the test layout according to the geometric inspection rules includes:
[0020] Arrange the relative positions of multiple seed graphics according to the preset edge spacing.
[0021] Optionally, the step of generating multiple seed patterns on the test layout according to the geometric check rules includes:
[0022] The relative positions of the seed graphics are arranged according to the preset vertex spacing.
[0023] Optionally, the geometric inspection rules include a minimum width rule, which is used to check the width dimension of any polygon in the mask design layout; the step of generating one or more seed graphics on the test layout according to the geometric inspection rules includes:
[0024] Arrange the shapes of each seed graphic according to the preset edge width.
[0025] Optionally, the step of generating one or more seed graphics on the test layout according to the geometric check rules includes:
[0026] Arrange the shapes of each seed graphic according to the preset vertex width.
[0027] Optionally, obtaining the first movement vector for each vertex of each of the seed graphics includes:
[0028] Calculate the total number of vertices of each seed graphic on the test layout;
[0029] Multiple sets of binary random numbers equal to the total number are generated using a preset algorithm;
[0030] Each group of binary random numbers is used to construct a first movement vector.
[0031] Optionally, the seed graphic is a Manhattan graphic.
[0032] According to another aspect of the present invention, a computer-readable storage medium is also provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the test pattern generation method for a test mask manufacturability rule checking system described above.
[0033] According to another aspect of the present invention, a computer program product is also provided, comprising a computer program that, when executed by a processor, implements the steps of the test pattern generation method for a test mask manufacturability rule checking system described above.
[0034] According to another aspect of the present invention, a computer device is also provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the test pattern generation method for testing a mask manufacturability rule checking system as described above.
[0035] The test pattern generation method for a test rule checking system of the present invention generates seed patterns based on the geometric checking rules to be tested on the test layout, and performs stretching operations on each vertex of each type of sub-pattern, thereby achieving the goal of generating a rich variety of test patterns quickly and efficiently.
[0036] The above and other objects, advantages and features of the present invention will become more apparent to those skilled in the art from the following detailed description of specific embodiments of the invention in conjunction with the accompanying drawings. Attached Figure Description
[0037] The following sections will describe some specific embodiments of the invention in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:
[0038] Figure 1 This is a flowchart illustrating a generation method according to an embodiment of the present invention;
[0039] Figure 2 This is a schematic flowchart illustrating the process of obtaining multiple first movement vectors according to a generation method of an embodiment of the present invention;
[0040] Figure 3 This is a schematic flowchart illustrating the stretching and moving operations of a generation method according to an embodiment of the present invention.
[0041] Figure 4 This is a schematic diagram showing the frame lines after generating multiple seed patterns on a test layout according to a generation method of an embodiment of the present invention.
[0042] Figure 5 This is a schematic diagram of the frame of a test graphic obtained after a movement operation according to a generation method of an embodiment of the present invention.
[0043] Figure 6 This is a schematic diagram of the frame of a test graphic obtained after performing a moving and stretching operation according to a generation method of an embodiment of the present invention.
[0044] Figure 7 This is a schematic diagram of a computer program product according to an embodiment of the present invention;
[0045] Figure 8 This is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention; and
[0046] Figure 9 This is a schematic diagram of a computer device according to an embodiment of the present invention. Detailed Implementation
[0047] Currently, integrated circuits are typically designed using electronic design automation (EDA) tools for mask layout. EDA tools (such as PanGen) use computational lithography, employing algorithms, computer simulations, and optimization techniques to continuously improve the precision and efficiency of lithography processes, thereby designing and manufacturing chips with increasingly smaller fabrication processes.
[0048] Manufacturing Rule Check (MRC), also known as Mask Rule Check, is a technique in computational lithography. It's a process for verifying the manufacturability of photomask designs in semiconductor manufacturing, ensuring that the mask geometry meets the physical limits and manufacturing capabilities of the lithography process. It's a crucial link between chip design and manufacturing, aiming to prevent yield degradation or chip failure due to mask design defects.
[0049] The core objectives of mask manufacturability rule checks include: ensuring manufacturability by verifying whether the mask pattern meets the physical limitations of processes such as lithography machines, photoresists, and anti-reflective coatings; and preventing defects by avoiding pattern distortion, bridging, and residues caused by mask design errors (such as excessively small linewidths or narrow spacing). The role of mask manufacturability rule checks is mainly reflected in: ensuring yield, as manufacturability violations are one of the primary causes of chip yield loss, directly impacting production success or failure; and controlling costs, as early manufacturability repairs can prevent significant economic losses due to mask errors after tape-out.
[0050] Mask manufacturability checks involve numerous aspects, with geometric rule checks being a crucial one. For example, geometric rule checks primarily include minimum spacing (space) rules and minimum width (width) rules. Minimum spacing rules check the spacing between adjacent polygons in the mask design layout, including minimum edge spacing (min space egde to edge) and minimum vertex spacing (min space corner to corner). Minimum spacing rules prevent short circuits or photoresist buildup by limiting the minimum spacing between the lines or shapes of adjacent polygons. Minimum width rules check the width of any polygon in the mask design layout, including minimum edge width (min width egde to edge) and minimum vertex width (min width corner to corner). Minimum width rules prevent breakage or uneven development due to excessive thinness by limiting the minimum width of the polygon's own lines. Geometric rule checks also include overlap and minimum area constraints. Overlap checks check alignment tolerances between different layers (such as metal layers and via layers) to prevent misalignment leading to open circuits. Area limits are used to check the pattern density or area ratio of a specific region to avoid uniformity issues caused by process fluctuations.
[0051] To ensure the proper functioning of the mask manufacturability rule checking system (hereinafter referred to as the system under test), and to enable the system under test to accurately and comprehensively detect various violations in the mask design layout, it is necessary to thoroughly test the functionality of the system under test. In related technologies, the basic process for testing the system under test includes: defining the types of geometric shapes to be checked in the mask design layout; designing geometric check rules for the system under test based on the geometric shape types; drawing test graphics according to the geometric check rules and forming a test layout; and testing the functionality of the system under test using the test layout.
[0052] In related technologies, test patterns are typically drawn manually according to geometric inspection rules. With the continuous development of integrated circuit technology, mask design layouts are becoming increasingly complex, and the environment surrounding each geometric shape in the layout is also becoming more complex. To improve testing effectiveness, test patterns need to cover as many scenarios as possible when designing them. On the one hand, this requires a significant amount of human resources to draw the test patterns and is inefficient; on the other hand, manually drawing test patterns can easily overlook some complex scenarios, resulting in insufficient test pattern coverage.
[0053] The purpose of the test pattern generation method for the test rule checking system in this embodiment is to automatically generate various test patterns for the test mask manufacturability rule checking system, thereby improving the efficiency of test pattern generation.
[0054] Figure 1 This is a flowchart illustrating a test pattern generation method for a test mask manufacturability rule checking system according to an embodiment of the present invention. The method generally includes:
[0055] S100, Obtain the geometric inspection rules of the system under test, which are used to check the manufacturability of the mask design layout based on the geometric inspection rules;
[0056] S200: Based on the geometric check rules, generate one or more seed graphics on the test layout. The seed graphics are polygons.
[0057] S400: For each vertex of various sub-graphs, obtain the first movement vector respectively;
[0058] S500 stretches the corresponding vertices according to each first movement vector, and saves all the graphics on the test layout after each stretching for use in testing the system under test.
[0059] In this embodiment, the geometric check rules may include one or more of the following: minimum spacing rule, minimum width rule, coverage relationship, and area limit. The seed pattern on the test layout can be generated according to one or more of the geometric check rules. The seed pattern can be configured to satisfy the geometric check rules or to violate the geometric check rules; no restrictions are imposed here.
[0060] For example, for geometric checking rules involving the width dimensions of polygons, such as minimum edge width and minimum vertex width, a seed shape can be generated on the test layout. This seed shape has a preset edge width (see reference). Figure 4 The annotations a) and / or vertex width (see reference) Figure 4 (See annotation b in the text). Of course, multiple seed graphics can also be generated on the test layout, each seed graphic having a different edge width and / or vertex width.
[0061] For example, for geometric checking rules involving the spacing between adjacent polygons, such as minimum edge spacing and minimum vertex spacing, two or more seed shapes can be generated on the test layout, with adjacent sub-shapes having preset edge spacing (please refer to...). Figure 4 The annotation c) and / or vertex spacing (please refer to) Figure 4 (d) in the text.
[0062] The seed graphic is a polygon, consisting of multiple vertices and line segments connecting any two vertices. Each vertex can be located at a preset coordinate position on the test layout. When multiple seed graphics exist on the test layout, the shapes and sizes of the various sub-graphics can be the same or different. All graphics on the test layout can serve as a test graphic (including the shape and size of each sub-graphic itself, as well as the relative positional relationships between the various sub-graphics).
[0063] To test the system under test, it is necessary to efficiently generate multiple test patterns and improve the coverage of these patterns. In this embodiment, the inventors creatively propose a method for automatically generating multiple test patterns: by stretching (moving) a vertex of a seed pattern and affecting all line segments connected to that vertex, the seed pattern can be easily transformed into a new polygon, using all patterns on the test layout as a new test pattern. The generated new test pattern is saved, and then by stretching (moving) another vertex of the seed pattern, another polygon can be easily formed, using all patterns on the test layout as another test pattern. This process is repeated, stretching each vertex of each seed pattern on the test layout, resulting in one test pattern per stretching operation. For example, please refer to... Figure 5-6 , Figure 5 The diagram illustrates a test layout with multiple seed graphics 50. Figure 6 It indicated that Figure 5 A new test graphic is obtained by performing multiple stretching operations on multiple vertices of several seed graphics 50. Specifically, Figure 5 The test pattern has 4 seed patterns (50), totaling 18 vertices. By stretching these 18 vertices sequentially, 18 different test patterns can be obtained.
[0064] It's important to understand that each stretching operation may change one or more of the following parameters in the test pattern: edge width, vertex width, edge spacing, and vertex spacing. Since only one vertex is stretched at a time, each resulting test pattern exhibits only minor variations. However, as multiple stretching operations accumulate, they transform a single, simple test pattern into a rich variety of complex test patterns, thus expanding the range of test patterns.
[0065] In this embodiment, each vertex corresponds to a first movement vector, and each first movement vector includes a stretching distance and a stretching direction. The stretching distance and stretching direction of each first movement vector can be the same or different. The stretching distance and stretching direction of each first movement vector can be preset values or derived by a specific algorithm. For example, each first movement vector can be generated by a random number script. It should be understood that by controlling the range of variation of the stretching distance and stretching direction of each first movement vector, the range of variation of each test pattern can be easily controlled, thereby limiting the types of test patterns and preventing the generation of unnecessary or valueless test patterns.
[0066] It is important to understand that for the same vertex, different first translation vectors can be used for stretching operations, thereby forming different test patterns and enriching the variety of test patterns.
[0067] The test pattern generation method for a test mask manufacturability rule checking system in this embodiment generates seed patterns based on the geometry check rules to be tested on the test layout, and performs stretching operations on each vertex of each type of sub-pattern, thereby achieving the goal of generating a wide variety of test patterns quickly and efficiently.
[0068] In some embodiments of the generation method of the present invention, such as Figure 2 As shown, for each vertex of various sub-graphs, the first movement vector is obtained, including:
[0069] S411, calculate the total number of vertices of each sub-graph on the test layout;
[0070] S413, using a preset algorithm to generate multiple sets of binary random numbers equal to the total number;
[0071] S415, each set of binary random numbers is used to form a first movement vector.
[0072] In this embodiment, each first movement vector is obtained by a preset random number algorithm. Specifically, a binary random number (x, y) can be generated using a binary random number script, and this binary random number can be used as a first movement vector to perform a stretching operation on a vertex.
[0073] In practical applications, the total number of vertices n of various sub-graphs on the test layout can be calculated first. Then, a binary random number script can be used to generate n sets of binary random numbers [(x1,y1),(x2,y2),...,(x...y1)...y2]... n ,y n Each set of binary random numbers corresponds to a vertex on the test board.
[0074] In this embodiment, by generating random first movement vectors, the stretching distance and stretching direction of each first movement vector are random. This makes the generated test patterns independent of human consciousness or habits, overcomes the statistical bias of manually drawing test patterns, generates more comprehensive and richer test patterns, and improves the coverage of test patterns.
[0075] It is important to understand that by setting the parameters of the binary random number script, the range of x and y in the generated binary random numbers can be easily controlled, thereby effectively controlling the range of the stretching distance of each first movement vector, thus limiting the types of test patterns and preventing the generation of unnecessary or worthless test patterns.
[0076] In some embodiments of the generation method of the present invention, such as Figure 4 As shown, multiple seed patterns are generated on the test layout and are set at intervals between each other.
[0077] In this embodiment, by generating multiple seed patterns with varying intervals on the test layout, test patterns involving geometric checking rules for the spacing between adjacent polygons can be generated, thereby improving the coverage of the test patterns.
[0078] In some embodiments of the generation method of the present invention, such as Figure 3 As shown, before the step of obtaining the first movement vector for each vertex of various sub-graphs, the following steps are also included:
[0079] S311, for each sub-graphic, obtain the second movement vector respectively;
[0080] S313, move the corresponding seed graphic according to each second movement vector, and save all graphics on the test board after each movement.
[0081] In this embodiment, the movement distance and stretching direction of each second movement vector can be preset values or derived by a specific algorithm. For example, referring to the method for generating the first movement vector, a binary random number script can be used to generate multiple sets of binary random numbers, thereby forming each second movement vector. By setting the parameters of the binary random number script, the range of x and y in the generated binary random numbers can be easily controlled, thereby effectively controlling the range of movement distance and direction of each second movement vector, thus limiting the types of test patterns and preventing the generation of unnecessary or worthless test patterns.
[0082] In this embodiment, as Figure 4-5 As shown, Figure 4 The diagram illustrates a test layout with multiple seed graphics 50. Figure 5 It indicated that Figure 4The new test pattern is obtained by moving one seed pattern 50 in the test layout. While keeping the shape, size, and angle of each sub-pattern unchanged, the relative positional relationships between the sub-patterns are changed by moving their positions within the test layout, thus forming different types of test patterns. Specifically, by changing the positional relationship between two adjacent sub-patterns, the edge spacing and / or vertex spacing between them can be easily altered, thereby forming various test patterns for testing geometric checking rules such as minimum edge spacing and minimum vertex spacing.
[0083] It is important to understand that when the second movement vector is a random number, the generated test pattern is also independent of human consciousness or habits, overcoming the statistical bias of manually drawing test patterns, generating more comprehensive and richer test patterns, and improving the coverage of test patterns.
[0084] For the same seed pattern, different second movement vectors can be used for movement operations, thereby forming different test patterns and enriching the variety of test patterns.
[0085] In some embodiments of the generation method of the present invention, such as Figure 3 As shown, each vertex is stretched according to its first movement vector, and all graphics on the test board are saved after each stretch, including:
[0086] S511, according to each first movement vector, stretch the corresponding vertex of each seed graphic in all graphics on the test board obtained after each movement of the corresponding seed graphic according to the second movement vector, and save all graphics on the test board after each stretching is completed.
[0087] By combining the stretching operation on vertices with the moving operation on the seed graphic, different test graphics can be formed, thus enriching the variety of test graphics.
[0088] It should be understood that this invention does not limit the order of stretching operations on vertices and moving operations on seed graphics. Those skilled in the art can arrange the order of stretching and moving operations according to testing needs. In practical use, the vertices can be stretched first, followed by the moving operations on various sub-graphics. Alternatively, the sub-graphics can be moved first, followed by the stretching operations on the vertices. Alternatively, operations can be performed in a crisscross manner; for example, stretching some vertices first, moving some seed graphics, then stretching the remaining vertices, and finally moving the remaining seed graphics.
[0089] In some embodiments of the generation method of the present invention, such as Figure 4As shown, the geometric inspection rules include a minimum spacing rule, which is used to check the spacing between adjacent polygons in the mask design layout. Based on the geometric inspection rules, the steps for generating multiple seed graphics on the test layout include:
[0090] Arrange the relative positions of multiple seed graphics according to the preset edge spacing.
[0091] In this embodiment, the preset edge spacing c can be equal to, greater than, or less than the minimum edge spacing, depending on the testing requirements. The preset edge spacing c between different seed graphics 50 can be the same or different, depending on the testing requirements. By using the preset edge spacing of the seed graphics 50, combined with each second movement vector, the variation range of each generated test graphic can be effectively controlled, generating a variety of more targeted test graphics for the minimum edge spacing between adjacent mask geometries.
[0092] In some embodiments of the generation method of the present invention, such as Figure 4 As shown, the steps for generating multiple seed graphics on the test layout according to the geometry checking rules include:
[0093] Arrange the relative positions of multiple seed shapes according to the preset vertex spacing.
[0094] In this embodiment, the preset vertex spacing d can be equal to, greater than, or less than the minimum vertex spacing, depending on the testing requirements. The preset vertex spacing d between different seed graphics 50 can be the same or different, depending on the testing requirements. By using the preset vertex spacing of the seed graphics 50, combined with each second movement vector, the variation range of each generated test graphic can be effectively controlled, generating more targeted test graphics with varying minimum vertex spacing between adjacent mask geometries.
[0095] In some embodiments of the generation method of the present invention, such as Figure 4 As shown, the geometric inspection rules include a minimum width rule, which is used to check the width dimension of any polygon in the mask design layout; according to the geometric inspection rules, the steps of generating one or more seed graphics on the test layout include:
[0096] Arrange the shapes of various sub-figures according to the preset edge width.
[0097] In this embodiment, the preset edge width 'a' can be equal to, greater than, or less than the minimum edge width, depending on the testing requirements. The preset edge width 'a' for different seed graphics 50 can be the same or different, depending on the testing requirements. By using the preset edge width of the seed graphics 50, combined with each first movement vector, the variation range of each generated test graphic can be effectively controlled, generating a variety of more targeted test graphics for each mask geometry's minimum edge width.
[0098] In some embodiments of the generation method of the present invention, such as Figure 4 As shown, the steps for generating one or more seed graphics on the test layout according to the geometry checking rules include:
[0099] Arrange the shapes of various sub-figures according to the preset vertex width.
[0100] In this embodiment, the preset vertex width can be equal to, greater than, or less than the minimum vertex width, depending on the testing requirements. The preset vertex width b of different seed graphics 50 can be the same or different, depending on the testing requirements. By using the preset vertex width of the seed graphics 50, combined with each first movement vector, the variation range of each generated test graphic can be effectively controlled, generating more targeted test graphics with the minimum vertex width of the same mask geometry.
[0101] In some embodiments of the generation method of the present invention, such as Figure 4-6 As shown, the seed graphic is a Manhattan graphic.
[0102] A Manhattan polygon is a polygon in a chip mask layout that consists only of vertices, horizontal lines, and vertical lines. It is used to represent components such as metal lines in a chip. Because it consists only of vertices, horizontal lines, and vertical lines, it simplifies computational complexity, improves computational efficiency, and reduces computing power consumption when processing chip layouts composed of multiple Manhattan polygons.
[0103] In this embodiment, by using the Manhattan graphic as the seed graphic, the efficiency of generating seed graphics according to geometric inspection rules can be improved, and one or more seed graphics based on the geometric inspection rules to be tested can be quickly generated on the test layout, thereby improving the efficiency of test graphic generation.
[0104] The flowchart provided in this embodiment is not intended to indicate that the operations of the method will be performed in any particular order, or that all operations of the method are included in every case. Furthermore, the method may include additional operations. Within the scope of the technical concept provided by the method in this embodiment, additional variations can be made to the above method.
[0105] It should be understood that in some embodiments, the components may be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods may be implemented using software or firmware stored in memory and executed by a suitable instruction execution system.
[0106] This invention also provides a computer program product 10, a computer-readable storage medium 20, and a computer device 30. Figure 7 This is a schematic diagram of a computer program product 10 according to an embodiment of the present invention. Figure 8 This is a schematic diagram of a computer-readable storage medium 20 according to an embodiment of the present invention. Figure 9 This is a schematic diagram of a computer device 30 according to an embodiment of the present invention. The computer program product 10 includes a computer program 11, which, when executed by the processor 32, implements the steps of any of the above-described generation methods. A computer-readable storage medium 20 stores the computer program 11 thereon, which, when executed by the processor 32, implements the steps of the generation method of any of the above embodiments. The computer device 30 may include a memory 31, a processor 32, and the computer program 11 stored in the memory 31 and running on the processor 32.
[0107] The computer program 11 used to perform the operations of this invention may be assembly instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages and procedural programming languages. The computer program 11 may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a Local Area Network (LAN) or Wide Area Network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, Field-Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), may execute computer-readable program instructions using status information from computer-readable program instructions to personalize the electronic circuits.
[0108] For the purposes of this embodiment, computer program product 10 is a related product that includes computer program 11.
[0109] For the purposes of this embodiment, the computer-readable storage medium 20 is a tangible device capable of holding and storing a computer program 11. It can be any device capable of containing, storing, communicating, propagating, or transmitting the computer program 11 for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable storage medium 20 include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital versatile disc (DVD), memory stick, floppy disk, mechanical encoding device, and any suitable combination thereof.
[0110] Computer device 30 can be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, computer device 30 can be a cloud computing node. Computer device 30 can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer device 30 can be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can reside on local or remote computing system storage media, including storage devices.
[0111] Computer device 30 may include a processor 32 adapted to execute stored instructions and a memory 31 that provides temporary storage space for the operation of said instructions during operation. The processor 32 may be a single-core processor, a multi-core processor, a computing cluster, or any other configuration. The memory 31 may include random access memory (RAM), read-only memory, flash memory, or any other suitable storage system.
[0112] Computer device 30 may also include a network adapter / interface and an input / output (I / O) interface. The I / O interface allows external devices that can be connected to the computer device to input and output data. The network adapter / interface provides communication between the computer device and a network, typically represented as a communication network.
[0113] Therefore, those skilled in the art should recognize that although numerous exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications conforming to the principles of the present invention can be directly determined or derived from the disclosure of the present invention without departing from the spirit and scope of the invention. Thus, the scope of the present invention should be understood and construed as covering all such other variations or modifications.
Claims
1. A method for generating test patterns for a test mask manufacturability rule checking system, characterized in that, include: Obtain the geometric inspection rules for the system under test, which are used to check the manufacturability of the mask design layout based on the geometric inspection rules; According to the geometric inspection rules, one or more seed graphics are generated on the test layout, wherein the seed graphics are polygons; For each vertex of each seed graphic, obtain the first movement vector respectively; Each vertex is stretched according to its respective first movement vector, and all graphics on the test layout are saved after each stretching for use in testing the system under test.
2. The generation method according to claim 1, characterized in that, The seed patterns generated on the test layout are multiple and are spaced apart from each other.
3. The generation method according to claim 2, characterized in that, Before the step of obtaining the first movement vector for each vertex of each of the seed graphics, the method further includes: For each of the seed graphics, obtain the second movement vector respectively; Move the corresponding seed graphic according to each of the second movement vectors, and save all graphics on the test board after each movement.
4. The generation method according to claim 3, characterized in that, The step of stretching the corresponding vertices according to each of the first movement vectors, and saving all the graphics on the test layout after each stretching, includes: Each vertex of each seed graphic in the test layout obtained after moving the corresponding seed graphic according to the second movement vector is stretched according to the first movement vector, and all graphics on the test layout are saved after each stretching is completed.
5. The generation method according to claim 2, characterized in that, The geometric inspection rules include a minimum spacing rule, which is used to check the spacing between two adjacent polygons in the mask design layout. The step of generating multiple seed graphics on the test layout according to the geometric check rules includes: Arrange the relative positions of multiple seed graphics according to the preset edge spacing; and / or The relative positions of the seed graphics are arranged according to the preset vertex spacing.
6. The generation method according to claim 1, characterized in that, The geometric inspection rules include a minimum width rule, which is used to check the width of any polygon in the mask design layout; The step of generating one or more seed graphics on the test layout according to the geometric check rules includes: Arrange the shapes of each seed graphic according to the preset edge width; and / or Arrange the shapes of each seed graphic according to the preset vertex width.
7. The generation method according to claim 1, characterized in that, The step of obtaining a first movement vector for each vertex of each of the seed graphics includes: Calculate the total number of vertices of each seed graphic on the test layout; Multiple sets of binary random numbers equal to the total number are generated using a preset algorithm; Each group of binary random numbers is used to construct a first movement vector.
8. The generation method according to claim 1, characterized in that, The seed graphic is a Manhattan graphic.
9. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the steps of the test pattern generation method for a test mask manufacturability rule checking system as described in any one of claims 1 to 8.
10. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the steps of the test pattern generation method for a test mask manufacturability rule checking system as described in any one of claims 1 to 8.
11. A computer device, characterized in that, The system includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the test pattern generation method for a test mask manufacturability rule checking system as described in any one of claims 1 to 8.