Memory device

Abstract

A memory device is provided. A memory device includes: a first memory block defined in a first wafer; and a second memory block defined in a second wafer disposed in a vertical direction with respect to the first wafer. A size of the first memory block is smaller than a size of the second memory block.

Description

[0001] This application is a divisional application of the invention patent application with the original application number 202110228991.9 (application date: March 2, 2021, invention name: Memory device, memory system having the same, and write method thereof). TECHNICAL FIELD

[0002] Various embodiments relate generally to semiconductor technology, and more particularly, to a memory device, a memory system having the same, and a write method thereof. BACKGROUND

[0003] As the demand for portable phones, mobile memory devices, and digital cameras increases, the demand for nonvolatile memory devices mainly used as memory devices for these products also increases. Among nonvolatile memory devices, flash memory devices are widely used as data storage devices. Recently, in order to increase the integration of memory devices, three-dimensional nonvolatile memory devices in which memory cells are three-dimensionally stacked have been actively researched. SUMMARY

[0004] Various embodiments relate to measures capable of improving the use efficiency of a memory.

[0005] In addition, various embodiments relate to measures capable of improving the performance of a memory.

[0006] In one embodiment, a memory device can include a first memory block defined in a first wafer, and a second memory block defined in a second wafer disposed in a vertical direction with respect to the first wafer. The size of the first memory block can be smaller than the size of the second memory block.

[0007] In one embodiment, a memory device can include a first wafer including a first substrate and a plurality of first electrode layers and a plurality of first interlayer dielectric layers alternately stacked on a top surface of the first substrate along a first vertical channel protruding in a vertical direction, and a second wafer disposed on the first wafer and including a second substrate and a plurality of second electrode layers and a plurality of second interlayer dielectric layers alternately stacked on a bottom surface of the second substrate along a second vertical channel protruding in the vertical direction. Each of the second electrode layers can include a pad portion. The first wafer can include a dielectric stack overlapping the pad portion of the second electrode layer in the vertical direction and configured by a plurality of dielectric layers and the plurality of first interlayer dielectric layers alternately stacked.

[0008] In one embodiment, a memory system can include a memory device and a memory controller. The memory device can include a small block defined in a first wafer and a large block defined in a second wafer disposed in a vertical direction with respect to the first wafer. The memory controller can store data in the small block or the large block by referring to a size of data requested to be written.

[0009] In one embodiment, a data write method of a memory device including a small block and a large block can include the steps of receiving a write request, detecting a size of data requested to be written, and storing the data in the small block or the large block according to a result of the detection. BRIEF DESCRIPTION OF DRAWINGS

[0010] FIG. 1 is a block diagram schematically showing an example of a representation of a memory device according to an embodiment of the present disclosure.

[0011] FIG. 2 is a schematic perspective view showing an example of a representation of a memory device. FIG. 1

[0012] FIG. 3 is a schematic perspective view showing an example of a representation of a memory device. FIG. 2

[0013] FIG. 4 is a schematic perspective view showing an example of a representation of a memory device. FIG. 3

[0014] FIG. 5 is a circuit diagram showing an example of a representation of a first memory block and a second memory block. FIG. 3

[0015] FIG. 6 is a schematic perspective view showing an example of a representation of a memory device. FIG. 2

[0016] FIG. 7 is a schematic perspective view showing an example of a representation of a memory device. FIG. 6

[0017] FIG. 8 is a circuit diagram showing an example of a representation of a first memory block and a second memory block. FIG. 6

[0018] FIG. 9 is a schematic perspective view showing an example of a representation of a memory device. FIG. 2 ​​​​​​​​

[0019] FIG. 10 is a representation of an example of a detailed structure of the first wafer and the second wafer shown. FIG. 9

[0020] FIG. 11 is a representation of an example of a schematic arrangement of the first wafer and the second wafer shown. FIG. 9

[0021] FIG. 12 is a representation of an example of a detailed structure of the first wafer and the second wafer shown. FIG. 2

[0022] FIG. 13 is a representation of an example of a schematic arrangement of the first wafer and the second wafer shown. FIG. 12

[0023] FIG. 14 is a representation of an example of a detailed structure of the first wafer and the second wafer shown. FIG. 12

[0024] FIG. 15 is a representation of an example of a schematic arrangement of the first wafer and the second wafer shown. FIG. 2

[0025] FIG. 16 is a representation of an example of a detailed structure of the first wafer and the second wafer shown. FIG. 15

[0026] FIG. 17 is a representation of an example of a schematic arrangement of the first wafer and the second wafer shown. FIG. 15

[0027] FIG. 18 is a representation of an example of a schematic arrangement of the first wafer and the second wafer shown. FIG. 2

[0028] FIG. 19 is a representation of an example of a detailed structure of the first wafer and the second wafer shown. FIG. 18

[0029] FIG. 20 is a representation of an example of a schematic arrangement of the first wafer and the second wafer shown. FIG. 18

[0030] FIG. 21 is a representation of an example of a schematic arrangement of the first wafer and the second wafer shown. ​​​​​​​​​​​

[0031] FIG. 22 is a cross-sectional view showing an example of a representation of a coupling structure between row lines and row decoders of a memory device according to an embodiment of the present disclosure.

[0032] FIG. 23 is a top view showing an example of a representation of main constituent elements of a first coupling region of FIG. 22

[0033] FIG. 24A to FIG. 24E is a cross-sectional view showing an example of a step of manufacturing a memory structure of a first wafer according to an embodiment of the present disclosure.

[0034] FIG. 25 is a cross-sectional view showing an example of a representation of another coupling structure between row lines and row decoders of a memory device according to an embodiment of the present disclosure.

[0035] FIG. 26A and FIG. 26B is a graph showing an example of a representation of a bias condition in an erase operation of a memory device according to an embodiment of the present disclosure.

[0036] FIG. 27 is a schematic block diagram showing an example of a representation of a memory system according to an embodiment of the present disclosure.

[0037] FIG. 28 is an example of a representation of a flowchart that helps explain a write method according to an embodiment of the present disclosure.

[0038] FIG. 29A to FIG. 29D is an example of a representation of a graph that helps explain a memory block management method according to an embodiment of the present disclosure.

[0039] FIG. 30 is a block diagram schematically showing an example of a representation of a computing system including a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] Advantages and features of the present disclosure and methods of accomplishing the same can be apparent from the following description taken in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of the present disclosure convey the scope of the present disclosure to those skilled in the art.

[0041] ​Since the numerical values, dimensions, ratios, angles, numbers, etc. of the elements that describe the embodiments of the disclosure given in the drawings are only illustrative, the disclosure is not limited to the shown content. Throughout the specification, like drawing reference numerals denote like parts. In describing the disclosure, detailed descriptions of related technologies will be omitted when it is determined that such detailed descriptions can obscure the gist or clarity of the disclosure. It should be noted or understood that the terms "include", "have", "comprise" and the like used in the specification and claims should not be interpreted as limiting to the means listed thereafter, unless otherwise specifically stated. When an indefinite article such as "a" or "an" is used in reference to a singular noun, the article can include a plurality of the noun, unless otherwise specifically stated.

[0042] When elements in the embodiments of the disclosure are explained, they should be interpreted to include error margins even if no explicit description is given.

[0043] In addition, in describing the components of the disclosure, terms such as first, second, A, B, (a), and (b) can be used. These terms are used only for the purpose of distinguishing one component from another component, and do not limit the substance, order, sequence, or number of the components. In addition, the components in the embodiments of the disclosure are not limited by these terms. These terms are used only to distinguish one component from another component. Therefore, as used herein, a first component can be a second component within the technical spirit of the disclosure.

[0044] If one component is described as being "connected", "coupled", or "linked" to another component, it can mean that the component can be not only directly "connected", "coupled", or "linked", but also indirectly "connected", "coupled", or "linked" via a third component. In describing positional relationships, for example, "element A on element B", "element A above element B", "element A below element B", and "element A beside element B", another element C can be disposed between element A and element B, unless the term "directly" or "exactly" is explicitly used.

[0045] The features of various exemplary embodiments of the disclosure can be partially or wholly coupled, combined, or separated. Various interactions and operations can be technically various. The various exemplary embodiments can be implemented individually or in combination.

[0046] Hereinafter, various examples of the embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0047] FIG. 1 is a block diagram schematically showing an example of a representation of a memory device 100 according to an embodiment of the disclosure.

[0048] Referring to FIG. 1The memory device 100 according to an embodiment of the disclosure can include a memory cell array 110 and a logic circuit 120. The logic circuit 120 can include a row decoder (X-DEC) 121, a page buffer circuit 122, and a peripheral circuit (PERI circuit) 123.

[0049] The memory cell array 110 can include a plurality of memory blocks BLK. The memory block BLK can include a plurality of memory cells. The memory block BLK can be coupled to the row decoder 121 through a plurality of row lines RL. The memory cell array 110 can be coupled to the page buffer circuit 122 through a plurality of bit lines BL.

[0050] The row decoder 121 can select any one of the plurality of memory blocks BLK included in the memory cell array 110 in response to a row address X_A provided from the peripheral circuit 123. The row decoder 121 can transfer an operation voltage X_V provided from the peripheral circuit 123 to the row line RL coupled to the memory block BLK selected from among the plurality of memory blocks BLK included in the memory cell array 110.

[0051] The page buffer circuit 122 can include a plurality of page buffers PB coupled to the bit lines BL, respectively. The page buffer circuit 122 can receive a page buffer control signal PB_C from the peripheral circuit 123, and can transmit and receive a data signal DATA to and from the peripheral circuit 123. The page buffer circuit 122 can control the bit lines BL disposed in the memory cell array 110 in response to the page buffer control signal PB_C. For example, the page buffer circuit 122 can detect data stored in the memory cells of the memory cell array 110 by sensing a signal of the bit lines BL of the memory cell array 110 in response to the page buffer control signal PB_C, and can transmit the data signal DATA to the peripheral circuit 123 according to the detected data. The page buffer circuit 122 can apply a signal to the bit lines BL based on the data signal DATA received from the peripheral circuit 123 in response to the page buffer control signal PB_C, and thereby can write data in the memory cells of the memory cell array 110. The page buffer circuit 122 can write data to or read data from the memory cells coupled to the activated word line.

[0052] The peripheral circuit 123 can receive a command signal CMD, an address signal ADD, and a control signal CTRL from outside the memory device 100, and can transmit and receive a data signal DATA to and from a device (e.g., a memory controller) outside the memory device 100. The peripheral circuit 123 can output a signal (e.g., a row address X_A and a page buffer control signal PB_C, etc.) for writing data to or reading data from the memory cell array 110 based on the command signal CMD, the address signal ADD, and the control signal CTRL. The peripheral circuit 123 can generate various voltages required for the memory device 100 including an operating voltage X_V.

[0053] Hereinafter, two directions parallel to a top surface of a substrate and intersecting each other in the drawings are defined as a first direction FD and a second direction SD, respectively, and a direction vertically protruding from the top surface of the substrate is defined as a vertical direction VD. For example, the first direction FD can correspond to an extension direction of a bit line, and the second direction SD can correspond to an extension direction of a row line. The first direction FD and the second direction SD can substantially perpendicularly intersect each other. The vertical direction VD can correspond to a direction perpendicular to the first direction FD and the second direction SD. In the drawings, a direction indicated by an arrow and a direction opposite thereto represent the same direction.

[0054] FIG. 2 is a schematic perspective view showing a representation of an example of a memory device. FIG. 1 is a schematic perspective view showing a representation of an example of a memory device.

[0055] Referring to FIG. 2 The memory device 100 according to the embodiment of the disclosure can include a first wafer W1 and a second wafer W2 disposed on the vertical direction VD and joined to each other. For the convenience of understanding, FIG. 2 is shown as being separated from each other in the vertical direction VD, but it is understood that the top surface of the first wafer W1 and the bottom surface of the second wafer W2 contact each other.

[0056] The first wafer W1 can include a logic structure P and a memory structure C stacked on the logic structure P. The logic structure P can include FIG. 1 a row decoder 121, a page buffer circuit 122, and a peripheral circuit 123 of the memory device 100. The memory structure C can include a plurality of first memory blocks (not shown).

[0057] The second wafer W2 can include a plurality of second memory blocks (not shown). The first memory blocks of the first wafer W1 and the second memory blocks of the second wafer W2 can constitute FIG. 1 a memory cell array 110 of the memory device 100.

[0058] A plurality of first bit lines BLa extending in the first direction FD and a plurality of first row lines RLa extending in the second direction SD can be provided in the first wafer W1. The first memory blocks defined in the first wafer W1 can be accessed by the plurality of first bit lines BLa and the plurality of first row lines RLa. For simplicity of illustration, FIG. 2 Only one first bit line BLa and only one first row line RLa are shown, but it is to be understood that a plurality of first bit lines BLa and a plurality of first row lines RLa are defined in the first wafer W1.

[0059] A plurality of second bit lines BLb extending in the first direction FD and a plurality of second row lines RLa extending in the second direction SD can be provided in the second wafer W2. The second memory blocks defined in the second wafer W2 can be accessed by the plurality of second bit lines BLb and the plurality of second row lines RLa. For simplicity of illustration, FIG. 2 Only one second bit line BLb and only one second row line RLa are shown, but it is to be understood that a plurality of second bit lines BLb and a plurality of second row lines RLa are defined in the second wafer W2.

[0060] Although not shown, the first and second bit lines BLa, BLb and the first and second row lines RLa, RLa can be electrically coupled to logic circuits defined in the logic structure P. The coupling structure between the first and second bit lines BLa, BLb and the first and second row lines RLa, RLa and the logic circuits will become apparent by referring to the following description made with reference to FIG. 21 to FIG. 25 The coupling structure between the first and second bit lines BLa, BLb and the first and second row lines RLa, RLa and the logic circuits will become apparent by referring to the following description made with reference to

[0061] FIG. 3 is a representation of an example of a schematic arrangement of the first and second wafers shown. FIG. 2 is a representation of an example of a schematic arrangement of the first and second wafers shown.

[0062] Referring to FIG. 3 The memory structure C of the first wafer W1 can comprise a plurality of first memory blocks BLK1 arranged in the first direction FD which is the direction of extension of the plurality of first bit lines BLa. The plurality of first memory blocks BLK1 can be commonly coupled to each of the plurality of first bit lines BLa. Although not shown, each first memory block BLK1 can comprise a plurality of cell strings coupled to the plurality of first bit lines BLa.

[0063] Each of the plurality of first memory blocks BLK1 can have the same size. The size of the first memory block BLK1 can be defined as the number of memory cells included in the first memory block BLK1. The number of memory cells included in the first memory block BLK1 can be proportional to the physical size of the first memory block BLK1. The physical size of the first memory block BLK1 can be defined by the width of the first memory block BLK1 in the first direction FD, the length of the first memory block BLK1 in the second direction SD, and the height of the first memory block BLK1 in the vertical direction VD. The size of the first memory block BLK1 can also be defined as the physical size of the first memory block BLK1. The size of the first memory block BLK1 can be defined as being proportional to the physical size of the first memory block BLK1.

[0064] The second wafer W2 can include a plurality of second memory blocks BLK2 arranged in the first direction FD which is the extension direction of the plurality of second bit lines BLb. The plurality of second memory blocks BLK2 can be commonly coupled to each of the plurality of second bit lines BLb. Although not shown, each of the second memory blocks BLK2 can include a plurality of cell strings coupled to the plurality of second bit lines BLb.

[0065] Each of the plurality of second memory blocks BLK2 can have the same size. The size of the second memory block BLK2 can be defined in the same manner as the size of the first memory block BLK1 described above.

[0066] The width of the first memory block BLK1 in the first direction FD can be A1. The width of the second memory block BLK2 in the first direction FD can be A2, A2 being greater than A1. The length of the first memory block BLK1 in the second direction SD and the length of the second memory block BLK2 in the second direction SD can be substantially the same. The height of the first memory block BLK1 in the vertical direction VD and the height of the second memory block BLK2 in the vertical direction VD can be substantially the same. Accordingly, the number of the second memory blocks BLK2 included in the second wafer W2 can be less than the number of the first memory blocks BLK1 included in the first wafer W1.

[0067] The physical size of the first memory block BLK1 can be smaller than the physical size of the second memory block BLK2. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0068] FIG. 4 is a cross-sectional view showing an example of a detailed structure of the first wafer and the second wafer. FIG. 3 is a cross-sectional view showing an example of a detailed structure of the first wafer and the second wafer.

[0069] Referring to FIG. 4The logic structure P may include a substrate 10 and a plurality of transistors TR defined on the substrate 10. Although not shown, the logic structure P may also include elements such as inductors, capacitors, and resistors. The transistors TR, inductors, capacitors, and resistors can constitute a logic circuit (e.g., FIG. 1 (of 120).

[0070] The memory structure C may include a substrate 12a and a plurality of electrode layers 20a and a plurality of interlayer dielectric layers 22a alternately stacked on the substrate 12a. The substrate 12a may be defined on a logic structure P. The electrode layers 20a may include a conductive material. For example, the electrode layers 20a may include at least one selected from doped semiconductors (e.g., doped silicon), metals (e.g., tungsten, copper, or aluminum), conductive metal nitrides (e.g., titanium nitride or tantalum nitride), and transition metals (e.g., titanium or tantalum). Among the electrode layers 20a, at least one electrode layer 20a starting from the bottommost electrode layer 20a may be configured with a source select line SSLa. Among the electrode layers 20a, at least one electrode layer 20a starting from the topmost electrode layer 20a may be configured with a drain select line DSLa. The electrode layers 20a between the source select line SSLa and the drain select line DSLa may be configured with word lines WLa. The interlayer dielectric layers 22a may include silicon oxide.

[0071] Multiple vertical channels Cha, passing through multiple electrode layers 20a and multiple interlayer dielectric layers 22a in the vertical direction VD, can be defined in the first wafer W1. Although not shown in detail, each vertical channel Cha may include a channel layer and a gate dielectric layer. The channel layer may include polysilicon or monocrystalline silicon and may include P-type impurities such as boron (B) in some regions therein. The gate dielectric layer may have a straw or cylindrical shell shape surrounding the outer wall of the channel layer. The gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a barrier layer sequentially stacked from the outer wall of the channel layer. In some embodiments, the gate dielectric layer may have an oxide-nitride-oxide (ONO) stack structure, wherein oxide layers, nitride layers, and oxide layers are sequentially stacked. A source select transistor may be configured around the vertical channel Cha via a source select line SSLa. A memory cell may be configured around the vertical channel Cha via a word line WLa. A drain select transistor may be configured around the vertical channel Cha via a drain select line DSLa. A cell string CSTRa can be configured by a source selection transistor, multiple memory cells, and a drain selection transistor arranged along a vertical channel CHa. The memory structure C can include multiple cell strings CSTRa.

[0072] Each of the plurality of first slits SLT1 is defined through the plurality of electrode layers 20a and the plurality of interlayer dielectric layers 22a. The plurality of first slits SLT1 divide the alternately stacked plurality of electrode layers 20a and the plurality of interlayer dielectric layers 22a into first memory block units. The first slits SLT1 can extend in the second direction SD and the perpendicular direction VD. The plurality of electrode layers 20a, the plurality of interlayer dielectric layers 22a, and the plurality of vertical channels CHa disposed between a pair of adjacent first slits SLT1 can configure one first memory block BLK1. The plurality of electrode layers 20a and the plurality of interlayer dielectric layers 22a included in one first memory block BLK1 can be defined as a first electrode structure ES1.

[0073] The plurality of first slits SLT1 can be arranged or aligned in the first direction FD, and thus, the plurality of first memory blocks BLK1 can be arranged or aligned in the first direction FD. The number of vertical channels CHa included in one first memory block BLK1 can be determined by the spacing between a pair of adjacent first slits SLT1.

[0074] The spacing between adjacent first slits SLT1 can be A1. A1 can correspond to the width of a first memory block BLK1 in the first direction FD. The number of vertical channels CHa included in different first memory blocks BLK1 can be the same, and thus, the number of cell strings CSTRa included in different first memory blocks BLK1 can be the same. The first memory blocks BLK1 can each include the same number of memory cells.

[0075] A first bit line BLa can be disposed over the plurality of first memory blocks BLK1. A bit line contact BLCa can be defined under the first bit line BLa to couple the first bit line BLa and the vertical channels CHa. FIG. 4 is a cross-sectional view taken along the first bit line BLa. Although FIG. 4 Only one first bit line BLa is shown, but it is understood that a plurality of first bit lines BLa are aligned in the second direction SD.

[0076] A dielectric layer 30a can be defined on the substrate 12a to fill the first slits SLT1 and cover the plurality of first memory blocks BLK1 and the first bit line BLa. A top surface of the dielectric layer 30a can constitute one surface of the first wafer W1 bonded to the second wafer W2. A bond pad PAD1 can be exposed on the top surface of the dielectric layer 30a. The bond pad PAD1 can be coupled to the first bit line BLa through a contact CNT1.

[0077] The second wafer W2 can include a substrate 12b and a plurality of electrode layers 20b and a plurality of interlayer dielectric layers 22b alternately stacked on a bottom surface of the substrate 12b. The electrode layers 20b can be formed of the same material as the electrode layers 20a. Among the electrode layers 20b, at least one electrode layer 20b from the uppermost electrode layer 20b can configure a source select line SSLb. Among the electrode layers 20b, at least one electrode layer 20b from the lowermost electrode layer 20b can configure a drain select line DSLb. The electrode layers 20b between the source select line SSLb and the drain select line DSLb can configure word lines WLb. The interlayer dielectric layers 22b can be formed of the same material as the interlayer dielectric layers 22a.

[0078] A plurality of vertical channels CHb passing through the electrode layers 20b and the interlayer dielectric layers 22b in the vertical direction VD can be defined in the second wafer W2. The vertical channels CHb can be configured in the same manner as the vertical channels CHa. A source select transistor can be configured at the vertical channel CHb surrounded by the source select line SSLb. A memory cell can be configured at the vertical channel CHb surrounded by the word line WLb. A drain select transistor can be configured at the vertical channel CHb surrounded by the drain select line DSLb. The source select transistor, the plurality of memory cells, and the drain select transistor disposed along one vertical channel CHb can configure one cell string CSTRb. The second wafer W2 can include a plurality of cell strings CSTRb.

[0079] Each of a plurality of second slits SLT2 is defined passing through the plurality of electrode layers 20b and the plurality of interlayer dielectric layers 22b. The plurality of second slits SLT2 divide the alternately stacked plurality of electrode layers 20b and the plurality of interlayer dielectric layers 22b into second memory block units. The second slits SLT2 can extend in the second direction SD and the vertical direction VD. The plurality of electrode layers 20b, the plurality of interlayer dielectric layers 22b, and the plurality of vertical channels CHb disposed between a pair of adjacent second slits SLT2 can configure one second memory block BLK2. The plurality of electrode layers 20b and the plurality of interlayer dielectric layers 22b included in one second memory block BLK2 can be defined as a second electrode structure ES2.

[0080] The number of layers of the word lines WLb of the second memory block BLK2 can be the same as the number of layers of the word lines WLa of the first memory block BLK1. Accordingly, the number of memory cells included in one cell string CSTRb can be the same as the number of memory cells included in one cell string CSTRa. The number of vertical channels CHa per unit area in the first memory block BLK1 and the number of vertical channels CHb per unit area in the second memory block BLK2 can be the same.

[0081] A plurality of second slits SLT2 can be arranged or arrayed in the first direction FD, and thus, a plurality of second memory blocks BLK2 can be arranged or arrayed in the first direction FD. The number of vertical channels CHb included in one second memory block BLK2 can be determined by the spacing between a pair of adjacent second slits SLT2.

[0082] The spacing between adjacent second slits SLT2 can be A2. A2 can correspond to the width of a second memory block BLK2 in the first direction FD. The number of vertical channels CHb (and the number of cell strings CSTRb) included in different second memory blocks BLK2 can be the same. The second memory blocks BLK2 can each include the same number of memory cells.

[0083] A1 can be less than A2, such that the number of vertical channels CHa (the number of cell strings CSTRa) included in a first memory block BLK1 can be less than the number of vertical channels CHb (the number of cell strings CSTRb) included in a second memory block BLK2.

[0084] A second bit line BLb can be disposed under the plurality of second memory blocks BLK2. A bit line contact BLCb can be defined over the second bit line BLb to couple the second bit line BLb and the vertical channels CHb. Although FIG. 4 Only one second bit line BLb is shown, but it is understood that a plurality of second bit lines BLb are arrayed in the second direction SD.

[0085] A dielectric layer 30b can be defined on a bottom surface of the substrate 12b to fill the second slits SLT2 and cover the plurality of second memory blocks BLK2 and the second bit line BLb. The bottom surface of the dielectric layer 30b can constitute one surface of the second wafer W2 that is bonded to one surface of the first wafer W1. Bonding pads PAD2 can be exposed on the bottom surface of the dielectric layer 30b. The bonding pads PAD2 can be coupled to the second bit line BLb through contacts CNT2. One surface of the second wafer W2 can be bonded to one surface of the first wafer W1, and the bonding pads PAD2 can be coupled to the bonding pads PAD1.

[0086] FIG. 5 is a circuit diagram showing FIG. 3 a representation of the example of the first memory block and the second memory block shown.

[0087] Reference is made to FIG. 5The first memory block BLK1 can include a plurality of cell strings CSTRa coupled between a plurality of first bit lines BLa and a common source line CSLa. The first bit lines BLa can extend in a first direction FD and can be arranged in a second direction SD. The plurality of cell strings CSTRa can be coupled in parallel to each of the first bit lines BLa. The plurality of cell strings CSTRa can be commonly coupled to the common source line CSLa. The plurality of cell strings CSTRa can be coupled between the plurality of first bit lines BLa and the common source line CSLa.

[0088] Each of the plurality of cell strings CSTRa can include a drain select transistor DSTa coupled to a first bit line BLa, a source select transistor SSTa coupled to a common source line CSLa, and a plurality of memory cells MCa coupled between the drain select transistor DSTa and the source select transistor SSTa. The drain select transistor DSTa, the plurality of memory cells MCa, and the source select transistor SSTa included in one cell string CSTRa can be coupled in series in a vertical direction VD.

[0089] The source select line SSLa, the plurality of word lines WLa, and the plurality of drain select lines DSl a can be arranged in the vertical direction VD between the common source line CSLa and the first bit lines BLa. Each of the drain select lines DSl a can be coupled to a gate of a corresponding drain select transistor DSTa. Each of the word lines WLa can be coupled to a gate of a corresponding memory cell MCa. The source select line SSLa can be coupled to a gate of the source select transistor SSTa. The memory cells MCa commonly coupled to one word line WLa can configure one physical page.

[0090] The second memory block BLK2 can include a plurality of cell strings CSTRb coupled between a plurality of second bit lines BLb and a common source line CSLb. The second bit lines BLb can extend in the first direction FD and can be arranged in the second direction SD. The plurality of cell strings CSTRb can be coupled in parallel to each of the second bit lines BLb. The plurality of cell strings CSTRb can be commonly coupled to the common source line CSLb. The plurality of cell strings CSTRb can be coupled between the plurality of second bit lines BLb and the common source line CSLb.

[0091] Each of the plurality of cell strings CSTRb can include a drain select transistor DSTb coupled to a second bit line BLb, a source select transistor SSTb coupled to a common source line CSLb, and a plurality of memory cells MCb coupled between the drain select transistor DSTb and the source select transistor SSTb. The drain select transistor DSTb, the plurality of memory cells MCb, and the source select transistor SSTb included in one cell string CSTRb can be coupled in series in a vertical direction VD.

[0092] The source select lines SSLb, the plurality of word lines WLb, and the drain select lines DSLb can be arranged in the vertical direction VD between the common source lines CSLb and the second bit lines BLb. Each drain select line DSLb can be coupled to a gate of a corresponding drain select transistor DSTb. Each word line WLb can be coupled to a gate of a corresponding memory cell MCb. A source select line SSLb can be coupled to a gate of a source select transistor SSTb. Memory cells MCb that are commonly coupled to a word line WLb can configure a physical page.

[0093] The number of the first bit lines BLa and the number of the second bit lines BLb can be the same as each other. The spacing between adjacent first bit lines BLa and the spacing between adjacent second bit lines BLb can be the same as each other. The number of memory cells MCA included in one cell string CSTRa and the number of memory cells MCb included in one cell string CSTRb can be the same as each other.

[0094] The number of memory cells MCA coupled to a word line WLa in a first memory block BLK1 can be less than the number of memory cells MCb coupled to a word line WLb in a second memory block BLK2. For example, the number of memory cells MCA coupled to a word line WLa in a first memory block BLK1 can be half of the number of memory cells MCb coupled to a word line WLb in a second memory block BLK2.

[0095] The number of cell strings CSTRa included in a first memory block BLK1 can be less than the number of cell strings CSTRb included in a second memory block BLK2. For example, each first bit line BLa can be coupled to two cell strings CSTRa of a first memory block BLK1, and each second bit line BLb can be coupled to four cell strings CSTRb of a second memory block BLK2. In this case, the number of cell strings CSTRa included in a first memory block BLK1 can be half of the number of cell strings CSTRb included in a second memory block BLK2.

[0096] The number of memory cells MCA included in a first memory block BLK1 can be less than the number of memory cells MCb included in a second memory block BLK2. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0097] Although the above refers to the memory array 100 as an example, the memory array 100 can be replaced by another memory array. For example, the memory array 100 can be replaced by a memory array including a plurality of memory blocks, each of which includes a plurality of cell strings, each of which includes a plurality of memory cells. FIG. 3 to FIG. 5The described embodiment shows an example in which the number of cell strings CSTRa included in the first memory block BLK1 is half the number of cell strings CSTRb included in the second memory block BLK2, but the present disclosure is not limited to this. The ratio of the number of cell strings CSTRa included in the first memory block BLK1 to the number of cell strings CSTRb included in the second memory block BLK2 can be variously changed.

[0098] FIG. 6 is a representation showing an example of a detailed structure of the first wafer and the second wafer shown in FIG. 2 is a representation showing an example of a detailed structure of the first wafer and the second wafer shown in

[0099] Referring to FIG. 6 , the width of the first memory block BLK1 in the first direction FD can be Al. The width of the second memory block BLK2 in the first direction FD can be A2, which is smaller than Al. Therefore, the number of first memory blocks BLK1 included in the first wafer Wl can be smaller than the number of second memory blocks BLK2 included in the second wafer W2.

[0100] The length of the first memory block BLK1 in the second direction SD and the length of the second memory block BLK2 in the second direction SD can be substantially the same. The height of the first memory block BLK1 in the vertical direction VD and the height of the second memory block BLK2 in the vertical direction VD can be substantially the same.

[0101] The physical size of the first memory block BLK1 can be larger than the physical size of the second memory block BLK2. The first memory block BLK1 can be a large block, and the second memory block BLK2 can be a small block.

[0102] FIG. 7 is a representation showing an example of a detailed structure of the first wafer and the second wafer shown in FIG. 6 is a representation showing an example of a detailed structure of the first wafer and the second wafer shown in

[0103] Referring to FIG. 7 , the interval Al between adjacent first slits SLT1 can be larger than the interval A2 between adjacent second slits SLT2. That is, the width of the first memory block BLK1 in the first direction FD can be larger than the width of the second memory block BLK2 in the first direction FD.

[0104] In FIG. 7 , the number of cell strings CSTRa included in one first memory block BLK1 can be larger than the number of cell strings CSTRb included in one second memory block BLKb.

[0105] FIG. 8 is a representation showing an example of a detailed structure of the first wafer and the second wafer shown in FIG. 6A circuit diagram showing an example of a representation of the first memory block and the second memory block.

[0106] Referring to FIG. 8 The number of memory cells Mca coupled to one word line WLa in a first memory block BLK1 can be greater than the number of memory cells MCb coupled to one word line WLb in a second memory block BLK2. For example, the number of memory cells Mca coupled to one word line WLa in a first memory block BLK1 can be twice the number of memory cells MCb coupled to one word line WLb in a second memory block BLK2.

[0107] The number of cell strings CSTRa included in the first memory block BLK1 can be greater than the number of cell strings CSTRb included in the second memory block BLK2. For example, each first bit line BLa can be coupled to four cell strings CSTRa of the first memory block BLK1, and each second bit line BLb can be coupled to two cell strings CSTRb of the second memory block BLK2. In this case, the number of cell strings CSTRa included in the first memory block BLK1 can be twice the number of cell strings CSTRb included in the second memory block BLK2.

[0108] The number of memory cells Mca included in the first memory block BLK1 can be greater than the number of memory cells MCb included in the second memory block BLK2. The first memory block BLK1 can be a large block, and the second memory block BLK2 can be a small block.

[0109] Although the embodiments described above with reference to FIG. 6 to FIG. 8 show an example in which the number of cell strings CSTRa included in the first memory block BLK1 is twice the number of cell strings CSTRb included in the second memory block BLK2, the present disclosure is not limited thereto. The ratio of the number of cell strings CSTRa included in the first memory block BLK1 to the number of cell strings CSTRb included in the second memory block BLK2 can be variously changed.

[0110] FIG. 9 is a diagram showing an example of a representation of another schematic arrangement of the first wafer and the second wafer. FIG. 2

[0111] Referring to FIG. 9 ​The width of the first memory block BLK1 in the first direction FD and the width of the second memory block BLK2 in the first direction FD can be substantially the same. The length of the first memory block BLK1 in the second direction SD and the length of the second memory block BLK2 in the second direction SD can be substantially the same. The height of the first memory block BLK1 in the vertical direction VD can be H1. The height of the second memory block BLK2 in the vertical direction VD can be H2, which is greater than H1.

[0112] The physical size of the first memory block BLK1 can be smaller than the physical size of the second memory block BLK2. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0113] FIG. 10 is a cross-sectional view showing an example of a detailed structure of the first wafer and the second wafer shown in FIG. 9

[0114] Referring to FIG. 10 , the interval A1 between adjacent first slits SLT1 and the interval A2 between adjacent second slits SLT2 can be the same as each other. The width of the first memory block BLK1 in the first direction FD and the width of the second memory block BLK2 in the first direction FD can be the same as each other. As described previously with reference to FIG. 9 , the length of the first memory block BLK1 in the second direction SD and the length of the second memory block BLK2 in the second direction SD can be substantially the same. In this case, the number of cell strings CSTRa included in the first memory block BLK1 and the number of cell strings CSTRb included in the second memory block BLKb can be the same as each other.

[0115] The number of layers of word lines WLa of the first memory block BLK1 can be smaller than the number of layers of word lines WLb of the second memory block BLK2. As a result, the number of memory cells included in one cell string CSTRa can be smaller than the number of memory cells included in one cell string CSTRb. For example, the number of layers of word lines WLa of the first memory block BLK1 can be half the number of layers of word lines WLb of the second memory block BLK2, and the number of memory cells included in one cell string CSTRa can be half the number of memory cells included in one cell string CSTRb.

[0116] FIG. 11 is a circuit diagram showing an example of a detailed structure of the first memory block and the second memory block shown in FIG. 9

[0117] Referring to FIG. 11 ​​The number of cell strings CSTRa included in the first memory block BLK1 and the number of cell strings CSTRb included in the second memory block BLK2 can be the same as each other.

[0118] The number of memory cells MCA included in one cell string CSTRa can be smaller than the number of memory cells MCb included in one cell string CSTRb. For example, the number of memory cells MCA included in one cell string CSTRa can be half of the number of memory cells MCb included in one cell string CSTRb. The number of memory cells MCA included in the first memory block BLK1 can be smaller than the number of memory cells MCb included in the second memory block BLK2. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0119] FIG. 12 is a representation of an example of a detailed structure of the first wafer and the second wafer shown in FIG. 1. FIG. 2 is a representation of an example of a detailed structure of the first wafer and the second wafer shown in FIG. 1.

[0120] Referring to FIG. 12 The width of the first memory block BLK1 in the first direction FD and the width of the second memory block BLK2 in the first direction FD can be substantially the same. The length of the first memory block BLK1 in the second direction SD and the length of the second memory block BLK2 in the second direction SD can be substantially the same. The height of the first memory block BLK1 in the vertical direction VD can be HI. The height of the second memory block BLK2 in the vertical direction VD can be H2, which is smaller than HI.

[0121] The physical size of the first memory block BLK1 can be larger than the physical size of the second memory block BLK2. The first memory block BLK1 can be a large block, and the second memory block BLK2 can be a small block.

[0122] FIG. 13 is a representation of an example of a detailed structure of the first wafer and the second wafer shown in FIG. 1. FIG. 12 is a representation of an example of a detailed structure of the first wafer and the second wafer shown in FIG. 1.

[0123] Referring to FIG. 13 The interval Al between adjacent first slits SLT1 and the interval A2 between adjacent second slits SLT2 can be the same as each other. The width of the first memory block BLK1 in the first direction FD and the width of the second memory block BLK2 in the first direction FD can be the same as each other. As previously described with reference to FIG. 12The length of the first memory block BLK1 in the second direction SD and the length of the second memory block BLK2 in the second direction SD can be substantially the same. In this case, the number of cell strings CSTRa included in the first memory block BLK1 and the number of cell strings CSTRb included in the second memory block BLK2 can be the same as each other.

[0124] The number of layers of word lines WLa of the first memory block BLK1 can be greater than the number of layers of word lines WLb of the second memory block BLK2. As a result, the number of memory cells included in one cell string CSTRa can be greater than the number of memory cells included in one cell string CSTRb. For example, the number of layers of word lines WLa of the first memory block BLK1 can be twice the number of layers of word lines WLb of the second memory block BLK2, and the number of memory cells included in one cell string CSTRa can be twice the number of memory cells included in one cell string CSTRb.

[0125] FIG. 14 is a representation of an example of another schematic arrangement of first and second wafers. FIG. 12 is a circuit diagram showing a representation of an example of the first and second memory blocks shown.

[0126] Referring to FIG. 14 The number of cell strings CSTRa included in the first memory block BLK1 and the number of cell strings CSTRb included in the second memory block BLK2 can be the same as each other.

[0127] The number of memory cells MCa included in each cell string CSTRa can be greater than the number of memory cells MCb included in each cell string CSTRb. For example, the number of memory cells MCa included in a cell string CSTRa can be twice the number of memory cells MCb included in a cell string CSTRb. The number of memory cells MCa included in the first memory block BLK1 can be greater than the number of memory cells MCb included in the second memory block BLK2. The first memory block BLK1 can be a large block, and the second memory block BLK2 can be a small block.

[0128] FIG. 15 is a representation of an example of another schematic arrangement of first and second wafers. FIG. 2 is a representation of an example of another schematic arrangement of first and second wafers.

[0129] Referring to FIG. 15The width of the first memory block BLK1 in the first direction FD can be Al. The width of the second memory block BLK2 in the first direction FD can be A2, which is greater than Al. As a result, the number of the second memory blocks BLK2 included in the second wafer W2 can be smaller than the number of the first memory blocks BLK1 included in the first wafer Wl.

[0130] The length of the first memory block BLK1 in the second direction SD and the length of the second memory block BLK2 in the second direction SD can be substantially the same. The height of the first memory block BLK1 in the vertical direction VD can be HI. The height of the second memory block BLK2 in the vertical direction VD can be H2, which is greater than HI.

[0131] The physical size of the first memory block BLK1 can be smaller than the physical size of the second memory block BLK2. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0132] FIG. 16 is a cross-sectional view showing an example of a detailed structure of the first wafer and the second wafer. FIG. 15 is a cross-sectional view showing an example of a detailed structure of the first wafer and the second wafer.

[0133] Referring to FIG. 16 , the interval Al between adjacent first slits SLT1 can be smaller than the interval A2 between adjacent second slits SLT2. That is, the width of the first memory block BLK1 in the first direction FD can be smaller than the width of the second memory block BLK2 in the first direction FD. As previously described with reference to FIG. 15 , the length of the first memory block BLK1 in the second direction SD and the length of the second memory block BLK2 in the second direction SD can be substantially the same. The number of cell strings CSTRa included in the first memory block BLK1 can be smaller than the number of cell strings CSTRb included in the second memory block BLK2.

[0134] The number of layers of word lines WLa of the first memory block BLK1 can be smaller than the number of layers of word lines WLb of the second memory block BLK2. As a result, the number of memory cells included in one cell string CSTRa can be smaller than the number of memory cells included in one cell string CSTRb. For example, the number of layers of word lines WLa of the first memory block BLK1 can be half the number of layers of word lines WLb of the second memory block BLK2, and the number of memory cells included in one cell string CSTRa can be half the number of memory cells included in one cell string CSTRb.

[0135] FIG. 17 is a cross-sectional view showing an example of a detailed structure of the first wafer and the second wafer. FIG. 15a circuit diagram of an example of a representation of the first memory block and the second memory block.

[0136] Referring to FIG. 17 The number of memory cells Mca coupled to one word line WLa in the first memory block BLK1 can be less than the number of memory cells MCb coupled to one word line WLb in the second memory block BLK2. For example, the number of memory cells Mca coupled to one word line WLa in the first memory block BLK1 can be half the number of memory cells MCb coupled to one word line WLb in the second memory block BLK2.

[0137] The number of cell strings CSTRa included in the first memory block BLK1 can be less than the number of cell strings CSTRb included in the second memory block BLK2. For example, each first bit line BLa can be coupled to two cell strings CSTRa of the first memory block BLK1, and each second bit line BLb can be coupled to four cell strings CSTRb of the second memory block BLK2. In this case, the number of cell strings CSTRa included in the first memory block BLK1 can be half the number of cell strings CSTRb included in the second memory block BLK2.

[0138] The number of memory cells Mca included in each cell string CSTRa can be less than the number of memory cells MCb included in each cell string CSTRb. For example, the number of memory cells Mca included in one cell string CSTRa can be half the number of memory cells MCb included in one cell string CSTRb.

[0139] In one example, the number of memory cells Mca included in the first memory block BLK1 can be one quarter (1 / 4) of the number of memory cells MCb included in the second memory block BLK2. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0140] Although in the foregoing examples, the number of memory cells Mca included in the first memory block BLK1 is less than the number of memory cells MCb included in the second memory block BLK2, the number of memory cells Mca included in the first memory block BLK1 can be greater than the number of memory cells MCb included in the second memory block BLK2. FIG. 15 to FIG. 17In the described embodiment, the number of cell strings CSTRa included in the first memory block BLK1 is less than the number of cell strings CSTRb included in the second memory block BLK2, and the number of memory cells M Ca included in one cell string CSTRa in the first memory block BLK1 is less than the number of memory cells MCb included in one cell string CSTRb in the second memory block BLK2, but relative or opposite embodiments can also be employed. In other words, the number of cell strings CSTRa included in the first memory block BLK1 can be greater than the number of cell strings CSTRb included in the second memory block BLK2, and the number of memory cells M Ca included in one cell string CSTRa in the first memory block BLK1 can be greater than the number of memory cells MCb included in one cell string CSTRb in the second memory block BLK2.

[0141] FIG. 18 is a representation of an example of a detailed structure of the first wafer and the second wafer shown in FIG. 2 is a representation of an example of a detailed structure of the first wafer and the second wafer shown in

[0142] Referring to FIG. 18 , the width of the first memory block BLK1 in the first direction FD can be Al. The width of the second memory block BLK2 in the first direction FD can be A2, which is less than Al. As a result, the number of first memory blocks BLK1 included in the first wafer Wl can be less than the number of second memory blocks BLK2 included in the second wafer W2.

[0143] The length of the first memory block BLK1 in the second direction SD and the length of the second memory block BLK2 in the second direction SD can be substantially the same. The height Hl of the first memory block BLK1 in the vertical direction VD can be less than the height H2 of the second memory block BLK2 in the vertical direction VD.

[0144] FIG. 19 is a representation of an example of a detailed structure of the first wafer and the second wafer shown in FIG. 18 is a representation of an example of a detailed structure of the first wafer and the second wafer shown in

[0145] Referring to FIG. 19 , the spacing Al between adjacent first slits SLT1 can be greater than the spacing A2 between adjacent second slits SLT2. That is, the width of the first memory block BLK1 in the first direction FD can be greater than the width of the second memory block BLK2 in the first direction FD. As previously mentioned with reference to FIG. 18The length of the first memory block BLK1 in the second direction SD and the length of the second memory block BLK2 in the second direction SD can be substantially the same. The number of cell strings CSTRa included in the first memory block BLK1 can be greater than the number of cell strings CSTRb included in the second memory block BLK2.

[0146] The number of layers of word lines WLa of the first memory block BLK1 can be less than the number of layers of word lines WLb of the second memory block BLK2. As a result, the number of memory cells included in one cell string CSTRa can be less than the number of memory cells included in one cell string CSTRb.

[0147] FIG. 20 is a circuit diagram showing an example of a representation of the first memory block and the second memory block. FIG. 18 is a circuit diagram showing an example of a representation of the first memory block and the second memory block.

[0148] Referring to FIG. 20 The number of memory cells MCa coupled to one word line WLa in the first memory block BLK1 can be greater than the number of memory cells MCb coupled to one word line WLb in the second memory block BLK2. For example, the number of memory cells MCa coupled to one word line WLa in the first memory block BLK1 can be twice the number of memory cells MCb coupled to one word line WLb in the second memory block BLK2.

[0149] The number of cell strings CSTRa included in the first memory block BLK1 can be greater than the number of cell strings CSTRb included in the second memory block BLK2. For example, each first bit line BLa can be coupled to four cell strings CSTRa of the first memory block BLK1, and each second bit line BLb can be coupled to two cell strings CSTRb of the second memory block BLK2. In this case, the number of cell strings CSTRa included in the first memory block BLK1 can be twice the number of cell strings CSTRb included in the second memory block BLK2.

[0150] The number of memory cells MCa included in one cell string CSTRa can be less than the number of memory cells MCb included in one cell string CSTRb. For example, the number of memory cells MCa included in one cell string CSTRa can be three, and the number of memory cells MCb included in one cell string CSTRb can be eight.

[0151] In this case, the number of memory cells Mca included in the first memory block BLK1 can be defined as the product of the number of cell strings CSTRa coupled to one first bit line BLa in the first memory block BLK1 (four), the number of memory cells Mca included in one cell string CSTRa (three), and the number of first bit lines BLa. That is, the number of memory cells Mca included in the first memory block BLK1 can be twelve (12) times the number of first bit lines BLa. Also, the number of memory cells Mcb included in the second memory block BLK2 can be defined as the product of the number of cell strings CSTRb coupled to one second bit line BLb in the second memory block BLK2 (two), the number of memory cells Mcb included in one cell string CSTRb (eight), and the number of second bit lines BLb. That is, the number of memory cells Mcb included in the second memory block BLK2 can be sixteen (16) times the number of second bit lines BLb.

[0152] Since the number of first bit lines BLa and the number of second bit lines BLb are the same, the ratio of the number of memory cells Mca included in the first memory block BLK1 to the number of memory cells Mcb included in the second memory block BLK2 can be 12:16. The first memory block BLK1 can be a small block, and the second memory block BLK2 can be a large block.

[0153] Hereinafter, a structure in which a memory cell array and a logic circuit of a memory device according to an embodiment of the disclosure are coupled will be described with reference to FIG. 21 to FIG. 25

[0154] FIG. 21 is a sectional view showing an example of a representation of a coupling structure between a bit line and a page buffer circuit of a memory device according to an embodiment of the disclosure.

[0155] Referring to FIG. 21 , the logic structure P can include a transistor TR_PB defined on the substrate 10. FIG. 21 The transistor TR_PB shown can configure a page buffer circuit.

[0156] As described above with reference to FIG. 4 , the first bit line BLa of the first wafer W1 and the second bit line BLb of the second wafer W2 corresponding thereto can be coupled to each other through the contact CNT1 and CNT2 and the bonding pads PAD1 and PAD2. The first bit line BLa of the first wafer W1 can be coupled to the transistor TR_PB through the contact CNT11 and CNT12 and the wiring M11.

[0157] ​To insulate the electrode layer 20a and the contact CNT11 from each other, the dielectric layer 24a (instead of the electrode layer 20a) can be alternately layered with the interlayer dielectric layer 22a in a partial region. That is, in the partial region, a plurality of dielectric layers 24a can be alternately layered with a plurality of interlayer dielectric layers 22a on the substrate 12a. The dielectric layer 24a can be formed of a dielectric material having etching selectivity with respect to the interlayer dielectric layer 22a. For example, the interlayer dielectric layer 22a can be silicon oxide, and the dielectric layer 24a can be silicon nitride.

[0158] The contact CNT11 can pass through the plurality of interlayer dielectric layers 22a and the plurality of dielectric layers 24a that are alternately layered in the vertical direction VD.

[0159] FIG. 22 is a cross-sectional view showing an example of a representation of a coupling structure between a row line and a row decoder of a memory device according to an embodiment of the present disclosure.

[0160] Referring to FIG. 22 , the memory device can include a plurality of cell regions CAR1 and CAR2 and a plurality of coupling regions CNR1 and CNR2. The plurality of cell regions CAR1 and CAR2 and the plurality of coupling regions CNR1 and CNR2 can be alternately disposed in the second direction SD. Hereinafter, for convenience of explanation, a coupling region CNR1 disposed between adjacent cell regions CAR1 and CAR2 will be defined as a first coupling region, and a coupling region CNR2 disposed at an edge of the memory device will be defined as a second coupling region. The cell region CAR2 can be disposed between the first coupling region CNR1 and the second coupling region CNR2.

[0161] The second transistor TR2_XDEC and the plurality of first transistors TR1_XDEC can be defined on the substrate 10 of the logic structure P. FIG. 22 is a cross-sectional view taken along the arrangement direction of the drain regions of the second transistor TR2_XDEC and the plurality of first transistors TR1_XDEC, and it should be understood that FIG. 22 Elements such as gate regions and source regions of the first transistors TR1_XDEC and the second transistors TR2_XDEC other than the drain regions are not shown. Although for simplicity of illustration, FIG. 22 only one second transistor TR2_XDEC is shown, it should be understood that a plurality of second transistors TR2_XDEC corresponding to a plurality of electrode layers 20a are defined on the substrate 10.

[0162] The plurality of first transistors TR1_XDEC can be transfer transistors for transferring an operating voltage to the electrode layer 20b of the second wafer W2, and the plurality of second transistors TR2_XDEC can be transfer transistors for transferring an operating voltage to the electrode layer 20a of the first wafer W1.FIG. 22 The first transistor TR1_XDEC and the second transistor TR2_XDEC shown can configure a row decoder.

[0163] In this embodiment, a plurality of the first transistors TR1_XDEC can be provided in the first coupling region CNR1. A plurality of bonding pads PAD3 respectively corresponding to the first transistors TR1_XDEC can be defined on one surface of the first wafer W1 bonded to the second wafer W2 in the first coupling region CNR1. Each bonding pad PAD3 can be coupled to the corresponding first transistor TR1_XDEC through the contacts CNT21, CNT22, and CNT23 and the wirings M21 and M22.

[0164] To insulate the electrode layer 20a and the contact CNT22 from each other, a dielectric layer 24a (instead of the electrode layer 20a) can be alternately stacked with the interlayer dielectric layer 22a in the first coupling region CNR1. That is, in the first coupling region CNR1, a dielectric stack can be defined since a plurality of the dielectric layers 24a are alternately stacked with a plurality of the interlayer dielectric layers 22a on the substrate 12a. The dielectric layer 24a can be formed of a dielectric material having etching selectivity with respect to the interlayer dielectric layer 22a. For example, the interlayer dielectric layer 22a can be silicon oxide, and the dielectric layer 24a can be silicon nitride. In the first coupling region CNR1, the contact CNT22 can pass through the plurality of the interlayer dielectric layers 22a and the plurality of the dielectric layers 24a alternately stacked in the vertical direction VD.

[0165] In the first coupling region CNR1, each electrode layer 20b of the second wafer W2 can have a pad portion LPb. Since the pad portions LPb of the electrode layers 20b are staggered from each other, a stepped structure can be configured. The contact CNT24 can be coupled to the pad portion LPb of the electrode layer 20b. In the first coupling region CNR1, the pad portion LPb of the electrode layer 20b can overlap with the insulating stack (i.e., the plurality of the interlayer dielectric layers 22a and the plurality of the dielectric layers 24a of the alternate stack) of the first wafer W1 in the vertical direction VD.

[0166] In the first coupling region CNR1, bonding pads PAD4 respectively corresponding to the pad portions LPb of the electrode layers 20b can be defined on one surface of the second wafer W2 bonded to the first wafer W1. The contact CNT24 coupled to the pad portion LPb of the electrode layer 20b can be coupled to the bonding pad PAD4 through the wiring M23 and the contact CNT25. The bonding pads PAD4 of the second wafer W2 can be bonded to the bonding pads PAD3 of the first wafer W1, respectively, to configure an electrical path coupling the electrode layer 20b and the first transistor TR1_XDEC.

[0167] In the second coupling region CNR2, each of the electrode layers 20a of the first wafer W1 can have a land portion LPa. Since the land portions LPa of the electrode layers 20a are staggered with each other, a step structure can be configured.

[0168] The contact CNT26 can be coupled to the land portion LPa of the electrode layer 20a. The contact CNT26 can be coupled to the second transistor TR2_XDEC through the wirings M24 and M25 and the contacts CNT27 and CNT28. In this way, an electrical path coupling the electrode layer 20a and the second transistor TR2_XDEC can be configured. Although only one of each of the contacts CNT26, CNT27, and CNT28 and the wirings M24 and M25 is shown for simplicity of illustration, FIG. 22 It is to be understood that each of the contacts CNT26, CNT27, and CNT28 and the wirings M24 and M25 can be provided as a plurality.

[0169] FIG. 23 is a plan view showing an example of a representation of the main constituent elements of the first coupling region. FIG. 22

[0170] Referring to FIG. 23 From a plan view, the land portions LPb of the electrode layers 20b can be arranged in the second direction SD. Each of the land portions LPb can have a first length dl in the second direction SD.

[0171] An active region ACT defined by the isolation layer can be defined in the substrate 10. The active region ACT can be arranged in the second direction SD. A gate G extending in the second direction SD and traversing the active region ACT can be defined on the substrate 10. Since the active region ACT is doped with impurities on both sides of the gate G, a drain region and a source region can be defined. The gate G and the drain region and the source region on both sides of the gate G can be included in the first transistor TR1_XDEC.

[0172] The first transistors TR1_XDEC can be provided at a constant pitch in the second direction SD. The pitch of the first transistors TR1_XDEC can be defined as a sum of a width of one active region ACT in the second direction SD and a spacing between adjacent edges of adjacent active regions ACT in the second direction SD. The pitch of the first transistors TR1_XDEC can be substantially the same as the first length dl that is the length of the land portions LPb in the second direction SD.

[0173] The contact CNT22 can overlap the drain region of the corresponding first transistor TR1_XDEC in the vertical direction VD. As described above with reference to FIG. 22 ​The first transistor TR1_XDEC can be coupled to the corresponding pad portion LPb through the contact CNT22. The first transistor TR1_XDEC can overlap the corresponding pad portion LPb in the vertical direction VD. By disposing the first transistor TR1_XDEC and the pad portion LPb coupled to each other to overlap each other in the vertical direction VD, an electrical path coupling the first transistor TR1_XDEC and the pad portion LPb can be configured in a linear shape. Accordingly, a length of the electrical path can be minimized, so that a load of the electrical path can be minimized, thereby helping to improve operational reliability of the memory device. Further, due to the configuration of the electrical path, area consumption can be reduced, thereby helping to reduce the size of the memory device.

[0174] As described above with reference to FIG. 3 to FIG. 20 , the memory device can include small blocks and large blocks. In some embodiments, a width of the large blocks in the first direction FD can be configured to be greater than a width of the small blocks in the first direction FD. In such embodiments, a number of the large blocks included in the memory device can be less than a number of the small blocks included therein. Accordingly, compared to embodiments in which all memory blocks are configured as small blocks, only a small number of electrical paths are needed to couple the word lines and the logic circuit. In the memory device according to some embodiments of the disclosure, the number of electrical paths coupling the word lines and the logic circuit can be reduced, thereby helping to reduce complexity of wiring configuring the electrical paths, and facilitating design of the wiring.

[0175] FIG. 24A to FIG. 24E is a cross-sectional view showing an example of a representation of a step of manufacturing a memory structure of a first wafer according to an embodiment of the disclosure.

[0176] Referring to FIG. 24A , as the plurality of interlayer dielectric layers 22a and the plurality of dielectric layers 24a are alternately laminated on the substrate 12a, a pre-lamination PS can be formed. Although not shown, the substrate 12a can be disposed on the logic structure P (see FIG. 22 ). The interlayer dielectric layers 22a and the dielectric layers 24a can be formed of different materials. The dielectric layers 24a as sacrificial layers can be formed of a material having etch selectivity with respect to the interlayer dielectric layers 22a. For example, the interlayer dielectric layers 22a can be formed of an oxide, and the dielectric layers 24a can be formed of a nitride.

[0177] A mask pattern PR exposing a portion of the second coupling region CNR2 can be formed on the pre-lamination PS. The pre-lamination PS can be etched by a pad etching process using the mask pattern PR as an etching mask. An etching thickness of the pad etching process can correspond to a vertical pitch of the interlayer dielectric layers 22a. The vertical pitch of the interlayer dielectric layers 22a can be defined as a sum of a thickness of one interlayer dielectric layer 22a and a thickness of one dielectric layer 24a.

[0178] A trimming process can be performed on the mask pattern PR. That is, an isotropic etching can be performed on the mask pattern PR. The trimming process can be performed using an etchant capable of removing the mask pattern PR. Thus, the height and width of the mask pattern PR can be reduced. As the width of the mask pattern PR is reduced, the area of the second connection region CNR2 exposed by the mask pattern PR can be increased. The pad etching process and the trimming process can constitute one cycle for forming one step in the second connection region CNR2.

[0179] Referring to FIG. 24B As the cycle is repeated multiple times, a step structure can be formed in the second connection region CNR2 in the pre-stack PS. The step structure can have multiple steps respectively corresponding to the multiple dielectric layers 24a. The mask pattern PR can be formed of photoresist, and can be removed after the step structure is formed.

[0180] Referring to FIG. 24C A dielectric layer 31 covering the pre-stack PS can be formed on the substrate 12a. A slit passing through the dielectric layer 31 and the pre-stack PS in the vertical direction VD can be formed at the periphery of the first connection region CNR1, and a sidewall dielectric layer 40 can be formed by filling the slit.

[0181] The sidewall dielectric layer 40 used as an etching barrier in a process of subsequently removing the dielectric layer 24a can be formed of a material having etching selectivity with respect to the dielectric layer 24a. For example, in the case where the dielectric layer 24a is formed of nitride, the sidewall dielectric layer 40 can be formed of oxide.

[0182] Multiple vertical channels CHa passing through the dielectric layer 31 and the pre-stack PS in the vertical direction VD can be defined in the first cell region CAR1 and the second cell region CAR2. The order of the process of forming the sidewall dielectric layer 40 and the process of forming the vertical channels CHa can be reversed.

[0183] Referring to FIG. 24D An etching process for removing the dielectric layer 24a can be performed. For this etching process, an etchant capable of removing the dielectric layer 24a can be introduced. As the sidewall dielectric layer 40 is used as an etching barrier in the etching process, the dielectric layer 24a of the first connection region CNR1 can be left without being removed, and the dielectric layer 24a of the first cell region CAR1 and the second cell region CAR2 and the second connection region CNR2 can be removed to create empty spaces.

[0184] The structure stability of the pre-stack PS can be decreased due to the empty space generated by removing the dielectric layer 24a. The dielectric layer 24a remaining in the first coupling region CNR1 can support the interlayer dielectric layer 22a to increase the structure stability, thereby preventing the bending or collapse of the pre-stack PS.

[0185] Referring to FIG. 24E The electrode layer 20a can be defined by filling a conductive material in the space where the dielectric layer 24a is removed. The conductive material can include at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum).

[0186] FIG. 25 is a cross-sectional view showing an example of a representation of another coupling structure between a row line and a row decoder of a memory device according to an embodiment of the disclosure.

[0187] Referring to FIG. 25 The plurality of cell regions CAR and the plurality of coupling regions CNR can be alternately arranged in the second direction SD. Each of the coupling regions CNR can be divided into a first coupling region CNR1 and a second coupling region CNR2. The first coupling region CNR1 and the second coupling region CNR2 included in one coupling region CNR can be arranged adjacent to each other in the second direction SD.

[0188] The plurality of electrode layers 20a and the plurality of interlayer dielectric layers 22a can be alternately stacked on the substrate 12a of the first wafer W1 in the cell regions CAR and the second coupling regions CNR2. A plurality of vertical channels CHa passing through the electrode layers 20a and the interlayer dielectric layers 22a alternately stacked in the vertical direction VD can be defined in the cell regions CAR.

[0189] Each of the electrode layers 20a can have a land portion LPa. The contact CNT31 can be coupled to the land portion LPa. Although for simplicity of illustration, FIG. 25 A limited number of the contacts CNT31 coupled to the land portions LPa are shown, but it is understood that the contacts CNT31 are coupled to the land portions LPa of each of the electrode layers 20a.

[0190] The land portions LPa of the electrode layers 20a can be arranged in the second coupling regions CNR2. The land portions LPa of the electrode layers 20a can be grouped into a plurality of groups according to a distance between the land portions LPa and the substrate 12a, each group being arranged in a different second coupling region CNR2. For example, the land portions LPa of the electrode layers 20a can be grouped into land portions LPa of the electrode layers 20a located relatively close to the substrate 12a in the vertical direction VD and land portions LPa of the electrode layers 20a located relatively far from the substrate 12a in the vertical direction VD. In FIG. 25In particular, pad portions LPa located relatively close to the electrode layer 20a of the substrate 12a can be provided in one second connection zone CN2 (e.g., on the left side in FIG. 25 In particular, pad portions LPa located relatively close to the electrode layer 20a of the substrate 12a can be provided in one second connection zone CN2 (e.g., on the left side in FIG. 25 In particular, pad portions LPa located relatively close to the electrode layer 20a of the substrate 12a can be provided in one second connection zone CN2 (e.g., on the left side in

[0191] In each second connection zone CNR2, a step structure can be configured since the pad portions LPa of the electrode layer 20a are staggered with respect to each other. The number of pad portions LPa provided in one second connection zone CNR2 can be less than the number of layers of the electrode layer 20a.

[0192] In each first connection zone CNR1, a dielectric stack can be configured since the plurality of dielectric layers 24a and the plurality of interlayer dielectric layers 22a are alternately stacked on the substrate 12a of the first wafer Wl. The dielectric layers 24a can be respectively provided on the same layers as the electrode layers 20a. The dielectric layers 24a can have the same thickness as the electrode layers 20a provided in the same layer. The dielectric layers 24a can be formed of a dielectric material having etch selectivity with respect to the interlayer dielectric layers 22a. For example, in the case where the interlayer dielectric layers 22a are formed of silicon oxide, the dielectric layers 24a can be formed of silicon nitride.

[0193] The plurality of electrode layers 20b and the plurality of interlayer dielectric layers 22b can be alternately stacked on the substrate 12b of the second wafer W2. A plurality of vertical channels CHb passing through the alternately stacked electrode layers 20b and interlayer dielectric layers 22b in the vertical direction VD can be defined in the cell area CAR.

[0194] Each electrode layer 20b can have a pad portion LPb. The contact CNT32 can be connected to the pad portion LPb. In each first connection zone CNR1, a step structure can be configured since the pad portions LPb of the electrode layers 20b are staggered with respect to each other. Although, for simplicity of illustration, FIG. 25 a limited number of contacts CNT32 connected to some of the pad portions LPb of the electrode layers 20b are shown, it should be understood that the contacts CNT32 are connected to the pad portions LPb of each electrode layer 20b.

[0195] The pad portions LPb of the electrode layer 20b can be disposed in multiple first connection areas CNR1. The pad portions LPb of the electrode layer 20b can be grouped into multiple groups based on the distance between the pad portions LPb and the substrate 12b, with each group disposed in a different first connection area CNR1. For example, the pad portions LPb of the electrode layer 20b can be grouped into lower pad portions LPb of the electrode layer 20b that are relatively close to the substrate 12b in the vertical direction VD, and upper pad portions LPb of the electrode layer 20b that are relatively far away from the substrate 12b in the vertical direction VD. FIG. 25 In this context, the pad portion LPb of the electrode layer 20b, which is relatively close to the substrate 12b, can be disposed in a first connection area CNR1 (e.g., in...). FIG. 25 The pad portion LPb of the electrode layer 20b, which is located on the left side and is relatively far from the substrate 12b, can be disposed in another first connection area CNR1 (e.g., in...). FIG. 25 (The middle is located on the right).

[0196] In each first connection region CNR1, since the pad portions LPb of the electrode layer 20b are staggered relative to each other, a stepped structure can be configured. The number of pad portions LPb provided in a first connection region CNR1 can be less than the number of electrode layers 20b stacked. In each of the plurality of first connection regions CNR1, the pad portions LPb of the electrode layer 20b can overlap with the insulating stack (configured by alternating layers of dielectric layers 24a and interlayer dielectric layers 22a) in the vertical direction VD.

[0197] Multiple first transistors TR1_XDEC and multiple second transistors TR2_XDEC can be defined on the substrate 10 of the logic structure P. The multiple first transistors TR1_XDEC can be transfer transistors for transferring operating voltage to the electrode layer 20b of the second wafer W2, and the multiple second transistors TR2_XDEC can be transfer transistors for transferring operating voltage to the electrode layer 20a of the first wafer W1. FIG. 25 The first transistor TR1_XDEC and the second transistor TR2_XDEC shown can be configured as line decoders.

[0198] In the first connection area CNR1, multiple bonding pads PAD3, each corresponding to a respective first transistor TR1_XDEC, can be defined on a surface of the first wafer W1 bonded to the second wafer W2. The bonding pads PAD3 can be connected to the corresponding first transistor TR1_XDEC via contacts CNT33, CNT34, and CNT35 and wirings M31 and M32. Contacts CNT34 can pass through the insulating stack in each of the multiple first connection areas CNR1 in the vertical direction VD.

[0199] In the first connection region CNR1, a plurality of bonding pads PAD4 respectively corresponding to the pad portions LPb of the electrode layers 20b can be defined on one surface of the second wafer W2 bonded to the first wafer W1. The bonding pads PAD4 can be connected to the pad portions LPb of the corresponding electrode layers 20b through the contacts CNT36 and CNT32 and the wiring M33. The bonding pads PAD4 of the second wafer W2 can be bonded to the bonding pads PAD3 of the first wafer W1, respectively. In accordance with this fact, the electrical paths of the electrode layers 20b and the first transistors TR1_XDEC can be configured.

[0200] The contacts CNT31 can be connected to the pad portions LPa of the electrode layers 20a in the second connection region CNR2, respectively. The wiring M34 can be connected to the top ends of the contacts CNT31. The wiring M34 can extend from the second connection region CNR2 to the adjacent first connection region CNR1. In the first connection region CNR1, the wiring M34 can be connected to the contact CNT37. The contact CNT37 can pass through the plurality of dielectric layers 24a and the plurality of interlayer dielectric layers 22a alternately laminated in the vertical direction VD in the first connection region CNR1. The contact CNT37 can be connected to the second transistors TR2_XDEC through the wiring M35 and the contact CNT38.

[0201] For simplicity of illustration, FIG. 25 Only the first transistors TR1_XDEC and the electrical paths connected to some of the electrode layers 20b are illustrated, but it is understood that the first transistors TR1_XDEC and the electrical paths are provided for each of the electrode layers 20b. For simplicity of illustration, FIG. 26A Only the second transistors TR2_XDEC and the electrical paths connected to some of the electrode layers 20a are illustrated, but it is understood that the second transistors TR2_XDEC and the electrical paths are provided for each of the electrode layers 20a.

[0202] When the memory device operates, a high-level operating voltage can be supplied to the electrode layers 20a and 20b. In order to transmit the high voltage, the first transistors TR1_XDEC and the second transistors TR2_XDEC should have a large size capable of withstanding the high voltage. Accordingly, the first transistors TR1_XDEC and the second transistors TR2_XDEC can be disposed in the length direction (i.e., the second direction SD).

[0203] As a measure to improve integration, the size of pads LPa and LPb is being reduced. If pads LPa and LPb are densely arranged in one area, the length difference between the electrical paths used to connect pads LPa and LPb to the first transistor TR1_XDEC and the second transistor TR2_XDEC may be large due to the mismatch between the dimensions of pads LPa and LPb and the dimensions of the first transistor TR1_XDEC and the second transistor TR2_XDEC, respectively. Large length deviations between electrical paths increase the load difference between them, which may reduce the operational reliability of the memory device.

[0204] According to this embodiment, the pad portions LPa of electrode layer 20a are distributed in multiple regions, and the pad portions LPb of electrode layer 20b are also distributed in multiple regions. Therefore, the length difference between the electrical paths used to connect the pad portions and the transistors can be reduced. This reduces the load difference between the electrical paths, thereby contributing to improved operational reliability of the memory device.

[0205] FIG. 26B and FIG. 26A This is a diagram illustrating an example of the bias conditions during an erase operation of a memory device according to an embodiment of the present disclosure. Specifically, FIG. 26B The bias conditions are shown in an example where only the first memory block BLK1 is erased, and FIG. 26A The bias conditions are shown in an example where only the second memory block BLK2 is erased.

[0206] Reference FIG. 26B A ground voltage is applied to the drain select line DSLa and the source select line SSLa of the first memory block BLK1, and then floated. A voltage of 0V is applied to the word line WLa of the first memory block BLK1.

[0207] Apply a ground voltage to the drain select line DSLb and source select line SSLb of the second memory block BLK2, and then float them. Float the word line WLb of the second memory block BLK2.

[0208] An erase voltage Verase is applied to the common source line CSLa and bit line BLa of the first memory block BLK1, and a voltage of 0V is applied to the common source line CSLb of the second memory block BLK2. Because the second bit line BLb of the second memory block BLK2 is connected to the first bit line BLa of the first memory block BLK1, the erase voltage Verase is also applied to the second bit line BLb of the second memory block BLK2.

[0209] Due to this bias, the channel potential of the cell string CSTRa of the first memory block BLK1 and the channel potential of the cell string CSTRb of the second memory block BLK2 rise to the level of the erase voltage Verase.

[0210] If the potential of the channel of the cell string CSTRa of the first memory block BLK1 rises to the level of the erase voltage Verase, the memory cell Mca of the first memory block BLK1 is erased because the difference between the potential of the channel and the potential of the word line WLa (0 V) becomes equal to or greater than the amplitude required to erase the memory cell. On the other hand, if the potential of the channel of the cell string CSTRb of the second memory block BLK2 rises to the level of the erase voltage Verase, the potential of the word line WLb in the floating state of the second memory block BLK2 rises along with the potential of the channel by the coupling phenomenon. Therefore, the memory cell Mcb of the second memory block BLK2 is not erased because the difference between the potential of the channel and the potential of the word line WLb becomes less than the amplitude required to erase the memory cell.

[0211] The erase operation on the second memory block BLK2 is also similar to the erase operation on the first memory block BLK1.

[0212] Referring to FIG. 27 A ground voltage is applied to the drain selection line DSLa and the source selection line SSl a of the first memory block BLK1, and then it is floated. The word line WLa of the first memory block BLK1 is floated. A ground voltage is applied to the drain selection line DSLb and the source selection line SSLb of the second memory block BLK2, and then it is floated. A voltage of 0 V is applied to the word line WLb of the second memory block BLK2.

[0213] A voltage of 0 V is applied to the common source line CSLa of the first memory block BLK1, and an erase voltage Verase is applied to the common source line CSLb and the bit line BLb of the second memory block BLK2. Because the first bit line BLa of the first memory block BLK1 is coupled to the second bit line BLb of the second memory block BLK2, the erase voltage Verase is also applied to the first bit line BLa of the first memory block BLK1.

[0214] Due to this bias, the channel potential of the cell string CSTRa of the first memory block BLK1 and the channel potential of the cell string CSTRb of the second memory block BLK2 rise.

[0215] If the potential of the channel of the cell string CSTRa of the first memory block BLK1 rises to the level of the erase voltage Verase, the potential of the word line WLa of the first memory block BLK1 in the floating state rises along with the potential of the channel by a coupling phenomenon. Thus, since the difference between the potential of the channel and the potential of the word line WLa becomes smaller than the amplitude required for erasing the memory cell, the memory cell MCa of the first memory block BLK1 is not erased. On the other hand, if the potential of the channel of the cell string CSTRb of the second memory block BLK2 rises to the level of the erase voltage Verase, since the difference between the potential of the channel and the potential of the word line WLb (0 V) becomes equal to or greater than the amplitude required for erasing the memory cell, the memory cell MCb of the second memory block BLK2 is erased.

[0216] According to the above-described erase bias, the first memory block BLK1 and the second memory block BLK2 having different sizes can be independently erased.

[0217] FIG. 27 is a schematic block diagram showing a representation of an example of a memory system according to an embodiment of the present disclosure.

[0218] Referring to FIG. 3 to FIG. 20 , the memory system 1000 according to an embodiment of the present disclosure can include a memory device 100 and a memory controller 200.

[0219] The memory device 100 can include a plurality of memory blocks, and can operate in response to a control of the memory controller 200. The operation of the memory device 100 can include, for example, a read operation, a write operation (also referred to as a program operation), and an erase operation.

[0220] The memory blocks of the memory device 100 can include a plurality of large blocks LB and a plurality of small blocks SB. As described above with reference to FIG. 26A , the large blocks LB and the small blocks SB can be defined in different wafers. For example, the small blocks SB can be defined in a first wafer, and the large blocks LB can be defined in a second wafer.

[0221] The memory device 100 can be configured to receive commands and addresses, etc. from the memory controller 200, and access a region selected by the address in the memory cell array. In other words, the memory device 100 can perform an operation corresponding to the command on the region selected by the address. For example, the memory device 100 can perform a write operation, a read operation, and an erase operation. In this regard, in the write operation, the memory device 100 can program data to the region selected by the address. In the read operation, the memory device 100 can read data from the region selected by the address. In the erase operation, the memory device 100 can erase data stored in the region selected by the address.

[0222] The memory controller 200 can control a write (program) operation, a read operation, an erase operation, and a background operation of the memory device 100. For example, the background operation can include at least one of a garbage collection operation (GC), a wear leveling (WL) operation, and a bad block management (BBM) operation, etc.

[0223] The memory controller 200 can control the operation of the memory device 100 according to a request of the host. Alternatively, the memory controller 200 can control the operation of the memory device 100 regardless of the request of the host. The memory controller 200 and the host can be devices separated from each other. The memory controller 200 and the host can be implemented by being integrated into one device. Hereinafter, for convenience of explanation, the memory controller 200 and the host will be described as devices separated from each other as an example.

[0224] The flash memory has a certain level of life that can be determined based on the number of write / erase times. The flash memory cannot perform an overwrite operation due to its physical characteristics. That is, in the flash memory, when a write operation is to be performed on a memory block in which data is written, an erase operation should be performed on the memory block before the write operation is performed. Due to this characteristic of the flash memory, a system software called a flash translation layer (hereinafter, referred to as "FTL") is used between the file system of the host and the memory device 100.

[0225] A flash translation layer (FTL) can provide an interface connection for hiding erase operations of a flash memory between a file system of a host and the memory device 100. Disadvantages of a flash memory device (e.g., a pre-write erase and a mismatch between an erase unit and a write unit) can be addressed by a flash translation layer (FTL). The flash translation layer (FTL) maps a logical address generated by a file system to a physical address of the memory device 100 during a write operation of the memory device 100. The flash translation layer (FTL) driven by the memory controller 200 can map addresses according to a log mapping method. However, advantages of the present disclosure can be applied to various address mapping methods other than the log mapping method.

[0226] The memory controller 200 can allocate a log block by referring to a size of input data. In particular, the memory controller 200 can allocate a log block in units of a small block SB or in units of a large block LB by referring to a size of data. Hereinafter, it will have a similar meaning that a memory block existing in a free block pool is allocated as a log block and a memory block existing in the free block pool is allocated as a data block. Accordingly, it will mean that a memory block selected from the free block pool is allocated as a log block, which also means that a memory block selected from the free block pool is allocated as a data block.

[0227] As described above, the memory device 100 is configured of a plurality of memory blocks, and each memory block is composed of a plurality of pages. For example, one memory block can be composed of 64 or 128 pages. The memory device 100 performs a write operation and a read operation based on a page, and performs an erase operation based on a memory block. Speeds of various operations are different from each other. For example, a speed of a read operation is about 25 microseconds (25 µs), a speed of a write operation is about 250 microseconds (250 µs), and a speed of an erase operation is about 2000 microseconds (2000 µs), and thus, the speeds of various operations are asymmetric. In particular, a speed of an erase operation is much slower than speeds of read and write operations. The speed of an erase operation decreases as a size of a memory block increases. A slow erase operation is a main cause of performance degradation of the memory device 100.

[0228] According to FIG. 26B and FIG. 28 an erase bias shown in FIGS. 1 to 3, the memory device 100 according to an embodiment of the present disclosure can perform an erase in units of a small block or in units of a large block. Accordingly, the memory controller 200 can allocate a log block in units of a small block or in units of a large block.

[0229] If a small block existing in the free block pool is allocated as a log block, the allocated log block can be erased by a pre-write erase operation. According to an embodiment of the disclosure, a memory block can be erased in units of small blocks, and thus performance of the memory block can be improved by reduction of erase time.

[0230] FIG. 28 is a representation that helps explain an example of a flowchart of a write method according to an embodiment of the disclosure.

[0231] Referring to FIG. 29A to FIG. 29D In step S10, the memory controller can detect a size of data requested to be written.

[0232] In step S20, when it is determined that the detected data size is smaller than a reference size (e.g., 30 MB) (i.e., the data is small size data), the process proceeds to step S30. On the other hand, when it is determined that the size of data requested to be written is equal to or greater than the reference size (i.e., the data is large size data), the process proceeds to step S40.

[0233] In step S30, a small block is allocated as a log block. That is, in the case where the data requested to be written is small size, a small block among memory blocks existing in the free block pool is provided as a log block. If the log block allocation is completed, the process proceeds to step S50 to program data into the allocated log block.

[0234] In step S40, a large block is allocated as a log block. That is, in the case where the data requested to be written is large size, a large block among memory blocks existing in the free block pool is provided as a log block. If the log block allocation is completed, the process proceeds to step S50 to program data into the allocated log block.

[0235] In step S50, the memory controller programs data requested to be written into the allocated small block or large block. Before the data is programmed, an erase operation can be performed on the allocated memory block. If the programming of data requested to be written is completed, a programming cycle corresponding to one write request ends.

[0236] According to the present embodiment, if data requested to be written has a small size, a small block is allocated instead of a large block. Accordingly, write amplification can be reduced, and thus memory utilization efficiency can be improved. Further, if data requested to be written has a small size, by allocating a small block instead of a large block, time required for a pre-write erase operation can be reduced, and thus performance of the memory device can be improved.

[0237] FIG. 29A to FIG. 29Dis an example of a representation that helps explain a diagram of a memory block management method according to an embodiment of the disclosure.

[0238] Referring to FIG. 29A , the memory device can include a plurality of memory blocks B1, B2, and B3. The memory blocks can be classified into large blocks LB or small blocks SB. FIG. 29B and FIG. 29C shows an example of classifying the memory blocks into the small blocks SB and the large blocks LB based on the number of cell strings included in each memory block, and FIG. 29D and FIG. 29A shows an example of classifying the memory blocks into the small blocks SB and the large blocks LB based on the number of layers of word lines included in each memory block.

[0239] The memory can be classified into a user area, a system area, and an over-provisioning (OP) area according to the type of data to be stored therein. The user blocks B1 denote memory blocks of the user area, the system blocks B2 denote memory blocks of the system area, and the OP blocks B3 denote memory blocks of the over-provisioning area.

[0240] Data requested to be written by the host can be stored in the user blocks B1. The user blocks B1 can be classified into free blocks or data blocks according to whether data is stored therein. The free blocks denote blocks in which no data is stored and are empty, and the data blocks denote blocks in which data is stored. Although not shown, a bad block is a memory block that cannot store data. The bad block can be classified into a manufacture bad block (MBB) that occurs during manufacturing of the memory device and a growing bad block (GBB) that occurs in the process of using the memory blocks, according to the time point at which the bad block is generated.

[0241] System information can be stored in the system blocks B2. The system information can be mapping data for mapping information between a logical address and a physical address, booting information for information necessary for a booting operation of the memory device, and setting information for operation of firmware of the memory controller.

[0242] The over-provisioning blocks B3 can be over-provisioning allocated to allow various functions (e.g., wear leveling, garbage collection, and bad block management) necessary to drive the memory device to operate smoothly.

[0243] Generally, the size of user data randomly generated by a user on a mobile device is not constant. For example, the size of one memory block can be 100 MB, and a user can generate and store 1 MB of data. In this case, memory efficiency is reduced since the remaining space corresponding to 99 MB becomes useless (write amplification). However, not all of the size of user data is small. In recent years, the number of pixels of a camera is increasing, and thus, it is possible to store large size image data. Meanwhile, large size data is mainly stored in an enterprise Solid State Drive (eSSD).

[0244] FIG. 29C and FIG. 29B are diagrams illustrating a memory block management method of a memory device used in a mobile device, and FIG. 29D and FIG. 29A are diagrams illustrating a memory block management method of a memory device used in an eSSD.

[0245] Referring to FIG. 29C and FIG. 29B if the memory device is used in a mobile device, since the size of data requested to be written is different, the memory controller can configure the proportion of small blocks SB and the proportion of large blocks LB among user blocks B1 managed as a user area to be the same as or similar to each other. For example, half of user blocks B1 managed as a user area can be small blocks SB, and the other half can be large blocks LB. Further, system blocks B2 and a reserved space block B3 can be configured using the remaining blocks other than user blocks B1.

[0246] Referring to FIG. 29D and FIG. 30 if the memory device is used in an eSSD, since the size of data requested to be written is large in most cases, all of the large blocks LB can be managed as a user area. A system area and a reserved space area can be managed to be configured in small blocks SB. Further, there can be small blocks SB remaining after the system area and the reserved space area are configured, and the remaining small blocks SB can be managed as a user area.

[0247] FIG. 30 is a block diagram schematically illustrating a representation of an example of a computing system including a memory device according to an embodiment of the disclosure.

[0248] Referring to ​According to one embodiment, the computing system 700 can include a memory system 710, a microprocessor (CPU) 720, a RAM 730, a user interface 740, and a modem 750 such as a baseband chipset, which are electrically coupled to the system bus 760. In the case where the computing system 700 according to the embodiment is a mobile device, a battery (not shown) for providing an operating voltage of the computing system 700 can be additionally provided. Although not shown in the drawing, it is apparent to those skilled in the art to which the embodiment pertains that the computing system 700 according to the embodiment can be additionally provided with an application chipset, a camera image processor (CIS), and a mobile DRAM, etc. The memory system 710 can be configured as a solid state drive / solid state disk (SSD) that stores data using a non-volatile memory, for example. Otherwise, the memory system 710 can be provided as a fusion flash memory (e.g., OneNAND flash memory).

[0249] Although the exemplary embodiments of the disclosure have been described for illustrative purposes, it will be understood by those skilled in the art that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure. Therefore, the embodiments disclosed above and in the drawings should be considered only as descriptive, not as limiting the technical scope. The technical scope of the disclosure is not limited by the embodiments and the drawings. The spirit and scope of the disclosure can be interpreted in conjunction with the appended claims, and include all equivalents falling within the scope of the appended claims.

[0250] Cross Reference to Related Applications

[0251] This application claims priority to Korean Patent Application No. 10-2020-0068781, filed on June 8, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A memory device comprising: A first wafer, the first wafer including a first substrate and a plurality of first electrode layers and a plurality of first interlayer dielectric layers, the plurality of first electrode layers and the plurality of first interlayer dielectric layers being alternately stacked on the top surface of the first substrate along a first vertical channel protruding in a vertical direction; as well as The second wafer is disposed on the first wafer and includes a second substrate, a plurality of second electrode layers, and a plurality of second interlayer dielectric layers, wherein the plurality of second electrode layers and the plurality of second interlayer dielectric layers are alternately stacked on the bottom surface of the second substrate along a second vertical channel protruding in the vertical direction. Each of the plurality of second electrode layers includes a pad portion, and The first wafer includes a dielectric stack that overlaps with the pad portion of the second electrode layer in the vertical direction and is configured by alternating layers of dielectric layers and the plurality of first interlayer dielectric layers.

2. The memory device according to claim 1, wherein, The plurality of dielectric layers are formed of a material whose etch selectivity differs from that of the plurality of first interlayer dielectric layers.

3. The memory device according to claim 1, wherein, The pads of the second electrode layer are staggered to form a stepped structure.

4. The memory device according to claim 1, further comprising: Multiple contacts are electrically connected to the multiple second electrode layers and pass through the dielectric stack in the vertical direction.

5. The memory device according to claim 4, wherein, The first wafer further includes logic circuitry defined on a third substrate below the first substrate and connected to the plurality of second electrode layers via the plurality of contacts.

6. The memory device according to claim 5, further comprising: Multiple first slits divide the alternately stacked multiple first electrode layers and multiple first interlayer dielectric layers into multiple first memory block cells; as well as Multiple second slits divide the alternately stacked multiple second electrode layers and multiple second interlayer dielectric layers into multiple second memory block cells. The interval between adjacent first slits is narrower than the interval between adjacent second slits.

7. The memory device according to claim 5, further comprising: Multiple first slits divide the alternately stacked multiple first electrode layers and multiple first interlayer dielectric layers into multiple first memory block cells; as well as Multiple second slits divide the alternately stacked multiple second electrode layers and multiple second interlayer dielectric layers into multiple second memory block cells. The interval between adjacent first slits is wider than the interval between adjacent second slits.

8. The memory device according to claim 5, wherein, The number of layers in the first electrode layer is less than the number of layers in the second electrode layer.

9. The memory device according to claim 5, wherein, The number of layers in the first electrode layer is greater than the number of layers in the second electrode layer.

10. The memory device according to claim 1, wherein, The pad portions of the plurality of second electrode layers are disposed in a plurality of connection areas and are grouped into a plurality of groups, such that the pad portions of different groups are disposed in different connection areas.

11. The memory device according to claim 10, wherein, In each of the plurality of connection areas, the pad portions of the second electrode layer are staggered to form a stepped structure.

12. The memory device according to claim 1, in, Each of the plurality of first electrode layers includes a pad portion, and The pad portions of the plurality of first electrode layers are disposed in a plurality of connection areas and are grouped into a plurality of groups, such that the pad portions of different groups are disposed in different connection areas.

13. The memory device according to claim 12, wherein, In each of the plurality of connection regions, the pad portions of the first electrode layer are staggered to form a stepped structure.

14. The memory device of claim 12, further comprising: Multiple contacts are electrically connected to the multiple first electrode layers and pass through the dielectric stack in the vertical direction.

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