MUX trigger circuit, MUX structure and SRAM write assist circuit

Abstract

The invention discloses an MUX trigger circuit, an MUX structure and an SRAM write assist circuit, the MUX trigger circuit is used for triggering SRAM write assist start, when SRAM write failure occurs, the levels of two word lines of the SRAM are reduced to be low, and the MUX trigger circuit outputs a high level; and the MUX trigger circuit outputs a signal for starting the write assist circuit. Compared with the prior art that the negative bit line is started in each write-in process and the power consumption is high, the method only triggers write assistance for write failure, dynamically reduces the power consumption, and ensures successful write-in through negative pressure assistance. A'detection-trigger 'mechanism is realized, and high-reliability and low-power-consumption writing of the SRAM under low voltage is realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a MUX trigger circuit, a MUX structure, and an SRAM write auxiliary circuit. Background Technology

[0002] SRAM (Static Random-Access Memory) is a high-speed semiconductor memory that can retain data without refreshing, and it is widely used in CPU cache, register file, GPU memory and other scenarios.

[0003] As semiconductor device technology continues to advance, SRAM achieves higher performance while its power consumption continues to rise. Among various methods to reduce power consumption, the most effective approach is to lower the power supply voltage. However, as the transistor channel length shortens, the threshold voltage cannot decrease proportionally, which reduces the reliability of SRAM at low voltages and makes writing to SRAM more difficult.

[0004] To address the difficulty of writing SRAM, the most commonly used write assistance technique is the negative bit line technique. The main working principle of the negative bit line technique is to temporarily pull the voltage to a negative voltage below 0V (usually -100mV to -300mV) on the bit line where "0" is written, thereby increasing the gate-source voltage difference of the transmission transistor NMOS, enhancing the pull-down driving force, making the memory node easier to flip, and significantly reducing the write error rate and the minimum operating voltage Vmin.

[0005] Negative bit lines, through additional voltage swing, continuous charging and discharging of negative pumps, and inefficient charge cycling, result in significantly higher write cycle energy than conventional solutions. Therefore, negative bit line technology will increase the power consumption of SRAM. Summary of the Invention

[0006] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0007] The technical problem to be solved by the present invention is to provide a MUX trigger circuit that can detect write failures and output a signal to trigger write assistance only when a write failure occurs.

[0008] In addition, a MUX structure having the MUX trigger circuit, and an SRAM write auxiliary circuit having the MUX structure.

[0009] To solve the above-mentioned technical problems, the present invention provides a MUX trigger circuit, which is used to trigger SRAM write auxiliary start. When an SRAM write failure occurs, the level of the two word lines of the SRAM drops to low, and the output of the MUX trigger circuit is set to high level.

[0010] The output signal of the MUX trigger circuit is used to start the write auxiliary circuit.

[0011] Optionally, the MUX trigger circuit can be further improved, including:

[0012] The first NOT gate has its input connected to the first column decoding strobe signal YCDSEL, and its output is the third column decoding strobe signal YCDSELB;

[0013] The first PMOS P1 has its gate connected to the gate of the first NMOS N1 to form a second connection terminal, which is connected to the second word line BLB. Its source is open, and its drain is connected to the source of the second PMOS P2.

[0014] The second PMOS P2 has its gate connected to the gate of the second NMOS N2 to form a first connection terminal, which is connected to the first word line BL. Its drain is connected to the drain of the third NPMOS N2, the source of the third PMOS P3, and the drain of the third NMOS N3.

[0015] The third PMOS P3 has its gate connected to the first column decoder strobe signal YCDSEL, and its drain connected to the source of the third NMOS N3 to form the output terminal OUT;

[0016] The first NMOS transistor, N1, has its source grounded.

[0017] The source of the second NMOS N2 is connected to the drain of the first NMOS N1;

[0018] The third NMOS N3 has its gate connected to the third column decoder strobe signal YCDSELB.

[0019] To solve the above-mentioned technical problems, the present invention provides a MUX structure, which has any of the above-mentioned MUX trigger circuits, and further includes:

[0020] The AND gate has its inputs connected to the low-level column select signal YPL and the high-level column select signal YPH. Its output, the first column decoding strobe signal YCDSEL, is connected to one input of the NAND gate. Its output, the first column decoding strobe signal YCDSEL, is connected to the first signal selection terminal of the column strobe and write drive circuit.

[0021] The NAND gate has its other input connected to the write enable signal WENB, and its output, the second column decoding strobe signal YCDSEL_, is connected to the second signal selection terminal of the column strobe and write drive circuit.

[0022] The second NOT gate takes the precharge signal PREB as its input and outputs the signal PRE to the precharge signal terminal of the column gating and write drive circuit.

[0023] Optionally, the MUX structure, column gating, and write drive circuit can be further improved, including:

[0024] The fourth PMOS P4 has an open source, its gate is connected to the gate of the fifth PMOS P5 and the gate of the sixth PMOS P6, and its drain is connected to the source of the sixth PMOS P6, the source of the seventh PMOS P7 and the drain of the fourth NMOS N4 to form the first line node BL;

[0025] The fifth PMOS P5 has an open source, and its drain is connected to the drain of the sixth PMOS P6, the source of the eighth PMOS P8, ​​and the drain of the fifth NMOS N5 to form the second bit line node BL_.

[0026] The seventh PMOS P7 has its gate forming the second signal selection terminal of the column gating and write drive circuit, which is connected to the second column decoding gating signal YCDSEL_, and its drain is connected to the first read bit line DR.

[0027] The eighth PMOS P8 has its gate forming the second signal selection terminal of the column gating and write drive circuit, which is connected to the second column decoding gating signal YCDSEL_, and its drain is connected to the second read bit line DR_.

[0028] The fourth NMOS N4 has its gate connected to the gate of the fifth NMOS N5 to form the first signal selection terminal of the column gating and write drive circuit, which is connected to the first column decoding gating signal YCDSEL, and its drain is connected to the first write bit line DW.

[0029] The fifth NMOS N5 has its drain connected to the second write bit line DW_.

[0030] To solve the above technical problems, the present invention provides an SRAM write auxiliary circuit, which has the MUX structure described above, and further includes: an auxiliary circuit;

[0031] The auxiliary circuit includes:

[0032] The third NOT gate has its input connected to the output terminal OUT of the MUX trigger circuit, and its output is written to the auxiliary control signal WAGTP to one input terminal of the NOR gate.

[0033] The NOR gate has its other input connected to the second write enable signal GTPB, and its output connected to the fourth NOT gate.

[0034] The fourth NOT gate's output is connected to the negative voltage node NVSS via capacitor C0;

[0035] The fourth NMOS N4 has its drain connected to the negative voltage node NVSS, its source grounded, and its gate connected to the second write enable signal GTPB.

[0036] The fifth NOT gate has its input connected to the first write enable signal GTP and its output connected to the second write enable signal GTPB.

[0037] The sixth NOT gate has its input connected to external data DATA, and its output connected to the inputs of the seventh and eighth NOT gates.

[0038] The output of the seventh NOT gate is connected to the input of the ninth NOT gate;

[0039] The eighth NOT gate is connected to the negative voltage node NVSS, and its output is connected to the first write data line DW.

[0040] The ninth NOT gate is connected to the negative voltage node NVSS, and its output is connected to the second write data line DW_.

[0041] Optionally, the SRAM write assist circuit can be further improved. When the output of the MUX trigger circuit is set to a high level, the write assist control signal WAGTP changes from a high level to a low level, the second write enable signal GTPB is at a low level, the voltage at the left end of capacitor C0 changes abruptly from a high level 1 to a low level 0, and the negative voltage node NVSS forms a negative voltage, making the end of the first write data line DW or the second write data line DW_ that needs to be written to a low level become a negative voltage, thus completing the write assist.

[0042] The working process and principle of this invention are as follows;

[0043] The work process includes:

[0044] 1. Write operation detection: When the SRAM performs a write operation, the MUX trigger circuit detects a write failure by using an inverter controlled by the newly added BL&BLB (i.e., BL and BLB are both 0).

[0045] 2. Trigger Write Assist: If a write failure is detected, the OUT signal is set to 1, and the write assist circuit WAGTP goes low.

[0046] 3. Negative voltage generation: The write auxiliary circuit generates negative voltage through the NVSS node, pulling the bit line (DW or DW_) that needs to be written with "0" to negative voltage, thus forcing the data writing to be completed.

[0047] 4. Return to normal: After a successful write operation, the circuit automatically disables write assistance to avoid continuous power consumption.

[0048] To address write failures in SRAM, the usual approach is to enable write assistance directly before writing. The most suitable write assistance circuit for SRAM is negative bit line writing, but since each write requires pulling BL or BLB to a negative voltage, this will generate extremely high power consumption.

[0049] This invention dynamically detects write failures (instead of the traditional approach of keeping the negative bit line constantly active), triggering an auxiliary circuit only upon failure. Write failure detection is triggered when both BL and BLB are 0, causing the inverter output OUT=1. OUT=1 lowers WAGTP, which, through capacitive coupling C0, pulls NVSS to a negative voltage, accelerating the discharge of the bit line that wrote "0" and creating a negative voltage.

[0050] Compared to existing technologies that require activating negative bit lines for every write operation, resulting in high power consumption, this invention triggers write assistance only upon write failure, dynamically reducing power consumption and ensuring successful writes through negative voltage assistance. It implements a "detection-trigger" mechanism, enabling negative voltage assistance only partially when a write fails, achieving highly reliable and low-power SRAM writing at low voltages. Attached Figure Description

[0051] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0052] Figure 1 This is a schematic diagram of the structure of the first embodiment of the present invention.

[0053] Figure 2 This is a schematic diagram of the structure of the second embodiment of the present invention. Figure 1 .

[0054] Figure 3 This is a schematic diagram of the structure of the second embodiment of the present invention. Figure 2 .

[0055] Figure 4 This is a schematic diagram of the structure of the second embodiment of the present invention. Figure 3 .

[0056] Figure 5 This is a schematic diagram of the structure of the second embodiment of the present invention. Figure 4 .

[0057] Figure 6 This is a schematic diagram of the third embodiment of the present invention. Figure 1 .

[0058] Figure 7 This is a schematic diagram of the third embodiment of the present invention. Figure 2 .

[0059] Figure 8This is a schematic diagram of the third embodiment of the present invention. Figure 3 .

[0060] Figure 9 This is a schematic diagram illustrating the simulation effect of the present invention. Detailed Implementation

[0061] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of the present invention is thorough and complete, and that the technical solutions of these exemplary embodiments are fully conveyed to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0062] First embodiment;

[0063] This invention provides a MUX trigger circuit for triggering SRAM write-assisted startup. When an SRAM write failure occurs, the level of the two word lines of the SRAM drops low, and the output of the MUX trigger circuit is set to high.

[0064] The output signal of the MUX trigger circuit is used to start the write auxiliary circuit.

[0065] refer to Figure 1 As shown, the preferred structure of the MUX trigger circuit includes:

[0066] The first NOT gate has its input connected to the first column decoding strobe signal YCDSEL, and its output is the third column decoding strobe signal YCDSELB;

[0067] The first PMOS P1 has its gate connected to the gate of the first NMOS N1 to form a second connection terminal, which is connected to the second word line BLB. Its source is open, and its drain is connected to the source of the second PMOS P2.

[0068] The second PMOS P2 has its gate connected to the gate of the second NMOS N2 to form a first connection terminal, which is connected to the first word line BL. Its drain is connected to the drain of the third NPMOS N2, the source of the third PMOS P3, and the drain of the third NMOS N3.

[0069] The third PMOS P3 has its gate connected to the first column decoder strobe signal YCDSEL, and its drain connected to the source of the third NMOS N3 to form the output terminal OUT;

[0070] The first NMOS transistor, N1, has its source grounded.

[0071] The source of the second NMOS N2 is connected to the drain of the first NMOS N1;

[0072] The third NMOS N3 has its gate connected to the third column decoder strobe signal YCDSELB.

[0073] Furthermore, it should be understood that although the terms "first," "second," etc., may be used herein to describe different elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of exemplary embodiments according to the present invention, the first element, component, region, layer, or portion discussed below may also be referred to as the second element, component, region, layer, or portion.

[0074] Second embodiment;

[0075] refer to Figures 2 to 5 As shown, the present invention provides a MUX structure having the MUX trigger circuit described in the first embodiment above, and further comprising:

[0076] The AND gate has its inputs connected to the low-level column select signal YPL and the high-level column select signal YPH. Its output, the first column decoding strobe signal YCDSEL, is connected to one input of the NAND gate. Its output, the first column decoding strobe signal YCDSEL, is connected to the first signal selection terminal of the column strobe and write drive circuit.

[0077] The NAND gate has its other input connected to the write enable signal WENB, and its output, the second column decoding strobe signal YCDSEL_, is connected to the second signal selection terminal of the column strobe and write drive circuit.

[0078] The second NOT gate takes the precharge signal PREB as its input and outputs the signal PRE to the precharge signal terminal of the column gating and write drive circuit.

[0079] The column selection and write drive circuit includes:

[0080] The fourth PMOS P4 has an open source, its gate is connected to the gate of the fifth PMOS P5 and the gate of the sixth PMOS P6, and its drain is connected to the source of the sixth PMOS P6, the source of the seventh PMOS P7 and the drain of the fourth NMOS N4 to form the first line node BL;

[0081] The fifth PMOS P5 has an open source, and its drain is connected to the drain of the sixth PMOS P6, the source of the eighth PMOS P8, ​​and the drain of the fifth NMOS N5 to form the second bit line node BL_.

[0082] The seventh PMOS P7 has its gate forming the second signal selection terminal of the column gating and write drive circuit, which is connected to the second column decoding gating signal YCDSEL_, and its drain is connected to the first read bit line DR.

[0083] The eighth PMOS P8 has its gate forming the second signal selection terminal of the column gating and write drive circuit, which is connected to the second column decoding gating signal YCDSEL_, and its drain is connected to the second read bit line DR_.

[0084] The fourth NMOS N4 has its gate connected to the gate of the fifth NMOS N5 to form the first signal selection terminal of the column gating and write drive circuit, which is connected to the first column decoding gating signal YCDSEL, and its drain is connected to the first write bit line DW.

[0085] The fifth NMOS N5 has its drain connected to the second write bit line DW_.

[0086] Third embodiment;

[0087] This invention provides an SRAM write auxiliary circuit, which has the MUX structure described in the second embodiment, and further includes: an auxiliary circuit;

[0088] refer to Figures 6 to 8 As shown, the auxiliary circuit includes:

[0089] The third NOT gate has its input connected to the output terminal OUT of the MUX trigger circuit, and its output is written to the auxiliary control signal WAGTP to one input terminal of the NOR gate.

[0090] The NOR gate has its other input connected to the second write enable signal GTPB, and its output connected to the fourth NOT gate.

[0091] The fourth NOT gate's output is connected to the negative voltage node NVSS via capacitor C0;

[0092] The fourth NMOS N4 has its drain connected to the negative voltage node NVSS, its source grounded, and its gate connected to the second write enable signal GTPB.

[0093] The fifth NOT gate has its input connected to the first write enable signal GTP and its output connected to the second write enable signal GTPB.

[0094] The sixth NOT gate has its input connected to external data DATA, and its output connected to the inputs of the seventh and eighth NOT gates.

[0095] The output of the seventh NOT gate is connected to the input of the ninth NOT gate;

[0096] The eighth NOT gate is connected to the negative voltage node NVSS, and its output is connected to the first write data line DW.

[0097] The ninth NOT gate is connected to the negative voltage node NVSS, and its output is connected to the second write data line DW_.

[0098] When the output of the MUX trigger circuit is set to high level, the write auxiliary control signal WAGTP changes from high level to low level, the second write enable signal GTPB is at level, the voltage at the left end of capacitor C0 changes abruptly from high level 1 to low level 0, the negative voltage node NVSS forms a negative voltage, making the end of the first write data line DW or the second write data line DW_ that needs to be written to a low level become a negative voltage, thus completing the write auxiliary.

[0099] refer to Figure 9 As shown, when GTP is high, the SRAM simulates write failures during data writing. It can be observed that when a data write failure occurs, both BL and BL_ are set to 0. This triggers the OUT signal to 1, generating a write auxiliary signal, creating a negative voltage, and setting DW_ to complete the normal write operation. Although this adds a small cost, it reduces the SRAM's power consumption.

[0100] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0101] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A MUX trigger circuit for triggering SRAM write-assisted startup, characterized in that: When an SRAM write failure occurs, the two word lines of the SRAM drop to low, and the output of the MUX trigger circuit goes high. The output signal of the MUX trigger circuit is used to start the write auxiliary circuit.

2. The MUX trigger circuit as described in claim 1, characterized in that, include: The first NOT gate has its input connected to the first column decoder strobe signal (YCDSEL) and its output is the third column decoder strobe signal (YCDSELB). The first PMOS (P1) has its gate connected to the gate of the first NMOS (N1) to form a second connection terminal, which is connected to the second word line (BLB). Its source is open, and its drain is connected to the source of the second PMOS (P2). The second PMOS (P2) has its gate connected to the gate of the second NMOS (N2) to form a first connection terminal, which is connected to the first word line (BL). Its drain is connected to the drain of the third NPMOS (N2), the source of the third PMOS (P3), and the drain of the third NMOS (N3). The third PMOS (P3) has its gate connected to the first column decoder strobe signal (YCDSEL), and its drain connected to the source of the third NMOS (N3) to form the output terminal (OUT); The first NMOS (N1) has its source grounded; The source of the second NMOS (N2) is connected to the drain of the first NMOS (N1); The third NMOS (N3) has its gate connected to the third column decoder strobe signal (YCDSELB).

3. A MUX structure having the MUX trigger circuit as described in claim 1 or 2, characterized in that, Also includes: The AND gate has its inputs connected to a low-level column select signal (YPL) and a high-level column select signal (YPH). Its output, the first column decoder strobe signal (YCDSEL), is connected to one input of the NAND gate. Its output, the first column decoder strobe signal (YCDSEL), is connected to the first signal selection terminal of the column strobe and write drive circuit. The NAND gate has its other input connected to the write enable signal (WENB), and its output, the second column decoder strobe signal (YCDSEL_), is connected to the second signal selection terminal of the column strobe and write drive circuit. The second NOT gate takes the precharge signal (PREB) as its input and outputs the signal (PRE) to the precharge signal terminal of the column gating and write drive circuit.

4. The MUX structure as described in claim 3, characterized in that, Column gating and write drive circuitry, including: The fourth PMOS (P4) has an open source, its gate is connected to the gate of the fifth PMOS (P5) and the gate of the sixth PMOS (P6), and its drain is connected to the source of the sixth PMOS (P6), the source of the seventh PMOS (P7) and the drain of the fourth NMOS (N4) to form the first line node (BL). The fifth PMOS (P5) has its source open, and its drain is connected to the drain of the sixth PMOS (P6), the source of the eighth PMOS (P8), and the drain of the fifth NMOS (N5) to form the second bit line node (BL_). The seventh PMOS (P7) has its gate forming the second signal selection terminal of the column gating and write drive circuit, which is connected to the second column decoding gating signal (YCDSEL_), and its drain is connected to the first read bit line (DR). The eighth PMOS (P8) has its gate forming the second signal selection terminal of the column gating and write drive circuit, which is connected to the second column decoding gating signal (YCDSEL_), and its drain is connected to the second read bit line (DR_). The fourth NMOS (N4) has its gate connected to the gate of the fifth NMOS (N5). The first signal selection terminal of the column gating and write drive circuit is connected to the first column decode gating signal (YCDSEL), and its drain is connected to the first write bit line (DW). The fifth NMOS (N5) has its drain connected to the second write bit line (DW_).

5. An SRAM write auxiliary circuit having the MUX structure as described in claim 3, characterized in that, It also includes: auxiliary circuits; The auxiliary circuit includes: The third NOT gate has its input connected to the output (OUT) of the MUX trigger circuit, and its output is written to the auxiliary control signal (WAGTP) to one input of the NOR gate. The NOR gate has its other input connected to the second write enable signal (GTPB), and its output connected to the fourth NOT gate. The fourth NOT gate's output is connected to the negative voltage node (NVSS) via a capacitor (C0); The fourth NMOS (N4) has its drain connected to the negative voltage node (NVSS), its source grounded, and its gate connected to the second write enable signal (GTPB). The fifth NOT gate has its input connected to the first write enable signal (GTP) and its output to the second write enable signal (GTPB). The sixth NOT gate has its input connected to external data (DATA) and its output connected to the inputs of the seventh and eighth NOT gates; The output of the seventh NOT gate is connected to the input of the ninth NOT gate; The eighth NOT gate is connected to the negative voltage node (NVSS), and its output is connected to the first write data line (DW). The ninth NOT gate is connected to the negative voltage node (NVSS), and its output is connected to the second write data line (DW_).

6. The SRAM write auxiliary circuit as described in claim 5, characterized in that: When the MUX trigger circuit output is set to high level, the write auxiliary control signal (WAGTP) changes from high level to low level, the second write enable signal (GTPB) is at level, the voltage at the left end of the capacitor (C0) changes abruptly from high level 1 to low level 0, the negative voltage node (NVSS) forms a negative voltage, making the end of the first write data line (DW) or the second write data line (DW_) that needs to be written to a low level become a negative voltage, thus completing the write auxiliary.

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