Method and device for mapping logic unit

Abstract

The embodiment of the invention provides a method and device for mapping a logic unit. The method comprises the steps that the packaging type of a solid state disk is determined according to the packaging type of each nonvolatile memory connected with the solid state disk; determining the type of the logic unit of the solid state disk according to the type of the logic unit of each nonvolatile memory connected with the solid state disk; and mapping the logic unit of the solid state disk to firmware according to the packaging type of the solid state disk and the logic unit type. Through the method and the device, the problem that a controller in the related technology cannot adapt to flash memory particles of different manufacturers and is compatible with flash memory particles of different packaging modes of the same manufacturer at the same time is solved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of computers, and in particular, to a method and apparatus for mapping logical units. BACKGROUND

[0002] In the field of storage devices, there are interface protocol differences, electrical characteristic fluctuations, and physical package diversities (such as BGA, TSOP, CSP, etc.) of NAND flash memory particles of different manufacturers, and controllers need to implement cross-manufacturer compatibility to adapt to the diversity requirements of the supply chain. Flash memory particles produced by the same manufacturer also have different packaging methods.

[0003] Current controllers cannot adapt to particles of different manufacturers, and simultaneously compatible with particles of different packaging methods of the same manufacturer.

[0004] Currently, there is no effective solution to the above problems. SUMMARY

[0005] Embodiments of the present application provide a method and apparatus for mapping logical units to at least solve the problem that the controller in the related art cannot adapt to flash memory particles of different manufacturers, and simultaneously compatible with flash memory particles of different packaging methods of the same manufacturer.

[0006] According to one embodiment of the present application, a method for mapping logical units is provided, comprising: determining the packaging type of a solid state disk according to the packaging type of each non-volatile memory connected to the solid state disk; determining the logical unit type of the solid state disk according to the type of the logical unit of each non-volatile memory connected to the solid state disk; and mapping the logical unit of the solid state disk to firmware according to the packaging type of the solid state disk and the logical unit type.

[0007] In one exemplary embodiment, mapping the logical unit of the solid state disk to firmware according to the packaging type of the solid state disk and the logical unit type comprises: in the case of a single packaging type and a single logical unit type, mapping the logical unit of each non-volatile memory in the solid state disk to the firmware through a channel and a chip enable pin; and in the case of a mixed packaging type of the solid state disk or a mixed logical unit type, mapping the logical unit of each non-volatile memory in the solid state disk to the firmware through a channel, a chip enable pin, and a logical unit number.

[0008] In one exemplary embodiment, mapping the logical unit of each non-volatile memory in the solid state disk to the firmware through a channel and a chip enable pin comprises: traversing the logical unit of each non-volatile memory in the solid state disk through the channel and the chip enable pin; and sequentially mapping the logical unit to the firmware.

[0009] In an example embodiment, mapping logical units of each of the non-volatile memories in the solid state disk to the firmware through the channel, chip enable pin and logical unit number comprises: traversing the logical units of each of the non-volatile memories in the solid state disk through the channel and chip enable pin; and mapping the logical units to the firmware in sequence.

[0010] In an example embodiment, determining the packaging type of the solid state disk according to the packaging type of each of the non-volatile memories connected to the solid state disk comprises: determining the packaging type of the solid state disk as a single packaging type if the packaging types of the non-volatile memories of the solid state disk are consistent; otherwise, as a hybrid packaging type.

[0011] In an example embodiment, determining the logical unit type of the solid state disk according to the type of the logical units of each of the non-volatile memories connected to the solid state disk comprises: determining the logical unit type of the solid state disk as a single logical unit type if the types of the logical units of the non-volatile memories of the solid state disk are consistent; otherwise, as a hybrid logical unit type.

[0012] In an example embodiment, the method further comprises: determining the total capacity of the solid state disk according to the number of logical units included in the solid state disk; and setting the corresponding on-chip termination resistance parameter for the logical unit of each of the non-volatile memories according to the total capacity and the on-chip termination resistance parameter table.

[0013] In an example embodiment, setting the corresponding on-chip termination resistance parameter for the logical unit of each of the non-volatile memories comprises: setting the delay-locked loop parameter for the logical unit of each of the non-volatile memories in sequence according to a preset delay-locked loop parameter range; performing erasing, writing and reading on the non-volatile memories to record the original bit error rate of each logical unit; and determining the delay-locked loop parameter corresponding to the smallest original bit error rate as the target delay-locked loop parameter of the logical unit.

[0014] In an example embodiment, before determining the packaging type of the solid state disk according to the packaging type of each of the non-volatile memories connected to the solid state disk, the method further comprises: reading first parameter information from each of the non-volatile memories connected to the solid state disk; and verifying the solid state disk through the first parameter information.

[0015] In one example embodiment, the verifying the solid state disk by the first parameter information comprises: obtaining information of each nonvolatile memory connected to the solid state disk; obtaining parameter information of each nonvolatile memory in a configuration file according to the information of each nonvolatile memory, to obtain second parameter information; and verifying the solid state disk in a case that the first parameter information is consistent with the second parameter information.

[0016] According to another embodiment of the present application, a device for mapping logical units is provided, comprising: a first determining module configured to determine a packaging type of a solid state disk according to a packaging type of each nonvolatile memory connected to the solid state disk; a second determining module configured to determine a logical unit type of the solid state disk according to a type of a logical unit of each nonvolatile memory connected to the solid state disk; and a mapping module configured to map the logical unit of the solid state disk to firmware according to the packaging type of the solid state disk and the logical unit type.

[0017] According to still another embodiment of the present application, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, wherein the computer program is executed by a processor to implement the steps of the method in any of the above embodiments.

[0018] According to still another embodiment of the present application, an electronic device is provided, comprising a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0019] According to still another embodiment of the present application, a computer program product is provided, comprising a computer program, and the computer program is executed by a processor to implement the steps of the method in any of the above embodiments.

[0020] According to the present application, the packaging type of the solid state disk is determined according to the packaging type of each nonvolatile memory connected to the solid state disk, the logical unit type of the solid state disk is determined according to the type of the logical unit of each nonvolatile memory connected to the solid state disk, and the logical unit of the solid state disk is mapped to firmware according to the packaging type of the solid state disk and the logical unit type. Therefore, the problem that the controller in the related art cannot adapt to flash memory particles of different manufacturers and simultaneously compatible with flash memory particles of different packaging manners of the same manufacturer can be solved, and the effect that the controller can adapt to flash memory particles of different manufacturers and simultaneously compatible with flash memory particles of different packaging manners of the same manufacturer can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a hardware structure block diagram of a mobile terminal of a method for mapping logical units according to an embodiment of the present application;

[0022] Figure 2 is a flowchart of a mapping logic unit according to an embodiment of the present application;

[0023] Figure 3 is a schematic diagram of a four-chip package grain according to an embodiment of the present application;

[0024] Figure 4 is a schematic diagram of an eight-chip package grain according to an embodiment of the present application;

[0025] Figure 5 is a schematic diagram of a physical nand flash sequential mapping according to an embodiment of the present application;

[0026] Figure 6 is a schematic diagram of a logical lun sequential mapping according to an embodiment of the present application;

[0027] Figure 7 is a structural block diagram of an apparatus of a mapping logic unit according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] Embodiments of the present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0029] Target (target) is the maximum unit of flash grain package, there are several lun (logical unit) in a target; lun is the unit that can be operated concurrently in the target, a lun contains several Blocks (blocks); Block is the smallest erasing unit of Nand Flash (non-volatile memory) grain, a Block contains several Pages (pages); Page is the smallest read-write operation unit of Nand Flash (non-volatile memory) grain; Raw Bit Error Rate (Raw Bit Error Rate, RBER) is an important indicator to measure the reliability of Nand Flash grain, Raw Bit Error Rate refers to the bit error rate in the data transmission or storage process before ECC (Error Correction Code) processing. It reflects the reliability of data in the most original state.

[0030] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0031] The method embodiments provided in the embodiments of the present application can be executed in a controller or similar computing device. Taking the case of running on a controller, Figure 1 is a hardware structural block diagram of a mobile terminal of a mapping logic unit method according to an embodiment of the present application. As Figure 1 shown, the controller can include one or moreFigure 1 The controller can include a processor 102 (the processor 102 can include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. The controller can also include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art can understand that the controller can include more or fewer components than those shown in the figure, or have a different configuration from that shown in the figure. Figure 1 The structure shown is only schematic and does not limit the structure of the controller. For example, the controller can include more or fewer components than those shown in the figure, or have a different configuration from that shown in the figure. Figure 1 The structure shown in the figure can include more or fewer components than those shown in the figure, or have a different configuration from that shown in the figure. Figure 1 The structure shown in the figure can include more or fewer components than those shown in the figure, or have a different configuration from that shown in the figure.

[0032] The memory 104 can be used to store computer programs, such as software programs of application software and modules, such as a computer program corresponding to the method of the mapping logic unit in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, i.e. implements the method described above. The memory 104 can include a high-speed random access memory, and can also include a non-volatile memory, such as one or more magnetic storage devices, a flash memory, or other non-volatile solid-state memories. In some examples, the memory 104 can further include a memory remotely arranged with respect to the processor 102, which can be connected to the mobile terminal through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0033] The transmission device 106 is used to receive or send data via a network. Specific examples of the network can include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet in a wireless manner.

[0034] In the embodiment, a method of a mapping logic unit running on a controller is provided, Figure 2 The flowchart of the mapping logic unit according to the embodiment of the present application is shown in the figure, which includes the following steps: Figure 2

[0035] In step S202, the packaging type of the solid state disk is determined according to the packaging types of the non-volatile memories connected to the solid state disk.

[0036] ​Specifically, in the case that the package types of the non-volatile memories of the solid state disk are consistent, the package type of the solid state disk is determined as a single package type; otherwise, as a mixed package type.

[0037] The package type of the non-volatile memory (NAND flash) is confirmed according to the obtained flash id. If the NAND flash used by the solid state disk (SSD) is of the same package type, the solid state disk is determined as a single package type. If the package types of the NAND flash used by the solid state disk (SSD) are different, the solid state disk is determined as a mixed package type.

[0038] In step S204, the logical unit type of the solid state disk is determined according to the types of the logical units of the non-volatile memories connected by the solid state disk.

[0039] Specifically, in the case that the package types of the non-volatile memories of the solid state disk are consistent, the package type of the solid state disk is determined as a single package type; otherwise, as a mixed package type.

[0040] Based on the read parameter page, the logical unit (lun) information of all the NAND flash used by the solid state disk (SSD) is obtained. If the logical unit types of all the NAND flash are consistent (all are single logical units (single lun) or all are multi logical units (multi lun)), the solid state disk is called as a single logical unit type (single lun type) SSD. If there are both single lun and multi lun in the NAND flash (i.e., the logical unit types of all the NAND flash of the solid state disk are inconsistent), the solid state disk is called as a mixed logical unit type (mixed lun type) SSD.

[0041] Multi lun and single lun are the differences in physical structure. Generally, the controller locks the logical unit (die) that needs to send a command through two signal lines of channel (CH) and chip enable pin (CE). Single lun is based on the logical unit (die) corresponding to CH / CE, which has and only has one. Multi lun is based on the die corresponding to CH / CE, which is greater than or equal to two. At this time, in order to distinguish these dies, the logical unit number (lun number) is introduced to confirm which logical unit (die) needs to be finally operated.

[0042] Die and Lun have the same meaning, which refers to a logical unit in a physical sense. In the semiconductor industry, LUN (Logical Unit Number) is a logical unit number used to identify different storage units in a storage device. In storage devices such as NAND Flash, LUN usually refers to the logical unit of a storage chip, which is the basic unit of storage space division. Only one command can be executed at the same time in the same LUN - read, write, erase, different LUNs do not affect each other, and different commands can be executed at the same time.

[0043] As shown in Figure 3 , it is a four-chip package (Quad Die Package, referred to as QDP) (single lun has four dies), Figure 4 It is an eight-chip package (Octal Die Package, referred to as ODP) (multi lun has eight dies). (Generally, when the package inside the particle exceeds four dies, it is a multi lun particle, but some manufacturers can also use single lun, so it needs to be accurately judged through the lun information in the parameter page).

[0044] Figure 3 As shown in the QDP, select DIE0 through CE0 CH0, and select all dies in this way; Figure 4 As shown in the ODP, select DIE0 through CE0 CH0 LUN0, and select all dies in this way.

[0045] Step S206, mapping the logical unit of the solid state disk to the firmware according to the packaging type of the solid state disk and the logical unit type.

[0046] In one exemplary embodiment, mapping the logical unit of the solid state disk to the firmware according to the packaging type of the solid state disk and the logical unit type includes: in the case of a single packaging type and a single logical unit type, mapping the logical unit of each non-volatile memory in the solid state disk to the firmware through a channel and chip enable pin.

[0047] Specifically, the logical unit of each non-volatile memory in the solid state disk is traversed through the channel and chip enable pin; and the logical unit is mapped to the firmware in turn.

[0048] For single package type SSD and single lun type SSD, physical nand flash sequential mapping is adopted. The specific logic is as follows: for example, there are x nand flashes in total, all the logical units (luns) in the nand flash 1 are sequentially mapped to the logical units (dies) used in the firmware (FW), and then the logical units (luns) in the nand flash 2 are mapped after the corresponding logical units (dies) of the nand flash 1, and the mapping is sequentially performed until the nand flash x.

[0049] As shown in Figure 5 , the physical nand flash sequential mapping is shown, and the bold black box is the sequential physical logical unit (die) inside the nand flash; the red font is the sequential logical unit (die) in the FW firmware.

[0050] In the case where the package type of the solid state disk is a hybrid package type or the logical unit type is a hybrid logical unit type, the logical units of each non-volatile memory in the solid state disk are mapped to the firmware through the channel, chip enable pin and logical unit number.

[0051] Specifically, the logical units of each non-volatile memory in the solid state disk are traversed through the channel and chip enable pin; and the logical units are sequentially mapped to the firmware.

[0052] For hybrid lun type SSD, logical lun sequential mapping is required. The specific logic is as follows: for example, there are x nand flashes in total, and the number of multi-lun is lun x, first, all the lun 0 of the nand flash is mapped to the die used in the FW, then all the lun 1 of the nand flash is mapped after the corresponding die of lun 0, and the mapping is sequentially performed until lun x.

[0053] The logical lun sequential mapping is specifically shown in Figure 6 : wherein the bold black box is the sequential physical die inside the nand flash; the red font is the sequential logical die in the FW firmware.

[0054] Finally, after the mapping is completed, the FW firmware is loaded and run.

[0055] Optionally, the execution subject of the above steps can be a background processor, or other devices with similar processing capabilities, and can also be a machine integrated with at least an image acquisition device and a data processing device, wherein the image acquisition device can include a camera and other graphic acquisition modules, and the data processing device can include a computer, a mobile phone and other terminals, but is not limited thereto.

[0056] The execution order of steps S202 and S204 can be interchanged, i.e., step S204 can be executed first, and then step S202 can be executed.

[0057] In one example embodiment, before determining the package type of the solid state disk according to the package types of the individual non-volatile memories connected to the solid state disk, the method further comprises: reading first parameter information in the individual non-volatile memories connected to the solid state disk; and verifying the solid state disk through the first parameter information.

[0058] In one example embodiment, verifying the solid state disk through the first parameter information comprises: obtaining information of the individual non-volatile memories connected to the solid state disk; obtaining parameter information of the individual non-volatile memories in a configuration file according to the information of the individual non-volatile memories, to obtain second parameter information; and verifying the solid state disk in a case where the first parameter information is consistent with the second parameter information.

[0059] The first parameter information and the second parameter information comprise: flash identification (flash id), communication interface protocol, read-write-erase operation instruction, timing parameter, etc.

[0060] When the card opening operation is performed on the solid state disk SSD, the card opening tool sends a read flash identification instruction (read flash id instruction) to the SSD first, and the controller returns flash identification (flash id) information of all the non-volatile memories (nand flash) currently connected, and the manufacturer of the nand flash is parsed according to the information.

[0061] Then the controller sends a corresponding read instruction (read parameter page instruction) according to the manufacturer, which is used to read nand-related parameter information written in a specific position of the nand flash by the manufacturer during production, and the parameter information read this time is recorded as parameter table B (first parameter information).

[0062] The NAND FLASH information of multiple manufacturers is recorded in the configuration file corresponding to the card opening tool, which includes flash identification (flash id), communication interface protocol, read-write-erase operation instruction, timing parameter, etc., and these information are saved one by one.

[0063] The flash id information of all the nand flash currently connected returned by the controller is used to parse the manufacturer of the nand flash, and the corresponding parameter information is obtained from the configuration file and is recorded as parameter table A (second parameter information) in the controller.

[0064] If the parameter tables A and B are inconsistent, the current process is terminated, and the developer can perform fault repair; if the verification is passed (the parameter table information is consistent), the verification is successful, and the preliminary parameter configuration is completed.

[0065] Optionally, the total amount of information of the parameter table A (obtained from the corresponding parameter information in the configuration file) and the parameter table B (parameter information in the parameter page) is inconsistent, the parameter table A is contained in the parameter table B, and therefore, only the information common to both can be compared during verification.

[0066] In an example embodiment, the method further includes determining the total capacity of the solid state disk according to the number of logical units included in the solid state disk, and setting the corresponding on-die termination resistance parameter for each logical unit of the non-volatile memory according to the total capacity and the on-die termination resistance parameter table.

[0067] In an example embodiment, setting the corresponding on-die termination resistance parameter for each logical unit of the non-volatile memory includes sequentially setting the delay-locked loop parameter for each logical unit of the non-volatile memory according to a preset delay-locked loop parameter range, erasing, writing and reading the non-volatile memory, and recording the original bit error rate of each logical unit, and determining the delay-locked loop parameter corresponding to the smallest original bit error rate as the target delay-locked loop parameter of the logical unit.

[0068] The nand flash information connected to the controller is read, the number of logical units (die) of the nand flash is obtained, the total capacity of the current SSD is calculated, and the on-die termination resistance parameter (ODT parameter) of the logical unit (die) is set according to the capacity and the on-die termination resistance parameter table (ODT parameter table).

[0069] Then, a suitable delay-locked loop parameter (DQS_DLL parameter) is screened, and a preset delay-locked loop parameter range (the range of the DLL parameter, which can be 0x00-0xFF, for example) is adopted. In a traversal manner, the DLL parameter is configured as 0x00 for each DIE, the first BLOCK (flash block) of each logical unit (Die) is erased, written and read, and the corresponding original bit error rate (RBER data) is recorded, until all the DLL parameters are used. Finally, all the RBER data are compared, the DLL corresponding to the lowest RBER is obtained, and the DLL parameter is considered as the most suitable target delay-locked loop parameter.

[0070] ODT (On-Die Termination) in NAND Flash is a signal integrity technology mainly used to reduce signal reflection and noise interference during high-speed data transmission. Here, the ODT parameter mainly refers to the programmable ODT resistance value (such as 40Ω, 60Ω, 120Ω), which is adjusted through a configuration register to adapt to different channel characteristics.

[0071] NAND Flash DQSDLL solves the timing offset problem in high-speed data transmission by adjusting the delay in real time, and is the core technology to ensure the reliability of DDR mode. Its design needs to balance precision, power consumption and anti-interference ability, and work with ODT to cope with higher bandwidth requirements. By adjusting the DLL delay range configuration, the phase alignment of DQS signal and DQ signal is realized.

[0072] The present application first determines the corresponding manufacturer of the NAND FLASH by reading the flash id (flash identification code, unique identifier of a device or storage chip), then configures the corresponding communication interface protocol (ONFI OR TOGGLE), read and write erase operation instructions, and corresponding timing parameters of the manufacturer. Then calculate the capacity, select the ODT drive (On-Die Termination) and DQSDLL parameters (Data Strobe Delay Locked Loop) used according to the capacity. Finally, read the package information of the controller connecting all non-volatile memories (nand flash), if not the same packaging form, change the mapping logic, complete the adaptation of flash particles.

[0073] The present application realizes the compatibility and adaptation of different manufacturers' particles and the same kind of particles with different packaging forms through reading and analyzing the particle information.

[0074] The present application first reads the particle information in multiple ways, verifies and determines its characteristic information, then configures the corresponding parameter information of the particle according to the characteristic information, and finally distinguishes different packaging forms of the same kind of particles. Finally, the controller adapts to multiple particles, and is compatible with the same kind of particles with different packaging forms.

[0075] Those skilled in the art can clearly understand that the method according to the above-mentioned embodiments can be realized by means of software on the necessary general hardware platform, and of course can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disc) and includes a plurality of instructions for causing a terminal device (which can be a mobile phone, a computer, a server, or a network device) to execute the method described in the various embodiments of the present application.

[0076] In the present embodiment, a device for mapping logical units is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, implementation of hardware, or a combination of software and hardware, is also possible and contemplated.

[0077] Figure 7 is a structural block diagram of a device for mapping logical units according to an embodiment of the present application, as shown in Figure 7 The device includes:

[0078] A first determining module 72 is configured to determine the package type of the solid state disk according to the package types of the individual non-volatile memories connected to the solid state disk;

[0079] A second determining module 74 is configured to determine the logical unit type of the solid state disk according to the logical unit types of the individual non-volatile memories connected to the solid state disk;

[0080] A mapping module 76 is configured to map the logical units of the solid state disk to the firmware according to the package type of the solid state disk and the logical unit type.

[0081] In an exemplary embodiment, the above-mentioned device is further configured to map the logical units of the individual non-volatile memories in the solid state disk to the firmware through channels and chip enable pins in the case of a single package type and a single logical unit type; and to map the logical units of the individual non-volatile memories in the solid state disk to the firmware through channels, chip enable pins, and logical unit numbers in the case of a mixed package type or a mixed logical unit type.

[0082] In an example embodiment, the device is further configured to traverse logical units of each of the non-volatile memories in the solid state disk through the channel and chip enable pin; and sequentially map the logical units to the firmware.

[0083] In an example embodiment, the device is further configured to traverse logical units of each of the non-volatile memories in the solid state disk through the channel and chip enable pin; and sequentially map the logical units to the firmware.

[0084] In an example embodiment, the device is further configured to determine the package type of the solid state disk as a single package type if the package types of the non-volatile memories of the solid state disk are consistent; otherwise, as a mixed package type.

[0085] In an example embodiment, the device is further configured to determine the logical unit type of the solid state disk as a single logical unit type if the types of the logical units of the non-volatile memories of the solid state disk are consistent; otherwise, as a mixed logical unit type.

[0086] In an example embodiment, the device is further configured to determine the total capacity of the solid state disk according to the number of logical units included in the solid state disk; and set the on-chip termination resistance parameter of each of the logical units of the non-volatile memories according to the total capacity and the on-chip termination resistance parameter table.

[0087] In an example embodiment, the device is further configured to set the delay-locked loop parameter of each of the logical units of the non-volatile memories according to a preset delay-locked loop parameter range; perform erasing, writing and reading on the non-volatile memories to record the original bit error rate of each of the logical units; and determine the delay-locked loop parameter corresponding to the smallest original bit error rate as the target delay-locked loop parameter of the logical unit.

[0088] In an example embodiment, the device is further configured to read first parameter information from each of the non-volatile memories connected to the solid state disk before determining the package type of the solid state disk according to the package types of the non-volatile memories connected to the solid state disk; and verify the solid state disk through the first parameter information.

[0089] In an example embodiment, the device is further configured to obtain information of each of the non-volatile memories connected to the solid state disk; obtain parameter information of each of the non-volatile memories in a configuration file according to the information of each of the non-volatile memories to obtain second parameter information; and pass the verification of the solid state disk if the first parameter information is consistent with the second parameter information.

[0090] It should be noted that the above various modules can be implemented by software or hardware, and for the latter, the implementation can be achieved by the following ways, but is not limited thereto: the above modules are located in the same processor; or the above various modules are located in different processors in any combination.

[0091] The embodiment of the present application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize the steps of the method in any one of the above embodiments.

[0092] In an example embodiment, the computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0093] The embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any one of the above method embodiments.

[0094] In an example embodiment, the electronic device can further comprise a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0095] The specific examples in the embodiment can refer to the examples described in the above embodiments and example embodiments, and the embodiment will not be described here.

[0096] The embodiment of the present application further provides a computer program product, comprising a computer program, and the computer program is executed by a processor to realize the steps of the method in the embodiments of the present application.

[0097] Obviously, those skilled in the art should understand that the above various modules or steps of the present application can be realized by a general computing device, which can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, which can be realized by program codes executable by a computing device, so that they can be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described can be executed in different order, or they can be manufactured into individual integrated circuit modules, or multiple modules or steps can be manufactured into a single integrated circuit module. Thus, the present application is not limited to any specific hardware and software combination.

[0098] The above merely provides the preferred embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall fall into the protective scope of the present application.

Claims

1. A method of mapping a logic unit, characterized by, The method comprises: determining the package type of the solid state disk according to the package types of the non-volatile memories connected to the solid state disk; determining the logical unit type of the solid state disk according to the logical unit types of the non-volatile memories connected to the solid state disk; mapping the logical units of the solid state disk to the firmware according to the package type and the logical unit type of the solid state disk.

2. The method of claim 1, wherein, The method of mapping the logical units of the solid state disk to the firmware according to the package type and the logical unit type of the solid state disk comprises: in the case that the package type of the solid state disk is a single package type and the logical unit type is a single logical unit type, mapping the logical units of each of the non-volatile memories in the solid state disk to the firmware through the channel and the chip enable pin; in the case that the package type of the solid state disk is a mixed package type or the logical unit type is a mixed logical unit type, mapping the logical units of each of the non-volatile memories in the solid state disk to the firmware through the channel, the chip enable pin and the logical unit number.

3. The method of claim 2, wherein, The method of mapping the logical units of each of the non-volatile memories in the solid state disk to the firmware through the channel and the chip enable pin comprises: traversing the logical units of each of the non-volatile memories in the solid state disk through the channel and the chip enable pin; mapping the logical units to the firmware in sequence.

4. The method of claim 2, wherein, The method of mapping the logical units of each of the non-volatile memories in the solid state disk to the firmware through the channel, the chip enable pin and the logical unit number comprises: traversing the logical units of each of the non-volatile memories in the solid state disk through the channel and the chip enable pin; mapping the logical units to the firmware in sequence.

5. The method of claim 1, wherein, The method of determining the package type of the solid state disk according to the package types of the non-volatile memories connected to the solid state disk comprises: in the case that the package types of the non-volatile memories of the solid state disk are consistent, determining the package type of the solid state disk as a single package type; otherwise, determining the package type of the solid state disk as a mixed package type.

6. The method of claim 1, wherein, The method of determining the logical unit type of the solid state disk according to the logical unit types of the non-volatile memories connected to the solid state disk comprises: in the case that the logical unit types of the non-volatile memories of the solid state disk are consistent, determining the logical unit type of the solid state disk as a single logical unit type; otherwise, determining the logical unit type of the solid state disk as a mixed logical unit type.

7. The method of claim 1, wherein, The method further comprises: determining the total capacity of the solid state disk according to the number of logical units included in the solid state disk; setting the corresponding on-chip termination resistance parameters for the logical units of each of the non-volatile memories according to the total capacity and an on-chip termination resistance parameter table.

8. The method of claim 7, wherein, The method of setting the corresponding on-chip termination resistance parameters for the logical units of each of the non-volatile memories comprises: setting the delay-locked loop parameters for the logical units of each of the non-volatile memories in sequence within a preset delay-locked loop parameter range, erasing, writing and reading the non-volatile memories, and recording the original bit error rates of the logical units. The delay-locked loop parameter corresponding to the minimum original bit error rate is determined as a target delay-locked loop parameter of the logic unit.

9. The method of claim 1, wherein, Before determining the package type of the solid state disk according to the package types of the individual non-volatile memories connected to the solid state disk, the method further comprises: reading first parameter information from the individual non-volatile memories connected to the solid state disk; verifying the solid state disk through the first parameter information.

10. The method of claim 9, wherein, verifying the solid state disk through the first parameter information comprises: obtaining information of the individual non-volatile memories connected to the solid state disk; obtaining parameter information of the individual non-volatile memories from a configuration file according to the information of the individual non-volatile memories, to obtain second parameter information; in a case where the first parameter information is consistent with the second parameter information, verifying the solid state disk is passed.

11. An apparatus for mapping a logic cell, the apparatus comprising: comprises: a first determining module configured to determine the package type of the solid state disk according to the package types of the individual non-volatile memories connected to the solid state disk; a second determining module configured to determine the logic unit type of the solid state disk according to the types of the logic units of the individual non-volatile memories connected to the solid state disk; a mapping module configured to map the logic units of the solid state disk to firmware according to the package type and the logic unit type of the solid state disk.

12. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, wherein the computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 10. 13.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is configured to run the computer program to execute the method in any one of claims 1 to 10.

14. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 10.

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