Data reading method of memory and memory

Abstract

The invention provides a data reading method of a memory and the memory. The data reading method of the memory comprises the following steps: in response to a data reading instruction of a processor, determining a first target area where a first address in the data reading instruction is located from a plurality of storage areas based on a plurality of address intervals of the plurality of storage areas; querying a value of a first state identification bit of the first target area, wherein the value of the first state identification bit represents whether the first target area enables a data verification function or not; when the value of the first state identification bit represents that the first target area enables a data verification function, reading data and a verification code of the data from the first address; and verifying the data through the verification code to obtain a verification result, and outputting the data to the processor based on the verification result. According to the method and the device, the flexibility of data verification during data reading can be improved.

Description

Technical Field

[0001] This application relates to computer technology, and more particularly to a data reading method for a memory and a memory. Background Technology

[0002] Digital integrated circuit design and System-on-a-Chip (SoC) design both require the use of memory, such as Static Random-Access Memory (SRAM), as the storage medium. As storage demands increase, memory capacity grows larger. However, some memory types, such as SRAM, can experience data errors in individual bits due to signal interference or unstable reliability during use. Furthermore, related technologies suffer from limited flexibility in data verification when reading data from memory. Summary of the Invention

[0003] This application provides a data reading method and a memory, which can improve the flexibility of data verification during data reading.

[0004] The technical solution of this application embodiment is implemented as follows: This application provides a data reading method for a memory, the memory including a RAM chip, the RAM chip including multiple storage areas, the method including: In response to a data read instruction from the processor, based on multiple address ranges of the multiple storage regions, a first target region containing the first address in the data read instruction is determined from the multiple storage regions; Query the value of the first status flag bit of the first target area. The value of the first status flag bit indicates whether the data verification function is enabled in the first target area. When the value of the first status flag indicates that the data verification function is enabled in the first target area, data is read from the first address, along with the verification code of the data. The data is verified using the verification code to obtain a verification result, and the data is output to the processor based on the verification result.

[0005] This application provides a data writing method for a memory, the memory including a RAM chip, the RAM chip including multiple storage areas, the method including: In response to a data write instruction from the processor, based on multiple address ranges of the multiple storage regions, a second target region containing the second address in the data write instruction is determined from the multiple storage regions; Query the value of the second status flag bit of the second target area. The value of the second status flag bit indicates whether the data verification function is enabled in the second target area. When the value of the second status flag indicates that the data verification function is enabled in the second target area, a verification code is generated for the data in the data writing instruction; At the second address, write the data and the verification code.

[0006] This application provides a memory, which includes: a region determination unit, a decoder, a RAM chip, and a register, wherein the RAM chip includes multiple storage regions; The region determination unit is configured to respond to a data read instruction from the processor, and based on multiple address ranges of multiple storage regions stored in the register, determine the first target region where the first address in the data read instruction is located from the multiple storage regions; and query the value of the first status flag bit of the first target region from the register, wherein the value of the first status flag bit indicates whether the data verification function is enabled in the first target region. The decoder is configured to read data from the first address and the checksum of the data when the value of the first status flag indicates that the data verification function is enabled in the first target area; and to verify the data using the checksum to obtain a verification result, and to output data to the processor based on the verification result. The RAM chip is used to store data and checksums; The register is used to store multiple address ranges of multiple storage regions, as well as the value of the first status flag bit of the first target region.

[0007] In the above scheme, the decoder is also used to determine the syndrome based on the data and the check code; and to check for errors in the data based on the syndrome to obtain the check result.

[0008] In the above scheme, the register also stores the values ​​of the first error flag bit and the second error flag bit; The decoder is also configured to correct the single-bit error in the data when the verification result indicates that the data has a single-bit error, and output the corrected data to the processor; and to set the value of the first error flag bit and the value of the second error flag bit in the register to a first preset value indicating the presence of an error, wherein the first error flag bit is used to indicate whether the data has an error, and the second error flag bit is used to indicate whether the data has a single-bit error.

[0009] In the above scheme, the register also stores the values ​​of the first error flag bit and the third error flag bit; The decoder is also configured to output the data to the processor when the verification result indicates that the data has a double-bit error; and to set the value of the first error flag bit and the value of the third error indicator bit in the register to a first preset value indicating the presence of an error, wherein the third error flag bit is used to indicate whether the data has a double-bit error.

[0010] In the above scheme, the register also stores the values ​​of the first error flag bit, the second error flag bit, and the third error flag bit; The decoder is also configured to output the data to the processor when the verification result indicates that the data does not contain any errors; and to set the values ​​of the first error indicator bit, the second error indicator bit, and the third error indicator bit in the register to a second preset value indicating that no errors exist.

[0011] In the above scheme, the decoder is also used to read the data from the first address and output the data to the processor when the value of the first status flag bit indicates that the data verification is not enabled in the first target area.

[0012] In the above scheme, the plurality of storage regions are obtained by the processor dividing the RAM chip, and the plurality of address ranges of the plurality of storage regions are generated by the processor; and, The value of the first status flag bit in the register is generated by the processor.

[0013] This application provides a memory, which includes: a region determination unit, an encoder, a RAM chip, and a register, wherein the RAM chip includes multiple storage regions; The region determination unit is configured to respond to a data write instruction from the processor, and based on multiple address ranges of multiple storage regions stored in the register, determine the second target region where the second address in the data write instruction is located from the multiple storage regions; and query the value of the second status flag bit of the second target region from the register, wherein the value of the second status flag bit indicates whether the data verification function is enabled in the second target region. The encoder is configured to generate a verification code for the data in the data writing instruction when the value of the second status flag bit indicates that the data verification function is enabled in the second target area; and to write the data and the verification code to the second address. The RAM chip is used to store data and checksums; The register is used to store multiple address ranges of multiple storage regions, as well as the value of the second status flag bit of the second target region.

[0014] In the above scheme, the encoder is also used to write the data to the second address when the value of the second status flag bit indicates that the data verification function is not enabled in the second target area.

[0015] This application provides an electronic device, which includes a processor and a memory provided in this application.

[0016] The embodiments of this application have the following beneficial effects: the RAM chip in the memory is divided into multiple storage areas, and the data verification function can be independently enabled or disabled for each storage area by the value of the status flag bit corresponding to each storage area. Thus, during the data reading process, the first target area is determined from multiple storage areas according to the first address specified by the data reading instruction. Then, by querying the value of the first status flag bit of the first target area, it is determined whether the data verification function of the first target area is enabled. Only when the data verification function is enabled, the data is verified using the verification code read from the first address, and then the data is output to the processor in combination with the verification result. Thus, it is possible to decide whether to start data verification as needed, which improves the flexibility of data verification when reading data while ensuring data reliability. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the architecture of the data reading system for the memory provided in an embodiment of this application; Figure 2 This is a flowchart illustrating the data reading method for a memory provided in an embodiment of this application. Figure 1 ; Figure 3 This is a flowchart illustrating the data reading method for a memory provided in an embodiment of this application. Figure 2 ; Figure 4 This is a flowchart illustrating the data reading method for a memory provided in an embodiment of this application. Figure 3 ; Figure 5 This is a flowchart illustrating the data writing method for a memory provided in an embodiment of this application. Figure 1 ; Figure 6 This is a flowchart illustrating the data writing method for a memory provided in an embodiment of this application. Figure 2 ; Figure 7 This is a schematic diagram of the data writing and data reading processes provided in the embodiments of this application; Figure 8 This is a schematic diagram of data bits during data transmission provided in an embodiment of this application; Figure 9A schematic diagram illustrating the transmission format of 8-bit data and 5-bit error correction code provided in an embodiment of this application; Figure 10 This is a schematic diagram of the SRAM region division provided in an embodiment of this application; Figure 11 This is a schematic diagram of the memory structure provided in the embodiments of this application. Figure 1 ; Figure 12 This is a schematic diagram of the memory structure provided in the embodiments of this application. Figure 2 . Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0020] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0021] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0022] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0023] In the implementation of this application, the collection and processing of relevant data should strictly comply with the requirements of relevant laws and regulations, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing within the scope of laws and regulations and the authorization of the personal information subject.

[0024] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0025] 1) Responding to: used to indicate the conditions or states on which the operation is performed depends. When the conditions or states on which it depends are met, one or more operations can be performed in real time or with a set delay. Unless otherwise specified, there is no restriction on the order in which the multiple operations are performed.

[0026] 2) Human-Computer Interaction Interface (HCI): An interface used to provide human-computer interaction functions or display information about business processing results. Examples include Graphical User Interface (GUI) displays, such as Augmented Reality (AR) interfaces, Virtual Reality (VR) interfaces, Voice User Interface (VUI) interfaces, interactive projection interfaces (using projection technology to display information on a flat surface), eye-tracking interfaces (interfaces controlled by detecting the user's gaze), holographic interfaces (three-dimensional holograms formed by projecting images using holographic projection technology, allowing users to see stereoscopic images without wearing special glasses), and multimodal interfaces (interfaces combining multiple interaction methods, such as tactile, visual, and auditory interaction).

[0027] 3) Memory refers to hardware devices used to store programs and data. Its core function is to store data (in binary form) in a certain location and to retrieve it accurately and perform calculations when needed later.

[0028] 4) Checksums are redundant bits appended to the original data to detect or correct errors. The core idea is to add extra information to verify whether the data has been corrupted after storage, and even to correct errors.

[0029] Digital integrated circuit design and System-on-a-Chip (SoC) design both require memory, such as Static Random-Access Memory (SRAM), as the storage medium. With increasing storage demands, memory capacity is growing. However, some memory types, such as SRAM, can experience errors in individual bits during use due to signal interference or unreliable performance. Errors in the retrieved data can render the data unusable or even render the entire computer system unusable. Therefore, it is crucial to detect and correct errors in memory promptly.

[0030] While some related technologies can use check codes to detect and correct errors in the data when reading data, i.e., perform error management, these solutions either verify the data of the entire RAM chip using check codes or do not verify the data of the entire RAM chip at all. This lack of fine-grained and on-demand processing results in a low degree of flexibility in data verification when reading data from memory.

[0031] This application provides a data reading method, a data writing method, and a memory, which can improve the flexibility of data verification during data reading. The following describes exemplary applications of the memory provided in this application. The memory provided in this application can be used as an independent memory IP core, which can be integrated as a key module into various systems-on-a-chip (SoC) or application-specific integrated circuits (ASICs). For example, it can be used as the final-level cache inside a central processing unit (CPU) or graphics processing unit (GPU), or as a cache for embedded flash memory or main static memory integrated into an industrial-grade microcontroller unit (MCU). The memory can be applied to various electronic devices, such as laptops, tablets, desktop computers, set-top boxes, smartphones, smart speakers, smartwatches, smart TVs, in-vehicle terminals, and other types of terminals, or it can be implemented as a server.

[0032] See Figure 1 , Figure 1This is a schematic diagram of the architecture of the data reading system for a memory provided in the embodiments of this application. In order to support a data reading application for a memory, in the data reading system 100, the terminal 400 is connected to the server 200 through the network 300. The server 200 is equipped with a memory. The network 300 can be a wide area network or a local area network, or a combination of the two.

[0033] In a scenario where data processing is performed using a machine learning model, terminal 400 sends a service request to server 200. The communication device in server 200 receives the service request, and the processor sends a data read instruction to the memory. The memory reads the corresponding data and outputs it to the processor. The processor processes the read data to obtain the service result and sends the result back to terminal 400. Terminal 400 receives the service result and displays it on the human-computer interaction interface 410.

[0034] The data reading method of the memory provided in this application embodiment will be described below with reference to exemplary applications and implementations of the memory provided in this application embodiment.

[0035] See Figure 2 , Figure 2 This is a flowchart illustrating the data reading method for a memory provided in an embodiment of this application. Figure 1 , will combine Figure 2 The steps shown are explained.

[0036] It should be noted that the memory includes RAM chips, or Random Access Memory chips. A RAM chip comprises multiple storage areas, each of which can be considered a part of the RAM chip. These storage areas are obtained by dividing the RAM chip into address ranges, thus each storage area can be viewed as a logical address range. The memory may also include registers, which are used to store information needed during data retrieval.

[0037] Step 101: In response to the processor's data read instruction, based on multiple address ranges of multiple memory regions, determine the first target region where the first address in the data read instruction is located from the multiple memory regions.

[0038] When a processor processes data, it first needs to read the data to be processed. Therefore, the processor generates a data read instruction, specifying the address of the data to be read (i.e., the first address where the data is located), and then sends the data read instruction to the memory. The memory parses the data read instruction to obtain the first address. Next, the memory obtains the address range of each memory region, and then, based on the address range of each memory region and the first address specified in the data read instruction, determines the memory region containing the first address from among multiple memory regions, and uses this memory region as the first target region.

[0039] It should be noted that, in the embodiments of this application, the address ranges of multiple storage regions can be stored in registers inside the memory. Thus, the memory can obtain the address range of each storage region from the registers, and then compare the first address with the start and end addresses of the address range to determine whether the read address falls within the address range.

[0040] For example, suppose the RAM chip has three storage regions with address ranges of [0x0000_0000, 0x0000_1FFF], [0x0000_2000, 0x0000_DFFF], and [0x0000_E000, 0x0000_FFFF], and the first address is 0x0000_1234. The memory compares these three address ranges with the first address and determines that the first address falls within [0x0000_0000, 0x0000_1FFF]. Therefore, the storage region corresponding to [0x0000_0000, 0x0000_1FFF] will be used as the first target region.

[0041] Step 102: Query the value of the first status flag bit of the first target area.

[0042] After determining the first target region where the first address is located, the memory will retrieve the status flag values ​​for the first target region from the status flag values ​​of all memory regions to obtain the first status flag value. This first status flag value is used to determine whether the data verification function is enabled in the first target region. In other words, the value of the first status flag value indicates whether the data verification function is enabled in the first target region.

[0043] It should be noted that the status flag is a binary bit in a register stored in memory. Its value is used to indicate whether the data verification function is enabled in the corresponding storage area. Here, each storage area will have its corresponding status flag, so there will be multiple status flags corresponding to multiple storage areas in the register, thus indicating whether the data verification function is enabled in multiple storage areas.

[0044] In other words, in this embodiment of the application, the RAM chip can be divided into multiple storage areas by the processor, and the activation of the data verification function in each storage area can be controlled separately. That is, some storage areas can enable the data verification function, while other storage areas do not enable the data verification function. The change of the activation status of the data verification function can be controlled by the processor by modifying the value of the corresponding status flag bit.

[0045] In some embodiments of this application, multiple storage regions can be partitioned by the processor from the RAM chip, and multiple address ranges of the multiple storage regions can be generated by the processor. The processor can write the multiple address ranges of the multiple storage regions into a register so that the memory can subsequently query the address range of each storage region from the register. Simultaneously, the activation of the data verification function for each storage region can be controlled by the processor. Therefore, the value of the first status flag bit of each storage region is generated by the processor, and the processor can write the value of the first status flag bit into a register so that the memory can retrieve the value of the first status flag bit of a certain storage region from the register during data reading.

[0046] It should be noted that the data verification function refers to the function of verifying the stored data during the data reading process to detect whether there are errors in the data and to handle the errors accordingly. For example, it can detect errors in the data in the RAM chip of the memory, then automatically correct single-bit errors and report double-bit errors, etc.

[0047] In this embodiment of the application, the value of the first status flag bit of each storage area can be stored in the register inside the memory. Thus, the memory can directly query the value of the first status flag bit of the first target area from its internal register to determine whether the data verification function is enabled in the first target area.

[0048] It should be noted that, in this embodiment, a first preset value can be used to indicate that the data verification function is enabled. That is, when the value of the first status flag bit of the first target area is the first preset value, it indicates that the data verification function has been enabled for the first target area. A second preset value can be used to indicate that the data verification function is not enabled. That is, when the value of the first status flag bit of the first target area is the second preset value, it indicates that the data verification function is not enabled for the first target area. Here, the values ​​of the first preset value and the second preset value can be set according to actual conditions, for example, the first preset value can be set to 1 and the second preset value can be set to 0, etc.

[0049] Step 103: When the value of the first status flag indicates that the data verification function is enabled in the first target area, read the data from the first address and the data verification code.

[0050] When the memory determines that the data verification function is enabled in the first target area based on the value of the first status flag bit, the first address not only stores the data written by the processor in the past, but also stores the checksum generated for that data. Therefore, when the memory queries the value of the first status flag bit and determines that the data verification function is enabled in the first target area, it will read all the data at the first address. This data includes the data and the data's checksum. The checksum is used to verify data errors and is a redundant bit appended to the original data for error correction. Thus, in this embodiment, by adding some additional information, namely the checksum, data verification can be performed, i.e., error detection or even error correction.

[0051] It should be noted that the memory can automatically separate the data and checksum at the first address according to a fixed mapping rule. This mapping rule defines the positions of the data bits and checksum bits in the physical storage space of the RAM chip, and can be determined by the design engineer during the hardware design phase of the RAM chip.

[0052] It should also be noted that since some RAM chips have an even number of interface bits, while the sum of the number of data bits and check bits is odd, the information stored in the first address not only includes the data itself and the data check bit, but also includes redundant bits. In this case, when the memory reads data from the first address, it will read the data, the data check bit, and the redundant bits at the same time, and then discard the redundant bits, and only process the data and its check bit.

[0053] For example, if the data bit width is 128 bits, the check code bit width is 9 bits, and the RAM chip port bit width is 138 bits, then the first address will simultaneously store 128 bits of data, 9 bits of check code, and 1 bit of redundancy.

[0054] Step 104: Verify the data using the verification code, obtain the verification result, and output the data to the processor based on the verification result.

[0055] After receiving the checksum and data, the memory performs data verification, i.e., retrieval or error correction, and obtains the verification result, i.e. whether there is an error in the data and the type of error. Then, based on the verification result, the memory performs subsequent processing on the data, such as real-time error correction for single-bit errors or triggering error flags for double-bit errors, and finally outputs the corresponding data to the processor.

[0056] See Figure 3 , Figure 3 This is a flowchart illustrating the data reading method for a memory provided in an embodiment of this application. Figure 2In some embodiments of this application, Figure 2 Step 104, which involves verifying the data using a checksum to obtain the verification result, can be achieved through the following processing: Step 1041: Determine the syndrome based on the data and check code.

[0057] It should be noted that the synthesis is a key intermediate result in the decoding process of error correction codes. The synthesis is a binary vector composed of a set of bits. The synthesis can determine whether there is an error in the data being read, and if so, where the error occurs.

[0058] In some embodiments of this application, the memory can use a check equation defined when generating the check code to regenerate a new check code for the data. The newly generated check code is then compared with the original check code read from the RAM chip, for example, through a bitwise XOR operation. The difference between the two, such as the result of the bitwise XOR operation, is then determined as the syndrome. The resulting syndrome is a binary vector that can be converted into a decimal value, which is the value of the syndrome.

[0059] For example, suppose the data has a bit width of 8, represented as D0 to D7, and the check code has a bit width of 5, represented as P0 to P5. If the check equation used when generating the check code generates new check codes P0', P1', P2', P3', and P4' for the data, and then performs an XOR operation on P0 and P0' to get S0, performs an XOR operation on P1 and P1' to get S1, ... performs an XOR operation on P4 and P4' to get S4, then the syndrome can be expressed as [S0S1S2S3S4], for example

[00000] .

[0060] It should be noted that the check equation defined when the check code is generated can be a check equation in a commonly used encoding method. For example, the check equation in the embodiments of this application can be a check equation of Hamming code, or a check equation of extended Hamming code, etc.

[0061] In some other embodiments of this application, the memory can also combine data and check code to directly calculate the syndrome. That is, the memory performs an XOR operation on the bits (including data bits and check code bits) involved in the check equation, and then uses the binary vector generated by the XOR operation of all bits as the syndrome, and then uses the decimal value corresponding to the binary vector as the value of the syndrome.

[0062] For example, if the check equation is P0=D0^D1^D3^D5, then the corresponding bit of the syndrome can be represented as S0=D0'^D1'^D3'^D5'^P0. Thus, the syndrome [S0S1S2S3S4] can also be obtained, for example

[00000] .

[0063] Step 1042: Based on the synergistic expression, verify the errors in the data and obtain the verification results.

[0064] After determining the syndrome, the memory checks if the syndrome's value is 0 to determine if an error exists in the data. If the syndrome's value is 0, the memory determines that no error exists in the data, meaning the data is correct. If the syndrome's value is not 0, the memory can also determine the number of errors, i.e., the number of erroneous bits in the data, based on the syndrome. In this way, the memory can complete data error checking, thereby determining whether an error exists in the data and, if so, the type of error.

[0065] When the value of the syndrome is not 0, the memory can calculate the number of 1s in the syndrome and determine the error type of the data based on this parity. Here, if there is an odd number of 1s in the syndrome, a single-bit error is confirmed in the data; if there is an even number of 1s in the syndrome, a double-bit error is confirmed in the data.

[0066] When the value of the syndrome is not zero, the memory can also determine the error type in the data—whether it is a single-bit error or a double-bit error—by looking up a table that records all possible syndromes, their corresponding error types, and error locations. The values ​​of all possible syndromes in this table can be pre-calculated by human experts.

[0067] For example, if the data bit width is 8, represented as D0 to D7, and the check code bit width is 5, represented as P0 to P4, then in the table above, the symptom 00000 corresponds to no error, the symptom 00111 corresponds to a single-bit error in D0, the symptom 01011 corresponds to a single-bit error in D1, and so on. The symptom 10100 represents a double-bit error in D0 and D7, and the symptom 11011 represents another double-bit error. When the memory determines the symptom and the value of the symptom is not 0, it can query the data table to determine the error type and error location of the data, thereby completing the data error verification and obtaining the verification result.

[0068] It is understood that in the embodiments of this application, the memory can first determine the value of the syndrome based on the data and the check code, and then quickly perform error verification based on the value of the syndrome. Therefore, error verification can be completed without comparing the read data with the original data written, which can improve the efficiency of error verification.

[0069] In some embodiments of this application, Figure 2 In step 104, the data output to the processor based on the verification result can be achieved through the following processing: when the verification result indicates that there is a single-bit error in the data, the single-bit error in the data is corrected and the corrected data is output to the processor; the values ​​of the first error flag bit and the second error flag bit are both set to a first preset value indicating the existence of an error, wherein the first error flag bit is used to indicate whether there is an error in the data and the second error flag bit is used to indicate whether there is a single-bit error in the data.

[0070] After determining the verification result, the memory will perform subsequent processing on the data based on the information represented by the verification result. When the verification result indicates that there is a single-bit error in the data, the memory will immediately perform error correction processing to obtain the corrected data, and then output the corrected data to the processor. At the same time, the memory also needs to inform the processor that a single-bit error occurred in the data it read, and that the single-bit error has been corrected.

[0071] In this embodiment, the memory registers are further provided with error flags to indicate data errors. The memory can inform the processor whether an error has occurred and the type of error by setting the values ​​of these flags. In this embodiment, the registers may be provided with a first error flag and a second error flag. The first error flag indicates whether an error exists in the data, and the second error flag indicates whether a single-bit error exists in the data. A single-bit error refers to an error in which only one bit in a binary data block flips from its original value to its opposite value. For example, if a bit was originally written with a value of 0, and it flips to 1, then a single-bit error has occurred in the data.

[0072] It should be noted that in this embodiment of the application, an error can be indicated by a first preset value. Therefore, the memory can set the value of the first error flag bit in the register to the first preset value and the value of the second error flag bit in the register to the first preset value. When the processor finds that the value of the first error flag bit in the register is the first preset value and the value of the second error flag bit is the second preset value, it will determine that there is a single-bit error in the data read from the memory and that the single-bit error has been automatically corrected by the memory.

[0073] It should also be noted that when the memory corrects a single-bit error, it first locates the data bit with the error based on the specific decimal value of the symptom. Then, the memory generates a flip signal for that data bit to flip the original data bit, for example, flipping 1 to 0 and 0 to 1. The data with the completed single-bit flip is then used as the data after error correction.

[0074] For example, the data bit width is 8, represented as D0 to D7, and the check code bit width is 5, represented as P0 to P4. If the original data to be stored at the first address is expected to be 0101_0101 and the check code is 10101, if the D0 bit is flipped, causing the read data to become 0101_0100 while the check code remains 10101, the memory can calculate the accompanying expression 00111 (decimal value 7), whose value is not 0 and contains an odd number of 1s, thus determining that a single-bit error has occurred. At this time, the memory will flip the value of D0, that is, flip 0 to 1, thereby obtaining the error-corrected data 0101_0101. The error-corrected data is output to the processor, and the values ​​of the first error flag bit and the second error flag bit in the register are both set to 1, that is, the first preset value, to realize error reporting.

[0075] It is understood that in the embodiments of this application, when the memory determines that there is a single-bit error in the data, it will immediately correct the data, thereby enabling the processor to avoid system crashes caused by minor errors, significantly improving the memory's resistance to transient errors, and thus improving the reliability of the memory.

[0076] In some embodiments of this application, Figure 2 In step 104, the data output to the processor based on the verification result can be achieved through the following processing: when the verification result indicates that there is a double-bit error in the data, the data is output to the processor; the value of the first error flag bit and the value of the third error indicator bit are both set to a first preset value indicating the existence of an error, wherein the third error flag bit is used to indicate whether there is a double-bit error in the data.

[0077] Since a two-bit error may exceed the memory's error correction capabilities, if the verification result indicates the presence of a two-bit error in the data, the memory will not perform error correction but will directly output the data to the processor. Simultaneously, the memory will inform the processor of the presence of a two-bit error by modifying the values ​​of the first and third error flag bits in the register. The third error flag bit is used to indicate whether a two-bit error exists in the data.

[0078] It should be noted that a double-bit error refers to an error in binary data where two different bits simultaneously flip from their original values ​​to their opposite values. Compared to single-bit errors, double-bit errors have a lower probability of occurrence, but the hardware complexity, area, power consumption, and latency required for error correction are much higher. Therefore, in this embodiment, error correction can be performed only on single-bit errors.

[0079] For example, if the expected original data stored at the first address is 0101_0101 and the checksum is 10101, if D0 and D1 are simultaneously flipped, the read data might become 0101_0110, while the checksum remains 10101. Assuming the memory calculates the syntactic expression as 01100, which is non-zero and contains an even number of 1s, it is confirmed as a double-bit error. The memory will not correct this error but will directly output the read data, 0101_0110, to the processor. Simultaneously, the memory will set the values ​​of the first and third error flag bits to 1, i.e., the first preset value. When the processor finds that the values ​​of these two error flag bits are 1 in the register, it will determine that a double-bit error exists in the data output by the memory.

[0080] It is understood that in the embodiments of this application, when there is a serious double-bit error in the data, the memory can detect the double-bit error in time and report it to the processor even if it does not correct it, so that the processor can handle the error in time through a higher level of fault tolerance technology.

[0081] In some embodiments of this application, Figure 2 In step 104, based on the verification result, data is output to the processor. This can also be achieved through the following processing: when the verification result indicates that there is no error in the data, data is returned to the processor; the values ​​of the first error indicator bit, the second error indicator bit, and the third error indicator bit are all set to the second preset value indicating that there is no error.

[0082] If the verification result indicates that there are no errors in the data, the memory will directly output the data to the processor, and at the same time set the values ​​of all error flag bits in the register to the second preset value indicating that there are no errors, such as 0, so that the processor can determine that there are no errors in the current data by querying the values ​​of the error flag bits in the register.

[0083] It is understood that in this embodiment of the application, when the memory determines that there are no errors in the data, it will directly output the data and set all error flag bits to a second preset value indicating that the data does not exist, so as to inform the processor that there are no errors in the current data.

[0084] Understandably, compared to related technologies that either verify data across the entire RAM chip using checksums or do not verify data at all, resulting in low flexibility in data verification when reading data from the memory, this embodiment divides the RAM chip into multiple storage areas. The data verification function can be independently enabled or disabled for each storage area based on the value of its corresponding status flag. During data reading, the memory first determines the first target area from among the multiple storage areas based on the first address specified by the data read instruction. Then, by querying the value of the first status flag of the first target area, it determines whether the data verification function is enabled in the first target area. Only when the data verification function is enabled is the data verified using the checksum read from the first address, and then the data is output to the processor based on the verification result. This allows for on-demand decision-making regarding whether to enable data verification, ensuring data reliability while improving the flexibility of data verification during data reading.

[0085] based on Figure 2 See Figure 4 , Figure 4 This is a flowchart illustrating the data reading method for a memory provided in an embodiment of this application. Figure 3 In some embodiments of this application, in Figure 2 Following step 102, i.e., after querying the value of the first status flag bit of the first target region, the method further includes the following processing: Step 105: When the value of the first status flag indicates that data verification is not enabled in the first target area, read the data from the first address and output the data to the processor.

[0086] The memory queries the value of the first status flag bit from its registers, and if it determines that the value of the first status flag bit indicates that data verification is not enabled in the first target area, it will directly read the data from the first address and output the read data to the processor.

[0087] It should be noted that, in order to facilitate the uniformity of the data writing process, the memory will also synchronously write a check code to the storage area where data verification is not enabled. Thus, in this embodiment, the first address of the memory can simultaneously store the data check code. When the memory reads data from the first address, it will also read the check code, but the memory will not use the check code for any processing.

[0088] It is understood that in this embodiment of the application, when the data verification function is not enabled in the first target area, the memory will not process the data read from the first address and will directly output it to the processor. In this way, it is possible to flexibly configure whether to enable the data verification function for different storage areas, thereby improving the flexibility of data verification when reading data.

[0089] The data writing method for the memory provided in this application will be described below with reference to exemplary applications and implementations of the memory provided in the embodiments of this application.

[0090] See Figure 5 , Figure 5 This is a flowchart illustrating the data writing method for a memory provided in an embodiment of this application. Figure 1 , will combine Figure 5 The steps shown are explained.

[0091] It should be noted that the memory includes RAM chips, or Random Access Memory chips. A RAM chip comprises multiple storage areas, each of which can be considered a part of the RAM chip. These storage areas are obtained by dividing the RAM chip into address ranges, thus each storage area can be viewed as a logical address range. The memory may also include registers, which are used to store information needed for data writing.

[0092] Step 201: In response to the processor's data write instruction, based on multiple address ranges in multiple memory regions, determine the second target region where the second address in the data write instruction is located from the multiple memory regions.

[0093] When the processor needs to write data to memory, it first generates a data write instruction, specifying the address of the data to be written (i.e., the second address) in the instruction, and then sends the instruction to the memory. The memory parses the instruction to obtain the second address and acquires the address range of each memory region. It then compares the second address with the address range of each memory region to determine the memory region containing the second address and uses that region as the second target region.

[0094] It should be noted that, in this embodiment, the address ranges of multiple storage regions can be stored in registers within the memory, so that the memory can obtain the address range of each storage region from the registers. The memory can compare the second address with the address range, the start address, and the end address to determine whether the read address falls within the address range.

[0095] Step 202: Query the value of the second status flag bit of the second target area.

[0096] After determining the second target region where the second address is located, the memory will query the status flag values ​​of all memory regions for the second target region to obtain the value of the second status flag. This value is used to determine whether error correction is enabled in the second target region. In other words, the value of the second status flag indicates whether data verification is enabled in the second target region.

[0097] It should be noted that the status flag is a binary bit in a register stored in memory. Its value is used to indicate whether the data verification function is enabled in the corresponding storage area. Here, each storage area will have its corresponding status flag, so there will be multiple status flags corresponding to multiple storage areas in the register, thus indicating whether the data verification function is enabled in multiple storage areas.

[0098] In other words, in this embodiment of the application, the RAM chip can be divided into multiple storage areas by the processor, and the activation of the data verification function in each storage area can be controlled separately. That is, some storage areas can enable the data verification function, while other storage areas do not enable the data verification function. The change of the activation status of the data verification function can be controlled by the processor by modifying the value of the corresponding status flag bit.

[0099] Step 203: When the value of the second status flag indicates that the data verification function is enabled in the second target area, a verification code is generated for the data in the data writing instruction.

[0100] When the memory determines that the data verification function is enabled in the second target area, it will generate a corresponding check code for the data using the check equation defined in a commonly used encoding method. This encoding method can be Hamming code or extended Hamming code.

[0101] Step 204: Write the data and verification code at the second address.

[0102] After receiving the checksum, the memory writes the data and checksum into the first address. It should be noted that if the memory's input interface has an even bit width, but the sum of the data bit width and the checksum bit width is odd, the memory will also add redundant bits to the data and checksum, and write the data, checksum, and redundant bits together into the second address.

[0103] It is understandable that, compared to related technologies, which either perform data verification on the entire RAM chip using a checksum or do not perform data verification on the entire RAM chip at all, resulting in low flexibility in data verification when reading data from the memory, this embodiment divides the RAM chip into multiple storage areas. The data verification function can be independently enabled or disabled for each storage area based on the value of its corresponding status flag. When writing data, the second target area containing the second address specified by the data write instruction is first determined from the multiple storage areas. Only when the data verification function is enabled in the second target area will a checksum be generated for the data carried in the data write instruction and written to the second address. This allows for subsequent data verification based on the checksum. Thus, it is possible to decide whether to enable data verification as needed, ensuring data reliability while improving the flexibility of data verification when reading data.

[0104] based on Figure 5 See Figure 6 , Figure 6 This is a flowchart illustrating the data writing method for a memory provided in an embodiment of this application. Figure 2 In some embodiments of this application, in Figure 5 Following step 202, i.e., after querying the value of the second status flag bit of the second target region, the scheme may further include the following processing: Step 205: When the value of the second status flag indicates that the data verification function is not enabled in the second target area, write the data to the second address.

[0105] The memory queries the value of the second status flag bit from the register. If it determines that the second target area does not have the data verification function enabled, it will directly write the data in the data write instruction into the second address, thereby completing the data write.

[0106] It should be noted that when the memory contains data bits for storing checksums (which may be determined during the memory design phase), the memory can generate a certain amount of redundancy for these data bits, for example, setting them all to 0, and then write these data bits and the generated redundancy together to the second address. Of course, the memory can generate checksums for the data by default and write them to the second address, but this checksum may not be used during subsequent data readings.

[0107] It is understood that in the embodiments of this application, the memory can directly write data into the second address when it is determined that the data verification function is not enabled in the second target area, thereby enabling data verification to be performed in different areas according to needs and improving the flexibility of data verification.

[0108] The following will describe an exemplary application of the embodiments of this application in a real-world application scenario.

[0109] The memory in this application embodiment is used to store data during the artificial intelligence operation. When the processor performs artificial intelligence operation, it needs to write data to the static random-access memory (SRAM) and read data from the SRAM (called RAM chip). The data reading method and data writing method of this application embodiment are also applicable in other scenarios, such as industrial automation scenarios, smart home scenarios, etc.

[0110] In related technologies, data is directly written into SRAM. However, if an error occurs in a single bit of the SRAM, the system will not function properly.

[0111] In this embodiment, the data to be written to SRAM is calculated and a corresponding error correction code (called a check code) is added. The data and the error correction code are then written together into the SRAM. During reading, the actual data and the corresponding error correction code are retrieved. Error correction and detection are achieved through the error correction code. Simultaneously, the SRAM can be pre-divided into multiple regions (called storage regions) as needed, and regions where error correction technology (called data verification function) can be applied can be specified. If a 1-bit error exists in the region where error correction technology is applied (called the first target region and the second target region) during data writing or reading, the 1-bit error (called a single-bit error) can be corrected. If a 2-bit error exists, the 2-bit error (called a double-bit error) can be reported to the processor. If the data is not written or read in the region where error correction technology is applied, normal read / write operations are performed.

[0112] In other words, firstly, in the embodiments of this application, error correction codes are added when writing data into the SRAM. Refer to Table 1, which provides the relationship between the data width, the error correction code width, and the actual width of the SRAM data. If the data being written is 128 bits wide, 9 bits of error correction code can be added, resulting in a total of 137 bits of information, which are then written into the SRAM. When reading data from the SRAM, all 137 bits of information are read out; if a 1-bit error exists, it will be directly corrected.

[0113] Table 1

[0114] Figure 7This is a schematic diagram illustrating the data writing and reading processes provided in this application embodiment. The SRAM controller (referred to as memory) 7-1 includes an SRAM 7-11 (referred to as RAM chip), an error correction control module 7-12, and a register 7-13. The error correction control module 7-12 includes an encoder 7-121, a decoder 7-122, and a region judgment unit 7-123. If the bit width of the written data is 128 bits, represented as [127:0], during the data writing process, the encoder 7-121 first adds 9 bits of error correction code and 1 bit of redundancy to the written data (since the number of ports of the SRAM is an even number of bits, 1 bit of redundancy needs to be added). Finally, 138 bits of information are written to the SRAM, represented as [137:0]. During the reading process, the region determination unit 7-123 reads the address of each region from register 7-123. Based on the address of the data to be read (called the first address) and the address range of each region, it determines the region where the address is located (called the first target region). Then, it queries the error correction technology enable status of the region from register 7-123. If it is enabled, the decoder 7-122 uses 9 bits of error correction code from the 138 bits read from SRAM to perform error correction and error detection on the 128 bits of data and outputs it to the processor.

[0115] In this embodiment, error correction codes are appended to the data and transmitted together, thus widening the data bit width. Figure 8 This is a schematic diagram of data bits during data transmission according to an embodiment of this application. See also... Figure 8 During transmission, n bits of data, i.e. D0 to Dn-1, are concatenated with k bits of error correction code, i.e. P0 to Pk-1, resulting in a wider bit width.

[0116] The error correction code is generated by calculating n bits of data. For example, taking 8 bits of data, a 5-bit error correction code can be calculated. The calculation process for each bit is shown in equations (1) to (5): P0 = ~(D0^D1^D3^D5)(1) P1 = ~(D0^D1^D2^D4^D6)(2) P2 = ~(D0^D2^D3^D4^D7)(3) P3 = ~(D1^D2^D5^D6^D7)(4) P4 = ~(D3^D4^D5^D6^D7)(5) Therefore, the data is transmitted in the following format: Figure 9 As shown, Figure 9The diagram illustrates the transmission format of 8-bit data and 5-bit error correction code provided in this application embodiment. As can be seen, during transmission, the 8-bit data, i.e., D0 to D7, and the 5-bit error correction code, i.e., P0 to P4, are concatenated together for transmission, resulting in a bit width of 13.

[0117] When reading data, the decoder directly reads 13 bits of information from the SRAM, where the first 8 bits are data and the last 5 bits are error correction codes. Based on the 13 bits of information, the decoder generates the symptom dec_parity[4:0], as shown in equations (6) to (10): dec_parity[0]= ~(D0^D1^D3^D5^D8) (6) dec_parity[1]= ~(D0^D1^D2^D4^D6^D9) (7) dec_parity[2]= ~(D0^D2^D3^D4^D7^D10)(8) dec_parity[3]= ~(D1^D2^D5^D6^D7^D11) (9) dec_parity[4]= ~(D3^D4^D5^D6^D7^D12) (10) Then, based on the accompaniment dec_parity[4:0], the judgments of equations (11) to (13) are performed to determine whether an error has occurred in the data and the type of error.

[0118] error = dec_parity[4:0] !=0 (11) single_err = (dec_parity[4:0] !=0)&&(^dec_parity[4:0]) (12) double_err = (dec_parity[4:0] !=0)&&(~^dec_parity[4:0]) (13) Here, error represents an error, single_err is a 1-bit error, and double_err is a 2-bit error.

[0119] If a 1-bit error occurs, the specific bit within the 8-bit data can be determined from the decimal value of the accompanying factor. For example, a decimal value of 7 indicates an error in bit 0, 11 indicates an error in bit 1, 14 indicates an error in bit 2, 21 indicates an error in bit 3, 22 indicates an error in bit 4, 25 indicates an error in bit 5, 26 indicates an error in bit 6, and 28 indicates an error in bit 7.

[0120] Before data writing and reading, the processor can divide the SRAM into multiple regions and specify which regions use error correction technology and which regions do not.

[0121] For example, Figure 10 This is a schematic diagram of SRAM region partitioning provided in an embodiment of this application. Assume the processor divides the SRAM into 8 regions, namely regions 0 to 7. The processor specifies that regions 0, 3, and 6 use error correction technology, while other regions do not.

[0122] Table 2 is a schematic diagram of the main ports in the embodiments of this application.

[0123] Table 2

[0124] Table 3 is an example of a register in an embodiment of this application, with SRAM divided into 8 regions as an example.

[0125] Table 3

[0126] The following example illustrates the specific implementation of this application's embodiments using a 128-bit SRAM.

[0127] In this embodiment, the SRAM with a depth of 16M (0x0~0x00ff_ffff) is divided into 8 regions, and their addresses are configured as follows: sec_adr0_s = 0x0000_0000, sec_adr0_p = 0x001f_ffff; sec_adr1_s = 0x0020_0000, sec_adr1_p = 0x003f_ffff; sec_adr2_s = 0x0040_0000, sec_adr2_p = 0x005f_ffff; sec_adr3_s = 0x0060_0000, sec_adr3_p = 0x007f_ffff; sec_adr4_s = 0x0080_0000, sec_adr4_p = 0x009f_ffff; sec_adr5_s = 0x00a0_0000, sec_adr5_p = 0x00bf_ffff; sec_adr6_s = 0x00c0_0000, sec_adr6_p = 0x00df_ffff; sec_adr7_s = 0x00e0_0000, sec_adr7_p = 0x00ff_ffff.

[0128] Processor 0#, 3#, and 6# are configured to use error correction technology, while other areas are not. The configuration is as follows: sec_ctrl.sec_addr_ecc_en=8'b0100_1001, / / bit0 / 3 / 6 enable.

[0129] Set the SRAM error correction technology enable flag to 1: sec_ctrl.sec_ecc_en=1.

[0130] When writing data to SRAM, error correction codes can be generated and written for each piece of data to be written.

[0131] When reading data from SRAM, there are three scenarios: a) Normal read operation, no error, i.e., read reg sec_ctrl.sec_ecc_err = 0; b) During a normal read operation, there was a 1-bit error, but it has been corrected, i.e., read reg sec_ctrl.sec_ecc_err = 1, read reg sec_ctrl.sec_sbit_err = 1, and read reg sec_ctrl.sec_dbit_err = 0.

[0132] c) There is a problem with the read operation, with 2 bits of error, namely read reg sec_ctrl.sec_ecc_err = 1, readreg sec_ctrl.sec_sbit_err = 0, and read reg sec_ctrl.sec_dbit_err = 1.

[0133] Finally, if there are errors in the read data, after error handling, set the clear flags, i.e., sec_ctrl.sec_ecc_err_clr = 1, sec_ctrl.sec_sbit_err_clr = 1 and sec_ctrl.sec_dbit_err_clr = 1.

[0134] This not only enables data error correction and detection, but also allows for flexible configuration of areas where error correction technology can be used, thus improving the flexibility of data verification.

[0135] The memory provided in the embodiments of this application will be described below, taking the memory built into the server as an example. Figure 11 This is a schematic diagram of the memory structure provided in the embodiments of this application. Figure 1 See Figure 11 The memory 210 includes: a region determination unit 211, a decoder 212, a RAM chip 213, and a register 214. The RAM chip 213 includes multiple storage regions. The region determination unit 211 is used to respond to the processor's data read instruction, and determine the first target region where the first address in the data read instruction is located from the multiple memory regions based on the multiple address ranges of the multiple memory regions stored in the register 214; and query the value of the first status flag bit of the first target region from the register 214, the value of the first status flag bit indicating whether the data verification function is enabled in the first target region; Decoder 212 is used to read data from the first address and the data check code when the value of the first status flag bit indicates that the data verification function is enabled in the first target area; and to verify the data through the check code, obtain the verification result, and output the data to the processor based on the verification result. RAM chip 213 is used to store data and checksums; Register 214 is used to store multiple address ranges of multiple storage areas, as well as the value of the first status flag bit of the first target area.

[0136] It should be noted that the region determination unit 211 mentioned above can be implemented using a hardware circuit structure, such as an Application-Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA) circuit; the RAM chip 213 can be implemented as an SRAM chip or a DRAM chip; the register 214 can be implemented as a latch or a D flip-flop; and the decoder 212 can be implemented as an ASIC circuit or an FPGA circuit.

[0137] In some embodiments, the decoder 212 is further configured to determine a symptom based on the data and the checksum; and to verify errors in the data based on the symptom to obtain the verification result.

[0138] In some embodiments, register 214 also stores the value of the first error flag bit and the value of the second error flag bit; Decoder 212 is also configured to correct the single-bit error in the data when the verification result indicates that the data has a single-bit error, and output the corrected data to the processor; and to set the value of the first error flag bit and the value of the second error flag bit in register 214 to a first preset value indicating the presence of an error, wherein the first error flag bit is used to indicate whether the data has an error, and the second error flag bit is used to indicate whether the data has a single-bit error.

[0139] In some embodiments, register 214 also stores the values ​​of the first error flag bit and the third error flag bit; Decoder 212 is also configured to output the data to the processor when the verification result indicates that the data has a double-bit error; and to set the value of the first error flag bit and the value of the third error indicator bit in register 214 to a first preset value indicating the presence of an error, wherein the third error flag bit is used to indicate whether the data has a double-bit error.

[0140] In some embodiments, register 214 also stores the values ​​of the first error flag bit, the second error flag bit, and the third error flag bit; Decoder 212 is also configured to output the data to the processor when the verification result indicates that the data does not contain any errors; and to set the values ​​of the first error indicator bit, the second error indicator bit, and the third error indicator bit in register 214 to a second preset value indicating that no errors exist.

[0141] In some embodiments, the decoder 212 is further configured to read the data from the first address and output the data to the processor when the value of the first status flag bit indicates that the data verification is not enabled in the first target area.

[0142] In some embodiments, the plurality of storage regions are divided by the processor from the RAM chip 213, and the plurality of address ranges of the plurality of storage regions are generated by the processor; and, The value of the first status flag bit in register 214 is generated by the processor.

[0143] Figure 12 This is a schematic diagram of the memory structure provided in the embodiments of this application. Figure 2 See Figure 12 The memory 210 includes: a region determination unit 211, an encoder 215, a RAM chip 213 and a register 214, wherein the RAM chip 213 includes multiple storage regions; The region determination unit 211 is configured to, in response to a data write instruction from the processor, determine a second target region where the second address in the data write instruction is located from the plurality of memory regions based on a plurality of address ranges of the plurality of memory regions stored in register 214; and query the value of the second status flag bit of the second target region from register 214, wherein the value of the second status flag bit indicates whether the data verification function is enabled in the second target region. Encoder 215 is configured to generate a check code for the data in the data writing instruction when the value of the second status flag bit indicates that the data verification function is enabled in the second target area; and to write the data and the check code to the second address. RAM chip 213 is used to store data and checksums; Register 214 is used to store multiple address ranges of multiple memory regions, as well as the value of the second status flag bit of the second target region.

[0144] It should be noted that the region determination unit 211 mentioned above can be implemented using a hardware circuit structure, such as an Application-Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA) circuit; the RAM chip 213 can be implemented as an SRAM chip or a DRAM chip; the register 214 can be implemented as a latch or a D flip-flop; and the encoder 215 can be implemented as an ASIC circuit or an FPGA circuit.

[0145] In some embodiments, encoder 215 is further configured to write the data to the second address when the value of the second status flag bit indicates that the data verification function is not enabled in the second target area.

[0146] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method for reading data from a memory, characterized in that, The memory includes a RAM chip, the RAM chip includes multiple storage areas, and the method includes: In response to a data read instruction from the processor, based on multiple address ranges of the multiple storage regions, a first target region containing the first address in the data read instruction is determined from the multiple storage regions; Query the value of the first status flag bit of the first target area. The value of the first status flag bit indicates whether the data verification function is enabled in the first target area. When the value of the first status flag indicates that the data verification function is enabled in the first target area, data is read from the first address, along with the verification code of the data. The data is verified using the verification code to obtain a verification result, and the data is output to the processor based on the verification result.

2. The method according to claim 1, characterized in that, The step of verifying the data using the verification code to obtain a verification result includes: Based on the data and the checksum, determine the syndrome; Based on the aforementioned syndrome, errors in the data are verified to obtain the verification result.

3. The method according to claim 1 or 2, characterized in that, The step of outputting data to the processor based on the verification result includes: When the verification result indicates that the data has a single-bit error, the single-bit error in the data is corrected, and the corrected data is output to the processor; The values ​​of the first error flag bit and the second error flag bit are both set to a first preset value that indicates the presence of an error. The first error flag bit is used to indicate whether there is an error in the data, and the second error flag bit is used to indicate whether there is a single-bit error in the data.

4. The method according to claim 1 or 2, characterized in that, The step of outputting data to the processor based on the verification result includes: When the verification result indicates that the data has a double-bit error, the data is output to the processor; The values ​​of the first error flag bit and the third error flag bit are both set to a first preset value that indicates the presence of an error, wherein the third error flag bit is used to indicate whether there is a double-bit error in the data.

5. The method according to claim 1 or 2, characterized in that, The step of outputting data to the processor based on the verification result includes: When the verification result indicates that the data is error-free, the data is output to the processor; The values ​​of the first error indicator bit, the second error indicator bit, and the third error indicator bit are all set to a second preset value that indicates that no error exists.

6. The method according to claim 1 or 2, characterized in that, After querying the value of the first status flag bit of the first target region, the method further includes: When the value of the first status flag indicates that the data verification is not enabled in the first target area, the data is read from the first address and the data is output to the processor.

7. The method according to claim 1, characterized in that, The plurality of storage regions are obtained by the processor dividing the RAM chip, and the plurality of address ranges of the plurality of storage regions are generated by the processor; The value of the first status flag bit is generated by the processor.

8. A memory, characterized in that, The memory includes: a region determination unit, a decoder, a RAM chip, and a register, wherein the RAM chip includes multiple storage regions; The region determination unit is configured to respond to a data read instruction from the processor, and based on multiple address ranges of multiple storage regions stored in the register, determine the first target region where the first address in the data read instruction is located from the multiple storage regions; and query the value of the first status flag bit of the first target region from the register, wherein the value of the first status flag bit indicates whether the data verification function is enabled in the first target region. The decoder is configured to read data from the first address and the checksum of the data when the value of the first status flag indicates that the data verification function is enabled in the first target area; and to verify the data using the checksum to obtain a verification result, and to output data to the processor based on the verification result. The RAM chip is used to store data and checksums; The register is used to store multiple address ranges of multiple storage regions, as well as the value of the first status flag bit of the first target region.

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