PCIe switch

Abstract

The embodiment of the application relates to the technical field of PCIe switchers, in particular to a PCIe switcher, which comprises a plurality of port modules, each of which comprises a message input unit, an arbitration unit and a message output unit. The message input unit of a local port module caches TLP messages to a first FIFO memory, performs ordered control on all TLP messages, and sends an arbitration request to the arbitration unit of a target port module if it is detected that the TLP messages meet the ordered control condition. If the TLP messages meet the arbitration condition, the arbitration unit sends the TLP messages to the message output unit of the target port module. The message output unit caches the TLP messages to a second FIFO memory, performs ordered control on all TLP messages, and outputs the TLP messages if the TLP messages meet the arbitration condition. Through the above structure and ordered control, the embodiment realizes safe transmission of TLP messages between any ports and guarantees that the ordered control requirement of the messages meets the PCIe protocol.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of PCIe switch, and particularly relate to a PCIe switch. BACKGROUND

[0002] As a core component of extended PCIe topology, PCIe switch plays a role similar to network switch, allowing multiple downstream devices to be connected to RC (Root Complex) through an upstream port, and can improve the expansion capability of the system. The data routing strategy of the traditional PCIe switch is usually based on DP (Downstream Port), that is, when a message enters a certain ingress port of the switch, the switch queries the internal routing table according to the routing information in the message header, and forwards it to the uniquely determined egress port. This static routing mechanism works well in a simple tree topology (such as a tree with root complex as root and device as leaf). In the switching model defined in the standard PCIe protocol, the communication path is usually limited in the vertical direction of "upstream-downstream" or "downstream-upstream". The PCIe protocol defines three types of key messages: P (posted) message, NP (non-posted) message and CPL (complete) message, wherein the P message does not need to be confirmed by the receiving party after sending, the NP message needs to be responded by the receiving party, and the CPL message is used to complete the processing of the NP message. The PCIe protocol strictly requires that the read-write operations and other key messages of the same address must be in order to prevent data consistency errors. In the simple upstream-downstream communication model, the traditional PCIe switch can still meet the ordering requirements through VC (Virtual Channel) arbitration and other mechanisms.

[0003] However, with the increasing demand for high-performance computing, supporting direct communication between any ports (especially peer ports) has become a key capability of PCIe switch. This brings a serious challenge to message ordering. When the PCIe switch enables multi-path load balancing or adopts parallel crossbar to improve the communication bandwidth between any ports, the messages belonging to the same ordered flow may be forwarded via different internal paths or queues. Since the delays and congestion of each path are independent, the later sent message may arrive at the target port before the early sent message, causing serious message disorder. SUMMARY

[0004] An object of embodiments of the present application is to provide a PCIe switch to solve the technical problem of message disorder between any ports in the related art.

[0005] In a first aspect, the embodiments of the present application provide a PCIe switch, comprising a plurality of port modules, each of the port modules comprising a packet input unit, an arbitration unit and a packet output unit;

[0006] The packet input unit of the local port module is configured to, in response to input of a first TLP packet, perform routing processing on the first TLP packet, and when the first TLP packet is successfully routed, buffer the first TLP packet on a first FIFO memory, perform in-order control processing on all TLP packets of the first FIFO memory, and when a second TLP packet of the first FIFO memory is detected to satisfy a preset in-order condition, send a packet arbitration request to the arbitration unit of a target port module; the arbitration unit of the target port module is configured to, in response to the packet arbitration request, when the second TLP packet is detected to satisfy a first preset arbitration condition, send the second TLP packet to the packet output unit of the target port module; and the packet output unit of the target port module is configured to buffer the second TLP packet on a second FIFO memory, perform in-order control processing on all TLP packets of the second FIFO memory, and when a third TLP packet is detected to satisfy a second preset arbitration condition, output the third TLP packet, the third TLP packet being a TLP packet in the second FIFO memory that satisfies the preset in-order condition.

[0007] Optionally, the packet input unit comprises a routing unit configured to: determine a target routing mode based on a packet type of the first TLP packet; perform routing detection on the first TLP packet based on the target routing mode to obtain routing detection information; in response to the routing detection information being routing success information, mark the first TLP packet as a routing success packet, the routing success information being used to indicate that the first TLP packet is successfully routed; in response to the routing detection information being routing failure information, mark the first TLP packet as a routing failure packet, the routing failure information being used to indicate that the first TLP packet is routed unsuccessfully; and buffer the first TLP packet on the first FIFO memory based on the packet type of the first TLP packet.

[0008] Optionally, the first FIFO memory comprises a P-packet buffer FIFO, an NP-packet buffer FIFO and a CPL-packet buffer FIFO, and the routing unit is configured to buffer the first TLP packet on the first FIFO memory based on a packet type of the first TLP packet, comprising: in response to the packet type of the first TLP packet being a P-packet type, buffering the first TLP packet on the P-packet buffer FIFO; in response to the packet type of the first TLP packet being an NP-packet type, buffering the first TLP packet on the NP-packet buffer FIFO; and in response to the packet type of the first TLP packet being a CPL-packet type, buffering the first TLP packet on the CPL-packet buffer FIFO.

[0009] Optionally, the NP-packet buffer FIFO is configured with a P-NP relationship FIFO table, and the packet input unit comprises a first order preserving unit, which is configured to: in response to a P-packet being written into the P-packet buffer FIFO and no NP-packet being written into the NP-packet buffer FIFO, write a first enqueuing identifier into a corresponding data bit of a P row of the P-NP relationship FIFO table and write a second enqueuing identifier into a corresponding data bit of an NP row of the P-NP relationship FIFO table; in response to no P-packet being written into the P-packet buffer FIFO and an NP-packet being written into the NP-packet buffer FIFO, write the second enqueuing identifier into the corresponding data bit of the P row of the P-NP relationship FIFO table and write the first enqueuing identifier into the corresponding data bit of the NP row of the P-NP relationship FIFO table; in response to a P-packet being written into the P-packet buffer FIFO and an NP-packet being written into the NP-packet buffer FIFO, write the first enqueuing identifier into the corresponding data bit of the P row and the corresponding data bit of the NP row of the P-NP relationship FIFO table; and in response to no P-packet being written into the P-packet buffer FIFO and no NP-packet being written into the NP-packet buffer FIFO, stop performing a write operation on the P-NP relationship FIFO table.

[0010] Optionally, the CPL packet buffer FIFO is configured with a P-CPL relationship FIFO table, and the packet input unit comprises a first order preserving unit, which is configured to: in response to a P packet being written into the P packet buffer FIFO and no CPL packet being written into the CPL packet buffer FIFO, write a first enqueuing identifier into a corresponding data bit of a P row of the P-CPL relationship FIFO table and write a second enqueuing identifier into a corresponding data bit of a CPL row of the P-CPL relationship FIFO table; in response to no P packet being written into the P packet buffer FIFO and a CPL packet being written into the CPL packet buffer FIFO, write the second enqueuing identifier into the corresponding data bit of the P row of the P-CPL relationship FIFO table and write the first enqueuing identifier into the corresponding data bit of the CPL row of the P-CPL relationship FIFO table; in response to a P packet being written into the P packet buffer FIFO and a CPL packet being written into the CPL packet buffer FIFO, write the first enqueuing identifier into the corresponding data bit of the P row and the corresponding data bit of the CPL row of the P-CPL relationship FIFO table; and in response to no P packet being written into the P packet buffer FIFO and no CPL packet being written into the CPL packet buffer FIFO, stop performing a write operation on the P-CPL relationship FIFO table.

[0011] Optionally, the first FIFO memory includes a P-packet buffer FIFO, an NP-packet buffer FIFO, and a CPL-packet buffer FIFO, the NP-packet buffer FIFO is configured with a P-NP relationship FIFO table, the P-NP relationship FIFO table is configured with a first overrun counter, the CPL-packet buffer FIFO is configured with a P-CPL relationship FIFO table, the P-CPL relationship FIFO table is configured with a second overrun counter, and the packet input unit includes a first order preserving unit, which is configured to: detect whether the P-packet buffer FIFO has a P-packet buffered in a first-in-first-out order; in response to the P-packet buffer FIFO having a P-packet buffered, control the P-packet buffer FIFO to output the P-packet, and obtain a target relationship FIFO table, the target relationship FIFO table being one of the P-NP relationship FIFO table and the P-CPL relationship FIFO table; read a reference enqueue identifier from the target relationship FIFO table, the reference enqueue identifier being an enqueue identifier of a non-P-packet written into the target relationship FIFO table at the same time as a first enqueue identifier of the P-packet; in response to the reference enqueue identifier being the first enqueue identifier, add a preset value to a count value of a target overrun counter, wherein the count value of the target overrun counter is used to represent a number of non-P-packets that can be continuously transmitted without violating an order preserving rule of a PCIe protocol, and the target overrun counter is one of the first overrun counter and the second overrun counter; and in response to the reference enqueue identifier being a second enqueue identifier, control the count value of the target overrun counter to remain unchanged.

[0012] Optionally, the first order preserving unit is further configured to: in response to the P-packet buffer FIFO not having a P-packet buffered and the count value of the target overrun counter being equal to a preset threshold value, read an enqueue identifier set of an earliest buffering time in the target relationship FIFO table, the enqueue identifier set including a P-enqueue identifier and a non-P-enqueue identifier of the earliest buffering time recorded in the target relationship FIFO table, wherein the P-enqueue identifier is a second enqueue identifier; in response to the non-P-enqueue identifier of the enqueue identifier set being a first enqueue identifier, determine the non-P-packet to be a TLP packet satisfying a preset order preserving condition, control the count value of the target overrun counter to remain unchanged, and delete the P-enqueue identifier and the non-P-enqueue identifier of the enqueue identifier set in the target relationship FIFO table when the non-P-packet is read out of the NP-packet buffer FIFO.

[0013] Optionally, the first order preserving unit is further configured to: in response to the P-packet cache FIFO having P-packets and the count value of the target overrun counter being greater than a preset count threshold, determine non-P-packets with a quantity of packets consistent with the count value as TLP-packets satisfying a preset order preserving condition; and read the non-P-packets with the quantity of packets consistent with the count value from the non-P-packet cache FIFO.

[0014] Optionally, the message input unit comprises a request unit configured to: obtain a target message satisfying a preset order preserving condition from the first FIFO memory; in response to the target message being a routing failure message and a message type of the target message not being an NP message type, discard the target message; in response to the target message being a routing failure message and the message type of the target message being an NP message type, send the target message to a message output unit of the local port module, so that the message output unit of the local port module discards the target message and outputs a CPL message corresponding to the target message; in response to the target message being a routing success message, determine a sending mode of the target message, and send a message arbitration request to an arbitration unit of a target port module based on the sending mode of the target message; and in response to the target message being a routing success message and also being a PME-off message of a PME mechanism, set the message output unit of the local port module to enter a PME state, and send the target message to the message output unit of the local port module, so that the message output unit of the local port module transmits the target message to the target port module, and the target port module is configured to forward the target message to a target port device, so that the target port device returns a PME response message conforming to the PME mechanism.

[0015] Optionally, the request unit is configured to send a message arbitration request to an arbitration unit of a target port module based on a sending mode of the target message, comprising: in response to the sending mode of the target message being a single-point sending mode, determining a target port number corresponding to the target message, and sending a message arbitration request to an arbitration unit of a target port module corresponding to the target port number; and in response to the sending mode of the target message being a broadcast mode, taking each non-local port module as a target port module, and sending a message arbitration request to an arbitration unit of each target port module.

[0016] Optionally, the request unit comprises a P request module, an NP request module and a CPL request module, the arbitration unit comprises a P arbitration module, an NP arbitration module and a CPL arbitration module, the second TLP packet comprises a P packet / NP packet / CPL packet, and the request unit is further configured to: the P request module is configured to send a packet arbitration request to the P arbitration module of the target port module when the P packet is detected to satisfy a preset order preserving condition; or the NP request module is configured to send a packet arbitration request to the NP arbitration module of the target port module when the NP packet is detected to satisfy a preset order preserving condition; or the CPL request module is configured to send a packet arbitration request to the CPL arbitration module of the target port module when the CPL packet is detected to satisfy a preset order preserving condition.

[0017] Optionally, the packet output unit comprises: a second order preserving unit configured to cache the second TLP packet on a second FIFO memory and perform order preserving control processing on all TLP packets of the second FIFO memory; and an arbitration output unit configured to obtain a third TLP packet output by the second order preserving unit and perform a packet output operation based on the third TLP packet in response to the third TLP packet satisfying a second preset arbitration condition.

[0018] Optionally, the arbitration output unit is configured to perform a packet output operation based on the third TLP packet in response to the third TLP packet satisfying a second preset arbitration condition, comprising: performing a PME mechanism operation in response to the third TLP packet being a PME reply packet of the PME mechanism; discarding the third TLP packet and outputting a CPL packet corresponding to the third TLP packet in response to the third TLP packet not being the PME reply packet, the third TLP packet being a routing failure packet and a packet type of the third TLP packet being an NP packet type; and outputting the third TLP packet in response to the third TLP packet not being the PME reply packet and the third TLP packet being a routing success packet.

[0019] Optionally, the arbitration output unit is configured to perform a PME mechanism operation in response to the third TLP packet being a PME reply packet of the PME mechanism, comprising: counting a number of packets of the PME reply packet received by the arbitration output unit in response to the third TLP packet being a PME reply packet of the PME mechanism; and generating a new PME reply packet and outputting the new PME reply packet in response to the number of packets being equal to a number of downstream port modules of the PCIe switch.

[0020] The embodiments of the present application can achieve the following technical effects: the embodiments of the present application set multiple port modules, each of which includes a message input unit, an arbitration unit and a message output unit, and combines the corresponding TLP message order preservation control processing, so as to realize the transmission of TLP messages between any ports in the PCIe switch, guarantee that the order preservation requirement of the TLP message meets the PCIe protocol, and unify the high performance and high reliability of the PCIe switch. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0022] Figure 1 A schematic diagram of the architecture of a PCIe switch provided by the embodiments of the present application is shown in FIG. 1.

[0023] Figure 2 A schematic diagram of message forwarding of a PCIe switch provided by the embodiments of the present application is shown in FIG. 2.

[0024] Figure 3 A schematic diagram of the structure of a first order preservation unit provided by the embodiments of the present application is shown in FIG. 3.

[0025] Figure 4 A schematic diagram of a P-NP relationship FIFO table provided by the embodiments of the present application is shown in FIG. 4.

[0026] Figure 5 A schematic diagram of another structure of a first order preservation unit provided by the embodiments of the present application is shown in FIG. 5.

[0027] Figure 6 A schematic diagram of an enqueuing identifier set in a P-NP relationship FIFO table provided by the embodiments of the present application is shown in FIG. 6. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present application more clear, the following will further describe the present application in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0029] It should be noted that the various features of the embodiments of the present application can be combined with each other, and all within the scope of the present application, if there is no conflict. In addition, although the functional modules are divided in the device schematic diagram, and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from the module division in the device or the order in the flowchart. Furthermore, the "first", "second", "third" and the like used in the present application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same function and effect.

[0030] In addition to the limitations of the prior art pointed out in the background section, the inventors have found that in modern high-performance computing and storage systems, data often needs to be simultaneously distributed from one PCIe device (such as a capture card or a main GPU) to multiple downstream devices (such as multiple computing nodes or slave GPUs), i.e. broadcast communication is implemented. However, the traditional PCIe architecture based on the point-to-point communication model lacks an efficient broadcast mechanism. In the prior art, if data broadcast is to be implemented, the deep involvement of the root complex is usually required. The source device needs to send data to the root complex first, and then the root complex needs to copy and send the data to each target device multiple times. Such a "single-point copy" software simulation method will occupy the upstream link bandwidth and the processing resources of the root complex, resulting in long transmission delay and low efficiency, and as the number of target devices increases, the performance bottleneck becomes more and more serious.

[0031] Referring to Figure 1 , Figure 1 is a schematic diagram of the architecture of a PCIe switch provided by an embodiment of the present application. The PCIe switch 1000 provided by an embodiment of the present application includes a plurality of port modules 100, and each port module 100 includes a packet input unit 10, an arbitration unit 20 and a packet output unit 30.

[0032] Referring to Figure 2 , Figure 2 is a schematic diagram of packet forwarding of a PCIe switch provided by an embodiment of the present application. The packet input unit 10 of the local port module 101 is configured to, in response to the input of the first TLP packet, perform routing processing on the first TLP packet, and when the first TLP packet is successfully routed, cache the first TLP packet on the first FIFO memory 121, perform in-sequence control processing on all TLP packets of the first FIFO memory 121, and when it is detected that the second TLP packet of the first FIFO memory 121 meets the preset in-sequence condition, send a packet arbitration request to the arbitration unit 20 of the target port module 102.

[0033] The local port module 101 is a port module in the PCIe switch 1000 that initiates the forwarding of the first TLP packet. The first TLP packet includes a P packet, a NP packet, or a CPL packet. It should be noted that in the PCIe protocol, the transmission of the three types of TLP packets needs to meet the specified order preservation requirement. In the PCIe protocol, the order preservation requirement for the three types of TLP packets can be simplified as shown in Table 1:

[0034]

[0035] It should be noted that in the PCIe protocol, "overriding" means that one type of packet can be sent in the transmission queue in priority to another type of packet (i.e., "queue jumping"), and the purpose is to optimize the timeliness of the packet under the premise of ensuring data consistency. The overriding relationship of the P (posted, posted) packet, the NP (non-posted, non-posted) packet, and the CPL (complete, complete) packet is shown in Table 1. The P packet can override the NP packet and the CPL packet, and the priority of the P packet is high, which can be sent before the NP packet or the CPL packet. The NP packet can override the CPL packet, but cannot override the P packet and the NP packet. The CPL packet can override the NP packet, but cannot override the P packet and the CPL packet. For example, four packets NP-1, P-1, NP-0, and P-0 are sent from port 1 to port 2 in sequence, and the order of the packets received by port 2 can be NP-1, P-1, NP-0, P-0, or NP-1, NP-0, P-1, P-0. That is, the P packet sent later can override the NP packet sent earlier, but the P packet sent later cannot override the P packet sent earlier, and the NP packet sent later cannot override the NP packet sent earlier.

[0036] The first FIFO memory 121 is a memory with a FIFO (First Input First Output) feature, used to buffer and perform in-order control processing on the TLP packet. The second TLP packet is a TLP packet stored and forwarded by the first FIFO memory 121. It should be noted that the packet type of the second TLP packet may be consistent with the packet type of the first TLP packet, or the packet type of the second TLP packet may be inconsistent with the packet type of the first TLP packet under the in-order requirement of the PCIe protocol. The target port module 102 is a port module in the PCIe switch 1000 that communicates with the local port module 101. When the second TLP packet of the first FIFO memory 121 is detected to meet the preset in-order condition, a packet arbitration request is sent to the arbitration unit 20 of the target port module 102. Specifically, the packet input unit 10 includes a request unit 13 that obtains the second TLP packet from the first FIFO memory 121, and sends a packet arbitration request to the arbitration unit 20 of the target port module 102 when the second TLP packet is detected to meet the preset in-order condition. The preset in-order condition is to meet the in-order requirement of the PCIe protocol for the TLP packet.

[0037] Please continue to refer to Figure 2 The arbitration unit 20 of the target port module 102 is configured to respond to the packet arbitration request and send the second TLP packet to the packet output unit 30 of the target port module 102 when the second TLP packet is detected to meet the first preset arbitration condition.

[0038] Specifically, the target port module 102 is a port module in the PCIe switch 1000 that communicates with the local port module 101. The arbitration unit 20 is used to determine which port module 100 to prioritize when multiple port modules 100 access the target port module 102 at the same time. When the arbitration unit 20 decides to schedule the packet arbitration request of the local port module 101, it detects whether the second TLP packet meets the first preset arbitration condition. The first preset arbitration condition includes determining whether the second TLP packet meets the in-order requirement of the PCIe protocol for the TLP packet. If the second TLP packet meets the first preset arbitration condition, the second TLP packet is sent to the packet output unit 30 of the target port module 102.

[0039] Please continue to refer to Figure 2The message output unit 30 of the target port module 102 is configured to buffer the second TLP message on a second FIFO memory 311, perform in-order control processing on all TLP messages of the second FIFO memory 311, and output the third TLP message when it is detected that the third TLP message meets the second preset arbitration condition, the third TLP message being a TLP message meeting a preset in-order condition in the second FIFO memory 311.

[0040] Specifically, the message output unit 30 includes the second FIFO memory 311, which is configured to store the second TLP message and perform in-order control processing on the second TLP message. The third TLP message is a TLP message meeting a preset in-order condition and stored and forwarded by the second FIFO memory 311. It should be noted that the message type of the third TLP message may be consistent with the message type of the second TLP message, or the message type of the third TLP message may be inconsistent with the message type of the second TLP message under the in-order requirement of the PCIe protocol. The message output unit 30 includes an arbitration output unit 32, which outputs the third TLP message when it is detected that the third TLP message meets the second preset arbitration condition, the second preset arbitration condition including judging whether the third TLP message meets the in-order requirement of the PCIe protocol on the TLP message.

[0041] The embodiments of the present application can realize the transmission of TLP messages between any ports in the PCIe switch by setting multiple port modules, each including a message input unit, an arbitration unit and a message output unit, and combining the corresponding in-order control processing of the TLP message, and can guarantee that the in-order requirement of the TLP message meets the PCIe protocol, thereby realizing the unification of high performance and high reliability of the PCIe switch.

[0042] In some embodiments, please continue to refer to Figure 2 The message input unit 10 includes a routing unit 11, which is configured to determine a target routing mode based on the message type of the first TLP message, perform routing detection on the first TLP message based on the target routing mode to obtain routing detection information, mark the first TLP message as a routing success message in response to the routing detection information being routing success information, the routing success information being used to indicate that the first TLP message is successfully routed, mark the first TLP message as a routing failure message in response to the routing detection information being routing failure information, the routing failure information being used to indicate that the first TLP message is routed unsuccessfully, and buffer the first TLP message on a first FIFO memory 121 based on the message type of the first TLP message.

[0043] Specifically, the target routing mode is a routing mode corresponding to a type of packet. It should be noted that the PCIe protocol defines a dedicated routing mode for different types of packets. For example, the routing mode of P packets / NP packets is address routing, which is to determine the target port of the TLP packet by parsing the Address field in the TLP packet. The routing mode of CPL packets is ID routing, which is to determine the target port of the TLP packet by matching the downstream device ID. In some embodiments, the routing mode also includes routing to RC, RC downlink broadcast, collecting and converging to RC, receiving end termination, etc.

[0044] The routing unit 11 parses the packet type of the first TLP packet and determines the target routing mode based on the packet type of the first TLP packet. After determining the routing mode, the routing unit 11 performs routing detection on the first TLP packet to obtain routing detection information, wherein the routing detection is to detect whether the routing target port module 102 is successful. The routing detection information includes routing failure information / routing success information. If the routing detection information is routing success information, the first TLP packet is marked as a routing success packet. If the routing detection information is routing failure information, the first TLP packet is marked as a routing failure packet. The routing unit 11 buffers the first TLP packet on the first FIFO memory 121 based on the packet type of the first TLP packet.

[0045] In some embodiments, please refer to Figure 2 , the first FIFO memory 121 includes a P packet buffer FIFO 1211, an NP packet buffer FIFO 1212, and a CPL packet buffer FIFO 1213. The routing unit 11 is configured to buffer the first TLP packet on the first FIFO memory 121 based on the packet type of the first TLP packet, including: in response to the packet type of the first TLP packet being a P packet type, buffering the first TLP packet on the P packet buffer FIFO 1211; in response to the packet type of the first TLP packet being an NP packet type, buffering the first TLP packet on the NP packet buffer FIFO 1212; and in response to the packet type of the first TLP packet being a CPL packet type, buffering the first TLP packet on the CPL packet buffer FIFO 1213.

[0046] Specifically, in the embodiment of the present application, the first FIFO memory 121 includes a P packet buffer FIFO 1211, an NP packet buffer FIFO 1212, and a CPL packet buffer FIFO 1213. If the packet type of the first TLP packet is the P packet type, the first TLP packet is sent to the P packet buffer FIFO 1211 for buffering. If the packet type of the first TLP packet is the NP packet type, the first TLP packet is sent to the NP packet buffer FIFO 1212 for buffering. If the packet type of the first TLP packet is the CPL packet type, the first TLP packet is sent to the CPL packet buffer FIFO 1213 for buffering.

[0047] In some embodiments, referring to Figure 3 , Figure 3 is a structural schematic diagram of a first order preserving unit 12 provided by the embodiment of the present application. The NP packet buffer FIFO 1212 is configured with a P-NP relationship FIFO table 1214. The packet input unit 10 includes the first order preserving unit 12, which is configured to: in response to that a P packet is written into the P packet buffer FIFO 1211 and no NP packet is written into the NP packet buffer FIFO 1212, write a first enqueuing identifier into a data bit corresponding to a P row of the P-NP relationship FIFO table 1214 and write a second enqueuing identifier into a data bit corresponding to an NP row of the P-NP relationship FIFO table 1214; in response to that no P packet is written into the P packet buffer FIFO 1211 and an NP packet is written into the NP packet buffer FIFO 1212, write the second enqueuing identifier into the data bit corresponding to the P row of the P-NP relationship FIFO table 1214 and write the first enqueuing identifier into the data bit corresponding to the NP row of the P-NP relationship FIFO table 1214; in response to that a P packet is written into the P packet buffer FIFO 1211 and an NP packet is written into the NP packet buffer FIFO 1212, write the first enqueuing identifier into the data bit corresponding to the P row of the P-NP relationship FIFO table 1214 and the data bit corresponding to the NP row of the P-NP relationship FIFO table 1214; and in response to that no P packet is written into the P packet buffer FIFO 1211 and no NP packet is written into the NP packet buffer FIFO 1212, stop performing a write operation on the P-NP relationship FIFO table 1214.

[0048] Specifically, the P-NP relationship FIFO table 1214 is used to maintain the order preserving relationship between the P packet and the NP packet. When the NP packet satisfies a preset order preserving condition, the first order preserving unit 12 sends an indication signal to the NP request module 132. Referring to Figure 2 In the embodiment of the present application, the packet input unit 10 includes a request unit 13, which includes a P request module 131, an NP request module 132, and a CPL request module 133. The indication signal is used to indicate that the current NP packet can be dequeued.

[0049] Please refer to Figure 4 , the P-NP relationship FIFO table 1214 includes P rows and NP rows, the data bits of the P rows are used to indicate the enqueuing condition of the P packets in the P packet buffer FIFO 1211, and the data bits of the NP rows are used to indicate the enqueuing condition of the NP packets in the NP packet buffer FIFO 1212. The data bits corresponding to the P rows and the NP rows record the enqueuing conditions of the two buffer FIFOs at the same time. It can be understood that if the packet type of the first TLP packet is a P packet, the routing unit 11 will buffer the first TLP packet to the P packet buffer FIFO 1211, and if the packet type of the first TLP packet is an NP packet, the routing unit 11 will buffer the first TLP packet to the NP packet buffer FIFO 1212. At the same time, the first order preservation unit 12 will update the content of the P-NP relationship FIFO table 1214 according to the enqueuing conditions of the P packet buffer FIFO 1211 and the NP packet buffer FIFO 1212.

[0050] Specifically, at the same time, if a P packet is written into the P packet buffer FIFO 1211 and no NP packet is written into the NP packet buffer FIFO 1212, the first order preservation unit 12 will write a first enqueuing identifier into the data bit corresponding to the P row of the P-NP relationship FIFO table 1214, and specifically, the first enqueuing identifier is 1, and a second enqueuing identifier is written into the data bit corresponding to the NP row of the P-NP relationship FIFO table 1214, and specifically, the second enqueuing identifier is 0; if no P packet is written into the P packet buffer FIFO 1211 and an NP packet is written into the NP packet buffer FIFO 1212, the first order preservation unit 12 will write the second enqueuing identifier into the data bit corresponding to the P row of the P-NP relationship FIFO table 1214, and write the first enqueuing identifier into the data bit corresponding to the NP row of the P-NP relationship FIFO table 1214; if a P packet is written into the P packet buffer FIFO 1211 and an NP packet is written into the NP packet buffer FIFO 1212, the first order preservation unit 12 will write the first enqueuing identifier into the data bit corresponding to the P row and the data bit corresponding to the NP row of the P-NP relationship FIFO table 1214; if no P packet is written into the P packet buffer FIFO 1211 and no NP packet is written into the NP packet buffer FIFO 1212, the first order preservation unit 12 will stop performing the write operation on the P-NP relationship FIFO table 1214.

[0051] In some embodiments, please continue to refer to Figure 3The P-CPL relationship FIFO table 1215 is configured with a P-CPL relationship FIFO table 1215, and the message input unit 10 includes a first order preserving unit 12, which is configured to: in response to a P message being written into the P message buffer FIFO 1211 and no CPL message being written into the CPL message buffer FIFO 1213, write a first enqueuing identifier into a corresponding data bit of a P row of the P-CPL relationship FIFO table 1215 and a second enqueuing identifier into a corresponding data bit of a CPL row of the P-CPL relationship FIFO table 1215; in response to no P message being written into the P message buffer FIFO 1211 and a CPL message being written into the CPL message buffer FIFO 1213, write the second enqueuing identifier into the corresponding data bit of the P row of the P-CPL relationship FIFO table 1215 and the first enqueuing identifier into the corresponding data bit of the CPL row of the P-CPL relationship FIFO table 1215; in response to a P message being written into the P message buffer FIFO 1211 and a CPL message being written into the CPL message buffer FIFO 1213, write the first enqueuing identifier into the corresponding data bit of the P row and the corresponding data bit of the CPL row of the P-CPL relationship FIFO table 1215; and in response to no P message being written into the P message buffer FIFO 1211 and no CPL message being written into the CPL message buffer FIFO 1213, stop performing a write operation on the P-CPL relationship FIFO table 1215.

[0052] Specifically, the P-CPL relationship FIFO table 1215 is used to maintain the order preserving relationship between the P message and the CPL message, and the first order preserving unit 12 sends an indication signal to the CPL request module 133 when the CPL message meets a preset order preserving condition. In the embodiment of the present application, the message input unit 10 includes a request unit 13, which includes a P request module 131, an NP request module 132, and a CPL request module 133. The indication signal is used to indicate that the current CPL message can be dequeued. The P-CPL relationship FIFO table 1215 includes a P row and a CPL row, the data bit of the P row is used to indicate the enqueuing situation of the P message on the P message buffer FIFO 1211, the data bit of the CPL row is used to indicate the enqueuing situation of the CPL message on the CPL message buffer FIFO 1213, and the corresponding data bits of the P row and the CPL row record the enqueuing situations of the two buffer FIFOs at the same time. It can be understood that if the message type of the first TLP message is a P message, the routing unit 11 will cache the first TLP message to the P message buffer FIFO 1211, and if the message type of the first TLP message is a CPL message, the routing unit 11 will cache the first TLP message to the CPL message buffer FIFO 1213. At the same time, the first order preserving unit 12 will update the content of the P-CPL relationship FIFO table 1215 according to the enqueuing situations of the P message buffer FIFO 1211 and the CPL message buffer FIFO 1213.

[0053] Specifically, at the same time, if the P packet is written into the P packet buffer FIFO 1211 and the CPL packet is not written into the CPL packet buffer FIFO 1213, the first order preserving unit 12 writes the first enqueuing identifier into the corresponding data bit of the P row of the P-CPL relationship FIFO table 1215 and writes the second enqueuing identifier into the corresponding data bit of the CPL row of the P-CPL relationship FIFO table 1215; if the P packet is not written into the P packet buffer FIFO 1211 and the CPL packet is written into the CPL packet buffer FIFO 1213, the first order preserving unit 12 writes the second enqueuing identifier into the corresponding data bit of the P row of the P-CPL relationship FIFO table 1215 and writes the first enqueuing identifier into the corresponding data bit of the CPL row of the P-CPL relationship FIFO table 1215; if the P packet is written into the P packet buffer FIFO 1211 and the CPL packet is written into the CPL packet buffer FIFO 1213, the first order preserving unit 12 writes the first enqueuing identifier into the corresponding data bit of the P row of the P-CPL relationship FIFO table 1215 and writes the first enqueuing identifier into the corresponding data bit of the CPL row of the P-CPL relationship FIFO table 1215; if the P packet is not written into the P packet buffer FIFO 1211 and the CPL packet is not written into the CPL packet buffer FIFO 1213, the first order preserving unit 12 stops performing the writing operation on the P-CPL relationship FIFO table 1215.

[0054] It should be noted that in the PCIe protocol, the P packet can override the NP packet and the CPL packet, so the P packet always satisfies the order preserving condition and can be dequeued when the P packet exists on the P packet buffer FIFO 1211.

[0055] In some embodiments, please refer to Figure 5 , Figure 5is another structural schematic diagram of the first in-order unit 12 provided by the embodiment of the present application. The first FIFO memory 121 includes a P-packet buffer FIFO 1211, an NP-packet buffer FIFO 1212, and a CPL-packet buffer FIFO 1213. The NP-packet buffer FIFO 1212 is configured with a P-NP relationship FIFO table 1214, and the P-NP relationship FIFO table 1214 is configured with a first overrun counter 1216. The CPL-packet buffer FIFO 1213 is configured with a P-CPL relationship FIFO table 1215, and the P-CPL relationship FIFO table 1215 is configured with a second overrun counter 1217. The packet input unit 10 includes the first in-order unit 12, which is configured to: detect, in a first-in-first-out order, whether the P-packet buffer FIFO 1211 stores a P-packet; in response to the P-packet buffer FIFO 1211 storing the P-packet, control the P-packet buffer FIFO 1211 to output the P-packet, and obtain a target relationship FIFO table, which is one of the P-NP relationship FIFO table 1214 and the P-CPL relationship FIFO table 1215; read a reference enqueue identifier from the target relationship FIFO table, the reference enqueue identifier being an enqueue identifier of a non-P-packet that is written into the target relationship FIFO table at the same time as a first enqueue identifier of the P-packet; in response to the reference enqueue identifier being the first enqueue identifier, add a preset value to a count value of a target overrun counter, wherein the count value of the target overrun counter is used to represent a number of non-P-packets that can be continuously transmitted without violating an in-order rule of a PCIe protocol, and the target overrun counter is one of the first overrun counter 1216 and the second overrun counter 1217; and in response to the reference enqueue identifier being a second enqueue identifier, control the count value of the target overrun counter to remain unchanged.

[0056] Specifically, the first in-order unit 12 first detects, in a first-in-first-out order, whether the P-packet buffer FIFO 1211 stores a P-packet. If the P-packet buffer FIFO 1211 stores the P-packet, the P-packet in the P-packet buffer FIFO 1211 is dequeued, and at the same time, a target relationship FIFO table is obtained, which is one of the P-NP relationship FIFO table 1214 and the P-CPL relationship FIFO table 1215. For example, if the target relationship FIFO table is the P-NP relationship FIFO table 1214, the first in-order unit 12 first searches the P-NP relationship FIFO table 1214 for a data bit whose enqueue identifier is the first enqueue identifier, which is 1, and then reads an enqueue identifier of a data bit corresponding to the data bit of the P row from an NP row, which is a reference enqueue identifier.

[0057] It should be noted that the target relationship FIFO table is the P-NP relationship FIFO table 1214, and the target overrun counter is the first overrun counter 1216. The count value of the first overrun counter 1216 indicates the number of NP packets that can be continuously transmitted without violating the order preserving rule of the PCIe protocol.

[0058] If the reference enqueue identifier is the first enqueue identifier, the count value of the first overrun counter 1216 is accumulated by a preset value, and the preset value is 1. The number of preset values accumulated by the count value of the first overrun counter 1216 depends on the number of times that the reference enqueue identifier is the first enqueue identifier. For example, if the number of sets of {P: 1, NP: 1} stored in the P-NP relationship FIFO table 1214 at this time is 2, the count value of the first overrun counter 1216 is accumulated by a total of 2. If the reference enqueue identifier is the second enqueue identifier, and the second enqueue identifier is 0, the count value of the first overrun counter 1216 remains unchanged. For example, if the P-NP relationship FIFO table 1214 stores a set of {P: 1, NP: 0}, when the P packet corresponding to the P row data bit is dequeued, the count value of the first overrun counter 1216 remains unchanged.

[0059] In some embodiments, the first order preserving unit 12 is further configured to: in response to the P packet buffer FIFO 1211 not storing a P packet, and the count value of the target overrun counter being equal to a preset count threshold, read an earliest time of storage enqueue identifier set in the target relationship FIFO table, the earliest time of storage enqueue identifier set including a P enqueue identifier and a non-P enqueue identifier recorded in the target relationship FIFO table at the earliest time of storage, wherein the P enqueue identifier is the second enqueue identifier; in response to the non-P enqueue identifier of the earliest time of storage enqueue identifier set being the first enqueue identifier, determining that the non-P packet is a TLP packet satisfying the preset order preserving condition, controlling the count value of the target overrun counter to remain unchanged, and deleting the P enqueue identifier and the non-P enqueue identifier of the earliest time of storage enqueue identifier set in the target relationship FIFO table when the non-P packet is read out of the non-P packet buffer FIFO.

[0060] For example, if the first order preserving unit 12 detects that the P packet buffer FIFO 1211 does not store a P packet, and the count value of the first overrun counter 1216 is equal to a preset count threshold, and the preset count threshold is 0, i.e., the count value of the first overrun counter 1216 is equal to 0, the first order preserving unit 12 will obtain the enqueue identifier set in the P-NP relationship FIFO table 1214, as shown in FIG. 12B. The enqueue identifier set includes a P enqueue identifier and an NP enqueue identifier recorded in the P-NP relationship FIFO table 1214 at the earliest time of storage. The number of data bits in the P row and the NP row in the figure is only illustrative, and should not be construed as limiting the scope of protection of the present application. Figure 6

[0061] ​It can be understood that the P packet buffer FIFO 1211 does not buffer the P packet, and the P enqueuing identifier in the enqueuing identifier set is the second enqueuing identifier 0. If the NP enqueuing identifier in the enqueuing identifier set is the first enqueuing identifier 1, it is determined that the NP packet is the TLP packet satisfying the preset ordering condition, and at this time, the NP packet can be dequeued from the NP packet buffer FIFO 1212, and the counting value of the first override counter 1216 remains unchanged. When the NP packet is read out from the NP packet buffer FIFO 1212, the first ordering unit 12 will delete the P enqueuing identifier and the NP enqueuing identifier in the enqueuing identifier set in the P-NP relationship FIFO table 1214.

[0062] In some embodiments, the first ordering unit 12 is further configured to: in response to the P packet buffer FIFO 1211 buffering the P packet, and the counting value of the target override counter being greater than the preset counting threshold, determining that the non-P packet with the number of packets consistent with the counting value is the TLP packet satisfying the preset ordering condition; and reading the non-P packet with the number of packets consistent with the counting value from the non-P packet buffer FIFO.

[0063] For example, if the P packet buffer FIFO 1211 buffers the P packet, and the counting value of the first override counter 1216 is greater than the preset counting threshold, which is 0, it is determined that the NP packet with the number of packets consistent with the counting value is the TLP packet satisfying the preset ordering condition, and the first ordering unit 12 can read the NP packet with the number of packets consistent with the counting value from the NP packet buffer FIFO 1212.

[0064] In some embodiments, the first ordering unit 12 can use bitmap, linked list, etc. to maintain the ordering relationship between the P packet and the NP packet, the P packet and the CPL packet.

[0065] In some embodiments, the packet input unit 10 includes a request unit 13, which is configured to:

[0066] Obtain the target packet satisfying the preset ordering condition from the first FIFO memory 121.

[0067] Specifically, the first ordering unit 12 sends the TLP packet satisfying the preset ordering condition in the first FIFO memory 121 to the request unit 13. The TLP packet received by the request unit 13 from the first FIFO memory 121 is the target packet satisfying the preset ordering condition.

[0068] In response to the target packet being a routing failure packet, and the packet type of the target packet not being the NP packet type, discarding the target packet.

[0069] Specifically, the target packet carries route detection information, and the route detection information includes route success information and route failure information. The route success information is used to indicate that the target packet is a route success packet, and the route failure information is used to indicate that the target packet is a route failure packet. If the target packet is a route failure packet and the packet type of the target packet is not the NP packet type, the target packet is directly discarded.

[0070] In response to the target packet being a route failure packet and the packet type of the target packet being the NP packet type, the target packet is sent to the message output unit 30 of the local port module 101, so that the message output unit 30 of the local port module 101 discards the target packet and outputs a CPL packet corresponding to the target packet.

[0071] Specifically, if the target packet is a route failure packet and the packet type of the target packet is the NP packet type, i.e., an NP packet, the target packet is sent to the message output unit 30 of the local port module 101. The message output unit 30 of the local port module 101 generates a CPL packet corresponding to the NP packet, discards the NP packet, and outputs the CPL packet corresponding to the NP packet.

[0072] In response to the target packet being a route success packet, a sending mode of the target packet is determined, and a message arbitration request is sent to the arbitration unit 20 of the target port module 102 based on the sending mode of the target packet.

[0073] Specifically, if the target packet is a route success packet, the sending mode of the target packet is determined. In the embodiment of the present application, the sending mode of the target packet includes a single-point mode and a broadcast mode. After the sending mode of the target packet is determined, the message arbitration request is sent to the arbitration unit 20 of the target port module 102.

[0074] In response to the target packet being a route success packet and also being a PME close packet of the PME mechanism, the message output unit 30 of the local port module 101 is set to enter a PME state, and the target packet is sent to the message output unit 30 of the target port module 102. The target port module 102 is configured to forward the target packet to a target port device, so that the target port device returns a PME response packet conforming to the PME mechanism.

[0075] Specifically, in the PCIe protocol, a PME (Power Management Event) mechanism is a mechanism for realizing device power state control and system wake-up. A PME off packet is a TLP packet used for triggering a device to enter deep sleep in the PME mechanism. If the target packet is a routing success packet and is also a PME off packet of the PME mechanism, the message output unit 30 of the local port module 101 is switched to a PME state suitable for PME packet transmission. The message output unit 30 entering the PME state needs to pause the sending of unnecessary transactions (such as ordinary data read-write TLP packets) and preferentially guarantee the low-delay transmission of the PME off packet; meanwhile, the reply monitoring logic is started to reserve resources for the subsequent reception of a PME reply packet of the target port device.

[0076] After the message output unit 30 of the local port module 101 enters the PME state, the request unit 13 sends the target packet to the message output unit 30 of the target port module 102, and the target port module 102 forwards the target packet to a target port device. The target port device is a device connected to the target port, and the target port device returns a PME reply packet conforming to the PME mechanism.

[0077] It should be noted that after the target port device receives the PME off packet, it will clean up unfinished transactions, switch to a low-power state, and generate a PME reply packet, which is returned to the RC root complex through the original path, thereby completing the closed loop of the PME mechanism.

[0078] In some embodiments, the request unit 13 is configured to send a message arbitration request to the arbitration unit 20 of the target port module 102 based on the sending mode of the target packet, including: in response to the sending mode of the target packet being a unicast sending mode, determining a target port number corresponding to the target packet, and sending a message arbitration request to the arbitration unit 20 of the target port module 102 corresponding to the target port number; and in response to the sending mode of the target packet being a broadcast mode, regarding each non-local port module 101 as a target port module 102, and sending a message arbitration request to the arbitration unit 20 of each target port module 102.

[0079] Specifically, if the sending mode of the target packet is a unicast sending mode, the request unit 13 determines a target port number corresponding to the target packet based on the analysis result of the routing unit 11 in advance, and sends a message arbitration request to the arbitration unit 20 of the target port module 102 corresponding to the target port number. If the sending mode of the target packet is a broadcast mode, the request unit 13 regards each non-local port module 101 as a target port module 102, and sends a message arbitration request to the arbitration unit 20 of each target port module 102.

[0080] It should be noted that for the broadcast mode, the request unit 13 simultaneously sends a message arbitration request to the arbitration unit 20 of all target port modules 102, when a target port module 102 arbitrates successfully, the target message is sent to the corresponding target port module 102, if the target message fails to complete the broadcast, the target port module information is updated, the target port module information includes the target port module 102 that needs to forward the target message, the next round of sending is continued, until the sending of all target port modules 102 is completed.

[0081] In some embodiments, referring to Figure 2 , the request unit 13 includes a P request module 131, an NP request module 132, and a CPL request module 133, the arbitration unit 20 includes a P arbitration module 21, an NP arbitration module 22, and a CPL arbitration module 23, the second TLP message includes a P message / NP message / CPL message, and the request unit 13 is further configured to: the P request module 131 is configured to send a message arbitration request to the P arbitration module 21 of the target port module 102 when it is detected that the P message satisfies the preset order preserving condition; or, the NP request module 132 is configured to send a message arbitration request to the NP arbitration module 22 of the target port module 102 when it is detected that the NP message satisfies the preset order preserving condition; or, the CPL request module 133 is configured to send a message arbitration request to the CPL arbitration module 23 of the target port module 102 when it is detected that the CPL message satisfies the preset order preserving condition.

[0082] Specifically, if the message type of the second TLP message is a P message, the P request module 131 in the request unit 13 will detect whether the second TLP message satisfies the preset order preserving condition, it can be understood that in the PCIe protocol, the P message can override the NP message and the CPL message, therefore the P message always satisfies the preset order preserving condition, as long as there is a P message on the P message buffer FIFO, the P message can be directly dequeued, the P request module 131 will send a message arbitration request to the P arbitration module 21 of the target port module 102; or, if the message type of the second TLP message is an NP message, the NP request module 132 in the request unit 13 will detect whether the second TLP message satisfies the preset order preserving condition, specifically, please continue to refer to Figure 5The NP request module 132 detects the indication signal output by the first order preserving unit 12. If the indication signal indicates that the NP packet meets the preset order preserving condition, the NP request module 132 sends a packet arbitration request to the NP arbitration module 22 of the target port. Alternatively, if the packet type of the second TLP packet is a CPL packet, the CPL request module 133 in the request unit detects whether the second TLP packet meets the preset order preserving condition. Specifically, the CPL request module 133 detects the indication signal output by the first order preserving unit 12. If the indication signal indicates that the CPL packet meets the preset order preserving condition, the CPL request module 133 sends a packet arbitration request to the CPL arbitration module 23 of the target port.

[0083] It should be noted that each port module has an arbitration unit 20, and each arbitration unit 20 includes a P arbitration module 21, an NP arbitration module 22, and a CPL arbitration module 23, which correspond to arbitrating P packets, NP packets, and CPL packets, respectively. Since the arbitration time of each arbitration module is the same, the delay of the P / NP / CPL packet from the packet input unit 10 of the local port module 101 to the packet output unit 30 of the target port module 102 is the same, which ensures that the order of the TLP packet reaching the packet output unit 30 is consistent with the order of the packet input unit 10, and the packet order can be preserved. In addition, when the arbitration unit 20 of the target port module 102 schedules the packet arbitration request of the local port module 101, the TLP packet of the local port module 101 must be sent before the packet arbitration request of other port modules 100 is scheduled. The arbitration unit 20 can use the SP (Strict Priority, strict priority scheduling) scheduling method, the RR (Round-Robin, round-robin scheduling) scheduling method, and the WRR (Weighted Round-Robin, weighted round-robin scheduling) scheduling method to schedule the packet arbitration request.

[0084] In some embodiments, the packet output unit 30 includes a second order preserving unit 31 configured to buffer the second TLP packet on a second FIFO memory 311 and perform order preserving control processing on all TLP packets of the second FIFO memory 311. An arbitration output unit 32 is configured to obtain a third TLP packet output by the second order preserving unit 31 and perform a packet output operation based on the third TLP packet in response to the third TLP packet meeting a second preset arbitration condition.

[0085] Specifically, the packet output unit 30 includes a second order preserving unit 31 and an arbitration output unit 32. The second order preserving unit 31 buffers the second TLP packet on the second FIFO memory 311 and performs order preserving control processing on all TLP packets of the second FIFO memory 311. The second order preserving unit 31 is designed in the same way as the first order preserving unit 12, and performs order preserving control processing on all TLP packets of the second FIFO memory 311 in the same way as the first order preserving unit 12. Details are not repeated here. The arbitration output unit 32 receives the third TLP packet output by the second order preserving unit 31, and outputs the third TLP packet when the third TLP packet meets a preset arbitration condition.

[0086] In some embodiments, the arbitration output unit 32 is configured to perform a packet output operation based on the third TLP packet in response to the third TLP packet meeting a second preset arbitration condition, including: in response to the third TLP packet being a PME mechanism PME response packet, performing a PME mechanism operation; in response to the third TLP packet not being a PME response packet, the third TLP packet being a routing failure packet, and the packet type of the third TLP packet being an NP packet type, discarding the third TLP packet and outputting a CPL packet corresponding to the third TLP packet; in response to the third TLP packet not being a PME response packet and the third TLP packet being a routing success packet, outputting the third TLP packet.

[0087] Specifically, if the third TLP packet is a PME mechanism PME response packet, the arbitration output unit 32 performs a PME mechanism operation. If the third TLP packet is not a PME response packet, the third TLP packet is a routing failure packet, and the packet type of the third TLP packet is an NP packet type, i.e. an NP packet, the arbitration output unit 32 discards the third TLP packet and outputs a CPL packet corresponding to the NP packet. If the third TLP packet is not a PME response packet and the third TLP packet is a routing success packet, the arbitration output unit 32 directly outputs the third TLP packet. For example, if the third TLP packet is a P packet / NP packet and the third TLP packet is a routing success packet, the P packet / NP packet is directly outputted.

[0088] In some embodiments, the arbitration output unit 32 is configured to perform a PME mechanism operation in response to the third TLP packet being a PME mechanism PME response packet, including: in response to the third TLP packet being a PME mechanism PME response packet, counting the number of PME response packets received by the arbitration output unit 32; and in response to the number of packets being equal to the number of downstream port modules of the PCIe switch, generating a new PME response packet and outputting the new PME response packet.

[0089] Specifically, if the third TLP packet is a PME response packet of the PME mechanism, the arbitration output unit 32 will count the number of received PME response packets, and if the number of received PME response packets is equal to the number of downstream port modules of the PCIe switch 1000 (i.e. all devices connected by the downstream port modules have returned PME response packets), the arbitration output unit 32 will generate a new PME response packet and output the new PME response packet. The new PME response packet is a summary confirmation packet sent by the PCIe switch 1000 to the RC after all downstream devices have returned PME response packets. In essence, it is a system-level response to the broadcast PME close packet, which replaces multiple scattered device-level responses.

[0090] It should be noted that the arbitration output unit 32 uses SP (Strict Priority, strict priority scheduling) scheduling to schedule the message arbitration request. For example, the priority of the message arbitration request from high to low is as follows: 1. The PME response packet generated by the local port module 101; 2. The CPL packet generated by the message output unit 30 of the local port module 101; 3. The P packet on the P packet buffer FIFO 1211 that meets the preset sequence preserving condition; 4. The NP packet on the NP packet buffer FIFO 1212 that meets the preset sequence preserving condition; 5. The CPL packet on the CPL packet buffer FIFO 1213 that meets the preset sequence preserving condition.

[0091] It should be noted that in the above various embodiments, there is no certain sequence between the above steps. Those skilled in the art can understand from the description of the embodiments of the present application that the above steps can have different execution sequences in different embodiments, that is, they can be executed in parallel, or they can be executed in exchange, etc.

[0092] The above disclosure is only the preferred embodiment of the present application, and of course cannot limit the scope of the rights of the present application, so the equivalent changes made according to the claims of the present application still fall within the scope covered by the present application.

Claims

1. A PCIe switch, characterized by, The plurality of port modules each include a message input unit, an arbitration unit and a message output unit; The message input unit of the local port module is configured to, in response to input of a first TLP message, perform routing processing on the first TLP message, and when the first TLP message is successfully routed, buffer the first TLP message on a first FIFO memory, perform in-sequence control processing on all TLP messages of the first FIFO memory, and when a second TLP message of the first FIFO memory is detected to satisfy a preset in-sequence condition, send a message arbitration request to the arbitration unit of a target port module; The arbitration unit of the target port module is configured to, in response to the message arbitration request, when the second TLP message is detected to satisfy a first preset arbitration condition, send the second TLP message to the message output unit of the target port module; The message output unit of the target port module is configured to buffer the second TLP message on a second FIFO memory, perform in-sequence control processing on all TLP messages of the second FIFO memory, and when a third TLP message satisfying a second preset arbitration condition is detected, output the third TLP message, the third TLP message being a TLP message of the second FIFO memory satisfying the preset in-sequence condition.

2. The PCIe switch of claim 1, wherein, The message input unit includes a routing unit configured to: determine a target routing mode based on a message type of the first TLP message; perform routing detection on the first TLP message based on the target routing mode to obtain routing detection information; in response to the routing detection information being routing success information, mark the first TLP message as a routing success message, the routing success information being used to indicate that the first TLP message is successfully routed; in response to the routing detection information being routing failure information, mark the first TLP message as a routing failure message, the routing failure information being used to indicate that the first TLP message is routed unsuccessfully; buffer the first TLP message on the first FIFO memory based on a message type of the first TLP message.

3. The PCIe switch of claim 2, wherein, The first FIFO memory includes a P message buffer FIFO, an NP message buffer FIFO and a CPL message buffer FIFO, and the routing unit is configured to buffer the first TLP message on the first FIFO memory based on a message type of the first TLP message, including: in response to the message type of the first TLP message being a P message type, buffer the first TLP message on the P message buffer FIFO; in response to the message type of the first TLP message being an NP message type, buffer the first TLP message on the NP message buffer FIFO; in response to the message type of the first TLP message being a CPL message type, buffer the first TLP message on the CPL message buffer FIFO.

4. The PCIe switch of claim 3, wherein, The NP packet buffer FIFO is configured with a P-NP relationship FIFO table, the packet input unit comprises a first order preserving unit, and the first order preserving unit is configured to: in response to that a P packet is written into the P packet buffer FIFO and no NP packet is written into the NP packet buffer FIFO, write a first enqueuing identifier into a corresponding data bit of a P row of the P-NP relationship FIFO table and write a second enqueuing identifier into a corresponding data bit of an NP row of the P-NP relationship FIFO table; in response to that no P packet is written into the P packet buffer FIFO and an NP packet is written into the NP packet buffer FIFO, write a second enqueuing identifier into a corresponding data bit of a P row of the P-NP relationship FIFO table and write a first enqueuing identifier into a corresponding data bit of an NP row of the P-NP relationship FIFO table; in response to that a P packet is written into the P packet buffer FIFO and an NP packet is written into the NP packet buffer FIFO, write a first enqueuing identifier into a corresponding data bit of a P row of the P-NP relationship FIFO table and write a first enqueuing identifier into a corresponding data bit of an NP row of the P-NP relationship FIFO table; in response to that no P packet is written into the P packet buffer FIFO and no NP packet is written into the NP packet buffer FIFO, stop performing a write operation on the P-NP relationship FIFO table.

5. The PCIe switch of claim 3, wherein, The CPL packet buffer FIFO is configured with a P-CPL relationship FIFO table, the packet input unit comprises a first order preserving unit, and the first order preserving unit is configured to: in response to that a P packet is written into the P packet buffer FIFO and no CPL packet is written into the CPL packet buffer FIFO, write a first enqueuing identifier into a corresponding data bit of a P row of the P-CPL relationship FIFO table and write a second enqueuing identifier into a corresponding data bit of a CPL row of the P-CPL relationship FIFO table; in response to that no P packet is written into the P packet buffer FIFO and a CPL packet is written into the CPL packet buffer FIFO, write a second enqueuing identifier into a corresponding data bit of a P row of the P-CPL relationship FIFO table and write a first enqueuing identifier into a corresponding data bit of a CPL row of the P-CPL relationship FIFO table; in response to that a P packet is written into the P packet buffer FIFO and a CPL packet is written into the CPL packet buffer FIFO, write a first enqueuing identifier into a corresponding data bit of a P row of the P-CPL relationship FIFO table and write a first enqueuing identifier into a corresponding data bit of a CPL row of the P-CPL relationship FIFO table; in response to that no P packet is written into the P packet buffer FIFO and no CPL packet is written into the CPL packet buffer FIFO, stop performing a write operation on the P-CPL relationship FIFO table.

6. The PCIe switch of claim 1, wherein, The first FIFO memory includes a P-packet buffer FIFO, an NP-packet buffer FIFO, and a CPL-packet buffer FIFO, the NP-packet buffer FIFO is configured with a P-NP relationship FIFO table, the P-NP relationship FIFO table is configured with a first overrun counter, the CPL-packet buffer FIFO is configured with a P-CPL relationship FIFO table, the P-CPL relationship FIFO table is configured with a second overrun counter, and the packet input unit includes a first order preserving unit, which is configured to: detect whether the P-packet buffer FIFO caches a P-packet in a first-in first-out order; in response to the P-packet buffer FIFO caching a P-packet, control the P-packet buffer FIFO to output the P-packet, and obtain a target relationship FIFO table, the target relationship FIFO table being one of the P-NP relationship FIFO table and the P-CPL relationship FIFO table; read a reference enqueue identifier from the target relationship FIFO table, the reference enqueue identifier being an enqueue identifier of a non-P-packet written into the target relationship FIFO table at the same time as a first enqueue identifier of the P-packet; in response to the reference enqueue identifier being the first enqueue identifier, add a preset value to a count value of a target overrun counter, wherein the count value of the target overrun counter is used to represent a number of non-P-packets that can be continuously transmitted without violating an order preserving rule of a PCIe protocol, and the target overrun counter is one of the first overrun counter and the second overrun counter; in response to the reference enqueue identifier being a second enqueue identifier, control the count value of the target overrun counter to remain unchanged.

7. The PCIe switch of claim 6, wherein, The first order preserving unit is further configured to: in response to the P-packet buffer FIFO not caching a P-packet and the count value of the target overrun counter being equal to a preset count threshold, read an enqueue identifier set of an earliest caching time in the target relationship FIFO table, the enqueue identifier set including a P-enqueue identifier and a non-P-enqueue identifier of the earliest caching time currently recorded in the target relationship FIFO table, wherein the P-enqueue identifier is a second enqueue identifier; in response to the non-P-enqueue identifier of the enqueue identifier set being the first enqueue identifier, determine that the non-P-packet is a TLP packet satisfying a preset order preserving condition, control the count value of the target overrun counter to remain unchanged, and delete the P-enqueue identifier and the non-P-enqueue identifier of the enqueue identifier set in the target relationship FIFO table when the non-P-packet is read out of the NP-packet buffer FIFO.

8. The PCIe switch of claim 6, wherein, The first order preserving unit is further configured to: in response to the P-packet buffer FIFO caching a P-packet and the count value of the target overrun counter being greater than the preset count threshold, determine that a non-P-packet with a number of packets consistent with the count value is a TLP packet satisfying a preset order preserving condition; read the non-P-packet with the number of packets consistent with the count value out of the NP-packet buffer FIFO.

9. The PCIe switch of claim 1, wherein, The packet input unit includes a request unit, which is configured to: acquire a target packet satisfying a preset in-order condition from the first FIFO memory; in response to the target packet being a routing failure packet and a packet type of the target packet not being an NP packet type, discard the target packet; in response to the target packet being a routing failure packet and the packet type of the target packet being the NP packet type, send the target packet to a packet output unit of the local port module, so that the packet output unit of the local port module discards the target packet and outputs a CPL packet corresponding to the target packet; in response to the target packet being a routing success packet, determine a sending mode of the target packet, and send a packet arbitration request to an arbitration unit of a target port module based on the sending mode of the target packet; in response to the target packet being a routing success packet and also being a PME close packet of a PME mechanism, set the packet output unit of the local port module to enter a PME state, and send the target packet to a packet output unit of the target port module, the target port module being configured to forward the target packet to a target port device, so that the target port device returns a PME response packet conforming to the PME mechanism.

10. The PCIe switch of claim 9, wherein, The request unit is configured to send a packet arbitration request to an arbitration unit of a target port module based on the sending mode of the target packet, including: in response to the sending mode of the target packet being a unicast sending mode, determine a target port number corresponding to the target packet, and send a packet arbitration request to the arbitration unit of the target port module corresponding to the target port number; in response to the sending mode of the target packet being a broadcast mode, take each non-local port module as a target port module, and send a packet arbitration request to the arbitration unit of each target port module.

11. The PCIe switch of claim 9, wherein, The request unit includes a P request module, an NP request module and a CPL request module, the arbitration unit includes a P arbitration module, an NP arbitration module and a CPL arbitration module, the second TLP packet includes a P packet / NP packet / CPL packet, and the request unit is further configured to: the P request module is configured to, when detecting that the P packet satisfies the preset in-order condition, send a packet arbitration request to the P arbitration module of the target port module; or the NP request module is configured to, when detecting that the NP packet satisfies the preset in-order condition, send a packet arbitration request to the NP arbitration module of the target port module; or the CPL request module is configured to, when detecting that the CPL packet satisfies the preset in-order condition, send a packet arbitration request to the CPL arbitration module of the target port module.

12. The PCIe switch of claim 1, wherein, The packet output unit includes: a second in-order unit configured to cache the second TLP packet on a second FIFO memory and perform in-order control processing on all TLP packets of the second FIFO memory; an arbitration output unit configured to acquire a third TLP packet output by the second in-order unit, and in response to the third TLP packet satisfying a second preset arbitration condition, perform a packet output operation based on the third TLP packet.

13. The PCIe switch of claim 12, wherein, The arbitration output unit is configured to, in response to the third TLP message satisfying a second preset arbitration condition, perform a message output operation based on the third TLP message, including: in response to the third TLP message being a PME response message of a PME mechanism, performing a PME mechanism operation; in response to the third TLP message not being the PME response message, the third TLP message being a routing failure message, and a message type of the third TLP message being an NP message type, discarding the third TLP message and outputting a CPL message corresponding to the third TLP message; in response to the third TLP message not being the PME response message and the third TLP message being a routing success message, outputting the third TLP message.

14. The PCIe switch of claim 13, wherein, The arbitration output unit is configured to, in response to the third TLP message being a PME response message of a PME mechanism, perform a PME mechanism operation, including: in response to the third TLP message being a PME response message of a PME mechanism, counting a message quantity of the PME response message received by the arbitration output unit; in response to the message quantity being equal to a quantity of downstream port modules of the PCIe switch, generating a new PME response message and outputting the new PME response message.

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