Reset gate for photodiode

Abstract

The invention discloses a reset gate for a photodiode. Embodiments relate to a buried channel partially covering a reset gate channel for a pixel of a light sensor. The buried channel may reduce a potential barrier between the photodiode and the reset gate such that charge may be discharged from the photodiode region faster during a reset period. This may result in a shorter reset period, so that the frame rate of the global shutter may be improved.

Description

Technical Field

[0001] This disclosure relates to an image sensor, and more specifically to a photosensitive pixel for an image sensor. Background Technology

[0002] Image sensors include a pixel array, which can be implemented as photodiodes arranged in rows and columns. Each photodiode is configured to measure photons during an exposure (i.e., a frame). Image capture can be achieved by addressing the photodiodes row by row; this is known as a rolling shutter. One problem with rolling shutters is that objects moving faster than the frame rate may appear distorted in the image captured by the pixel array. In other words, a fast-moving object might change position within the time it takes to scan from the first row to the last. To eliminate this effect, a global shutter is used. In a global shutter image sensor, all photodiodes in the pixel array are exposed simultaneously before readout, and after readout, all photodiodes are reset before the next frame is exposed. While a global shutter can accurately image fast-moving objects, it reduces the frame rate of the image sensor. Summary of the Invention

[0003] This disclosure describes a photosensitive pixel that can help increase the frame rate of a global shutter image sensor based on a reduced barrier between a photodiode and a reset gate, which allows for faster pixel reset between frames.

[0004] In some aspects, the technology described herein relates to a photosensitive pixel comprising: a channel layer adjacent to a photodiode region and a reset node region, extending in length to fill the space (i.e., area, volume) between the photodiode region and the reset node region; a reset gate adjacent to a top surface of the channel layer and extending in length such that a reset gate voltage applied to the reset gate creates a conductive channel between the photodiode region and the reset node region; and a photodiode extension layer adjacent to a bottom surface of the channel layer opposite the top surface, the photodiode extension layer extending from the photodiode region in an extension length less than the channel length.

[0005] In some aspects, the technology described herein relates to a photosensitive pixel comprising: a photodiode configured to generate charge based on received light; and a reset transistor coupled between the photodiode and a reset node and comprising: a reset gate; a channel layer adjacent to the reset gate at a top surface, the channel layer being configured to create a conductive channel between the photodiode and the reset node when a reset gate voltage is applied to the reset gate; and a buried channel located on a bottom surface of the channel layer opposite the top surface, the buried channel having an extension length less than the channel length of the channel layer in a direction aligned with the conductive channel.

[0006] In some aspects, the technology described herein relates to a method for resetting a photosensitive pixel, the method comprising: generating a charge in a photodiode region of the photosensitive pixel; applying a reset voltage to a reset node region of the photosensitive pixel, the reset node region being separated from the photodiode region by a channel layer, the photosensitive pixel including a photodiode extension layer partially covering the bottom surface of the channel layer; applying a reset gate voltage to a reset gate adjacent to the channel layer; generating a conductive channel between the photodiode region and the reset node region in response to the reset gate voltage; and discharging the charge from the photodiode region through the conductive channel to reset the photosensitive pixel.

[0007] The foregoing illustrative invention, as well as other exemplary objectives and / or advantages and implementation methods of this disclosure, are further explained in the following detailed description and accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a diagram of an exemplary imaging and response system, which includes an imaging system that captures images using an image sensor.

[0009] Figure 2 yes Figure 3 An example of the arrangement of image sensors is shown.

[0010] Figure 3 This is a schematic block diagram of an image sensor that may be implemented according to this disclosure.

[0011] Figure 4 This is a diagram showing the timing of frames of an image sensor according to a possible implementation of this disclosure.

[0012] Figure 5 This is a schematic diagram of the photosensitive pixels of an image sensor according to a possible implementation of this disclosure.

[0013] Figure 6 This is a top view of a photosensitive pixel that may be implemented according to this disclosure.

[0014] Figure 7A This is a cross-sectional view of the transfer gate portion of a photosensitive pixel according to a possible implementation of this disclosure.

[0015] Figure 7B This is a cross-sectional view of the reset gate portion of a photosensitive pixel according to a possible implementation of this disclosure.

[0016] Figure 8A This is a cross-sectional view illustrating the drain path of the reset gate portion of a photosensitive pixel that does not have a photodiode extension layer.

[0017] Figure 8B This is a cross-sectional view illustrating the drain path of the reset gate portion of a photosensitive pixel with a photodiode extension layer.

[0018] Figure 9 This is a diagram illustrating the potential barrier along the drain path of photosensitive pixels having and not having photodiode extension layers, according to possible implementations of this disclosure.

[0019] Figure 10 This is a diagram illustrating the reset period of photosensitive pixels with and without photodiode extension layers, according to possible implementations of this disclosure.

[0020] Figure 11 This is a flowchart of a method for resetting photosensitive pixels according to an embodiment of this disclosure.

[0021] The components in the accompanying drawings are not necessarily drawn to scale relative to each other. Similar reference numerals may be used in several drawings to indicate corresponding parts. Detailed Implementation

[0022] Embodiments of the present invention relate to image sensors. Those skilled in the art will understand that exemplary embodiments of the invention can be practiced without some or all of these specific details. In other instances, well-known operations have not been described in detail to avoid unnecessarily obscuring embodiments of the invention.

[0023] Electronic devices such as digital cameras, computers, mobile phones, and other electronic devices may include image sensors that collect incoming light to capture images. Image sensors may include pixel arrays. Pixels in an image sensor may include photosensitive elements, such as photodiodes, that convert incoming light into image signals. Image sensors may have any number (e.g., hundreds, thousands, or more) of pixels. Typical image sensors may, for example, have hundreds, thousands, or millions of pixels (e.g., megapixels). Image sensors may include control circuitry (such as circuitry for manipulating the pixels) and readout circuitry for reading out image signals corresponding to the charges generated by the photosensitive elements.

[0024] Figure 1 This is a diagram of an exemplary imaging and response system, which includes an imaging system that captures images using an image sensor. Figure 1 The system 100 may be an electronic device, such as a camera, cellular phone, video camera or other electronic device that captures digital image data, may be a vehicle safety system (e.g., an active braking system or other vehicle safety system), or may be a surveillance system.

[0025] like Figure 1 As shown, system 100 may include an imaging system (such as imaging system 10) and a host subsystem (such as host subsystem 20). Imaging system 10 may include camera module 12. Camera module 12 may include one or more image sensors 14, such as those in an image sensor array integrated circuit, and one or more lenses. During image capture operation, each lens may focus light onto its associated image sensor 14. Image sensor 14 may include photosensitive elements (i.e., image sensor pixels) that convert light into analog data. Image sensors may have any number (e.g., hundreds, thousands, millions, or more) of pixels. A typical image sensor may, for example, have millions of pixels (e.g., megapixels).

[0026] Each image sensor in camera module 12 may be identical, or different types of image sensors may exist in a given image sensor array integrated circuit. In some examples, image sensor 14 may also include bias circuitry (e.g., source follower load circuitry), sample and hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital converter circuitry, data output circuitry, memory (e.g., buffer circuitry), and / or addressing circuitry.

[0027] Still and video image data from image sensor 14 can be provided to image processing and data formatting circuitry 16 via path 28. Image processing and data formatting circuitry 16 can be used to perform image processing functions such as data formatting, adjusting white balance and exposure, implementing video image stabilization, or face detection. Image processing and data formatting circuitry 16 can additionally or alternatively be used to compress raw camera image files when needed (e.g., compressing to Joint Photographic Experts Group or JPEG format).

[0028] In an exemplary arrangement, such as a system-on-a-chip (SoC) arrangement, sensor 14 and image processing and data formatting circuitry 16 are implemented on a common semiconductor substrate (e.g., a common silicon image sensor integrated circuit die). If desired, sensor 14 and image processing circuitry 16 may be formed on separate semiconductor substrates. For example, sensor 14 and image processing circuitry 16 may be formed on separate, stacked substrates.

[0029] Imaging system 10 can transmit acquired image data to host subsystem 20 via path 18. Host subsystem 20 may include input-output device 22 and storage and processing circuitry 24. Host subsystem 20 may include processing software for detecting objects in the image, detecting motion of objects between image frames, determining distances to objects in the image, or filtering or otherwise processing the image provided by imaging system 10. For example, image processing and data formatting circuitry 16 of imaging system 10 can transmit acquired image data to storage and processing circuitry 24 of host subsystem 20.

[0030] If needed, system 100 can provide users with many advanced functions. For example, in a computer or mobile phone, it can provide users with the ability to run user applications. For these functions, the input-output devices 22 of the host subsystem 20 may include a keyboard, input-output ports, buttons, and a display, as well as storage and processing circuitry 24. The storage and processing circuitry 24 of the host subsystem 20 may include volatile memory and / or non-volatile memory (e.g., random access memory, flash memory, hard disk drive, solid-state drive, etc.). The storage and processing circuitry 24 may additionally or alternatively include a microprocessor, microcontroller, digital signal processor, and / or application-specific integrated circuit.

[0031] Figure 2 It shows Figure 1 An example of the arrangement of the image sensor 14. For example... Figure 2 As shown, the image sensor 14 may include control and processing circuitry 44. Control and processing circuitry 44 (sometimes referred to as control and processing logic) may be... Figure 1 The image processing and data formatting circuitry 16 may be part of, or separate from, the image sensor 14. The image sensor 14 may include an array of pixels, such as an array 32 of pixels 34 (sometimes referred to herein as image sensor pixels, imaging pixels, or image pixels). The control and processing circuitry 44 may be coupled to the row control circuitry 40 via control path 27 and to the column control and readout circuitry 42 via data path 26.

[0032] The line control circuit 40 can receive a line address from the control and processing circuit 44 and can provide the corresponding line control signal to the image pixel 34 through one or more control paths 36. The line control signal may include a pixel reset control signal, a charge transfer control signal, an overflow control signal, a line selection control signal, a double conversion gain control signal, or any other desired pixel control signal.

[0033] Column control and readout circuitry 42 may be coupled to one or more columns of pixel array 32 via one or more wires (such as column lines 38). A given column line 38 may be coupled to a column of image pixels 34 in image pixel array 32 and may be used to read image signals from image pixels 34 and to provide bias signals (e.g., bias current or bias voltage) to image pixels 34. In some examples, each pixel column may be coupled to a corresponding column line 38. For image pixel readout operations, row driver circuitry 40 may be used to select a pixel row in image pixel array 32, and image data associated with the image pixels 34 of that pixel row may be read out by column readout circuitry 42 on column line 38. Column readout circuitry 42 may include column circuitry, such as column amplifiers for amplifying signals read from array 32, sample-and-hold circuitry for sampling and storing signals read from array 32, analog-to-digital converter circuitry for converting readout analog signals into corresponding digital signals, or column memory for storing readout signals and any other desired data. The column control and readout circuit 42 can output the digital pixel readout value to the control and processing logic unit 44 via line 26.

[0034] Array 32 may have any number of rows and columns. Generally, the size of array 32 and the number of rows and columns in array 32 will depend on the specific implementation of image sensor 14. Although rows and columns are generally described herein as horizontal and vertical, respectively, rows and columns may refer to any grid-like structure. Features described herein as rows may be arranged vertically, and features described herein as columns may be arranged horizontally.

[0035] Pixel array 32 may include a color filter array with multiple color filter elements, which allows a single image sensor to sample different colors of light. For example, image sensor pixels (such as image pixels in array 32) may include a color filter array that allows a single image sensor to sample red, green, and blue light (RGB) using corresponding red, green, and blue image sensor pixels. The red, green, and blue image sensor pixels may be arranged in a Bayer mosaic pattern. A Bayer mosaic pattern consists of repeating cells of 2×2 image pixels, where two green image pixels are diagonally opposite each other and adjacent to a red image pixel diagonally opposite a blue image pixel. In another example, wideband image pixels with wideband color filter elements (e.g., transparent color filter elements) may be used instead of the green pixels in the Bayer pattern. These examples are merely illustrative, and in general, color filter elements of any desired color (e.g., cyan, yellow, red, green, blue, etc.) and any desired pattern can be formed on any desired number of image pixels 34.

[0036] Image sensors typically include imaging pixels configured to sense visible light (e.g., light in the visible spectrum from approximately 580 nm to 900 nm). Some imaging applications employ near-infrared (NIR) sensors, which include imaging pixels configured to sense NIR light in the near-infrared spectrum from approximately 950 nm to 1000 nm. However, NIR sensing requires the emission of NIR light in the 950 nm to 1000 nm range, and if not handled carefully, NIR light can potentially cause eye damage.

[0037] Image sensor pixels can accumulate charge, which can negatively impact light sensing during the exposure period of a frame. Therefore, pixels can be reset before exposure to remove unwanted charge. To reset a pixel, the photodiode of the image sensor can be electrically coupled to a reset voltage via a conductive channel created by the reset gate of the image sensor. When the reset gate is turned on, charge may flow as current through the conductive channel to the reset voltage source. This flow may continue throughout the reset period until the charge is removed. A long reset period is a technical problem because it limits the maximum frame rate of the image sensor, and increasing the reset voltage to reduce the reset period may not be a practical solution because higher voltages may violate reliability standards. This disclosure describes an image sensor that shortens the reset period without using high voltage. The technical effect of the disclosed image sensor can be to increase the frame rate of an image sensor with a global shutter and / or to more completely reset the image sensor. The technical advantage of this approach is that this reset performance can be achieved without adding any steps to the image sensor during the manufacturing process.

[0038] Figure 3 This is a schematic block diagram of an image sensor according to a possible implementation of the present disclosure. Image sensor 300 may include a photosensitive pixel array (i.e., pixel array 305). Each photosensitive pixel (i.e., pixel) is configured to generate a charge corresponding to light incident on that pixel. The charge may be converted into a voltage, which may be amplified by an amplifier 350 at the output of image sensor 300.

[0039] The photosensitive pixel 500 can be addressed based on its row and column in the pixel array 305. For example, the photosensitive pixel 500 can be coupled (e.g., via one or more switches) to a word line 302 corresponding to a row in the pixel array 305. The photosensitive pixel 500 can also be coupled (e.g., via one or more switches) to a bit line 301 corresponding to a column in the pixel array 305.

[0040] All pixels can be exposed simultaneously (i.e., global shutter) to generate a certain amount of charge in each pixel based on the light at each pixel. The charge generated in each photosensitive pixel 500 can be read out row by row and column by column (i.e., output). For example, to read out the charge from the photosensitive pixel 500, the controller 340 can configure the word line driver 320 to couple the photosensitive pixels in the row to their corresponding bit lines. The controller 340 can also configure the bit line driver 330 to sequentially transfer the charge to the amplifier 350 for each pixel in the row. The amplifier 350 can be configured to output a voltage corresponding to the charge of each pixel.

[0041] A frame may include the exposure and readout of all pixels in pixel array 305. In image sensor 300 with a global shutter, all pixels are exposed simultaneously. The global shutter has advantages over line-by-line exposure methods (e.g., rolling shutter) because it reduces (e.g., eliminates) artifacts caused by moving objects. The global shutter may take longer than the rolling shutter because the readout of all lines occurs before the start of the next frame.

[0042] Light can be focused (i.e., imaged) onto pixel array 305 so that image sensor 300 can generate a two-dimensional image corresponding to the focused light frame by frame. The speed at which images can be captured is called the frame rate, and it may be necessary to increase the frame rate to capture fast-moving objects.

[0043] Figure 4 This is a diagram illustrating the timing of frames of an image sensor according to a possible implementation of the present disclosure. The image sensor includes a global shutter, wherein all rows are exposed during exposure period 412 before the start of readout period 413.

[0044] like Figure 4 As shown, during exposure period 412, all rows of pixel array 305 are exposed simultaneously. During exposure period 412, the photodiodes in each pixel generate and accumulate charge based on photons of the light received during exposure period 412. In addition to exposure period 405, exposure period 412 also includes transfer period 404 (i.e., TRAN.), during which the charge accumulated in the photodiode region of the photosensitive pixel during exposure period 405 is transferred to the storage node of the photosensitive pixel.

[0045] like Figure 4 As shown, the frame 410 of the global shutter image sensor also includes a readout period 413. Each row can be read out sequentially (e.g., from top row to bottom row) such that the readout period 413 can be the cumulative sum of the readout periods 403 for each row.

[0046] like Figure 4As shown, frame 410 also includes a reset period 411. All rows in pixel array 305 can be reset simultaneously. During reset period 411, the charge in pixels attributable to sources (e.g., thermal noise, dark current, etc.) is discharged (e.g., reset) before the start of exposure period 412 in the frame. Resetting can reduce noise in the captured image and increase the dynamic range of image sensor 300, but it ultimately limits the speed (i.e., frame rate) of image sensor 300, especially when reset period 411 is long (e.g., relative to frame 410). Therefore, minimizing reset period 411 may help improve the performance of image sensor 300.

[0047] Figure 5 This is a schematic diagram of a photosensitive pixel of an image sensor according to a possible implementation of the present disclosure. The photosensitive pixel 500 includes a photodiode 520 configured to undergo a change (i.e., charge carriers) due to exposure to light 525.

[0048] The photosensitive pixel 500 also includes a transfer transistor 510 controlled by a transfer gate signal (TG) at the transfer gate. During the row readout period 403, the transfer gate signal (TG) can configure the transfer transistor 510 to be in an ON state. As shown, the transfer transistor 510 may be an n-type metal-oxide-semiconductor transistor (MOSFET) configured to conduct charge (i.e., current) through a conductive channel between the source and drain terminals, while the transfer gate signal (TG) generates a voltage higher than a threshold voltage of the transfer transistor 510. Therefore, when in the ON state, the transfer transistor 510 can electrically couple a photodiode 520 to a storage node (SN) such that the charge generated by the photodiode 520 can be stored in a storage node capacitor 515 for readout. Readout may include driving a word line 302 to configure a row select transistor 511 to be in an ON state such that the charge stored in the storage node capacitor 515 can be coupled to a bit line 301 via a buffer amplifier 521.

[0049] The photosensitive pixel 500 also includes a reset transistor 530 controlled by a reset gate signal (RG) at the reset gate. During the reset period 411, the reset gate signal (RG) can configure the reset transistor 530 to be in an ON state. As shown, the reset transistor 530 may be an n-type metal-oxide-semiconductor transistor (MOSFET) configured to conduct charge (i.e., current) through a conductive channel between the source and drain terminals, while the reset gate signal (RG) generates a voltage higher than the threshold voltage of the transfer transistor 510. Therefore, when in the ON state, the reset transistor 530 can electrically couple the photodiode 520 to the reset node (RN) so that unwanted charge generated by the photodiode 520 can be conducted to the reset voltage source 540. In other words, a reset voltage (VR) is applied to the reset node (RN) during the reset period to discharge charge from the photodiode through the conductive channel created in the reset transistor 530 by the reset gate signal (RG).

[0050] At the end of reset period 411, some charge may remain in the conductive channel of reset transistor 530. To prevent this charge from flowing back into photodiode 520 (i.e., overflow), a barrier 535 is configured between the conductive channel of reset transistor 530 and photodiode 520. In other words, the barrier makes conduction during reset unidirectional (i.e., one-way). While helping to prevent overflow, the barrier also resists the flow of charge during reset. In other words, the barrier counteracts the charge dissipation effect of the reset voltage at the reset node. Therefore, the emission rate of photodiode 520 may be reduced due to barrier 535. Methods to increase the reset voltage to overcome this reduction may be limited by safety and reliability concerns. Therefore, reset period 411 may be longer than required for some applications. Photosensitive pixel 500 includes structures for reducing barrier 535, thereby increasing the emission rate of photodiode 520 during reset period 411. The disclosed reduction amount can be selected to balance overflow protection and reset speed.

[0051] Figure 6 This is a top view of a photosensitive pixel according to a possible implementation of the present disclosure. The photosensitive pixel 500 includes a photodiode region 610. The photosensitive pixel 500 also includes a transfer gate 630 configured to create a conductive channel beneath the transfer gate 630 between the photodiode region 610 and the memory node region 637 when a voltage (i.e., a transfer gate signal) is applied to the transfer gate 630. The photosensitive pixel 500 includes an anti-overflow layer 635 beneath the transfer gate 630. The anti-overflow layer 635 may be configured as a drain for excess charge generated by the photodiode region 610 during exposure period 412, to prevent such excess charge from overflowing into adjacent pixels.

[0052] like Figure 6 As shown, the photosensitive pixel 500 also includes a reset gate 620 configured to create a conductive channel beneath the reset gate 620 between the photodiode region 610 and the reset node region 627 when a voltage (i.e., a reset gate signal) is applied to the reset gate 620. The photosensitive pixel 500 includes a photodiode extension layer 625 located beneath the reset gate 620. The photodiode extension layer can be configured to lower the potential barrier between the photodiode region 610 and the conductive channel beneath the reset gate 620. The photosensitive pixel 500 is a multilayer semiconductor device. The photodiode extension layer 625 and the spill prevention layer 635 may be located on the same layer among multiple layers.

[0053] The regions in the following exemplary figures may be spatially specified as they appear in the figures, with terms such as top, upper, front, or above used to indicate features on the page that are above features specified by terms such as bottom, lower, back, or below. In practice, the shape and size of the regions may vary without departing from the basic spatial relationships shown and described herein.

[0054] The following exemplary diagrams illustrate portions of a silicon device, where regions and layers are designated based on their doping. Doping can be performed using semiconductor processes such as ion implantation. An ion implantation process involves masking a silicon substrate and implanting ions into unmasked regions.

[0055] Figure 7A This is a cross-sectional view of the transfer gate portion of a photosensitive pixel according to a possible implementation of the present disclosure. The transfer gate portion 700 of the photosensitive pixel 500 includes multiple regions and layers. The transfer gate portion 700 includes a photodiode region 610. The photodiode region 610 may be an n-type (e.g., with a carrier concentration of approximately 1 × 10⁻⁶) configured to collect photogenerated electrons. 16 / cm 3 The photodiode region may be located in the p-well region 710 of the n-type region configured as an isolation device (e.g., with a carrier concentration of approximately 1 × 10⁻⁶). 17 / cm 3 Between the p-type). Pinning layer 720 (e.g., carrier concentration approximately 1 × 10⁻⁶). 18 / cm 3 The p+ type photodiode is located on the top surface of the photodiode region 610 and is configured to provide surface passivation to reduce dark current in the photodiode region 610 attributable to the air-surface interface. The transfer gate portion 700 also includes a transfer channel layer 740 (e.g., with a carrier concentration of approximately 3 × 10⁻⁶). 17 / cm 3The transfer channel layer consists of a photodiode region 610 and a storage node region 637 (n+ type, with a carrier concentration of approximately 1 × 10⁻⁶). 20 / cm 3 The transfer gate portion 700 also includes an overflow prevention layer 635 (i.e., an overflow prevention channel, a buried channel) located at the bottom surface of the transfer channel layer 740. The bottom surface of the channel layer is opposite to the top surface of the channel layer. The overflow prevention layer 635 extends along the bottom surface of the transfer channel layer 740 between the photodiode region 610 and the storage node region 637. In other words, the overflow prevention layer 635 has an overflow prevention channel length 636 equal to the channel length of the transfer channel layer 740.

[0056] The transfer gate portion 700 also includes a transfer gate 630. The transfer gate includes a transfer gate electrode 731 (e.g., with a carrier concentration of 1 × 10⁻⁶). 18 / cm 3 The transfer gate electrode (a p-type polysilicon n-type gate) is separated from the top surface of the transfer channel layer 740 by a transfer gate oxide layer 732. The transfer gate oxide layer isolates the p-type channel layer from the polysilicon gate electrode. In other words, the transfer gate 630 and the transfer channel layer 740 form a metal-oxide-semiconductor (MOS) gate that, when a voltage is applied to the transfer gate electrode 731, creates a conductive channel (e.g., an inversion layer) between the photodiode region 610 and the memory node region 637. When no voltage is applied to the transfer gate electrode 731 to suppress dark current, the conductive channel can be turned off. The anti-overflow layer 635 can be configured as a junction field-effect transistor connected in parallel with the MOS gate to extract excess charge (e.g., electrons) from the photodiode region 610.

[0057] Figure 7B This is a cross-sectional view of the reset gate portion of a photosensitive pixel according to a possible implementation of the present disclosure. The reset gate portion 750 of the photosensitive pixel 500 includes multiple regions and layers. The reset gate portion 750 includes a photodiode region 610. As shown, the photodiode region (i.e., the photodiode) is located between p-well regions 710. A pinning layer 720 is located on the top surface of the photodiode region 610. The reset gate portion 750 also includes a transfer channel layer 740 (i.e., a reset channel layer) that connects the photodiode region 610 to the reset node region 627 (with a carrier concentration of approximately 1 × 10⁻⁶). 20 / cm 3 The overflow prevention channel length 636 extends between the n+ type. The reset node region 627 can be coupled to the reset power supply (i.e., the reset voltage source (V)). R )).

[0058] The reset gate portion 750 also includes a photodiode extension layer 625 (i.e., a partially buried channel) located on the bottom surface of the reset channel layer 760. The photodiode extension layer 625 extends from the photodiode region 610 along a portion of the bottom surface of the reset channel layer 760. In other words, the photodiode extension layer 625 has an extension length 656 that is less than the channel length 686 between the photodiode region 610 and the reset node region 627. The extension length 656 may be in the range of approximately 1 / 4 to 3 / 4 of the channel length. For example, the extension length 656 may be 1 / 2 of the channel length 686.

[0059] The reset gate portion 750 also includes a reset gate 620. The reset gate 620 includes a reset gate electrode 761 (e.g., with a carrier concentration of 1 × 10⁻⁶). 18 / cm 3 (Polycrystalline silicon n-type), the reset gate electrode is connected to the reset gate oxide layer 762 and the reset channel layer 760 (e.g., the carrier concentration is approximately 3 × 10⁻⁶). 17 / cm 3 The top surface of the p-type channel layer is separated from the polysilicon gate electrode. The reset gate oxide layer isolates the p-type channel layer from the polysilicon gate electrode. In other words, the reset gate 620 and the reset channel layer 760 form a metal-oxide-semiconductor (MOS) gate that, when a voltage is applied to the reset gate electrode 761, creates a conductive channel (e.g., an inversion layer) between the photodiode region 610 and the reset node region 627. When no voltage is applied to the reset gate electrode 761 for conduction, the conductive channel can be turned off.

[0060] The photodiode extension layer 625 may be shorter than the overflow prevention layer 635. The photodiode extension layer 625 and the overflow prevention layer 635 may be located on the same layer (i.e., a common layer) of the photosensitive pixel. A single mask can be used to fabricate both the photodiode extension layer 625 and the overflow prevention layer 635. In other words, the photodiode extension layer 625 can be added to the photosensitive pixel 500 having the overflow prevention layer 635 without significantly affecting the manufacturing process.

[0061] Figure 8A This is a cross-sectional view showing the drain path ([z]-[z']) of the reset gate portion of a photosensitive pixel without a photodiode extension layer (i.e., without a buried channel). As shown, when a reset gate voltage (V) is applied to the reset gate, a conductive channel 810 is generated in the reset channel layer. The conductive channel 810 is configured to discharge (i.e., conduct) charge from the photodiode region along the drain path 820 to the conductive channel 810.

[0062] Figure 8BThis is a cross-sectional view showing the drain path ([z]-[z']) of the reset gate portion of a photosensitive pixel having a photodiode extension layer (i.e., a buried channel). As shown, when a reset gate voltage (V) is applied to the reset gate, a conductive channel 810 is generated in the reset channel layer. The conductive channel 810 is configured to discharge (i.e., conduct) charge from the photodiode region along the drain path 820 to the conductive channel 810.

[0063] Figure 9 This is a diagram illustrating the potential barrier along the drain path 820 ([z]-[z']) in embodiments without a photodiode extension layer (i.e., [A]) and with a photodiode extension layer (i.e., [B]). The diagram shows the potential barrier along... Figure 8A and Figure 8B The potential of the drain path 820 is shown. The barrier is defined as the potential difference between the photodiode and the conductive channel (i.e., the n-type inversion layer). As shown, the first barrier 910 without the photodiode extension layer (see figure) Figure 8A The second barrier 920 with a photodiode extension layer is greater than that (see...). Figure 8B ).

[0064] Figure 10 This diagram illustrates the reset periods of photosensitive pixels with and without a photodiode extension layer according to possible implementations of the present disclosure. As shown, the reset voltage 1010 is turned on at the beginning of the reset period (e.g., rising from a negative voltage to a positive voltage). As shown, when the photodiode extension layer is present (i.e., [B]), charge is discharged at a first discharge rate, while when the photodiode extension layer is absent (i.e., [A]), charge is discharged at a second discharge rate. Therefore, when a photodiode extension layer is included, the reset period for complete discharge of charge from the photodiode may be shorter.

[0065] Figure 11 This is a flowchart of a method for resetting a photosensitive pixel according to an embodiment of the present disclosure. Method 1100 includes generating a charge 1110 in a photodiode region of the photosensitive pixel. Method 1100 further includes applying a reset voltage to a reset node region 1120 to discharge the generated charge. The reset node region is separated from the photodiode region by a channel layer having a channel length, and a photodiode extension layer partially covers the bottom surface of the channel layer. In other words, the extension length of the photodiode extension layer is less than the channel length. Method 1100 further includes applying a reset gate voltage 1130 to a reset gate adjacent to the channel layer between the photodiode region and the reset node region. Method 1100 further includes generating a conductive channel 1140 in the channel layer between the photodiode region and the reset node region in response to the reset gate voltage. Method 1100 further includes discharging a charge 1150 from the photodiode region through the conductive channel to reset the photosensitive pixel.

[0066] Therefore, one aspect of the present invention discloses a photosensitive pixel, the photosensitive pixel comprising:

[0067] A channel layer adjacent to the photodiode region and the reset node region, and extending the channel length to fill the space between the photodiode region and the reset node region;

[0068] A reset gate, the reset gate being adjacent to the top surface of the channel layer and extending the channel length, such that a reset gate voltage applied to the reset gate creates a conductive channel between the photodiode region and the reset node region; and

[0069] A photodiode extension layer is provided, which is adjacent to the bottom surface of the channel layer opposite to the top surface, and extends from the photodiode region with an extension length less than the channel length.

[0070] According to one embodiment of the photosensitive pixel described above, during the reset period, a reset voltage is applied to the reset node region to discharge charge from the photodiode region through the conductive channel at a certain discharge rate.

[0071] According to one embodiment of the photosensitive pixel described above, the photodiode extension layer reduces the potential barrier between the photodiode region and the conductive channel to increase the discharge rate.

[0072] According to one embodiment of the photosensitive pixel described above, the conductive channel is an inversion layer adjacent to the reset gate at the top surface of the channel layer.

[0073] According to one embodiment of the above-described photosensitive pixel, the photodiode region is an n-type semiconductor, the reset node region is an n-type semiconductor, and the channel layer is a p-type semiconductor.

[0074] According to one embodiment of the photosensitive pixel described above, the extension length is in the range of 1 / 4 to 3 / 4 of the channel length.

[0075] According to one embodiment of the above-described photosensitive pixel, the reset gate includes an insulating oxide layer located between the top surface of the channel layer and the n-type polysilicon gate electrode.

[0076] According to one embodiment of the photosensitive pixel described above, wherein the channel layer is a first channel layer and the conductive channel is a first conductive channel, the photosensitive pixel further includes: a second channel layer, the second channel layer being adjacent to the photodiode region and adjacent to the memory node region, and extending the second channel length to fill the region between the photodiode region and the memory node region; and an anti-overflow layer, the anti-overflow layer being adjacent to the bottom surface of the second channel layer opposite to the top surface of the second channel layer, the anti-overflow layer extending the second channel length from the photodiode region to the memory node region.

[0077] According to one embodiment of the above-described photosensitive pixel, the photodiode extension layer and the spill prevention layer are located on a common manufacturing layer of the photosensitive pixel.

[0078] According to one embodiment of the photosensitive pixel described above, the photosensitive pixel further includes a transfer gate, the transfer gate being adjacent to the top surface of the second channel layer and extending the length of the second channel, such that a transfer gate voltage applied to the transfer gate generates a second conductive channel between the photodiode region and the memory node region.

[0079] Another aspect of the present invention discloses a photosensitive pixel, the photosensitive pixel comprising:

[0080] A photodiode, the photodiode being configured to generate charge based on received light; and

[0081] A reset transistor coupled between the photodiode and a reset node, and the reset transistor comprising:

[0082] Reset gate;

[0083] A channel layer, adjacent to the reset gate at its top surface, is configured to create a conductive channel between the photodiode and the reset node when a reset gate voltage is applied to the reset gate; and

[0084] A burial trench is located on the bottom surface of the trench layer opposite the top surface, and the burial trench has an extension length in a direction aligned with the conductive trench that is less than the trench length of the trench layer.

[0085] According to one embodiment of the photosensitive pixel described above, during the reset period, a reset voltage is applied to the reset node when the reset gate voltage is applied to the reset gate, thereby discharging the charge from the photodiode through the conductive channel at a discharge rate.

[0086] According to one embodiment of the above-described photosensitive pixel, the buried trench reduces the potential barrier between the photodiode and the reset transistor to increase the discharge rate.

[0087] According to one embodiment of the photosensitive pixel described above, the conductive channel is an inversion layer in the channel layer.

[0088] According to one embodiment of the photosensitive pixel described above, the reset transistor is an n-type metal-oxide-semiconductor field-effect transistor.

[0089] According to one embodiment of the photosensitive pixel described above, the extension length is in the range of 1 / 4 to 3 / 4 of the channel length.

[0090] According to one embodiment of the photosensitive pixel described above, wherein the channel layer is a first channel layer and the conductive channel is a first conductive channel, the photosensitive pixel further includes: a transfer transistor coupled between the photodiode and the memory node, the transfer transistor including: a transfer gate; a second channel layer adjacent to the transfer gate on a top surface of the second channel layer, the second channel layer being configured to generate a second conductive channel between the photodiode and the memory node when a transfer gate voltage is applied to the transfer gate; and an overflow prevention channel located on a bottom surface of the second channel layer opposite to the top surface, the overflow prevention channel extending a length longer than the extended length of the overflow prevention channel.

[0091] According to one embodiment of the above-described photosensitive pixel, the buried trench and the anti-overflow trench are formed on the common layer of the photosensitive pixel.

[0092] In another aspect, the present invention discloses a method for resetting photosensitive pixels, the method comprising:

[0093] Charge is generated in the photodiode region of the photosensitive pixel;

[0094] A reset voltage is applied to the reset node region of the photosensitive pixel, the reset node region being separated from the photodiode region by a channel layer, and the photosensitive pixel including a photodiode extension layer that partially covers the bottom surface of the channel layer;

[0095] A reset gate voltage is applied to the reset gate adjacent to the channel layer;

[0096] A conductive channel is generated between the photodiode region and the reset node region in response to the reset gate voltage; and

[0097] The charge is discharged from the photodiode region through the conductive channel to reset the photosensitive pixel.

[0098] According to one embodiment of the above method, the photodiode extension layer that partially covers the bottom surface of the channel layer lowers the barrier to reduce the time required to reset the photosensitive pixel.

[0099] Typical embodiments have been disclosed in the specification and / or drawings. This disclosure is not limited to such exemplary embodiments. The use of the term "and / or" includes any and all combinations of one or more of the associated listed items. The drawings are schematic representations and therefore not necessarily drawn to scale. Unless otherwise stated, particular terms are used in a general and descriptive sense and not for limiting purposes.

[0100] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Methods and materials similar to or equivalent to those described herein may be used in practice or testing of this disclosure. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include multiple referents unless the context clearly specifies otherwise. The term “comprising” and its variations are used synonymously with the term “comprising” and its variations as used herein and are open-ended, non-limiting terms. The terms “optional” or “optionally” as used herein mean that a feature, event, or condition subsequently described may or may not occur, and the description includes instances where the feature, event, or condition occurs and instances where it does not occur. Scopes may be expressed herein as from “about” a particular value and / or to “about” another particular value. When such a scope is expressed, an aspect includes from one particular value and / or to another particular value. Similarly, when a value is expressed as an approximate value using the antecedent “about,” it should be understood that the particular value forms another aspect. It should also be understood that each endpoint of a range is significant relative to another endpoint and independent of the other endpoint.

[0101] Some specific implementations can be achieved using various semiconductor processing and / or packaging technologies. Some specific implementations can be achieved using various types of semiconductor processing technologies associated with a semiconductor substrate, including but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0102] While certain features of the described embodiments have been illustrated herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of the embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and various changes in form and detail are possible. Any parts of the apparatus and / or method described herein can be combined in any way, except for mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

[0103] It will be understood that in the foregoing description, when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to the other element, or one or more intermediate elements may be present. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled to another element, no intermediate elements are present. Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used throughout the specific embodiments, elements shown as being directly on, directly connected to, or directly coupled to an element can be referred to in this manner. The claims of this application, if any, may be amended to state the exemplary relationships described in the specification or shown in the drawings.

[0104] As used herein, the singular form may include the plural form unless the context clearly indicates otherwise. In addition to the orientations shown in the figures, spatial relative terms (e.g., above, on, above, below, under, beneath, etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms above and below may respectively include vertically above and vertically below. In some embodiments, the term proximity may include lateral proximity or horizontal proximity.

Claims

1. A photosensitive pixel, the photosensitive pixel comprising: A channel layer adjacent to the photodiode region and the reset node region, and extending the channel length to fill the space between the photodiode region and the reset node region; A reset gate, the reset gate being adjacent to the top surface of the channel layer and extending the channel length, such that a reset gate voltage applied to the reset gate creates a conductive channel between the photodiode region and the reset node region; and A photodiode extension layer is provided, which is adjacent to the bottom surface of the channel layer opposite to the top surface, and extends from the photodiode region with an extension length less than the channel length.

2. The photosensitive pixel according to claim 1, wherein: During the reset period, a reset voltage is applied to the reset node region to discharge charge from the photodiode region through the conductive channel at a discharge rate.

3. The photosensitive pixel of claim 2, wherein the photodiode extension layer reduces the potential barrier between the photodiode region and the conductive channel to increase the discharge rate.

4. The photosensitive pixel according to claim 1, wherein the conductive channel is an inversion layer adjacent to the reset gate at the top surface of the channel layer.

5. The photosensitive pixel according to claim 1, wherein the photodiode region is an n-type semiconductor, the reset node region is an n-type semiconductor, and the channel layer is a p-type semiconductor.

6. The photosensitive pixel according to claim 1, wherein the extension length is in the range of 1 / 4 to 3 / 4 of the channel length.

7. The photosensitive pixel according to claim 1, wherein the reset gate comprises: An insulating oxide layer is located between the top surface of the channel layer and the n-type polysilicon gate electrode.

8. The photosensitive pixel according to claim 1, wherein the channel layer is a first channel layer and the conductive channel is a first conductive channel, and the photosensitive pixel further comprises: A second channel layer is adjacent to the photodiode region and the memory node region, and extends the length of the second channel to fill the area between the photodiode region and the memory node region. and An overflow prevention layer is provided, which is adjacent to the bottom surface of the second channel layer opposite to the top surface of the second channel layer, and extends the length of the second channel from the photodiode region to the storage node region.

9. The photosensitive pixel according to claim 8, wherein: The photodiode extension layer and the spill prevention layer are located on the common manufacturing layer of the photosensitive pixel.

10. The photosensitive pixel according to claim 8, wherein the photosensitive pixel further comprises: A transfer gate, the transfer gate being adjacent to the top surface of the second channel layer and extending the length of the second channel, such that a transfer gate voltage applied to the transfer gate creates a second conductive channel between the photodiode region and the memory node region.

11. A photosensitive pixel, the photosensitive pixel comprising: A photodiode configured to generate charge based on received light; and A reset transistor coupled between the photodiode and a reset node, and the reset transistor comprising: Reset gate; A channel layer, adjacent to the reset gate at its top surface, is configured to create a conductive channel between the photodiode and the reset node when a reset gate voltage is applied to the reset gate; and A buried trench located on the bottom surface of the trench layer opposite the top surface, the buried trench having an extension length less than the trench length of the trench layer in a direction aligned with the conductive trench.

12. The photosensitive pixel according to claim 11, wherein: During the reset period, a reset voltage is applied to the reset node when the reset gate voltage is applied to the reset gate, thereby discharging the charge from the photodiode through the conductive channel at a discharge rate.

13. The photosensitive pixel of claim 12, wherein the buried trench lowers the potential barrier between the photodiode and the reset transistor to increase the discharge rate.

14. The photosensitive pixel according to claim 11, wherein the conductive channel is an inversion layer in the channel layer.

15. The photosensitive pixel according to claim 11, wherein the reset transistor is an n-type metal-oxide-semiconductor field-effect transistor.

16. The photosensitive pixel of claim 11, wherein the extension length is in the range of 1 / 4 to 3 / 4 of the channel length.

17. The photosensitive pixel of claim 11, wherein the channel layer is a first channel layer and the conductive channel is a first conductive channel, and the photosensitive pixel further comprises: A transfer transistor, coupled between the photodiode and the storage node, the transfer transistor comprising: Transfer gate; A second channel layer, the second channel layer being adjacent to the transfer gate on its top surface, the second channel layer being configured to create a second conductive channel between the photodiode and the memory node when a transfer gate voltage is applied to the transfer gate; and An overflow prevention channel is located on the bottom surface of the second channel layer opposite to the top surface, and the overflow prevention channel extends for a length longer than the extension length.

18. The photosensitive pixel according to claim 17, wherein: The burial trench and the overflow prevention trench are fabricated on the common layer of the photosensitive pixels.

19. A method for resetting a photosensitive pixel, the method comprising: Charge is generated in the photodiode region of the photosensitive pixel; A reset voltage is applied to the reset node region of the photosensitive pixel, the reset node region being separated from the photodiode region by a channel layer, and the photosensitive pixel including a photodiode extension layer that partially covers the bottom surface of the channel layer; A reset gate voltage is applied to the reset gate adjacent to the channel layer; A conductive channel is generated between the photodiode region and the reset node region in response to the reset gate voltage; as well as The charge is discharged from the photodiode region through the conductive channel to reset the photosensitive pixel.

20. The method of claim 19, wherein the photodiode extension layer that partially covers the bottom surface of the channel layer lowers the barrier to reduce the time required to reset the photosensitive pixel.

Images