Chip vector accelerator design method based on decoupling vector architecture

Abstract

The invention provides a chip vector accelerator design method based on a decoupling vector architecture, which is applied to a memory system with consistent caches, solves deadlock and optimizes storage delay. The method comprises the steps that when a vector instruction is received, execution characteristics are collected according to a vector execution unit; coordinating data movement characteristics according to the vector storage unit; and the features are sent to a vector advanced operation unit, and optimization delay is prefetched by using a constant stride rule. The decoupling process generates a first execution array and a second mobile array as execution and storage units, respectively. The fusion features optimize an access sequence through a pre-fetching scheduler, time windows are distributed according to complexity, and a dynamic adjustment strategy is generated; in conclusion, deadlock can be avoided, efficiency can be improved, and the method is suitable for high-performance calculation.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip design and memory access, and particularly relates to a chip vector accelerator design method based on decoupled vector architecture. BACKGROUND

[0002] With the development of chip design and memory access technology, cache coherent memory systems are widely used in high-performance computing. However, cache coherence in the prior art often leads to deadlock problems, especially in a multi-core or vector processing environment, the complexity of resource competition and data synchronization increases significantly. In addition, long and variable storage latency significantly reduces the efficiency of processor access to memory, especially when processing large-scale vector data, traditional SIMD out-of-order kernels rely on a reorder buffer, and GPUs rely on multi-threading to alleviate latency problems, but these methods have the disadvantages of complex state management or low prefetch efficiency.

[0003] The present application aims at the above-mentioned defects, and proposes a chip vector accelerator design method based on decoupled vector architecture, which combines access / execution decoupling, decoupled vector architecture and cache refresh / access decoupling, aims to work in a cache coherent memory system, while avoiding deadlock and effectively tolerating long and variable storage latency, thereby improving data processing efficiency and system stability. SUMMARY

[0004] The present application aims to design an efficient solution to the deadlock problem existing in the cache coherent memory system and the limitation of long and variable storage latency on data processing efficiency. By collecting the execution characteristics of the vector execution unit and coordinating the data movement characteristics of the vector storage unit, and using the vector lookahead unit for prefetching operation, the purpose of avoiding deadlock and optimizing storage latency is achieved. It aims to overcome the shortcomings of traditional SIMD out-of-order kernels and GPU multi-threading methods in state management complexity and prefetch efficiency, improve the performance and stability of the vector accelerator, and meet the needs of high-performance computing, large-scale vector operation and real-time data processing for efficient memory access and system reliability.

[0005] To achieve the above-mentioned purpose, the present application provides a chip vector accelerator design method based on decoupled vector architecture, specifically applied to a cache coherent memory system, avoiding deadlock through decoupled vector architecture, the method comprising:

[0006] Upon receiving a vector instruction, collecting the execution characteristics of the vector execution unit;

[0007] According to the data movement characteristics of the vector storage unit between the memory system and the vector execution unit;

[0008] The execution characteristic and the data movement characteristic are sent to a vector look ahead unit, and the vector look ahead unit performs prefetching according to the characteristics, and optimizes long and variable storage delay.

[0009] Further, the method further comprises:

[0010] The encoding unit of the execution characteristic change is decoupled to obtain a first execution array, wherein an output point of the first execution array is a vector execution unit;

[0011] The encoding unit of the data movement characteristic change is decoupled to obtain a second movement array, wherein an output point of the second movement array is a vector storage unit;

[0012] The vector accelerator is constructed according to the first execution array and the second movement array.

[0013] Further, the step of collecting the execution characteristic of the vector execution unit according to the instruction comprises:

[0014] The execution change data generated by the first execution array according to the vector instruction is determined, wherein the execution change data comprises an instruction amplitude of the encoding unit;

[0015] The characteristic intensity of each vector execution unit is determined according to the execution change data, and the execution characteristic is determined according to the characteristic intensity.

[0016] Further, the step of coordinating the data movement characteristic between the memory system and the vector execution unit according to the vector storage unit comprises:

[0017] The movement change data generated by the second movement array according to the vector instruction is determined, wherein the movement change data comprises a data transmission amplitude of the encoding unit;

[0018] The data transmission amplitude of each vector storage unit is converted into the data movement characteristic.

[0019] Further, the step of performing prefetching according to the execution characteristic and the data movement characteristic by the vector look ahead unit, and optimizing long and variable storage delay comprises:

[0020] The execution characteristic sent by the vector execution unit in real time and the data movement characteristic sent by the vector storage unit are acquired;

[0021] The prefetching is performed according to the characteristics, and the storage delay is optimized.

[0022] Further, the step of performing prefetching according to the execution characteristic and the data movement characteristic comprises:

[0023] fusing the execution feature and the data movement feature, a prefetch feature is generated;

[0024] processing the prefetch feature by a prefetch scheduler, an optimized storage access sequence is generated.

[0025] Further, the step of optimizing the long and variable storage latency comprises:

[0026] allocating an access time window according to the complexity of the storage access sequence, a dynamic latency adjustment strategy is generated;

[0027] inputting the dynamic latency adjustment strategy into a vector control unit, an optimized storage access path is generated.

[0028] Further, the step of allocating an access time window according to the complexity of the storage access sequence comprises:

[0029] extracting features of the storage access sequence by a multi-scale analyzer, a first scale feature and a second scale feature are obtained;

[0030] calculating a relative importance distribution according to a formula R I = P1·K1 / P2·K2·δ, wherein R I represents the relative importance distribution, P1 and P2 represent the importance of the first and second scale features respectively, K1 and K2 are weight coefficients, and δ is a small constant;

[0031] determining an access time window allocation manner according to the relative importance distribution, a dynamic latency adjustment strategy is generated.

[0032] Further, the step of determining the access time window allocation manner according to the relative importance distribution comprises:

[0033] generating a dynamic threshold corresponding to the relative importance distribution by an adaptive filter, wherein the dynamic threshold is represented as T H .

[0034] calculating an allocation factor according to the relative importance distribution and the dynamic threshold, wherein the allocation factor is determined by a formula: , and F represents the allocation factor.

[0035] determining an access time window allocation manner according to the allocation factor, wherein a longer time window is allocated when F is greater than a preset threshold, otherwise a shorter time window is allocated, and a dynamic latency adjustment strategy is generated.

[0036] Further, the step of inputting the dynamic latency adjustment strategy into a vector control unit, an optimized storage access path is generated.

[0037] convert the dynamic latency adjustment strategy into a control vector and superimpose timing information;

[0038] process the control vector through a multi-layer vector optimization mechanism and a feedback network;

[0039] generate a final storage access path through feedback network optimization processing results.

[0040] The chip vector accelerator design method based on the decoupled vector architecture provided by the application effectively solves the deadlock problem in the cache consistent memory system, eliminates the complexity caused by resource competition and data synchronization in the multi-core or vector processing environment, and ensures the stable operation of the system in the high concurrency scenario; by collecting the execution characteristics of the vector execution unit and coordinating the data movement characteristics between the memory system and the execution unit of the vector storage unit, the negative impact of long and variable storage latency on the memory access efficiency of the processor is significantly improved, and the performance bottleneck caused by latency fluctuation in the traditional method is avoided; by sending the execution characteristics and data movement characteristics to the vector lookahead unit and using it for prefetching operation, the data access efficiency is further optimized, and the shortcomings of the existing SIMD out-of-order kernel and GPU multithread prefetching efficiency are overcome; the overall design improves the data processing speed and system throughput, and is especially suitable for high-performance computing, large-scale vector operation and real-time data processing scenarios, significantly enhancing the adaptability and reliability of the chip under complex workloads. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 The flowchart of the chip vector accelerator design method based on the decoupled vector architecture provided by the application;

[0042] Figure 2 The flowchart of the vector accelerator decoupling construction method provided by the application;

[0043] Figure 3 The flowchart of the vector lookahead unit prefetching and latency optimization method provided by the application;

[0044] Figure 4 The micro-architecture diagram of the chip vector accelerator based on the decoupled vector architecture provided by the application. DETAILED DESCRIPTION

[0045] To make the purpose, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below in conjunction with the drawings in the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0046] The terms "first", "second", "third", etc. are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or an indicated number of technical features. Thus, features defined with "first", "second" can explicitly or implicitly include one or more of the features; in the description of the present application, unless otherwise stated, the meaning of "multiple" is two or more.

[0047] In order to more clearly illustrate the technical solutions of the present application, the present application will be described in detail below in conjunction with specific embodiments, but should not be understood as limiting the scope of protection of the present application.

[0048] The present embodiment provides an implementation of a chip vector accelerator design method based on a decoupled vector architecture, as shown in Figure 1 for the vector acceleration requirements in the cache coherent memory system, focusing on the process of receiving vector instructions and optimizing long and variable storage delays to support efficient data processing.

[0049] Step S01: When a vector instruction is received, the execution characteristics of the vector execution unit are collected.

[0050] Specifically, in a cache coherent memory system, when the vector accelerator receives a vector instruction from the scalar submission stage, the vector execution unit (VXU) begins to analyze the instruction content to extract the execution characteristics. The vector execution unit is composed of multiple functional units, responsible for handling the arithmetic and logical operations of the vector instruction. Further, the VXU identifies the operation type and dependency relationship of each vector element, such as addition, multiplication or data loading operation, by monitoring the execution flow of the instruction, and records the execution mode of these operations. Understandably, considering the possible race conditions in the memory system, the VXU adopts a decoupled design to ensure that the collection of instruction execution characteristics is independent of the storage access, thereby avoiding the risk of deadlock.

[0051] Step S02: According to the data movement characteristics between the vector storage unit and the vector execution unit.

[0052] Specifically, the vector storage unit (VMU) is responsible for managing the data transfer between the vector execution unit and the memory system, and when receiving a vector instruction, the VMU begins to coordinate the data movement. VMU dynamically allocates read-write ports through the 1R1W SRAM structure connected to Bank0-7 to support data flow. Further, VMU monitors the amplitude and timing of data transfer, identifies the characteristics of data movement, such as the size of data block and the direction of transmission (such as from memory to VXU or vice versa). Understandably, VMU is separated from VXU through a decoupling mechanism, ensuring that the extraction of data movement characteristics is not directly disturbed by the execution unit, thereby optimizing the data access efficiency under cache coherence.

[0053] Step S03: sending the execution feature and data movement feature to a vector look ahead unit, wherein the vector look ahead unit performs prefetching operation according to the execution feature and data movement feature, and optimizes long and variable storage latency.

[0054] Specifically, the execution feature and data movement feature are transmitted to a vector look ahead unit (VRU) through an internal communication channel. The VRU is responsible for prefetching data to improve system performance. The VRU analyzes the received features, identifies vector access patterns, and actively loads data blocks in memory according to these patterns. Further, the VRU takes advantage of the regularity of constant stride vector memory access to predict subsequent data requirements, such as prefetching adjacent memory blocks in consecutive vector operations, thereby reducing latency. Understandably, in the context of long and variable storage latency, the VRU optimizes the overall access path by dynamically adjusting the prefetching strategy, such as prioritizing high-priority data blocks, to ensure data processing efficiency in cache-coherent systems is not affected by latency.

[0055] The embodiment effectively solves the deadlock problem in cache-coherent memory systems by using a chip vector accelerator design method based on a decoupled vector architecture, eliminating the complexity caused by resource competition in multi-core or vector processing. By collecting the execution features of the vector execution unit and coordinating the data movement features of the vector storage unit, the long and variable storage latency is significantly optimized, and the efficiency of processor memory access is improved. The execution feature and data movement feature are sent to the vector look ahead unit for prefetching operation, further reducing data latency and overcoming the shortcomings of traditional methods in latency processing. The overall design enhances system stability and data processing efficiency, and is particularly suitable for high-performance computing and real-time data processing scenarios.

[0056] In some embodiments, as shown in Figure 2 for the vector acceleration requirements in cache-coherent memory systems, the process of building a vector accelerator is described to support efficient data processing:

[0057] Step S21: decoupling the encoding unit of the execution feature change to obtain a first execution array, wherein the output point in the first execution array is a vector execution unit.

[0058] Specifically, for the encoding units responsible for execution feature changes, such as functional modules responsible for vector addition or multiplication, decoupling processing technology is adopted for separation. The decoupling process generates a first execution array by grouping these encoding units according to functions and dependencies, ensuring that each unit operates independently. Further, the output points of the first execution array are configured as vector execution units (VXU) responsible for processing specific vector instruction execution tasks. Understandably, in a cache-consistent memory system, this decoupling design helps to avoid the risk of deadlock and improves system throughput by isolating the parallel operation of execution units.

[0059] Step S22: Decoupling processing is performed on the encoding units responsible for data movement feature changes to obtain a second movement array, wherein the output points of the second movement array are used as vector storage units.

[0060] Specifically, for the encoding units responsible for data movement feature changes, such as interface modules responsible for memory read / write operations, decoupling processing technology is also adopted for separation. The decoupling process groups these units according to data transmission requirements to generate a second movement array, ensuring that data movement is independent of the execution process. Further, the output points of the second movement array are configured as vector storage units (VMU) responsible for coordinating data interaction between the memory system and the execution units. Understandably, through this decoupling design, the second movement array can effectively adapt to complex data flow under cache consistency and optimize storage access efficiency.

[0061] Step S23: A vector accelerator is constructed according to the first execution array and the second movement array.

[0062] Specifically, based on the output points of the first execution array and the second movement array, the system integrates these modules to form a complete vector accelerator architecture. During integration, the vector execution units of the first execution array and the vector storage units of the second movement array are connected through internal communication channels to collaboratively process vector instructions. Further, as shown in Figure 4 , the architecture design refers to the 1R1W SRAM structure of Bank0-7, ensuring the parallelism and consistency of data transmission. Understandably, in actual applications, such as high-performance computing environments, this construction method supports the stable operation of the vector accelerator under long and variable storage delays, meeting the needs of complex computing tasks.

[0063] In some embodiments, for the vector acceleration requirements in a cache-consistent memory system, the process of collecting instruction execution features is described in detail to support efficient data processing.

[0064] Specifically, the execution change data generated by the first execution array according to the vector instruction is determined, wherein the execution change data includes the instruction amplitude of the encoding units in the first execution array.

[0065] As can be appreciated, during the vector accelerator runtime, the first execution array receives vector instructions from the scalar commit stage, and the encoding units begin processing these instructions. The system determines execution variation data by monitoring the operational activity of each encoding unit, for example, recording the amount of instructions processed and the range of variation in vector addition or multiplication operations. Further, instruction width, as part of the execution variation data, reflects the number of vector elements processed and the operation intensity of each encoding unit. As can be appreciated, in a cache coherent memory environment, this process ensures that data collection is independent of memory access through decoupled design, avoiding performance bottlenecks due to race conditions.

[0066] Further, the characteristic intensity of each vector execution unit in the first execution array is determined based on the execution variation data.

[0067] In particular, based on the collected execution variation data, the system performs a characteristic analysis of each vector execution unit in the first execution array. The characteristic intensity is determined by evaluating the instruction width and processing frequency of each unit, for example, units with high frequency addition operations are labeled as high intensity units. Further, the system combines these intensity data with the dependency relationships of the vector instructions to generate a characteristic description of each vector execution unit. As can be appreciated, this step helps identify critical execution units in long and variable memory latency scenarios, thereby optimizing subsequent prefetching strategies.

[0068] Further, the execution characteristic is determined based on the characteristic intensity.

[0069] In particular, the system analyzes the characteristic intensity of all vector execution units in the first execution array and extracts the overall execution characteristic. The execution characteristic includes operation type distribution and intensity patterns, for example, a characteristic pattern dominated by consecutive addition operations. Further, the execution characteristic is encoded as a data packet for use by the vector lookahead unit to guide prefetching operations. As can be appreciated, in practical applications, for example, scientific computing tasks, this characteristic determination process supports the vector accelerator to adapt to different workload requirements, ensuring efficient operation.

[0070] In some embodiments, for vector acceleration requirements in cache coherent memory systems, the process of coordinating data movement characteristics between the memory system and the vector execution unit is highlighted to support efficient data processing.

[0071] In particular, the second movement array is determined based on movement variation data generated by the vector instructions, wherein the movement variation data includes the data transfer width of the encoding units in the second movement array.

[0072] As can be appreciated, during the vector accelerator runtime, the second mobile array receives vector instructions, and the encoding unit starts managing data transfer between the memory system and the vector execution unit. The system determines the mobile change data by tracking the read-write activities of each encoding unit, for example, recording the data block size transferred from the 1R1W SRAM of Bank0-7 to the vector execution unit. Further, the data transfer magnitude, as part of the mobile change data, reflects the number of vector elements and the data volume change for each transfer. As can be appreciated, in a cache coherent memory environment, this process ensures data movement independent of execution operations through decoupled design, avoiding performance degradation due to coherence conflicts.

[0073] Further, the data transfer magnitude of each of the vector storage units is converted into data movement features.

[0074] In particular, based on the collected mobile change data, the system converts each vector storage unit in the second mobile array into features. The data transfer magnitude is mapped into data movement features, for example, larger transfer magnitudes are identified as high data traffic features, while smaller magnitudes are identified as low traffic features. Further, the system generates a mobile feature description for each vector storage unit in combination with the transfer timing and direction. As can be appreciated, this step helps optimize data movement paths in long and variable memory latency scenarios, thereby improving memory access efficiency.

[0075] In some embodiments, as shown in Figure 3 For vector acceleration needs in a cache coherent memory system, the process of pre-fetching operations and optimizing long and variable memory latency is highlighted to support efficient data processing.

[0076] Step S51: Obtain execution features sent by the vector execution unit and data movement features sent by the vector storage unit in real time.

[0077] In particular, during the vector accelerator runtime, the vector execution unit (VXU) continuously generates execution features, such as operation type and intensity mode, and sends them to the vector run-ahead unit (VRU) in real time through an internal communication channel. At the same time, the vector storage unit (VMU) monitors data transfer and generates data movement features, such as transfer magnitude and timing, and also sends them to the VRU. Further, the VRU receives these features through a buffer to ensure data synchronization. As can be appreciated, in a cache coherent memory environment, this real-time acquisition process avoids direct interference between execution and storage through decoupled design, improving system stability.

[0078] Step S52: Perform pre-fetching operations based on the execution features and the data movement features to optimize long and variable memory latency.

[0079] Specifically, the VRU analyzes the received execution features and data movement features, identifies patterns of vector access, such as access requirements for contiguous memory blocks. Based on these patterns, the VRU proactively prefetches relevant data blocks from the memory system, filling the cache to reduce latency. Further, for long and variable storage latencies, the VRU prioritizes prefetching of frequently accessed data regions, dynamically adjusting the prefetch range to accommodate latency variations. Understandably, in practical applications, such as high-performance computing tasks, this prefetching operation avoids deadlock risks by exploiting decoupled vector architectures, ensuring efficient data processing.

[0080] In some embodiments, for vector acceleration needs in cache coherent memory systems, the generation process of prefetching operations is highlighted to support efficient data processing.

[0081] Specifically, the execution features and the data movement features are fused to generate prefetching features.

[0082] Understandably, in a vector run-ahead unit (VRU), received execution features (such as operation types and intensity patterns) and data movement features (such as transfer amplitudes and timing) are input into a fusion module. The fusion module extracts common access rules, such as memory regions corresponding to contiguous vector operations, by comparing the patterns of these features. Further, the fusion results are organized into prefetching features, representing the priority and location information of data blocks that need to be prefetched. Understandably, in a cache coherent memory environment, this fusion process ensures that feature integration is independent of real-time execution through decoupled design, reducing potential conflicts.

[0083] Further, the prefetching features are processed by a prefetching scheduler to generate an optimized storage access sequence.

[0084] Specifically, the prefetching scheduler receives the fusion-generated prefetching features and plans the data access order based on the priority and location information in the features. The scheduler maps the prefetching features to specific addresses in memory, generating an ordered storage access sequence that prioritizes loading of high-priority data blocks. Further, the scheduler dynamically adjusts the sequence based on system load to ensure that the access order matches the current vector task requirements. Understandably, in long and variable storage latency scenarios, this process effectively shortens latency and improves overall performance by optimizing the access sequence.

[0085] In some embodiments, for vector acceleration needs in cache coherent memory systems, the process of optimizing long and variable storage latencies is highlighted to support efficient data processing.

[0086] Specifically, an access time window is assigned according to the complexity of the storage access sequence to generate a dynamic latency adjustment strategy.

[0087] It can be understood that after the vector run-ahead unit (VRU) generates the storage access sequence, the system analyzes the access mode and dependency of the data blocks in the sequence, evaluates the complexity, such as the degree of mixing of continuous access and random access. Based on this analysis, the system allocates appropriate access time windows for each data block, and longer time windows are allocated for more complex sequences to ensure sufficient data preparation. Further, a dynamic latency adjustment strategy is formed by integrating these time window allocations, guiding the optimization of subsequent access paths. It can be understood that in a cache-coherent memory environment, this allocation process avoids the risk of deadlock caused by complex sequences through decoupling design.

[0088] Further, the dynamic latency adjustment strategy is input into the vector control unit to generate an optimized storage access path.

[0089] Specifically, the dynamic latency adjustment strategy is transmitted to the vector control unit, and the unit adjusts the timing and order of data access according to the time window allocation in the strategy. The control unit coordinates the 1R1W SRAM read-write ports of Bank0-7 to ensure that data is loaded in the optimized order. Further, the control unit fine-tunes the access path according to real-time load conditions, prioritizing critical data blocks to reduce latency. It can be understood that in the context of long and variable storage latency, this process improves the adaptability and efficiency of the vector accelerator by optimizing the access path.

[0090] In some embodiments, for the vector acceleration needs in a cache-coherent memory system, the process of allocating access time windows is highlighted to support the optimization of long and variable storage latency.

[0091] Specifically, the storage access sequence is feature-extracted by a multi-scale analyzer to obtain first-scale features and second-scale features.

[0092] It can be understood that after the vector run-ahead unit (VRU) generates the storage access sequence, the multi-scale analyzer starts processing the sequence and analyzes the access mode of different time periods and data blocks. The first-scale feature extraction focuses on the access frequency within a short time, such as the local pattern of continuous vector operations; the second-scale feature focuses on the overall trend over a longer time span, such as the periodic changes in the access sequence. Further, the analyzer generates these two types of feature data by scanning the data block boundaries and dependencies in the sequence. It can be understood that in a cache-coherent memory environment, this process ensures that feature extraction is not disturbed by real-time execution through decoupling design, improving analysis accuracy.

[0093] Further, the first-scale features and the second-scale features are respectively evaluated for importance to obtain first importance distribution and second importance distribution.

[0094] Specifically, the system evaluates the importance of the first scale features, determines their impact on the overall performance according to the access frequency and data dependency, and generates a first importance distribution; similarly, the system evaluates the second scale features, considers their impact on the long-term access pattern, and generates a second importance distribution. Further, the evaluation process quantifies the importance level of each feature by counting the access times and delay sensitivity. Understandably, in the context of long and variable storage latency, this evaluation helps to identify the critical access pattern, which provides the basis for subsequent time window allocation.

[0095] Further, according to the first importance distribution and the second importance distribution, a relative importance distribution is calculated, wherein the relative importance distribution is calculated according to the formula R I = P1·K1 / P2·K2·δ, R I represents the relative importance distribution, P1 represents the first importance distribution, P2 represents the second importance distribution, K1 and K2 are the weight coefficients of the first and second scale features, respectively, and δ is a small constant to prevent division by zero.

[0096] Specifically, the system inputs the first importance distribution and the second importance distribution into the calculation module, and calculates the relative importance distribution according to the above formula. The weight coefficients K1 and K2 are preset by the system, and respectively reflect the relative contribution of short-time and long-time features, for example, based on experimental data, K1 = 0.6 and K2 = 0.4; δ is set to a small value such as 0.01 to avoid division by zero and ensure the stability of the calculation. Further, the calculation result R I represents the comprehensive importance of each data block, which is used to guide the time window allocation. Understandably, in practical applications, such as high-performance computing tasks, this calculation process ensures the rationality of the access time window allocation, which adapts to different load requirements.

[0097] Further, according to the relative importance distribution, the access time window allocation manner is determined, and a dynamic latency adjustment strategy is generated.

[0098] Specifically, the system allocates longer time windows to data blocks with higher R I values to ensure sufficient data preparation; and allocates shorter time windows to data blocks with lower R I values to optimize overall efficiency. Further, the dynamic latency adjustment strategy is formed by integrating these allocation manners, guiding the vector control unit to adjust the access order. Understandably, in the cache coherent memory system, this allocation manner avoids the risk of deadlock by decoupling the vector architecture, significantly improving the adaptability of storage access.

[0099] In some embodiments, for the vector acceleration requirements in the cache coherent memory system, the process of determining the access time window allocation manner is emphasized to support the optimization of long and variable storage latency.​​​​​

[0100] Specifically, the adaptive filter processes the relative importance distribution to generate a dynamic threshold value T H .

[0101] It can be understood that after the vector run-ahead unit (VRU) calculates the relative importance distribution, the adaptive filter starts processing these data to generate a dynamic threshold value T H . The filter adjusts the threshold value according to the real-time changes of the load status of the current system and the access sequence to adapt to different working environments, such as increasing the threshold value to filter secondary data in high load. Further, the filter updates T H by analyzing the trend of the relative importance distribution in the previous period to keep it matched with the actual demand. It can be understood that in the cache coherent memory environment, this process ensures that the threshold value generation is independent of the execution operation through decoupling design, avoiding performance fluctuations caused by coherence problems.

[0102] Further, the allocation factor is calculated according to the relative importance distribution and the dynamic threshold value, wherein the allocation factor is determined by the formula , and F represents the allocation factor.

[0103] Specifically, the system inputs the relative importance distribution R I and the dynamic threshold value T H into the calculation module to calculate the allocation factor according to the above formula. The value of the allocation factor F reflects the proportion of the importance of each data block relative to the threshold value, for example, when R I is much greater than T H , F is close to 1, indicating high priority. Further, the calculation process is performed in real time in the vector control unit to ensure timely updating of the allocation factor. It can be understood that in the long and variable storage delay scenario, this calculation supports dynamic adjustment of the access strategy to improve data access efficiency.

[0104] Further, the access time window allocation manner is determined according to the allocation factor, wherein a longer time window is allocated when F is greater than a preset threshold value, otherwise a shorter time window is allocated, to generate a dynamic delay adjustment strategy.

[0105] Specifically, the system calculates the allocation factor according to . It can be understood that when F=0.5 is the midpoint of the sigmoid function, it represents the balance point when the relative importance distribution R I is equal to the dynamic threshold value T H . Further, based on experimental verification, 0.5 is selected as the preset threshold value, which can effectively distinguish high-priority and low-priority data blocks at this demarcation point to ensure the rationality of the time window allocation. Higher than 0.5 indicates that R I significantly exceeds TH , a longer time window is assigned; lower than or equal to 0.5, a shorter time window is assigned. Understandably, T H This preset threshold is fine-tuned to adapt to different loads. In summary, in the long latency scenario, this threshold setting supports dynamic optimization through decoupling design, avoids deadlock risk, and ensures that the vector accelerator adapts to complex memory access requirements.

[0106] In some embodiments, for the vector acceleration requirements in cache-coherent memory systems, the process of generating optimized storage access paths is described in detail to support optimizing long and variable storage latency.

[0107] Specifically, the dynamic latency adjustment strategy is converted into a control vector, and timing information is superimposed.

[0108] Understandably, in the vector control unit, the dynamic latency adjustment strategy is parsed into a set of control parameters that define the access time window and priority of each data block. The system converts these parameters into a control vector, representing the execution order of the access sequence. Further, timing information such as the expected load time and dependency of each data block is superimposed on the control vector to ensure the coordination of access operations. Understandably, in a cache-coherent memory environment, this conversion process avoids the risk of deadlock due to timing conflicts through decoupling design.

[0109] Further, the control vector is processed by a multi-layer vector optimization mechanism and a feedback network, where each layer of the vector optimization mechanism adjusts and calculates the current and previous control vectors.

[0110] Specifically, the multi-layer vector optimization mechanism processes the control vector in layers, with the first layer adjusting the initial access order based on timing information, and the second layer optimizing the priority of data blocks in combination with the current load situation. The feedback network then receives the results of each layer, analyzes the actual access delay and data preparation state, and fine-tunes the control vector. Further, the optimization mechanism ensures the adaptability and accuracy of the control vector through iterative adjustment. Understandably, in the long and variable storage latency scenario, this process supports the vector accelerator to dynamically respond to changing memory conditions.

[0111] Further, the adjustment calculation results are further optimized by the feedback network to generate the final storage access path.

[0112] Specifically, the feedback network performs final optimization on the adjusted control vector based on the actual performance data of the previous access, such as delay time and hit rate. The network adjusts the access path, prioritizes low-latency paths and avoids conflict areas, and finally generates the storage access path. Further, the path is transmitted to the Figure 4The 1R1W SRAM structure of Bank 0-7 shown guides the data loading operation. Understandably, in practical applications, such as real-time data processing tasks, this optimization process ensures efficient and stable memory access performance through decoupling of the vector architecture.

[0113] The above merely describes exemplary embodiments of the present application, and is not intended to limit the patent scope of the present application. Any equivalent structural transformation, or direct / indirect application in other related technical fields, made under the technical concept of the present application, using the content of the present application specification and drawings, is included in the patent protection scope of the present application.

Claims

1. A chip vector accelerator design method based on decoupled vector architecture, characterized by, The method is applied to a cache consistent memory system, and avoids deadlock by decoupling a vector architecture, and specifically comprises the following steps: Upon receiving a vector instruction, a vector execution unit collects execution characteristics of the instruction; a vector storage unit coordinates data movement characteristics between a memory system and the vector execution unit; the execution characteristics and the data movement characteristics are sent to a vector lookahead unit, which performs prefetching operations according to the characteristics to optimize long and variable storage latency.

2. The method of claim 1, wherein, The method further comprises: decoupling processing of execution characteristic changing encoding units to obtain a first execution array, wherein an output point of the first execution array serves as the vector execution unit; decoupling processing of data movement characteristic changing encoding units to obtain a second movement array, wherein an output point of the second movement array serves as the vector storage unit; constructing a vector accelerator according to the first execution array and the second movement array.

3. The method of claim 2, wherein, The step of collecting execution characteristics of the instruction by the vector execution unit comprises: determining execution change data generated by the first execution array according to the vector instruction, wherein the execution change data comprises instruction amplitude of an encoding unit; determining characteristic intensity of each vector execution unit according to the execution change data; and determining execution characteristics according to the characteristic intensity.

4. The method of claim 2, wherein, The step of coordinating data movement characteristics between the memory system and the vector execution unit by the vector storage unit comprises: determining movement change data generated by the second movement array according to the vector instruction, wherein the movement change data comprises data transmission amplitude of an encoding unit; converting the data transmission amplitude of each vector storage unit into data movement characteristics.

5. The method of claim 1, wherein, The step of performing prefetching operations according to the execution characteristics and the data movement characteristics by the vector lookahead unit to optimize long and variable storage latency comprises: obtaining execution characteristics sent by the vector execution unit in real time and data movement characteristics sent by the vector storage unit; performing prefetching operations according to the characteristics to optimize storage latency.

6. The method of claim 5, wherein, The step of performing prefetching operations according to the execution characteristics and the data movement characteristics comprises: fusing the execution characteristics and the data movement characteristics to generate prefetching characteristics; processing the prefetching characteristics by a prefetching scheduler to generate an optimized storage access sequence.

7. The method of claim 5, wherein, The step of optimizing long and variable storage latency comprises: allocating an access time window according to complexity of the storage access sequence to generate a dynamic latency adjustment strategy; inputting the dynamic latency adjustment strategy into a vector control unit to generate an optimized storage access path.

8. The method of claim 7, wherein, The step of allocating an access time window according to complexity of the storage access sequence comprises: extracting first scale characteristics and second scale characteristics from the storage access sequence by a multi-scale analyzer; According to the formula R I = P1·K1 / P2·K2·δ, the relative importance distribution is calculated, wherein R I represents the relative importance distribution, P1 and P2 represent the importance of the first and second scale features respectively, K1 and K2 are weight coefficients, and δ is a small constant; determining an access time window allocation manner according to the relative importance distribution to generate a dynamic latency adjustment strategy.

9. The method of claim 8, wherein, The step of determining an access time window allocation manner according to the relative importance distribution comprises: generating a dynamic threshold corresponding to the relative importance distribution by an adaptive filter, wherein the dynamic threshold is represented as T H ; A distribution factor is calculated based on the relative importance distribution and the dynamic threshold, wherein the distribution factor is calculated by the formula: where F represents the distribution factor. determining the access time window allocation manner according to the allocation factor, wherein a longer time window is allocated when F is greater than a preset threshold, otherwise a shorter time window is allocated to generate a dynamic latency adjustment strategy.

10. The method of claim 7, wherein, The step of inputting the dynamic latency adjustment strategy into a vector control unit to generate an optimized storage access path includes: Converting the dynamic latency adjustment strategy into a control vector and superimposing timing information; Processing the control vector through a multi-layer vector optimization mechanism and a feedback network; Optimizing the processing result through the feedback network to generate a final storage access path.

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