Amplifier circuit, radio frequency chip, and electronic device

Abstract

The present disclosure provides an amplifier circuit, a radio frequency chip and an electronic device, wherein the amplifier circuit comprises a parallel plate coupler, a carrier amplifier, a peak amplifier and a reconfigurable load network; the carrier amplifier is configured to receive and amplify a first input signal; the peak amplifier is configured to receive and amplify a second input signal; the first input signal and the second input signal are formed by separating the same radio frequency input signal; the parallel plate coupler is connected to the carrier amplifier and the peak amplifier respectively, configured to receive the amplified first input signal and the amplified second input signal, and combine the amplified first input signal and the amplified second input signal into an output signal; the reconfigurable load network is connected to an isolation port of the parallel plate coupler, configured to adjust the load impedance of the isolation port based on the frequency of the radio frequency input signal; wherein the load impedance of the isolation port is inversely proportional to the frequency of the radio frequency input signal.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an amplifier circuit, a radio frequency chip, and an electronic device. Background Technology

[0002] With the rapid development of wireless communication technology, radio frequency (RF) transmitter modules are evolving towards higher integration, smaller size, and greater bandwidth. As a core component of the transmit link, the performance of the power amplifier (PA) directly determines the efficiency and reliability of the entire system.

[0003] However, in modern communication systems, the design of power amplifiers faces multiple challenges: on the one hand, the contradiction between the trend of low operating voltage and the demand for high output power exacerbates the difficulty of energy efficiency optimization; on the other hand, the design requirements of miniaturization and broadband make it difficult for traditional lumped parameter matching networks to meet the spatial constraints and bandwidth expansion requirements. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an amplifier circuit, a radio frequency chip, and an electronic device that further expands bandwidth while improving integration.

[0005] The technical solution of this disclosure embodiment is implemented as follows:

[0006] This disclosure provides an amplifier circuit, including: a parallel-plate coupler, a carrier amplifier, a peak amplifier, and a reconfigurable load network; wherein the carrier amplifier is configured to receive and amplify a first input signal; the peak amplifier is configured to receive and amplify a second input signal; wherein the first input signal and the second input signal are formed by separating the same radio frequency input signal; the parallel-plate coupler is connected to the carrier amplifier and the peak amplifier respectively, and is configured to receive the amplified first input signal and the second input signal, and combine the amplified first input signal and the second input signal into an output signal; the reconfigurable load network is connected to the isolation port of the parallel-plate coupler, and is configured to adjust the load impedance of the isolation port based on the frequency of the radio frequency input signal; wherein the load impedance of the isolation port is inversely proportional to the frequency of the radio frequency input signal.

[0007] In the above scheme, the reconfigurable load network is configured to increase the load impedance of the carrier amplifier to more than n+1 times the load impedance of the parallel plate coupler when the power of the second input signal is less than the turn-on power of the peak amplifier.

[0008] In the above scheme, the reconfigurable load network is further configured to increase the load impedance of the carrier amplifier to more than n times the load impedance of the parallel plate coupler, provided that the power of the output signal does not increase linearly with the increase of the power of the RF input signal.

[0009] In the above scheme, the reconfigurable load network includes: a variable capacitor and a control module; wherein, the control module is connected to the variable capacitor and is configured to receive the radio frequency input signal and adjust the capacitance value of the variable capacitor based on at least one of the frequency and power of the radio frequency input signal.

[0010] In the above scheme, the variable capacitor includes: multiple switches and multiple first capacitors; wherein, the first end of each of the multiple first capacitors is connected to the isolation port of the parallel plate coupler; the second end of each of the multiple first capacitors is connected in series with one of the switches, and is grounded through the series-connected switches respectively.

[0011] In the above scheme, the input port of the parallel plate coupler is connected to the carrier amplifier; the through port of the parallel plate coupler outputs the output signal; and the coupling port of the parallel plate coupler is connected to the peak amplifier.

[0012] In the above scheme, the parallel plate coupler includes an upper plate, a lower plate, and a second capacitor; wherein, the two ends of the second capacitor are respectively connected to the upper plate and the lower plate.

[0013] In the above scheme, the coupling coefficient of the parallel plate coupler is greater than or equal to 0.8.

[0014] In the above scheme, the amplifier circuit further includes a splitter; wherein the splitter is connected to the carrier amplifier and the peak amplifier respectively, and is configured to receive the radio frequency input signal and split the radio frequency input signal into the first input signal and the second input signal.

[0015] This disclosure provides an RF chip, including the amplifier circuit described in any of the above embodiments.

[0016] This disclosure provides an electronic device including the radio frequency chip described above.

[0017] The parallel-plate coupler in this disclosure receives a first input signal amplified by a carrier amplifier and a second input signal amplified by a peak amplifier, and combines the amplified first and second input signals into an output signal. During signal synthesis, the parallel-plate coupler, by virtue of its inherent physical structure characteristics (e.g., a fixed 90° phase difference between the through port and the coupling port), can ensure that the two input signals maintain the required phase difference (e.g., 90°) within the coupling region. This disclosure eliminates the need for an additional λ / 4 transmission line to provide the phase difference. Therefore, embodiments of this disclosure avoid the bandwidth limitations imposed by λ / 4 wavelength transmission line structures, further improving the bandwidth of the amplifier circuit.

[0018] Simultaneously, the reconfigurable load network connecting the isolation port of the parallel-plate coupler is configured to adjust the load impedance of the isolation port based on the frequency of the RF input signal. The load impedance of the isolation port is inversely proportional to the frequency of the RF input signal. Thus, embodiments of this disclosure can dynamically adjust the load of the isolation port of the parallel-plate coupler according to the frequency, enabling the parallel-plate coupler to be suitable for impedance modulation amplification by a carrier amplifier, and for impedance balancing performance of the carrier amplifier and the peak amplifier, thereby achieving independent performance optimization in different frequency bands. This expands the bandwidth of the amplifier circuit. Attached Figure Description

[0019] Figure 1 A schematic diagram of the amplifier circuit provided in the embodiments of this disclosure. Figure 1 ;

[0020] Figure 2 Schematic diagram of the performance curve of the output signal provided in the embodiments of this disclosure Figure 1 ;

[0021] Figure 3 Schematic diagram of the performance curve of the output signal provided in the embodiments of this disclosure Figure 2 ;

[0022] Figure 4 A schematic diagram of the amplifier circuit provided in the embodiments of this disclosure. Figure 2 ;

[0023] Figure 5 This is a schematic diagram of the structure of a reconfigurable load network provided in an embodiment of the present disclosure;

[0024] Figure 6 A schematic diagram of the amplifier circuit provided in the embodiments of this disclosure. Figure 3 ;

[0025] Figure 7 A schematic diagram of the structure of the radio frequency chip provided in the embodiments of this disclosure. Figure 1 ;

[0026] Figure 8 A schematic diagram of the structure of the radio frequency chip provided in the embodiments of this disclosure. Figure 2 ;

[0027] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0029] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0030] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0032] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0033] Figure 1 This is a schematic diagram of an optional amplifier circuit 100 provided in an embodiment of this disclosure. It should be noted that... Figure 1The first and second input signals are formed by separating the same radio frequency input signal. For example, the amplifier circuit 100 may include devices such as quadrature couplers, which can separate the radio frequency input signal into a first input signal and a second input signal.

[0034] In this embodiment of the disclosure, reference is made to Figure 1 The amplifier circuit 100 may include a carrier amplifier 10 and a peaking amplifier 20. Both the carrier amplifier 10 and the peaking amplifier 20 may be composed of bipolar transistors such as heterojunction bipolar transistors (HBTs) or transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0035] In this embodiment of the disclosure, reference is made to Figure 1 The carrier amplifier 10 is configured to receive and amplify a first input signal. For example, the carrier amplifier 10 can amplify the first input signal using either Class AB or Class B amplification. The peak amplifier 20 is configured to receive and amplify a second input signal. For example, the peak amplifier 20 can amplify the second input signal using Class C amplification. Thus, when the input power of the amplifier circuit 100 is in the low power range, the peak amplifier 20 is off, and the carrier amplifier 10 provides output power independently. As the input power of the amplifier circuit 100 increases to the peak level, the peak amplifier 20 is activated and current is injected. The peak amplifier 20 and the carrier amplifier 10 work together to provide output power.

[0036] In this embodiment of the disclosure, reference is made to Figure 1The amplifier circuit 100 may further include a parallel-plate coupler 30. The parallel-plate coupler 30 connects the carrier amplifier 10 and the peak amplifier 20 respectively. In this way, the characteristic impedance of the port of the parallel-plate coupler 30 connected to the carrier amplifier 10 (or peak amplifier 20) can be directly set to be equal to the optimal load impedance of the carrier amplifier 10 (or peak amplifier 20), without needing to match it to the system impedance (e.g., 20-50 ohms). Therefore, this embodiment does not require an additional matching structure to achieve system impedance matching between the carrier amplifier 10 and the peak amplifier 20, simplifying circuit design and further improving integration. Simultaneously, the optimal load impedance of the carrier amplifier 10 (or peak amplifier 20) is relatively small (typically 2-5 ohms), therefore, the impedance of the parallel-plate coupler 30 can be reduced from the system impedance (20-50 ohms) to 2-5 ohms, significantly reducing the size of the parallel-plate coupler 30 and further improving integration.

[0037] It should be noted that the phase of the first input signal can be 0 degrees, and the phase of the second input signal can be 90 degrees. Figure 1 The fixed phase offset of the parallel plate coupler 30 in the example can be 90°. Figure 1 The fixed phase offset of the parallel plate coupler 30 can also be other values ​​that match the phase difference between the first input signal and the second input signal, and there are no restrictions here.

[0038] It should also be noted that the core function of the λ / 4 transmission line in the prior art is to provide a precise 90° phase shift and impedance transformation at the center frequency of a set frequency band. The phase and impedance transformation characteristics of the λ / 4 transmission line are quite sensitive to frequency changes. Therefore, when the operating frequency deviates, the load impedance seen by the carrier amplifier will deviate from the design value (such as the high impedance required at the backoff point), destroying the load modulation effect and deteriorating the efficiency curve. These frequency-sensitive characteristics cause the high-efficiency range of the Doherty amplifier to be typically limited to a relative bandwidth of 10% to 20%.

[0039] In this embodiment of the disclosure, reference is made to Figure 1The parallel plate coupler 30 is configured to receive amplified first and second input signals and combine them into an output signal. Specifically, the two amplified signals (i.e., the amplified first and second input signals) output from the carrier amplifier 10 and the peak amplifier 20 are injected into the parallel plate coupler 30. The parallel plate coupler 30 can utilize its internal electromagnetic field coupling effect to make the two signals interact and perform vector synthesis, outputting the synthesized output signal. The output signal can be output from the through port of the parallel plate coupler 30. During signal synthesis, the parallel plate coupler 30 can ensure that the two input signals maintain the required phase difference (e.g., 90°) within the coupling region by virtue of its inherent physical structure characteristics (e.g., the through port and coupling port of the parallel plate coupler 30 have a fixed phase difference of 90°). Thus, this embodiment of the present disclosure does not require an additional λ / 4 transmission line to provide the phase difference. Therefore, this embodiment of the present disclosure can avoid the bandwidth limitation caused by the λ / 4 wavelength transmission line structure and further improve the bandwidth of the amplifier circuit 100.

[0040] Figure 2 and Figure 3 This is a schematic diagram illustrating the performance of optional radio frequency input signals at different frequencies according to embodiments of this disclosure. It should be noted that... Figure 2 The frequency of the RF input signal in the example can be the center frequency in the low-frequency band (e.g., 1.9 GHz), and the frequency range of the low-frequency band can be 1.7 GHz to 2.1 GHz. Figure 3 The frequency of the RF input signal in the example can be the center frequency in the high-frequency band (e.g., 2.5 GHz), and the frequency range of the high-frequency band can be 2.3 GHz to 2.7 GHz. Figure 2 L1 and Figure 3 L4 in the figure represents the gain variation curve of the output signal. Figure 2 L2 and Figure 3 L5 in the figure represents the variation curve of power added efficiency (PAE). Figure 2 L3 and Figure 3 L6 in the figure represents the phase change curve of the output signal.

[0041] It should also be noted that the reference Figure 1When amplifier circuit 100 receives and amplifies RF input signals from different frequency bands, the phase characteristics of parallel plate coupler 30 are closely related to the signal frequency. As the frequency increases (signal wavelength shortens), the phase difference of the output signal of parallel plate coupler 30 shifts, potentially reducing power combining efficiency. Simultaneously, the phase delay characteristics of parallel plate coupler 30 differ across frequency bands, affecting the overall phase consistency of amplifier circuit 100. Furthermore, as the frequency band changes, the distributed parameters (parasitic capacitance, inductance) of parallel plate coupler 30 change with frequency, causing the actual impedance to deviate from the target value, resulting in impedance mismatch. For example, at high frequencies, the effect of parasitic capacitance increases, potentially causing the port of parallel plate coupler 30 to exhibit capacitive impedance, while at low frequencies, it may exhibit inductive impedance due to the dominance of parasitic inductance. Both lead to increased signal reflection, reducing the power transmission efficiency of amplifier circuit 100 and exacerbating losses caused by mismatch.

[0042] In this embodiment of the disclosure, reference is made to Figure 1 The reconfigurable load network 40 connects to the isolation port of the parallel plate coupler 30. The reconfigurable load network 40 is configured to adjust the load impedance of the isolation port based on the frequency band of the RF input signal. The load impedance of the isolation port refers to the terminating impedance connected to the isolation port of the parallel plate coupler 30, i.e., the impedance of the reconfigurable load network 40. Since the parallel plate coupler 30 has two ports receiving input signals (i.e., the parallel plate coupler 30 is in dual-port excitation mode), the isolation port is no longer an "idle" port. The load impedance of the isolation port determines the reflection characteristics of the signal incident on the isolation port. The vector superposition of the reflected wave from the isolation port and the original input signal in the core coupling region significantly changes the relative phase difference between the signals at the two ports (the through port and the coupled port), thus altering the signal amplitude flowing to the through port and the coupled port. In other words, the reflected wave from the isolation port contributes a different additional phase shift to the signal on each path. Thus, this embodiment of the present disclosure can dynamically adjust the load on the isolation port of the parallel plate coupler 30 according to the frequency, enabling the parallel plate coupler 30 to be used for impedance modulation amplification of the carrier amplifier 10, and to utilize the impedance balancing performance of the carrier amplifier 10 and the peak amplifier 20, thereby achieving independent performance optimization in different frequency bands. This expands the bandwidth of the amplifier circuit 100.

[0043] In this embodiment of the disclosure, reference is made to Figure 1 The load impedance of the isolation port of the parallel plate coupler 30 is inversely proportional to the frequency of the RF input signal. For example, the reconfigurable load network 40 can be an adjustable capacitor. As the frequency of the RF input signal increases, the capacitance value of the reconfigurable load network 40 can be decreased. At this time, since the load impedance of the reconfigurable load network 40 is inversely proportional to the capacitance value, the load impedance of the isolation port can be increased. Figure 2The operating frequency of the RF input signal shown is 1.9 GHz. In this case, the impedance of the reconfigurable load network 40 can be set to 6 picofarads (pF). For example, Figure 3 The operating frequency of the RF input signal shown is 2.5 GHz. At this frequency, the impedance of the reconfigurable load network 40 can be set to 0 picofarads. Thus, the load impedance at the isolation port of the parallel plate coupler 30 exhibits high impedance in the low-frequency range and low impedance in the high-frequency range. Dynamically lowering the peak branch impedance with power changes allows the carrier amplifier to receive additional load boost in the back-off region, enabling it to enter saturation earlier and maintain high efficiency by shifting the inflection point outwards. Simultaneously, the phase compensation generated by this inverse slope cancels out transistor nonlinearity, flattens the AM-PM curvature, and simultaneously improves back-off power and linearity.

[0044] Figure 4 This is a schematic diagram of an optional amplifier circuit 100 provided in an embodiment of this disclosure, specifically illustrating the connection relationship between the parallel plate coupler 30 and the reconfigurable load network 40. It should be noted that the load impedance of the parallel plate coupler 30 refers to the terminating impedance at both ends of the main transmission line of the parallel plate coupler, that is, the connection impedance between the input port P1 and the output port (straight-through port P2) of the parallel plate coupler 30.

[0045] It should also be noted that, Figure 4 The input port P1 of the parallel plate coupler 30 is connected Figure 1 The carrier amplifier 10 is located in the parallel plate coupler 30. The through port P2 of the parallel plate coupler 30 outputs the output signal. The coupling port P4 of the parallel plate coupler 30 is connected to the peak amplifier 20.

[0046] In some embodiments of this disclosure, reference is made to Figure 4 The reconfigurable load network 40 is configured to increase the load impedance of the carrier amplifier 10 to at least n+1 times the load impedance of the parallel plate coupler 30 when the power of the second input signal is less than the turn-on power of the peak amplifier 20. The value of n can range from 1 to 2. For example, if the characteristic impedance of the parallel plate coupler 30 is Z0, then the load impedance of the parallel plate coupler 30 is Z0 / At this point, the parallel plate coupler 30 weakens the dynamic impedance modulation effect, thus reducing the efficiency improvement during power back-off. Therefore, when the power ratio of the first input signal and the second input signal is 1:1, the reconfigurable load network 40 increases the load impedance of the carrier amplifier 10 to more than twice the load impedance of the parallel plate coupler 30. In this way, when the RF input signal is at low power, the load impedance of the isolation port is in a high-impedance state, causing the carrier amplifier 10 to saturate earlier. This allows the output voltage of the carrier amplifier 10 to quickly reach the transistor's saturation voltage with a smaller output current, entering the saturation operating region earlier. The amplifier efficiency in the saturation region is much higher than in the linear region, thus significantly improving the overall efficiency below the peak power (e.g., the 6dB back-off point), thereby extending the high-efficiency range to a larger power back-off range and improving back-off power.

[0047] It should be noted that the amplitude-phase characteristic (AM-PM) describes the relationship between the amplitude change of the input signal and the phase change of the output signal. Essentially, it is the coupling between amplitude and phase caused by device nonlinearity. As the operating point moves towards the linear region, the nonlinearity of the device decreases, and the impact of amplitude changes on phase also diminishes.

[0048] In some embodiments of this disclosure, reference is made to Figure 4 The reconfigurable load network 40 is also configured to increase the load impedance of the carrier amplifier 10 to more than n times the load impedance of the parallel plate coupler 30, provided that the power of the output signal does not increase linearly with the increase of the power of the RF input signal. The signal transmission characteristics of the parallel plate coupler 30 are based on an ideal transmission line, i.e., when the frequency of the RF input signal is lower than the design center frequency, the signal transmission delay is less than 90 degrees; conversely, when the frequency of the RF input signal is higher than the center frequency, the signal transmission delay is greater than 90 degrees. In the case of impedance mismatch of the parallel plate coupler 30 (e.g., when the isolation port P3 is not connected to a load with a specific characteristic impedance), the signal transmission delay will fluctuate more drastically with frequency. The signal phase difference between the carrier amplifier 10 and the peak amplifier 20 introduced by the input power distribution is typically -90 degrees. Therefore, the reconfigurable load network 40 can adjust the load impedance of the carrier amplifier 10 by adjusting the load impedance of the isolation port P3, thereby performing specific phase compensation. For example, when the power ratio of the first input signal and the second input signal is 1:1, the reconfigurable load network 40 increases the load impedance of the carrier amplifier 10 to more than twice the load impedance of the parallel plate coupler 30. Thus, in this embodiment of the present disclosure, the phase difference of the carrier amplifier 10 in both the small-signal output power range and the large-signal output power range is reduced, thereby optimizing the amplitude-phase characteristic (AM-PM) of the overall amplifier circuit 100.

[0049] In some embodiments of this disclosure, reference is made to Figure 4The parallel plate coupler 30 includes an upper plate 310, a lower plate 320, and a second capacitor C2. The two ends of the second capacitor C2 are connected to the upper plate 310 and the lower plate 320, respectively. The coupling strength of the parallel plate coupler 30 is directly related to the total capacitance of the upper plate 310 and the lower plate 320. Thus, the second capacitor C2 increases the total capacitance between the upper plate 310 and the lower plate 320, effectively enhancing the signal coupling of the parallel plate coupler 30. For example, during the propagation of a high-frequency signal in the strongly coupled structure (parallel plate coupler 30), phase error accumulates more slowly, offsetting the negative impact of the short coupling length on bandwidth. Therefore, the strong coupling characteristics of the parallel plate coupler 30 can further enhance the bandwidth of the amplifier circuit 100.

[0050] Figure 5 This is a schematic diagram of the structure of an optional reconfigurable load network 40 provided in an embodiment of this disclosure.

[0051] In some embodiments of this disclosure, reference is made to Figure 5 The reconfigurable load network 40 includes a variable capacitor 41 and a control module 42. The variable capacitor 41 can set the impedance of the isolation port of the parallel plate coupler 30 according to the operating frequency band of the amplifier circuit 100. Therefore, this disclosure can adjust the impedance value of the isolation port of the parallel plate coupler 30 through the reconfigurable load network 40 to apply impedance modulation amplification of the carrier amplifier 10, and to apply impedance balancing performance of the carrier amplifier 10 and the peak amplifier 20, thereby achieving independent performance optimization in different frequency bands.

[0052] In this embodiment of the disclosure, reference is made to Figure 5 The control module 42 is connected to the variable capacitor 41. The control module 42 is configured to receive radio frequency input signals and adjust the capacitance value of the variable capacitor based on at least one of the frequency band and power of the radio frequency input signals. For example, the control module 42 is connected one-to-one with each switch (switch T1, T2...Tn), and is configured to generate multiple control signals according to the power level, transmitting each control signal to a corresponding switch to control the switches. Specifically, the control module 42 can calculate or determine the operating frequency band based on the received signal strength (RSSI), communication services, etc., or can obtain the operating frequency band from an external module, and generate control signals based on the operating frequency band to control each switch to control and adjust the capacitance value of the variable capacitor 41, so that the load impedance of the isolation port of the parallel plate coupler 30 corresponds to the operating frequency band.

[0053] In this embodiment of the disclosure, reference is made to Figure 5The control module 42 can be an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field-programmable gate array (FPGA), a central processing unit (CPU), a graphics processing unit (GPU), or an embedded neural network processor. Any combination of one or more of the following: network processing units (NPU), controllers, microcontrollers, and microprocessors.

[0054] In some embodiments of this disclosure, reference is made to Figure 5 The variable capacitor 41 includes multiple switches T1 and multiple first capacitors C1.

[0055] In this embodiment of the disclosure, reference is made to Figure 5 The first ends of multiple first capacitors C1 are all connected to the isolation port of the parallel plate coupler 30. The second ends of multiple first capacitors C1 are connected in series with a switch T1, and are grounded through the series-connected switch T1. In this embodiment, the reconfigurable load network 40 can control the optimal phase and optimal modulation impedance for amplifying signals of different frequency bands using multiple first capacitors C1. Furthermore, by recording and saving the optimal first capacitor values ​​for each frequency band, individual optimization can be performed for each communication frequency band, resulting in a highly efficient and highly linear signal amplification effect.

[0056] In some embodiments of this disclosure, reference is made to Figure 5 The coupling coefficient of the parallel plate coupler 30 is greater than or equal to 0.8.

[0057] Figure 6 This is a schematic diagram of an optional amplifier circuit 100 provided in an embodiment of this disclosure. It should be noted that... Figure 6 The “RFIN” in the code is used to receive radio frequency input signals. Figure 6 The “RFOUT” in the code is used to output the output signal. Figure 6 The separator 50 in the middle can also be used for... Figure 6 Other devices for separating signals besides the quadrature coupler shown. Figure 6Amplifier 60 in the diagram can be a driver-stage amplifier.

[0058] In some embodiments of this disclosure, reference is made to Figure 6 The amplifier circuit 100 also includes a splitter 50. The splitter 50 is connected to both the carrier amplifier 10 and the peak amplifier 20. The splitter 50 is configured to receive a radio frequency (RF) input signal and split it into a first input signal and a second input signal. For example, the first input signal output by the splitter 50 may maintain its original phase, while the second input signal output by the splitter 50 may introduce a precise 90° phase shift. Alternatively, the splitter 50 may adjust the amplitudes of the first and second input signals according to a preset power distribution ratio (e.g., 1:1 or an asymmetrical ratio).

[0059] Figure 7 and Figure 8 This is an optional structural diagram of the optional radio frequency chip 200 provided in the embodiments of this disclosure. Figure 7 and Figure 8 The illustrated RF chip 200 includes the amplifier circuit 100 described in any of the above embodiments. It should be noted that... Figure 7 and Figure 8 The load matching structures 70a and 70b shown are composed of circuits consisting of inductor and capacitor elements with specific values. The main functions of the load matching structures 70a and 70b include providing power supply bias for the amplifier circuit and achieving RF impedance matching for the RF output circuit at the fundamental frequency and higher harmonic frequencies such as the first and second orders. Figure 7 and Figure 8 The substrate 201 shown may be made of silicon or other semiconductor elements, such as germanium (Ge), or may include semiconductor compounds such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or may include other semiconductor alloys such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof, without limitation herein.

[0060] In some embodiments of this disclosure, reference is made to Figure 7 In the amplifier circuit 100, the ports corresponding to the upper plate 310 and lower plate 320 of the parallel plate coupler 30 can be located on the same side. In other embodiments of this disclosure, reference is made to... Figure 8 In the amplifier circuit 100, the ports of the upper plate 310 and lower plate 320 of the parallel plate coupler 30 can be set on opposite sides.

[0061] Figure 9This is a schematic diagram of the structure of an electronic device 300 provided in an embodiment of the present disclosure, as shown below. Figure 9 As shown, the electronic device 300 includes the aforementioned radio frequency chip 200. The electronic device 300 can be any of the following: a server, mobile phone, tablet computer, computer with wireless transceiver function, handheld computer, desktop computer, personal digital assistant, portable media player, smart speaker, navigation device, smartwatch, smart glasses, smart necklace and other wearable devices, pedometer, digital TV, virtual reality (VR) terminal device, augmented reality (AR) terminal device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, vehicle in a vehicle networking system, in-vehicle equipment, in-vehicle module, etc.

[0062] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0063] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An amplifier circuit, characterized in that, include: Parallel plate coupler, carrier amplifier, peak amplifier, and reconfigurable load network; among which, The carrier amplifier is configured to receive and amplify the first input signal; The peak amplifier is configured to receive and amplify the second input signal; wherein the first input signal and the second input signal are formed by separating the same radio frequency input signal; The parallel plate coupler, which is connected to the carrier amplifier and the peak amplifier respectively, is configured to receive the amplified first input signal and the second input signal, and to combine the amplified first input signal and the second input signal into an output signal. The reconfigurable load network, connected to the isolation port of the parallel plate coupler, is configured to adjust the load impedance of the isolation port based on the frequency of the RF input signal; wherein the load impedance of the isolation port is inversely proportional to the frequency of the RF input signal. The reconfigurable load network includes a variable capacitor; as the frequency of the radio frequency input signal increases, the reconfigurable load network decreases its capacitance value.

2. The amplifier circuit according to claim 1, characterized in that, The power ratio of the first input signal to the second input signal is n:1; The reconfigurable load network is configured to increase the load impedance of the carrier amplifier to more than n+1 times the load impedance of the parallel plate coupler when the power of the second input signal is less than the turn-on power of the peak amplifier.

3. The amplifier circuit according to claim 2, characterized in that, The reconfigurable load network is further configured to increase the load impedance of the carrier amplifier to more than n times the load impedance of the parallel plate coupler, provided that the power of the output signal does not increase linearly with the increase of the power of the RF input signal.

4. The amplifier circuit according to claim 3, characterized in that, The reconfigurable load network further includes: a control module; wherein... The control module, connected to the variable capacitor, is configured to receive the radio frequency input signal and adjust the capacitance value of the variable capacitor based on at least one of the frequency and power of the radio frequency input signal.

5. The amplifier circuit according to claim 4, characterized in that, The variable capacitor includes: multiple switches and multiple first capacitors; wherein... The first terminals of the plurality of first capacitors are all connected to the isolation ports of the parallel plate coupler; The second terminals of the plurality of first capacitors are connected in series with a switch, and are grounded through the series-connected switches.

6. The amplifier circuit according to claim 1, characterized in that, The input port of the parallel plate coupler is connected to the carrier amplifier; the through port of the parallel plate coupler outputs the output signal; and the coupling port of the parallel plate coupler is connected to the peak amplifier.

7. The amplifier circuit according to claim 6, characterized in that, The parallel plate coupler includes an upper plate, a lower plate, and a second capacitor; wherein... The two ends of the second capacitor are connected to the upper plate and the lower plate, respectively.

8. The amplifier circuit according to claim 1, characterized in that, Also includes: Separator; wherein, The splitter, connected to the carrier amplifier and the peak amplifier respectively, is configured to receive the radio frequency input signal and separate the radio frequency input signal into the first input signal and the second input signal.

9. A radio frequency chip, characterized in that, Includes the amplifier circuit described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the radio frequency chip as described in claim 9.

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