Pcie forking adaptive configuration method and related apparatus

Abstract

The application relates to a PCIe bifurcation adaptive configuration method and related devices. The method is cooperatively executed by a BMC and a BIOS: the BMC scans and accesses an expansion slot adapter card in a mainboard slot through an IIC bus, and obtains a board card identifier of the expansion slot adapter card; the BMC matches a predefined hardware configuration mapping table according to a combination of the board card identifier, and if the matching is successful, a configuration identifier of the hardware configuration mapping table is obtained, otherwise a default identifier is obtained; the BIOS sends a request to the BMC, and if the request is successful, the configuration identifier returned by the BMC is stored, otherwise the request is resent after a delay period; the BIOS indexes a predefined PCIe bifurcation parameter table according to the configuration identifier to adaptively configure a bifurcation mode of a CPU integrated PCIe channel controller; the BIOS indexes a predefined slot allocation table according to the configuration identifier to associate the mainboard slot with a PCIe channel, and restricts bandwidth allocation of the mainboard slot according to the bifurcation mode.

Description

Technical Field

[0001] This application relates to the field of bandwidth configuration technology, and in particular to a PCIe fork adaptive configuration method and related apparatus. Background Technology

[0002] High-speed components in computer devices are interconnected using the Peripheral Component Interconnect Rapid (PCIe) standard. Devices have PCIe input / output (I / O) units with multiple channels for communicating data. These I / O units can include 4, 8, or 16 channels, which can be divided into different communication channels for connecting to different PCIe devices. A forking control mechanism from the Basic Input / Output System (BIOS) allows the bus I / O unit to be split into smaller buses for use with different PCIe devices.

[0003] Given that the number of slots on a server motherboard is fixed, an RC (Regulator / Adapter) is typically installed on the motherboard to accommodate multiple PCIe devices. Different types of RCs are used to connect to different types of PCIe external cards, such as network cards or smart network cards. For this hardware design, the BIOS needs to allocate PCIe bandwidth based on the different wiring methods of the hardware. Since the peripherals used in servers vary depending on the application scenario, the PCIe configuration will also differ.

[0004] However, currently, a single BIOS version only supports a single default IIO (Integrated I / O) branch configuration. When customers connect different peripherals, they need to manually adapt the PCIe configuration in the BIOS. After updating the BIOS version, the configuration will be reset, requiring manual reconfiguration. This results in a poor user experience and inconvenient maintenance in the future.

[0005] Therefore, how to adapt PCIe fork configurations to various hardware combinations is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] To address the aforementioned issues, this application provides a PCIe fork adaptive configuration method and related apparatus.

[0007] In a first aspect, embodiments of this application provide a PCIe fork adaptive configuration method, which is executed collaboratively by the BMC and BIOS within a computer device, wherein:

[0008] The BMC scans the expansion slot adapter cards connected to the motherboard slot via the IIC bus and obtains the board identifier of the expansion slot adapter card.

[0009] The BMC matches the combination of the board identifiers with a predefined hardware configuration mapping table. If the match is successful, it obtains the configuration identifier of the hardware configuration mapping table; otherwise, it obtains the default identifier.

[0010] The BIOS sends a request to the BMC. If the request is successful, it stores the configuration identifier or the default identifier returned by the BMC. Otherwise, it waits for a delay period and then resends the request.

[0011] The BIOS adapts the configuration of the CPU integrated PCIe channel controller's fork mode by indexing a predefined PCIe fork parameter table based on the configuration identifier, or loads the default configuration of the CPU integrated PCIe channel controller's fork mode based on the default identifier.

[0012] The BIOS indexes a predefined slot allocation table based on the configuration identifier to associate the motherboard slot with the PCIe channel, and constrains the bandwidth allocation of the motherboard slot according to the fork pattern.

[0013] In some embodiments, the hardware configuration mapping table includes the board identifier of the expansion slot adapter card, the model of the expansion slot adapter card, and the location of the expansion slot adapter card; the PCIe fork parameter table includes the CPU identifier, PCIe channel, and fork mode code corresponding to the configuration identifier; and the slot mapping table includes the motherboard slot, CPU identifier, and PCIe channel corresponding to the configuration identifier.

[0014] In some embodiments, when the BMC returns the configuration identifier, the BIOS stores the configuration identifier in non-volatile memory and in an identifier storage unit accessible to the BIOS runtime.

[0015] In some embodiments, after the BIOS constrains the bandwidth allocation of the motherboard slot according to the fork mode, the BIOS traverses the PCIe channels and determines whether the PCIe channel is in a specific fork mode; if so, it calls the volume management device function of the corresponding PCIe channel; otherwise, it skips the corresponding PCIe channel.

[0016] In some embodiments, after the BIOS constrains the bandwidth allocation of the motherboard slot according to the fork mode, it dynamically updates the SMBIOS system slot information table and marks the PCIe channels that share the same motherboard slot.

[0017] In some embodiments, when the BIOS repeatedly resends the request but fails each time, and the accumulated delay period exceeds a preset threshold, it reads the historically stored configuration identifier from the non-volatile memory.

[0018] In some embodiments, the BIOS indexes a predefined PCIe forking parameter table based on the historically stored configuration identifiers to adaptively configure the forking mode of the CPU integrated PCIe channel controller; at the same time, it indexes a predefined slot allocation table based on the historically stored configuration identifiers to associate the motherboard slots with the PCIe channels, and constrains the bandwidth allocation of the motherboard slots according to the forking mode.

[0019] Secondly, embodiments of this application also provide a server motherboard, which includes:

[0020] Motherboard slots are used to connect expansion slot adapter cards to PCIe devices.

[0021] BMC; and

[0022] The BIOS, the BMC, and the BIOS work together to execute any of the PCIe fork adaptive configuration methods described above.

[0023] Thirdly, embodiments of this application also provide a server, which includes:

[0024] Server motherboards of any of the types described above;

[0025] An expansion slot adapter card is connected to the motherboard slot of the server motherboard; and

[0026] PCIe devices that are plugged into the expansion slot adapter card.

[0027] In some embodiments, the PCIe device includes one or more combinations of a graphics card, a sound card, a smart network card, a storage controller card, and a disk array card.

[0028] Compared to related technologies, the PCIe fork adaptive configuration method provided in this application achieves higher-dimensional PCIe fork adaptive configuration by abstracting hardware combinations into configuration identifiers. It eliminates the need for manual intervention in the BIOS interface, making it convenient to operate. The method provided in this application achieves synchronous linkage between PCIe fork mode, VMD function, and SMBIOS information updates, ensuring the accuracy of hardware topology. In addition, it provides a fault tolerance mechanism, recalling historical configurations when requests fail to avoid system startup anomalies. The method provided in this application has high reliability.

[0029] This application also provides a server motherboard and server, which have the same technical effects as the aforementioned PCIe fork adaptive configuration method. Attached Figure Description

[0030] Figure 1 This is a flowchart illustrating the PCIe fork adaptive configuration method (BMC) implemented according to an embodiment of this application.

[0031] Figure 2 This is a flowchart illustrating the PCIe fork adaptive configuration method performed by the BIOS according to one embodiment of this application.

[0032] Figure 3 A flowchart illustrating the PCIe fork adaptive configuration method for enabling volume management device functionality according to one embodiment of this application.

[0033] Figure 4 A flowchart illustrating the PCIe fork adaptive configuration method for updating visualization information provided in one embodiment of this application.

[0034] Figure 5 The flowchart illustrates the startup fault tolerance mechanism of the PCIe fork adaptive configuration method provided in one embodiment of this application.

[0035] Figure 6 This is a schematic diagram of the hardware structure of a server provided in one embodiment of this application. Detailed Implementation

[0036] This application provides a PCIe fork adaptive configuration method, which achieves higher-dimensional adaptive configuration by abstracting hardware combinations into configuration identifiers, eliminating the need for manual intervention in the BIOS interface and making the operation convenient.

[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0038] Please see Figure 1 , Figure 1 This is a flowchart illustrating the PCIe fork adaptive configuration method performed by the Baseboard Management Controller (BMC) according to one embodiment of this application. The method is executed collaboratively by the BMC and BIOS within a computer device, and includes the following steps for the BMC:

[0039] In step S100, the BMC scans the expansion slot adapter cards connected to the motherboard slot via the IIC bus and obtains the board ID of the expansion slot adapter cards.

[0040] In step S200, the BMC matches the combination of the board identifiers against a predefined hardware configuration mapping table (SKU table). If the match is successful, the process proceeds to S201; otherwise, the process proceeds to S202.

[0041] Step S201: Obtain the configuration identifier (SKU ID) of the hardware configuration mapping table.

[0042] The hardware configuration mapping table includes the board identifier of the expansion slot adapter card, the model of the expansion slot adapter card, and the location of the expansion slot adapter card.

[0043] It is understood that the expansion slot adapter card (RiserCard, hereinafter referred to as RC) is a hardware device used to connect different types of external devices to the PCIe slot of the server motherboard. It can be a PCIe to USB (Universal Serial Bus) expansion card, a PCIe to SATA (Serial ATA) expansion card, or a PCIe to SlimSAS (Slim Serial Attached SCSI) expansion card, etc. The selection of the expansion slot adapter card depends on the type of external device actually connected to the server motherboard, and no specific limitation is made here.

[0044] It is understood that the configuration identifier is a distinguishing identifier for the hardware configuration mapping table. Each SKU table corresponds to a unique SKU ID, and a valid combination of RCs exists in a unique SKU table.

[0045] It is understood that the model number of the expansion slot adapter card is a common naming convention for a type of RC (Radio Control Controller), describing the physical specifications and functional characteristics of the RC, such as physical size, supported PCIe generations, maximum number of channels, etc. The board identifier of the expansion slot adapter card is a hardware fingerprint burned and fixed by the manufacturer. Even if two cards have the same model number but different Board IDs, they are considered as two independent entities.

[0046] It is understood that the location of the expansion slot adapter card refers to the location of the motherboard slot into which the expansion slot adapter card is connected, and is represented by the physical identifier of the motherboard slot, such as a silkscreen number. For ease of explanation, Tables 1 and 2 exemplarily disclose some SKU table representations, and Table 1 can be defined as SKU ID=1, and Table 2 as SKU ID=2.

[0047] Step S202: Obtain the default identifier. If the expansion slot adapter card connected to the motherboard slot has an unknown configuration, and the BMC cannot match the corresponding hardware configuration mapping table based on the combination of the card identifiers, then it obtains the SKU ID corresponding to the default configuration SKU table to ensure successful system startup. Of course, the default PCIe fork configuration may not perfectly meet actual usage requirements, but the configuration can still be manually adjusted later to obtain a more reasonable bandwidth allocation. In this embodiment, the default identifier SKU ID can be set to 0.

[0048] Furthermore, step S201 or step S202 can proceed to step S300. In step S300, the BMC writes the configuration identifier or the default identifier into an internal register, and simultaneously sets the status identifier to a completed state.

[0049] In this embodiment, the BMC writes the configuration identifier or the default identifier into memory, and simultaneously sets the single-byte status identifier (Flag) stored in the BMC memory to 1. The Flag has only two valid states: Flag=0 indicates that the BMC has not yet completed the aforementioned steps; Flag=1 indicates that the BMC has completed the aforementioned steps and has saved the SKU ID. In other embodiments, the status identifier can also be designed as other status bits.

[0050] Since the BMC and the BIOS work together, the BIOS may request the SKU ID from the BMC early in the PEI (Pre-Equilibrium Initialization) phase, and the time required for BMC scanning depends on the actual number of RCs. Step S300 resolves the timing competition between BMC scanning and BIOS startup, avoiding blind polling by the BIOS.

[0051] Please see Figure 2 For the BIOS, the following steps are included:

[0052] In step S400, the BIOS sends a request to the BMC. In this embodiment, the BIOS requests the SKU ID value from the BMC by calling a general PPI (Platform PEI Interface, a communication interface in the PEI stage), such as SendIpmiCommand, and sending the command "OEM IPMI 0x2a 0x80".

[0053] In step S500, the BIOS determines whether the request is successful. If the request is successful, the process proceeds to S501; otherwise, the process proceeds to S502.

[0054] In this embodiment, the BIOS determines whether the request was successful based on the return status of the SendIpmiCommand command and the status of the Flag. If the SendIpmiCommand command returns "success" and Flag=1, it means the command was sent successfully and the BMC completed steps S100 to S300, the BIOS request was successful, and the BMC can be considered to have returned a correct and reliable SKU ID. Conversely, if the SendIpmiCommand command returns another status or the Flag has another status value, the BIOS request was unsuccessful.

[0055] Step S501: The BIOS stores the configuration identifier or the default identifier returned by the BMC. In this embodiment, when the BMC returns the configuration identifier, the BIOS stores the SKU ID to non-volatile memory, such as a CMOS chip, using the PcdSet function. Simultaneously, it stores it to an identifier storage unit accessible to the BIOS runtime, for example, by defining a global variable PcdSkulId(Platform Configuration Database - SKUID, SKU identifier in the platform configuration database).

[0056] In step S502, the BIOS waits for a delay period, and the process returns to S400. In this embodiment, the BIOS can be configured to wait 10 seconds and then resend the request to the BMC starting from step S400.

[0057] After step S501, the process proceeds to step S600.

[0058] Step S600: Determine whether it is the configuration identifier. If it is the configuration identifier, proceed to S700; otherwise, proceed to S701.

[0059] In step S700, the BIOS adaptively configures the fork mode of the CPU integrated PCIe channel controller by indexing the predefined PCIe fork parameter table (IioBifurcationTable) according to the configuration identifier, or loads the default configured fork mode of the CPU integrated PCIe channel controller according to the default identifier.

[0060] In this embodiment, the BIOS obtains the saved SKU ID from the PcdSkulId using the PcdGet function. Based on the IioBifurcationTable corresponding to the SKU ID index, the BIOS configures the IIO module mode using the parameters in the IioBifurcationTable to achieve adaptive configuration of the PCIe fork.

[0061] It can be understood that the IIO module is a PCIe controller built into the CPU, which physically manages the branching of PCIe channels, signal routing, clock control, etc.

[0062] It is understood that the IioBifurcationTable includes a CPU identifier (CPUSocket), PCIe channel (PE Port), and fork mode encoding (IIO Bifurcation) corresponding to the SKU ID. The CPU identifier is used to identify the target CPU. In this embodiment, each CPU supports 5 PCIe channels, and bandwidth is allocated for each PCIe channel using a fork mode encoding of x16, x8, or x4. For ease of explanation, Table 3 exemplarily discloses one representation of the IioBifurcationTable, where SKU ID=1 can be defined for Table 3.

[0063] Table 3, from top to bottom, represents the parameter configurations of CPU0's PE0 channel having exclusive x16 bandwidth, CPU0's PE1 channel split into dual x8 bandwidth, and CPU1's PE0 channel split into four x4 bandwidth.

[0064] After step S700, the process proceeds to step S800.

[0065] In step S800, the BIOS indexes a predefined slot allocation table (IioSlotTable) based on the configuration identifier to associate the motherboard slot with the PCIe channel, and constrains the bandwidth allocation of the motherboard slot according to the fork mode.

[0066] It can be understood that IioSlotTable establishes a dynamic mapping relationship between the motherboard slot and the CPU's internal PCIe controller channel (PE Port), allowing the same motherboard slot to be mapped to different CPU PCIe channels under different SKU IDs, thus achieving adaptive configuration of PCIe branching in the physical topology. For ease of explanation, Table 4 exemplarily discloses a representation of IioBifurcationTable, where SKU ID=1 can be defined for Table 4.

[0067] Referring to Tables 1 to 4, in this embodiment, the RC-A card inserted into Slot 1 occupies the full bandwidth of CPU0 PE0 channel x16, the RC-B card inserted into Slot 2 occupies the bandwidth of CPU0 PE1 channel x8, and the RC-C card inserted into Slot 3 occupies the bandwidth of CPU1 PE0 channel x4.

[0068] Step S701: Load the default configuration of the CPU integrated PCIe channel controller's fork mode according to the default identifier. It can be understood that the basic principle of the BIOS loading the default configuration of the CPU integrated PCIe channel controller's fork mode according to the default identifier is similar to that described above. The difference is that it does not need to index the IioBifurcationTable or IioSlotTable, but directly loads the default configuration without modifying the parameters.

[0069] Furthermore, to make the configuration functionality more complete, the adaptive configuration of the PCIe channel controller's fork mode also accommodates the enabling of the Volume Management Device (VMD) function. Please refer to [link to relevant documentation]. Figure 3 In another embodiment, step S700 may proceed to step S800.

[0070] In step S900, the BIOS traverses the PCIe channels and determines whether each PCIe channel is in a specific fork mode; if so, proceed to step S901; otherwise, proceed to step S902. In this embodiment, the BIOS traverses the PCIe channels and determines whether each PCIe channel is in an x4 fork mode. Specifically, the GetVariable service is used to read the set bandwidth of a CPU's PE Port channel.

[0071] Step S901: Invoke the volume management device function of the corresponding PCIe channel. Specifically, enable the corresponding Port VMD function using SetVariable.

[0072] Step S902: Skip the corresponding PCIe channel.

[0073] Furthermore, to facilitate later maintenance, after adaptively configuring the PCIe channel controller's fork mode, the visualization information of the PCIe channel controller's fork mode is updated. Please refer to [link / reference needed]. Figure 4 In another embodiment, step S800 may proceed to step S801.

[0074] Step S801: Dynamically update the SMBIOS system slot information table and mark the PCIe channels sharing the same motherboard slot. In this embodiment, the UpdateSmbiosType9Table function is used to update the relevant information in the system slot information table (Type 9) in the SMBIOS (System Management BIOS) table.

[0075] Specifically, the value of PcdSkuId is read using PcdGet to reconfirm the current SKU ID. The motherboard slot information is obtained using the GetSKUIdAndMatchSlotinfo function, and the global slot information pointer gSlotInfo is checked for null. If null, the EFI_INVALID_PARAMETER error code is returned. Each slot information is iterated over; if the motherboard slot information is null, the current loop is skipped; otherwise, the SMBIOS type 9 basic information is filled according to the current SKU table. Finally, the gEfiSmbiosProtocol->Add function is called to add the updated Type 9 table structure to the SMBIOS table.

[0076] To ensure a smooth system startup, if the process still cannot continue from step S501 after multiple attempts at step S502, please refer to [the relevant documentation / reference]. Figure 5 In another embodiment, if the BIOS repeatedly resends the request but fails each time, and the cumulative delay exceeds a preset threshold, such as more than 2 minutes, the historically stored configuration identifier is invoked to prevent abnormal system startup.

[0077] In this embodiment, after step S502, steps S503-S506 are also included.

[0078] Step S503: Determine whether the cumulative delay period exceeds a preset threshold. If not, the process returns to step S400; if so, the process proceeds to step S504.

[0079] In step S504, the BIOS reads the configuration identifier stored in the history from the non-volatile memory.

[0080] It is understandable that in the historical process, when the BMC returned the configuration identifier, the BIOS stored the SKU ID in non-volatile memory using the PcdSet function. Therefore, in the current process, the BIOS can retrieve the previously stored SKU ID from the PcdSkulId using the PcdGet function.

[0081] Step S505: The BIOS indexes a predefined PCIe fork parameter table based on the historically stored configuration identifier to adaptively configure the fork mode of the CPU integrated PCIe channel controller.

[0082] In step S506, the BIOS indexes a predefined slot allocation table based on the historically stored configuration identifiers to associate the motherboard slots with the PCIe lanes, and constrains the bandwidth allocation of the motherboard slots according to the fork mode.

[0083] It is understood that the basic principles of steps S505 to S506 are similar to or the same as those of steps S600 to S700, and therefore will not be repeated. Steps S505 to S506 provide a fault tolerance mechanism, which calls the historical configuration when the request fails, to avoid abnormal system startup. The method provided in this application has high reliability.

[0084] It is understandable that, similar to step S700, step S506 can also proceed to step S800 or step S900.

[0085] Please refer to Figure 6 , Figure 6 This is a schematic diagram of the hardware structure of a server provided in one embodiment of this application. The server 100 includes a server motherboard 101, which has a motherboard slot 1011, a BMC 1013, and a BIOS 1015. The motherboard slot 1011 is used to connect an expansion slot adapter card 103, which is used to connect a PCIe device 105. The BMC and the BIOS cooperate to execute the PCIe fork adaptive configuration method as described above.

[0086] It is understood that the PCIe device 105 includes one or more combinations of graphics cards, sound cards, smart network cards, storage controller cards, and disk array cards. Of course, the PCIe device 105 can also be other types of PCIe devices, and this application does not make any special limitations here.

[0087] The server motherboard 101 includes a motherboard slot 1011, a BMC 1013, and a BIOS 1015. The BMC 1013 and the BIOS 1015 work together to perform the operations described above.

[0088] It should be noted that, in this specification, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0089] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A PCIe fork adaptive configuration method, characterized in that, This is executed collaboratively by the BMC and BIOS within the computer device, where: The BMC scans the expansion slot adapter cards connected to the motherboard slot via the IIC bus and obtains the board identifier of the expansion slot adapter card. The BMC matches the combination of the board identifiers with a predefined hardware configuration mapping table. If the match is successful, the configuration identifier of the hardware configuration mapping table is obtained; otherwise, the default identifier is obtained. The hardware configuration mapping table includes the board identifier of the expansion slot adapter card, the model of the expansion slot adapter card, and the location of the expansion slot adapter card. The BIOS sends a request to the BMC. If the request is successful, it stores the configuration identifier or the default identifier returned by the BMC. Otherwise, it waits for a delay period and then resends the request. The BIOS adapts the configuration of the CPU integrated PCIe channel controller's fork mode by indexing a predefined PCIe fork parameter table based on the configuration identifier, or loads the default configuration of the CPU integrated PCIe channel controller's fork mode based on the default identifier. The PCIe fork parameter table includes the CPU identifier, PCIe channel, and fork mode code corresponding to the configuration identifier. The BIOS indexes a predefined slot allocation table based on the configuration identifier to associate the motherboard slot with the PCIe channel, and constrains the bandwidth allocation of the motherboard slot according to the fork mode. The slot allocation table includes the motherboard slot, CPU identifier, and PCIe channel corresponding to the configuration identifier.

2. The PCIe fork adaptive configuration method according to claim 1, characterized in that, When the BMC returns the configuration identifier, the BIOS stores the configuration identifier in non-volatile memory and in an identifier storage unit accessible to the BIOS runtime.

3. The PCIe fork adaptive configuration method according to claim 1, characterized in that, After constraining the bandwidth allocation of the motherboard slot according to the fork mode, the BIOS traverses the PCIe channels and determines whether the PCIe channel is in a specific fork mode; if so, it calls the volume management device function of the corresponding PCIe channel; otherwise, it skips the corresponding PCIe channel.

4. The PCIe fork adaptive configuration method according to claim 2, characterized in that, After constraining the bandwidth allocation of the motherboard slot according to the fork mode, the BIOS dynamically updates the SMBIOS system slot information table and marks the PCIe channels that share the same motherboard slot.

5. The PCIe fork adaptive configuration method according to claim 2, characterized in that, If the BIOS fails to send the request multiple times and the accumulated delay exceeds a preset threshold, it reads the configuration identifier stored in the historical memory from the non-volatile memory.

6. The PCIe fork adaptive configuration method according to claim 5, characterized in that, The BIOS uses the historically stored configuration identifiers to index a predefined PCIe fork parameter table to adaptively configure the fork mode of the CPU integrated PCIe channel controller; at the same time, it uses the historically stored configuration identifiers to index a predefined slot allocation table to associate the motherboard slots with the PCIe channels, and constrains the bandwidth allocation of the motherboard slots according to the fork mode.

7. A server motherboard, characterized in that, include: Motherboard slots are used to connect expansion slot adapter cards to PCIe devices. BMC; and The BIOS, wherein the BMC cooperates with the BIOS to execute the PCIe fork adaptive configuration method as described in any one of claims 1-6.

8. A server, characterized in that, include: The server motherboard as described in claim 7; An expansion slot adapter card is connected to the motherboard slot of the server motherboard; and PCIe devices that are plugged into the expansion slot adapter card.

9. The server according to claim 8, characterized in that, The PCIe devices include one or more combinations of graphics cards, sound cards, smart network cards, storage controller cards, and disk array cards.

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