Flash information display method and server

Abstract

This invention relates to the field of server technology, and discloses a flash memory information display method and a server. In response to a system switching command sent by a baseboard management controller (BMC), a complex programmable logic device (CLP) selects a target basic input / output system (BIOS) from the set of input / output systems and switches to the target BOS. The BMC records the switch from the current BOS to the target BOS and saves the flash memory information of the target BOS. The target BOS performs a power-on self-test and retrieves the flash memory information from the BMC. The flash memory information is displayed to characterize the model of the BOS connected to the server host. In this way, the flash memory information of the target BOS can be obtained, allowing users to understand the operating status of the BOS and determine the currently running BOS based on the flash memory information, ensuring the normal operation of the server.

Description

Technical Field

[0001] This invention relates to the field of server technology, and more specifically to a flash memory information display method and server. Background Technology

[0002] The Basic Input / Output System (BIOS) typically stores basic server settings and configuration information, such as boot order and hardware parameters, in the form of a chip. When the server starts, the BIOS reads this information and initializes the hardware accordingly. If the BIOS chip fails, the server may fail to boot or experience other hardware problems, leading to malfunctions and impacting its reliability and stability. Even if a backup BIOS is configured within the server, switching to the backup BIOS after the current one fails, users are often unaware of the BIOS failure or which BIOS is damaged. Consequently, the damaged BIOS may not be replaced during server maintenance, further compromising server reliability and stability. Summary of the Invention

[0003] In view of this, the present invention provides a flash memory information display method and server to solve the problem that when a backup basic input / output system is set up, it is not possible to directly know which basic input / output system is currently running, resulting in poor server reliability and stability.

[0004] In a first aspect, the present invention provides a flash memory information display method, the method comprising:

[0005] In response to a system switching command sent by the baseboard management controller, the complex programmable logic device (CPLP) selects a target basic input / output system from the set of input / output systems and switches to the target basic input / output system. The set of input / output systems includes multiple basic input / output systems. The system switching command is generated by the baseboard management controller based on the detection results obtained by the complex programmable logic device from detecting the current basic input / output system. The current basic input / output system is the basic input / output system connected to the server host when the server host is powered on.

[0006] The baseboard management controller records the switching from the current basic input / output system to the target basic input / output system and saves the flash memory information of the target basic input / output system;

[0007] The target basic input / output system performs a power-on self-test and obtains flash memory information from the baseboard management controller; the flash memory information is used to display and characterize the model of the basic input / output system connected to the server host.

[0008] In this way, when an abnormality occurs in the basic input / output system (PIS), a target PIS can be selected from the set of PIS based on the system switching command. This ensures that the target PIS connected to and running on the server can operate normally, thereby guaranteeing the normal operation of the server and improving its reliability and stability. At the same time, the flash memory information of the target PIS can be obtained, allowing users to understand the operating status of the PIS and determine the currently running PIS based on the flash memory information, ensuring the normal operation of the server.

[0009] In one optional implementation, the method for generating system switching instructions includes:

[0010] When the server host is powered on, the complex programmable logic device detects the current basic input / output system;

[0011] When a complex programmable logic device detects an anomaly in the current basic input / output system, the complex programmable logic device determines the detection result as an anomaly and sends system anomaly information to the baseboard management controller.

[0012] The baseboard management controller generates system switching instructions based on system anomaly information and sends the system switching instructions to the complex programmable logic device.

[0013] In this way, when there is an anomaly in the current basic input / output system, a system switching command can be generated to switch the basic input / output system and ensure that the basic input / output system of the access server can operate normally.

[0014] In one alternative implementation, the complex programmable logic device detects the current basic input / output system, including:

[0015] The complex programmable logic device detects the status indication signals and reset signals of the current basic input / output system;

[0016] When the complex programmable logic device (CPL) detects that the status indication signal or the reset signal is at a high level, the CPL detects the first input / output signal; the first input / output signal is a set signal sampled during the firmware initialization phase; the first input / output signal is used to determine the completion status of firmware initialization;

[0017] When the complex programmable logic device (CPL) detects that the first input / output signal is at a high level within a first preset time, the CPL detects the second input / output signal; the second input / output signal is a set signal sampled at the end of the current basic input / output system startup; the second input / output signal is used to determine the startup completion status of the current basic input / output system.

[0018] When the complex programmable logic device detects that the second input / output signal is at a low level within a second preset time, the complex programmable logic device determines that an anomaly has been detected in the current basic input / output system.

[0019] In one alternative implementation, the complex programmable logic device detects the current basic input / output system, further including:

[0020] When a complex programmable logic device (CPL) detects a status indicator signal at a low level or a reset signal at a low level, the CPL determines that an anomaly has been detected in the current basic input / output system.

[0021] When the complex programmable logic device (CPL) detects that the first input / output signal is not detected to be at a low level within a first preset time, the CPL determines that an anomaly has been detected in the current basic input / output system.

[0022] In this way, it is possible to determine whether there is an anomaly in the current basic input / output system based on the relevant signals when the server is powered on.

[0023] In one alternative implementation, the method further includes:

[0024] When the server host is powered on, the baseboard management controller adds sampling points for the first input / output signal during the firmware initialization phase based on the server's hardware structure, and adds sampling points for the second input / output signal when the current basic input / output system finishes startup.

[0025] In one alternative implementation, the target basic input / output system performs a power-on self-test, including:

[0026] The target basic input / output system checks the hardware devices of the server host to obtain the device information of the hardware devices;

[0027] When the target basic input / output system detects an abnormal situation, the target basic input / output system determines the error information corresponding to the abnormal situation;

[0028] The target basic input / output system acquires device startup information.

[0029] In this way, the flash memory information of the target basic input / output system, the device information of the hardware devices, as well as the abnormal situations that occur during the server startup process and the relevant information of the startup devices can be obtained during the power-on self-test, so that users can understand the detailed situation of the server startup process.

[0030] In one alternative implementation, before the target basic input / output system performs a power-on self-test and obtains flash memory information from the baseboard management controller, the following steps are also included:

[0031] The target basic input / output system initializes the display adapter and obtains the server host's identification information.

[0032] In a second aspect, the present invention provides a server, comprising: a baseboard management controller, a complex programmable logic device, an input / output system assembly, and a server host; the baseboard management controller, the complex programmable logic device, the input / output system assembly, and the server host are communicatively connected; the server host includes hardware devices for server operation; the input / output system assembly includes multiple basic input / output systems;

[0033] The complex programmable logic device (CPLD) is used to select a target basic input / output system (PIS) from the set of input / output systems and switch to the target PIS in response to a system switching command sent by the baseboard management controller. The system switching command is generated by the baseboard management controller based on the detection results obtained by the CPLD from detecting the current PIS. The current PIS is the PIS connected to the server host when the server host is powered on.

[0034] The baseboard management controller is used to record the switching of the current basic input / output system to the target basic input / output system and to save the flash memory information of the target basic input / output system;

[0035] The target basic input / output system is used for power-on self-test and obtains flash memory information from the baseboard management controller; the flash memory information is used to display and characterize the basic input / output system connected to the server host.

[0036] In one alternative implementation, when the server host is powered on, the complex programmable logic device is used to detect the current basic input / output system, and when an anomaly is detected in the current basic input / output system, to determine that the detection result is an anomaly and to send system anomaly information to the baseboard management controller.

[0037] The baseboard management controller is used to generate system switching instructions based on system anomaly information and send system switching instructions to complex programmable logic devices.

[0038] In one alternative implementation, when the server host is powered on, the baseboard management controller adds sampling points for a first input / output signal during the firmware initialization phase and adds sampling points for a second input / output signal when the current basic input / output system finishes startup, based on the server's hardware architecture. Attached Figure Description

[0039] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0040] Figure 1 This is a flowchart illustrating a flash memory information display method according to an embodiment of the present invention;

[0041] Figure 2 This is a flowchart illustrating another flash memory information display method according to an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of a specific embodiment of the flash memory information display method according to an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of the server structure according to an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0046] The Basic Input Output System (BIOS) is a crucial component of a server. It's responsible for booting the computer and initializing its hardware. Typically stored as firmware on the server's motherboard, it's battery-powered and retains data even when the server is powered off. The BIOS contains basic server settings and configuration information, such as boot order, hardware detection and initialization, system time, and date. During server startup, the BIOS runs first, entering the Power-On Self-Test (POST) phase. It initializes and performs self-tests on the server's hardware, displays relevant information on the screen, and then hands control over to the operating system. If the BIOS chip is damaged or malfunctions, the server may fail to boot or experience other hardware problems, leading to malfunctions and impacting its reliability and stability. Even if a backup basic input / output system is set up, after the basic input / output system is switched, the user does not know which basic input / output system the server is currently running. The inability to replace the abnormal basic input / output system in time can lead to the backup basic input / output system also becoming abnormal. The server has no backup basic input / output system, or it is not clear which basic input / output system needs to be replaced. As a result, the normal basic input / output system is replaced while the abnormal basic input / output system is retained, which affects the reliability and stability of the server.

[0047] To address the aforementioned issues, this invention provides a flash memory information display method. In response to a system switching command sent by a baseboard management controller (BMC), a complex programmable logic device (CPU) selects a target basic input / output system (PIS) from a set of input / output systems (IPS) and switches to that target PIS. The IPS set includes multiple PISs. The system switching command is generated by the BMC based on the detection results obtained from the CPU's detection of the current PIS. The current PIS is the PIS connected to the server host when it is powered on. The BMC records the switch from the current PIS to the target PIS and saves the flash memory information of the target PIS. The target PIS performs a power-on self-test and retrieves the flash memory information from the BMC. The flash memory information is displayed to characterize the model of the PIS connected to the server host. In this way, when an abnormality occurs in the basic input / output system (PIS), a target PIS can be selected from the set of PIS based on the system switching command. This ensures that the target PIS connected to and running on the server can operate normally, thereby guaranteeing the normal operation of the server and improving its reliability and stability. At the same time, the flash memory information of the target PIS can be obtained, allowing users to understand the operating status of the PIS and determine the currently running PIS based on the flash memory information, ensuring the normal operation of the server.

[0048] According to an embodiment of the present invention, a flash memory information display method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0049] This embodiment provides a flash memory information display method, which can be used in the aforementioned server. Figure 1 This is a flowchart of a flash memory information display method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0050] In step S101, in response to the system switching command sent by the board management controller, the complex programmable logic device selects a target basic input / output system from the set of input / output systems and switches to the target basic input / output system.

[0051] In this embodiment of the invention, the input / output system set includes multiple basic input / output systems. These basic input / output systems can serve as backup basic input / output systems, forming redundancy of basic input / output systems. When the basic input / output system currently connected to the server, i.e., the basic input / output system connected to the server host when the server host is powered on, malfunctions and cannot operate normally, a target basic input / output system can be selected from the input / output system set for replacement and connected to the server to ensure the normal operation of the server.

[0052] In this embodiment of the invention, when the Complex Programmable Logic Device (CPLD) receives a system switching instruction sent by the Baseboard Management Controller (BMC), it responds to the system switching instruction, selects a target Basic Input / Output System from the input / output systems, and switches from the current Basic Input / Output System to the target Basic Input / Output System.

[0053] In this embodiment of the invention, the system switching instruction is generated by the baseboard management controller based on the detection results obtained by the complex programmable logic device (CPL) from detecting the current basic input / output system. When the CPL detects an anomaly in the current basic input / output system, it determines the detection result as an anomaly and sends system anomaly information to the baseboard management controller. The baseboard management controller then generates a system switching instruction based on this system anomaly information, instructing the CPL to switch the basic input / output system.

[0054] In one alternative implementation, after switching the current basic input / output system to the target basic input / output system, the current basic input / output system can be moved into the abnormal input / output system set, the flash memory information of the current basic input / output system can be recorded, and the flash memory information can be stored in the abnormal information log so that the user can retrieve the abnormal information log to identify the abnormal basic input / output system and replace the chip of the abnormal basic input / output system in a timely manner.

[0055] In one optional implementation, the method for generating system switching instructions may specifically include the following steps:

[0056] Step a1: When the server host is powered on, the complex programmable logic device detects the current basic input / output system.

[0057] In this embodiment of the invention, as described above, the current basic input / output system is the basic input / output system connected to the server host when it is powered on. The complex programmable logic device (CPL) detects the current basic input / output system, mainly by detecting relevant signals of the current basic input / output system, thereby determining whether the current basic input / output system has started normally and entered the power-on self-test (POST) phase normally. If no relevant signals for normal startup or normal entry into the POST phase are detected, it indicates that the current basic input / output system is abnormal and cannot operate normally, requiring a switch to select a backup basic input / output system from the input / output systems to connect to the server.

[0058] In one alternative implementation, step a1, where the complex programmable logic device detects the current basic input / output system, may specifically include:

[0059] First, the complex programmable logic controller (CPL) detects the status indicator and reset signals of the current basic input / output system (PIS). The status indicator is the SLP# signal, and the reset signal is the Platform Reset signal. Both the status indicator and reset signals should be high when the PIS flash memory is accessible. This step primarily determines whether the flash memory of the current PIS is accessible.

[0060] At this point, there are two scenarios regarding the status indicator signal or reset signal. First, if the complex programmable logic controller (CPLC) detects a low-level status indicator signal or a low-level reset signal, it indicates that the flash memory of the basic input / output system (PIS) cannot be accessed normally, confirming an anomaly in the current PIS. Second, if the CPLC detects a high-level status indicator signal or reset signal, it further detects the first input / output signal. This first input / output signal is a set signal sampled during the firmware initialization phase, used to determine the completion status of firmware initialization. This step primarily determines whether the current PIS has successfully completed the initialization of the server's firmware and hardware devices.

[0061] At this point, there are two scenarios regarding the first input / output signal. First, if the complex programmable logic controller (CPL) detects the first input / output signal as low within a first preset time period, it indicates that the current basic input / output system (PIS) has not completed the initialization of the server's firmware and hardware within the specified time, confirming an anomaly in the current PIS. Second, if the CPL detects the first input / output signal as high within the first preset time period, it then checks the second input / output signal. If the CPL detects the first input / output signal as high within the first preset time period, it indicates that the current PIS has completed the initialization of the server's firmware and hardware within the specified time, and the second input / output signal is checked at this stage. The second input / output signal is a set signal sampled at the end of the current PIS startup process, used to determine the startup completion status of the current PIS. This step primarily determines whether the current PIS has successfully completed startup and can proceed to the power-on self-test (POST) phase.

[0062] If the complex programmable logic controller (CPLC) detects that the second input / output signal is low within the second preset time period, the CPLC determines that an anomaly has been detected in the current basic input / output system (PIS). If the CPLC detects that the second input / output signal is high within the second preset time period, it indicates that the current PIS has successfully started within the specified time and can normally enter the power-on self-test (POST) phase. If the CPLC detects that the second input / output signal is low within the second preset time period, it indicates that the current PIS has not completed startup within the specified time, and an anomaly has been detected in the current PIS.

[0063] In one optional implementation, the first input / output signal and the second input / output signal are obtained by the baseboard management controller based on the server's hardware structure by configuring general purpose input / output (GPIO) as indication signals respectively. The first input / output signal is a set signal added during the pre-initialization (PEI) phase, which can be denoted as GPIOx signal, and the sampling point of the first input / output signal is added during the firmware initialization phase. The second input / output signal is a set signal added at the end of the basic input / output system startup, which can be denoted as GPIOy signal, and the sampling point of the second input / output signal is added at the end of the current basic input / output system startup.

[0064] Specifically, the anomalies of the current basic input / output system can be divided into 6 categories, as follows:

[0065] The first type is where the flash memory of the current basic input / output system is damaged, resulting in the flash memory becoming inaccessible.

[0066] The second type is that the peripheral circuitry of the flash memory in the current basic input / output system has a problem, or the clock has a problem, which makes the flash memory inaccessible.

[0067] The third type is where the flash memory of the current basic input / output system is empty;

[0068] The fourth type is that the contents of the Management Engine (ME) area of ​​the flash memory of the current basic input / output system are corrupted or empty;

[0069] The fifth type is where the firmware of the flash memory management engine of the current basic input / output system is normal, but the contents of its boot block area are corrupted or empty;

[0070] The sixth category is where the boot block firmware of the flash memory of the current basic input / output system is fine, but its main firmware volume area (Firmware Volume_MAIN, FV_MAIN) is damaged or empty.

[0071] Among them, the first to fourth types of anomalies can be detected by detecting the status indication signal or the reset signal, the fifth type of anomaly can be detected by detecting the first input / output signal, and the sixth type of anomaly can be detected by detecting the second input / output signal.

[0072] Step a2: When the complex programmable logic device detects an anomaly in the current basic input / output system, the complex programmable logic device determines that the detection result is abnormal and sends system anomaly information to the baseboard management controller.

[0073] Step a3: The baseboard management controller generates a system switching instruction based on the system anomaly information and sends the system switching instruction to the complex programmable logic device.

[0074] In one optional implementation, when the baseboard management controller receives system abnormality information, it will also perform a forced shutdown to switch the basic input / output system, ensuring that the basic input / output system of the access server can operate normally.

[0075] In step S102, the baseboard management controller records the switch from the current basic input / output system to the target basic input / output system and saves the flash memory information of the target basic input / output system.

[0076] In this embodiment of the invention, to prevent situations where, after a basic input / output (PI) system switch, users are unaware of which PI is currently running on the server, and fail to promptly replace faulty PIs, leading to all PIs in the PI set becoming faulty, the server lacking a backup PI, or unsure which PI needs replacement, resulting in the replacement of a normal PI while retaining the faulty one, the baseboard management controller (BMC), as monitoring and management hardware, can record the switch from the current PI to the target PI and save the flash memory information of the target PI. This allows users to understand the operating status of the PI and determine the currently running PI based on the flash memory information. In other words, the BMC can record the flash memory information of the target PI and the corresponding PI switch information in the system switch log, facilitating users' understanding of the server's historical operation and maintenance. Specifically, the switch information may include the PI switch time, the switch reason, and the flash memory information of the PI before the switch, etc.

[0077] Step S103: The target basic input / output system performs a power-on self-test and obtains flash memory information from the baseboard management controller.

[0078] In this embodiment of the invention, the flash memory information refers to relevant information about the flash memory of the basic input / output system (PIS), used to distinguish between the basic I / O systems included in the I / O system set. The flash memory information is used to display and characterize the model of the basic I / O system accessing the server host. Specifically, the target basic I / O system sends an IPMI (Intelligent Platform Management Interface) command to the baseboard management controller to query the baseboard management controller for the flash memory information stored therein; upon receiving the IPMI command, the baseboard management controller returns the flash memory information to the target basic I / O system.

[0079] In one alternative implementation, each basic input / output system included in the input / output system set may be numbered and corresponding identification information may be generated to distinguish each basic input / output system.

[0080] The flash memory information display method provided in this invention can select a target basic input / output system from the set of input / output systems according to a system switching instruction when a basic input / output system malfunctions. This ensures that the target basic input / output system connected to and running on the server can operate normally, thereby guaranteeing the normal operation of the server and improving its reliability and stability. Simultaneously, it can acquire the flash memory information of the target basic input / output system, enabling users to understand the operating status of the basic input / output system and determine the currently running basic input / output system based on the flash memory information, thus ensuring the normal operation of the server.

[0081] This embodiment provides a flash memory information display method, which can be used in the aforementioned server. Figure 2 This is a flowchart of a flash memory information display method according to an embodiment of the present invention, such as... Figure 2 As shown, the process includes the following steps:

[0082] In step S201, in response to a system switching command sent by the board management controller, the complex programmable logic device selects a target basic input / output system from the set of input / output systems and switches to the target basic input / output system. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0083] In step S202, the baseboard management controller records the switch from the current basic input / output system to the target basic input / output system and saves the flash memory information of the target basic input / output system. For details, please refer to [link to relevant documentation]. Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0084] Step S203: The target basic input / output system performs a power-on self-test and obtains flash memory information from the baseboard management controller.

[0085] Specifically, step S203, the target basic input / output system power-on self-test, includes:

[0086] In step S2031, the target basic input / output system checks the hardware devices of the server host and obtains the device information of the hardware devices.

[0087] In this embodiment of the invention, during the power-on self-test (POST) of the target basic input / output system, the system first checks the hardware devices of the server host to obtain device information. This device information may include information about devices such as the processor, memory, and hard drives in the server host; specifically, it may include information such as the processor model, memory capacity, number of hard drives, and capacity of each hard drive.

[0088] Step S2032: When the target basic input / output system detects an abnormal situation, the target basic input / output system determines the error information corresponding to the abnormal situation.

[0089] In this embodiment of the invention, the error information may include error codes and prompts, and the target basic input / output system can display the error information corresponding to the abnormal situation through the corresponding display device so that the user can understand the details of the server startup process.

[0090] Step S2033: The target basic input / output system acquires device startup information.

[0091] In this embodiment of the invention, device startup information may include already started devices, as well as their model and serial number. The target basic input / output system can display the device startup information through a corresponding display device so that users can understand the details of the server startup process.

[0092] In an optional implementation, a step of initializing the display adapter is included before step S203 to ensure that the display adapter can function properly and that the display device can display correctly. Specifically, the target basic input / output system initializes the display adapter and displays the server host's identification information on the screen based on the display adapter. The initialization of the display adapter includes setting the display adapter's display mode, resolution, and character set, etc.; the server host's identification information includes the server manufacturer's logo and the target basic input / output system's version number, etc.

[0093] Figure 3 This is a schematic diagram of a specific embodiment of the flash memory information display method according to an embodiment of the present invention, such as... Figure 3As shown, after the server system is powered on, the complex programmable logic device (CLP) performs a test on the basic input / output system, first checking for the SLP# signal or the Platform signal. If the Reset signal is normal, and the SLP# or PlatformReset signal is normal, the GPIOx signal is checked. If the GPIOx signal is normal, the GPIOy signal is checked. If the GPIOy signal is normal, the check ends, and the basal input / output system enters the power-on self-test (POST) phase. If any abnormal signal is detected during the above checks, a system abnormality message is sent to the baseboard management controller (BMC). The BMC generates a system switching command to instruct the complex programmable logic device (CPLD) to switch the basal input / output system. At the same time, the BMC records the flash memory information of the basal input / output system after the switch. On the other hand, the BMC adds sampling points for the GPIOx and GPIOy signals according to the server's hardware design. During the firmware startup phase, the GPIOx signal is configured to a high level, and the monitoring duration for this phase is set, for example, 45 seconds. If no abnormality occurs during the firmware startup phase, the GPIOx signal will remain high. Before the basal input / output system finishes startup, the GPIOy signal is configured to a high level, and the monitoring duration for this phase is set, for example, 20 minutes. If no abnormality occurs before the basal input / output system finishes startup, the GPIOy signal will remain high.

[0094] This embodiment also provides a server, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the terms "module" and "unit" can refer to a combination of software and / or hardware that performs a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0095] This embodiment provides a server. Figure 3 This is a schematic diagram of the server structure according to an embodiment of the present invention, such as... Figure 4 As shown, the server includes: a baseboard management controller 100, a complex programmable logic device 200, an input / output system assembly 300, and a server host 400, wherein the baseboard management controller 100, the complex programmable logic device 200, the input / output system assembly 300, and the server host 400 are communicatively connected.

[0096] In this embodiment of the invention, the server host 400 includes hardware devices for server operation, such as a processor, hard disk, etc. The input / output system set 300 includes multiple basic input / output systems (PIS). These PIS can serve as backup PIS, forming redundancy. When the currently connected PIS malfunctions and cannot operate normally, a replacement PIS 310 can be selected from the PIS set 300 and connected to the server to ensure normal server operation.

[0097] In this embodiment of the invention, the complex programmable logic device 200, in response to a system switching command sent by the baseboard management controller 100, selects a target basic input / output system 310 from the input / output system set 300 and switches to the target basic input / output system 310. The system switching command is generated by the baseboard management controller 100 based on the detection result obtained by the complex programmable logic device 200 detecting the current basic input / output system. The current basic input / output system is the basic input / output system connected to the server host 400 when it is powered on. The baseboard management controller 100 records the switching from the current basic input / output system to the target basic input / output system and saves the flash memory information of the target basic input / output system 310. The target basic input / output system 310 performs a power-on self-test and obtains the flash memory information from the baseboard management controller 100. The flash memory information is used to display and characterize the model of the basic input / output system connected to the server host.

[0098] In one optional implementation, when the server host 400 is powered on, the complex programmable logic device 200 is used to detect the current basic input / output system, and when an anomaly is detected in the current basic input / output system, it determines the detection result as an anomaly and sends system anomaly information to the baseboard management controller 100; the baseboard management controller 100 is used to generate a system switching instruction based on the system anomaly information and send the system switching instruction to the complex programmable logic device 200.

[0099] In one optional implementation, the complex programmable logic device 200 detects the current basic input / output system as follows: First, the complex programmable logic device detects the status indication signal and reset signal of the current basic input / output system. The status indication signal is the SLP# signal, and the reset signal is the Platform Reset signal. When the flash memory of the basic input / output system is accessible, both the status indication signal and the reset signal should be at a high level. This step primarily determines whether the flash memory of the current basic input / output system is accessible.

[0100] At this point, there are two scenarios regarding the status indicator signal or reset signal. First, if the complex programmable logic controller (CPLC) detects a low-level status indicator signal or a low-level reset signal, it indicates that the flash memory of the basic input / output system (PIS) cannot be accessed normally, confirming an anomaly in the current PIS. Second, if the CPLC detects a high-level status indicator signal or reset signal, it further detects the first input / output signal. This first input / output signal is a set signal sampled during the firmware initialization phase, used to determine the completion status of firmware initialization. This step primarily determines whether the current PIS has successfully completed the initialization of the server's firmware and hardware devices.

[0101] At this point, there are two scenarios regarding the first input / output signal. First, if the complex programmable logic controller (CPL) detects the first input / output signal as low within a first preset time period, it indicates that the current basic input / output system (PIS) has not completed the initialization of the server's firmware and hardware within the specified time, confirming an anomaly in the current PIS. Second, if the CPL detects the first input / output signal as high within the first preset time period, it then checks the second input / output signal. If the CPL detects the first input / output signal as high within the first preset time period, it indicates that the current PIS has completed the initialization of the server's firmware and hardware within the specified time, and the second input / output signal is checked at this stage. The second input / output signal is a set signal sampled at the end of the current PIS startup process, used to determine the startup completion status of the current PIS. This step primarily determines whether the current PIS has successfully completed startup and can proceed to the power-on self-test (POST) phase.

[0102] If the complex programmable logic controller (CPLC) detects that the second input / output signal is low within the second preset time period, the CPLC determines that an anomaly has been detected in the current basic input / output system (PIS). If the CPLC detects that the second input / output signal is high within the second preset time period, it indicates that the current PIS has successfully started within the specified time and can normally enter the power-on self-test (POST) phase. If the CPLC detects that the second input / output signal is low within the second preset time period, it indicates that the current PIS has not completed startup within the specified time, and an anomaly has been detected in the current PIS.

[0103] In one optional implementation, the first input / output signal and the second input / output signal are obtained by the baseboard management controller based on the server's hardware structure by configuring general purpose input / output (GPIO) as indication signals respectively. The first input / output signal is a set signal added during the pre-initialization (PEI) phase, which can be denoted as GPIOx signal, and the sampling point of the first input / output signal is added during the firmware initialization phase. The second input / output signal is a set signal added at the end of the basic input / output system startup, which can be denoted as GPIOy signal, and the sampling point of the second input / output signal is added at the end of the current basic input / output system startup.

[0104] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A flash information display method characterized by comprising: The method includes: In response to a system switching command sent by the baseboard management controller, the complex programmable logic device (CPLD) selects a target basic input / output system from the set of input / output systems and switches to the target basic input / output system. The set of input / output systems includes multiple basic input / output systems. The system switching command is generated by the baseboard management controller based on the detection result obtained by the complex programmable logic device from detecting the current basic input / output system. The current basic input / output system is the basic input / output system connected to the server host when the server host is powered on. The baseboard management controller records the switching of the current basic input / output system to the target basic input / output system and saves the flash memory information of the target basic input / output system; The target basic input / output system performs a power-on self-test and obtains the flash memory information from the baseboard management controller; the flash memory information is used to display and characterize the model of the basic input / output system connected to the server host; The method for generating the system switching command includes: when the server host is powered on, the complex programmable logic device (CPLD) detects the current basic input / output system (PIS); when the CPLD detects an anomaly in the current PIS, the CPLD determines the detection result as an anomaly and sends system anomaly information to the baseboard management controller (BMC); the BMC generates the system switching command based on the system anomaly information and sends the system switching command to the CPLD. The complex programmable logic device (CPL) performs detection on the current basic input / output system (PIS), including: detecting a status indication signal and a reset signal of the current PIS; when the CPL detects that the status indication signal or the reset signal is at a high level, the CPL detects a first input / output signal; the first input / output signal is a set signal sampled during the firmware initialization phase; the first input / output signal is used to determine the completion status of firmware initialization; when the CPL detects that the first input / output signal is at a high level within a first preset time, the CPL detects a second input / output signal; the second input / output signal is a set signal sampled when the current PIS startup ends; the second input / output signal is used to determine the startup completion status of the current PIS; when the CPL detects that the second input / output signal is at a low level within a second preset time, the CPL determines that an anomaly has been detected in the current PIS.

2. The method of claim 1, wherein, The complex programmable logic device performs detection on the current basic input / output system, and also includes: When the complex programmable logic device detects that the status indication signal is at a low level, or detects that the reset signal is at a low level, the complex programmable logic device determines that an anomaly has been detected in the current basic input / output system; If, within the first preset time period, the complex programmable logic device detects that the first input / output signal is not detected to be at a low level, the complex programmable logic device determines that an anomaly has been detected in the current basic input / output system.

3. The method according to claim 1 or 2, characterized in that, The method further includes: When the server host is powered on, the baseboard management controller, based on the server's hardware structure, adds sampling points of the first input / output signal during the firmware initialization phase and adds sampling points of the second input / output signal when the current basic input / output system starts up.

4. The method of claim 1, wherein, The target basic input / output system's power-on self-test includes: The target basic input / output system checks the hardware devices of the server host to obtain the device information of the hardware devices; When the target basic input / output system detects an abnormal situation, the target basic input / output system determines the error information corresponding to the abnormal situation; The target basic input / output system acquires device startup information.

5. The method of claim 1, wherein, Before the target basic input / output system performs a power-on self-test and obtains the flash memory information from the baseboard management controller, the system further includes: The target basic input / output system initializes the display adapter and obtains the identification information of the server host.

6. A server, characterized by include: Baseboard management controller, complex programmable logic devices, input / output system integration, and server host; The baseboard management controller, the complex programmable logic device, the input / output system assembly, and the server host are communicatively connected; the server host includes hardware devices for running the server; the input / output system assembly includes multiple basic input / output systems; The complex programmable logic device (CLPD) is used to select a target basic input / output system (PIS) from the set of input / output systems and switch to the target PIS in response to a system switching command sent by the baseboard management controller. The system switching command is generated by the baseboard management controller based on the detection result obtained by the CLPD from detecting the current PIS. The current PIS is the PIS connected to the server host when the server host is powered on. The baseboard management controller is used to record the switching of the current basic input / output system to the target basic input / output system, and to save the flash memory information of the target basic input / output system; The target basic input / output system is used for power-on self-test and obtains the flash memory information from the baseboard management controller; the flash memory information is used to display and characterize the model of the basic input / output system connected to the server host; When the server host is powered on, the complex programmable logic device is used to detect the current basic input / output system, and when an anomaly is detected in the current basic input / output system, the complex programmable logic device determines that the detection result is abnormal and sends system anomaly information to the baseboard management controller; The baseboard management controller is used to generate the system switching command based on the system anomaly information and send the system switching command to the complex programmable logic device. The complex programmable logic device detects the current basic input / output system, including: the complex programmable logic device detects the status indication signal and reset signal of the current basic input / output system; When the complex programmable logic device (CPL) detects that the status indication signal or the reset signal is at a high level, the CPL detects a first input / output signal; the first input / output signal is a set signal sampled during the firmware initialization phase; the first input / output signal is used to determine the completion status of firmware initialization; when the CPL detects that the first input / output signal is at a high level within a first preset time, the CPL detects a second input / output signal; the second input / output signal is a set signal sampled when the current basic input / output system (PIS) finishes startup; the second input / output signal is used to determine the completion status of the current PIS startup; when the CPL detects that the second input / output signal is at a low level within a second preset time, the CPL determines that an anomaly has been detected in the current PIS.

7. The server of claim 6, wherein, When the server host is powered on, the complex programmable logic device is used to detect the current basic input / output system, and when an anomaly is detected in the current basic input / output system, to determine that the detection result is an anomaly, and to send system anomaly information to the baseboard management controller; The baseboard management controller is used to generate the system switching instruction based on the system anomaly information and send the system switching instruction to the complex programmable logic device.

8. The server of claim 6, wherein, When the server host is powered on, the baseboard management controller is used to add sampling points of the first input / output signal during the firmware initialization phase and add sampling points of the second input / output signal when the current basic input / output system starts up, based on the server's hardware structure.

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