Phase interpolator unit circuit and phase interpolator
By adding a current control unit and a multi-capacitor parallel design to the phase interpolator unit circuit, the problems of narrow frequency range and poor linearity of traditional phase interpolators are solved, achieving flexible frequency adjustment and reduced power consumption, thus improving the applicability of the circuit and the accuracy of the signal.
Patent Information
- Application Number
- CN202511091692.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-05
- Publication Date
- 2025-11-28
AI Technical Summary
Traditional phase interpolator unit circuits have poor adaptability over a wide frequency range, cannot simultaneously achieve low-frequency and high-frequency performance, and have fixed output capacitors that cannot be dynamically adjusted, resulting in inaccurate signal phase shift.
A current control unit is added to the phase interpolator unit circuit, and a multi-capacitor parallel design is adopted. The drive current and output capacitor are adjusted by the current control unit to achieve flexible frequency adjustment.
It expands the applicable frequency range of the phase interpolator, reduces power consumption at low frequencies, improves circuit flexibility and energy efficiency, and ensures signal phase accuracy.
Smart Images
Figure CN121036732A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of high-speed data transmission, in particular to a phase interpolator unit circuit and a phase interpolator. BACKGROUND
[0002] A phase interpolator (PI) is a device that can mix two periodic input clock signals with the same frequency but different phases according to a specific ratio, and then generate an output clock signal with the same frequency as the input but with a phase between the two.
[0003] However, the conventional phase interpolator unit circuit has significant defects. On the one hand, it performs poorly in wide frequency range input adaptability. If the circuit design is oriented to meet the low frequency input demand, the element parameters and structure are optimized for low frequency characteristics. When facing high frequency input, due to insufficient driving ability, it will cause signal distortion and attenuation, and cannot accurately process and transmit high frequency signals. If the high frequency input design is emphasized, although it can cope with high frequency signals, the driving design is large, which will cause large power waste when low frequency input, affecting the stability and reliability of the circuit, and it is difficult to balance the low frequency and high frequency performance. On the other hand, the output capacitance of the conventional phase interpolator unit circuit is fixed. Different frequency input clocks have different requirements for circuit linearity, and the fixed capacitance cannot be dynamically adjusted with the input frequency, making it difficult to provide appropriate electrical characteristics to ensure linearity. This will cause inaccurate signal phase shift, and the output clock signal phase cannot be accurately between the two input signals, limiting the implementation of multi-frequency input design. SUMMARY
[0004] The purpose of the present application is to provide a phase interpolator unit circuit and a phase interpolator, which solves the technical problems of narrow input frequency range and poor linearity faced by existing phase interpolators by adding a current control unit in the unit circuit architecture and using the innovative design of multiple capacitances in parallel to configure the output capacitance.
[0005] To solve the above technical problems, the present application is realized by the following technical scheme:
[0006] The present application provides a phase interpolator unit circuit, which comprises a driving unit, an enable control unit and a current control unit.
[0007] The input end of the driving unit is connected with an input clock signal, and the output end is connected with the input end of the enable control unit and the current control unit, respectively.
[0008] The control end of the enable control unit is connected with an enable control signal, and is used to open or close the phase interpolator unit circuit according to the enable control signal.
[0009] The control end of the current control unit is connected with a current control signal, and the output end is connected with the output end of the enable control unit, for adjusting the driving current of the phase interpolator unit circuit according to the frequency of the input clock signal, so as to meet the driving requirements of different frequency input clock signals.
[0010] In an embodiment of the present application, the driving unit comprises a first PMOS tube and a first NMOS tube.
[0011] The control end of the first PMOS tube and the first NMOS tube is connected with the input clock signal.
[0012] The source end of the first PMOS tube is connected with a system power supply, and the drain end is connected with the first input end of the enable control unit and the current control unit as the first output end of the driving unit.
[0013] The source end of the first NMOS tube is connected with a system ground, and the drain end is connected with the second input end of the enable control unit and the current control unit as the second output end of the driving unit.
[0014] In an embodiment of the present application, the enable control unit comprises a second PMOS tube, a first resistor, a second resistor and a second NMOS tube.
[0015] The control end of the second PMOS tube is connected with a first enable control signal, the source end is connected with the first output end of the driving unit, and the drain end is connected with the first end of the first resistor.
[0016] The control end of the second NMOS tube is connected with a second enable control signal, the source end is connected with the second output end of the driving unit, and the drain end is connected with the first end of the second resistor.
[0017] The second end of the first resistor and the second resistor is connected with the output end of the enable control unit and the output end of the current control unit.
[0018] In an embodiment of the present application, the first enable control signal and the second enable control signal are opposite.
[0019] In an embodiment of the present application, the current control unit comprises a third PMOS tube, a third resistor, a fourth resistor and a third NMOS tube.
[0020] The control end of the third PMOS tube is connected with a first current control signal, the source end is connected with the first output end of the driving unit, and the drain end is connected with the first end of the third resistor.
[0021] The control end of the third NMOS transistor is connected with a second current control signal, the source end is connected with the second output end of the driving unit, and the drain end is connected with the first end of the fourth resistor;
[0022] The second ends of the third resistor and the fourth resistor are connected with the output end of the enable control unit as the output end of the current control unit.
[0023] In one embodiment of the present application, the first current control signal and the second current control signal are opposite.
[0024] Based on the same inventive concept, another embodiment of the present application further provides a phase interpolator, comprising: a first phase interpolator unit circuit, a second phase interpolator unit circuit and a linearity adjusting unit, wherein the first phase interpolator unit circuit and the second phase interpolator unit circuit adopt the phase interpolator unit circuit structure as described in any of the above embodiments;
[0025] The input end of the first phase interpolator unit circuit is connected with a first input clock signal, for performing phase adjustment on the first input clock signal.
[0026] The input end of the second phase interpolator unit circuit is connected with a second input clock signal, for performing phase adjustment on the second input clock signal.
[0027] The output end of the first phase interpolator unit circuit is connected with the output end of the second phase interpolator unit circuit, for performing signal superposition on the output signals of the first phase interpolator unit circuit and the second phase interpolator unit circuit to generate a phase interpolation signal.
[0028] The input end of the linearity adjusting unit is connected with the output ends of the first phase interpolator unit circuit and the second phase interpolator unit circuit, for receiving the phase interpolation signal and performing linearity adjustment on the phase interpolation signal.
[0029] In one embodiment of the present application, the phase interpolator further comprises a driving circuit, the input end of the driving circuit is connected with the output end of the linearity adjusting unit, for providing stable driving capability to the subsequent circuit.
[0030] In one embodiment of the present application, the first input clock signal and the second input clock signal have the same frequency but different phases.
[0031] In one embodiment of the present application, the linearity adjusting unit comprises a plurality of capacitance control units arranged in parallel, each capacitance control unit comprises a transmission gate and a capacitance.
[0032] The first end of the transmission gate is connected with the output ends of the first phase interpolator unit circuit and the second phase interpolator unit circuit, and the control end of the transmission gate is connected with a capacitance control signal, and the transmission gate is controlled to be turned on or turned off through the capacitance control signal.
[0033] The first end of the capacitance is connected with the second end of the transmission gate, and the second end of the capacitance is connected with a system ground.
[0034] As described above, the phase interpolator unit circuit provided by the application comprises a driving unit, an enable control unit and a current control unit. The input end of the driving unit is connected with an input clock signal, and the output ends are respectively connected with the input ends of the enable control unit and the current control unit. The control end of the enable control unit is connected with an enable control signal, and the phase interpolator unit circuit is turned on or turned off according to the enable control signal. The control end of the current control unit is connected with a current control signal, and the output end is connected with the output end of the enable control unit, and the driving current of the phase interpolator unit circuit is adjusted according to the frequency of the input clock signal, so as to meet the driving requirements of different frequency input clock signals. The phase interpolator unit circuit realizes accurate regulation of the current size through the switch connected with the current control bit, and based on this, the phase interpolator unit circuit can flexibly adjust the driving parameters according to the requirements of different frequency scenes, thereby effectively expanding the applicable frequency range of the phase interpolator. At the same time, in the low-frequency working state, such current control mechanism can also reduce the power consumption of the circuit, and improve the energy efficiency performance of the circuit. In the design of the output capacitance, a multi-capacitance parallel structure is adopted, and an additional large-capacitance control bit is arranged. Through this design, a capacitance value meeting the lowest frequency requirement can be flexibly selected according to the actual requirements. In this way, when the design requirements of the low-frequency clock are met, a large number of capacitance configuration bits do not need to be additionally increased, and the functional requirements can be realized only through the large-capacitance control bit, thereby effectively avoiding the redundant increase of the capacitance configuration bits, and significantly improving the flexibility and simplicity of the circuit design. Of course, any product implementing the application does not necessarily need to achieve all the advantages described above. BRIEF DESCRIPTION OF DRAWINGS
[0035] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without creative labor.
[0036] Figure 1 A structural schematic diagram of a phase interpolator unit circuit provided by an exemplary embodiment of the application.
[0037] Figure 2A structure diagram of a phase interpolator unit circuit provided for another exemplary embodiment of the present application.
[0038] Figure 3 A whole circuit diagram of a phase interpolator provided for an exemplary embodiment of the present application.
[0039] Figure 4 A first diagram of a phase interpolator control implementation provided for an exemplary embodiment of the present application.
[0040] Figure 5 A second diagram of a phase interpolator control implementation provided for an exemplary embodiment of the present application
[0041] Reference signs are as follows:
[0042] 100 driving unit
[0043] 200 enable control unit
[0044] 300 current control unit DETAILED DESCRIPTION
[0045] The present application is described by way of specific examples, and those skilled in the art will readily recognize how best to implement the present application from the description, drawings and claims. The present application can be implemented in various ways, and those skilled in the art will readily recognize variations of the specific implementation described that fall within the scope of the present application. It should be noted that where a method comprising two or more steps is claimed, the order of the steps can be modified and still fall within the scope of the present application. It is therefore contemplated to cover any and all modifications, variations or equivalents that fall within the scope of the present application. It is also contemplated to cover all alternatives, modifications and variations thereof with the scope of the present application including sub-combinations of the elements falling within the scope of claims, abiding with the doctrine of equivalents.
[0046] It is to be understood that the drawings are to be used only for illustrative purposes and that they are not to be used to limit the present application. The drawings employed herein are intended to further explain the preferred embodiments of the application, and do not limit the scope of the application. It is also to be understood that not necessarily all objects or aspects of the application can be included within a single embodiment of the application.
[0047] In the following description, numerous specific details are discussed so as to provide a thorough understanding of embodiments of the application. However, it will be apparent to one of ordinary skill in the art that embodiments of the application can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the application.
[0048] In order to solve the technical problems of narrow input frequency range and poor linearity of the existing phase interpolator, the application provides a phase interpolator unit circuit, which expands the applicable frequency range of the phase interpolator and significantly improves the flexibility of the circuit design by adding a current control unit in the unit circuit architecture and adopting the innovative design of multiple capacitors in parallel to configure the output capacitor.
[0049] In an example embodiment of the present application, referring to Figure 1 The input end of the driving unit 100 is connected with an input clock signal phi, and the output ends are respectively connected with the input ends of the enable control unit 200 and the current control unit 300. The control end of the enable control unit 200 is connected with an enable control signal en / enb, which is used to turn on or off the phase interpolator unit circuit according to the enable control signal en / enb. The control end of the current control unit 300 is connected with a current control signal hi_en / hi_enb, and the output end is connected with the output end of the enable control unit 200, which is used to adjust the driving current of the phase interpolator unit circuit according to the frequency of the input clock signal phi, so as to meet the driving requirements of the input clock signal phi with different frequencies.
[0050] In an example embodiment of the present application, referring to Figure 1 The driving unit 100 includes a first PMOS tube Q1 and a first NMOS tube Q8. The control ends of the first PMOS tube Q1 and the first NMOS tube Q8 are connected with the input clock signal phi. The source end of the first PMOS tube Q1 is connected with a system power supply vdd, and the drain end is connected with the first input ends of the enable control unit 200 and the current control unit 300 as the first output end of the driving unit 100. The source end of the first NMOS tube Q8 is connected with a system ground vss, and the drain end is connected with the second input ends of the enable control unit 200 and the current control unit 300 as the second output end of the driving unit 100.
[0051] In an example embodiment of the present application, referring to Figure 1As shown, the enable control unit 200 comprises a second PMOS Q2, a first resistor R1, a second resistor R2 and a second NMOS Q7. The control terminal of the second PMOS Q2 is connected with the first enable control signal enb, the source terminal is connected with the first output terminal of the drive unit 100, and the drain terminal is connected with the first terminal of the first resistor R1. The control terminal of the second NMOS Q7 is connected with the second enable control signal en, the source terminal is connected with the second output terminal of the drive unit 100, and the drain terminal is connected with the first terminal of the second resistor R2. The second terminals of the first resistor R1 and the second resistor R2 are connected with the output terminal of the current control unit 300 as the output terminal of the enable control unit 200. It is worth noting that in the present embodiment, the first resistor R1 and the second resistor R2 have the same resistance value.
[0052] It is to be noted that in other embodiments, there are alternatives, the first resistor R1 can be replaced by a plurality of PMOSs connected in series, the control terminals of which are all connected with the control terminal of the second PMOS Q2, as long as the equivalent resistance of the PMOSs after being turned on is consistent with the resistance value of the first resistor R1. Similarly, the second resistor R2 can be replaced by a plurality of NMOSs connected in series, the control terminals of which are all connected with the control terminal of the second NMOS Q7. Similarly, as long as the equivalent resistance of the NMOSs after being turned on is the same as the resistance value of the second resistor R2. In addition, in the present embodiment, the first enable control signal enb and the second enable control signal en are inversely phased. Specifically, when the first enable control signal enb presents a high level state, the second enable control signal en is in a low level state. Conversely, when the first enable control signal enb presents a low level state, the second enable control signal en is in a high level state.
[0053] In an exemplary embodiment of the present application, please refer to Figure 1As shown, the current control unit 300 includes a third PMOS transistor Q9, a third resistor R3, a fourth resistor R4, and a third NMOS transistor Q10. The control terminal of the third PMOS transistor Q9 is connected to a first current control signal hi_enb, its source terminal is connected to the first output terminal of the driving unit 100, and its drain terminal is connected to the first terminal of the third resistor R3. The control terminal of the third NMOS transistor Q10 is connected to a second current control signal hi_en, its source terminal is connected to the second output terminal of the driving unit 100, and its drain terminal is connected to the first terminal of the fourth resistor R4. The second terminals of the third resistor R3 and the fourth resistor R4 serve as output terminals of the current control unit 300 and are connected to the output terminal of the enable control unit 200. It is worth noting that in this embodiment, the resistance values of the third resistor R3 and the fourth resistor R4 are the same.
[0054] It should be noted that in other embodiments, there are optimization schemes. By replacing the third PMOS transistor Q9 with PMOS transistors of different channel width-to-length ratios (W / L), the on-resistance of the PMOS transistor can be changed, thereby eliminating the third resistor R3. Similarly, by replacing the third NMOS transistor Q10 with NMOS transistors of different channel width-to-length ratios to adjust the on-resistance of the NMOS transistor, the fourth resistor R4 can also be eliminated. Furthermore, in this embodiment, the first current control signal hi_enb and the second current control signal hi_en are out of phase. Specifically, when the first current control signal hi_enb is high, the second current control signal hi_en is low. Conversely, when the first current control signal hi_enb is low, the second current control signal hi_en is high.
[0055] In one exemplary embodiment of this application, please refer to Figure 2 As shown, Figure 2 An implementation of the phase interpolator unit circuit structure is shown. In this implementation, the channel width-to-length ratio (W / L) of MOS transistors Q2 to Q7, as well as Q11 and Q12, is kept consistent. The first enable control signal enb controls PMOS transistors Q2, Q3, and Q4 with the same W / L, and the second enable control signal en controls NMOS transistors Q5, Q6, and Q7 with the same W / L. From an equivalent perspective, the overall effect of Q3 and Q4 connected in series is equivalent to... Figure 1 The overall effect of the first resistor R1, Q5 and Q6 connected in series is equivalent to Figure 1 The second resistor R2 in the circuit. The equivalent effect of PMOS transistor Q11 is equivalent to... Figure 1 After the third PMOS transistor Q9 is turned on, the total resistance of the transistor connected in series with the third resistor R3, and the equivalent effect of Q12, are equivalent to...Figure 1 The total resistance value after the third NMOS tube Q10 is turned on and is in series with the fourth resistor R4. In actual application, the conversion of the current size under different frequencies is realized by precisely controlling the first enable control signal enb, the second enable control signal en, the first current control signal hi_enb and the second current control signal hi_en. Meanwhile, by reasonably configuring the pins hi_en, hi_enb, en and enb in the phase interpolator unit circuit, the switching of the working state of the unit circuit can be realized. For example, when enb=hi_enb=0 and en=hi_en=1, the function of the phase interpolator unit circuit is equivalent to that of an inverter, at this time, the output signal pho is the inverse of the input signal phi, that is, pho=~phi. The implementation mode adopts MOS tubes to replace resistor devices, which can reduce the occupied area of the chip, thereby reducing the chip manufacturing cost, and is more conducive to promoting the miniaturization of the chip.
[0056] In summary, the phase interpolator unit circuit provided by the application comprises a driving unit 100, an enable control unit 200 and a current control unit 300. The input end of the driving unit 100 is connected with an input clock signal phi, and the output ends are respectively connected with the input ends of the enable control unit 200 and the current control unit 300. The control end of the enable control unit 200 is connected with an enable control signal en / enb, and is used for opening or closing the phase interpolator unit circuit according to the enable control signal en / enb. The control end of the current control unit 300 is connected with a current control signal hi_en / hi_enb, and the output end is connected with the output end of the enable control unit 200, and is used for adjusting the driving current of the phase interpolator unit circuit according to the frequency of the input clock signal phi, so as to meet the driving requirements of the input clock signal phi with different frequencies. The phase interpolator unit circuit realizes precise regulation and control of the current size through the switch connected with the current control bit, and based on this, the circuit can flexibly adjust the driving parameters according to the requirements of different frequency scenes, thereby effectively expanding the applicable frequency range of the phase interpolator. Meanwhile, in the low-frequency working state, such current control mechanism can also reduce the power consumption of the circuit, and improves the energy efficiency performance of the circuit. In the output capacitor design aspect, a multi-capacitor parallel structure is adopted, and an additional large-capacitor control bit is additionally arranged. Through this design, a capacitor value meeting the lowest frequency requirement can be flexibly selected according to the actual requirements, so that when the low-frequency clock design requirements are met, a large number of capacitor configuration bits do not need to be additionally increased, and the functional requirements can be realized only through the large-capacitor control bit, thereby effectively avoiding the redundant increase of the capacitor configuration bits, and significantly improving the flexibility and simplicity of the circuit design.
[0057] Based on the same inventive concept, please refer to Figure 3As shown, another embodiment of the present application further provides a phase interpolator, comprising: a first phase interpolator unit circuit, a second phase interpolator unit circuit and a linearity adjustment unit, wherein the first phase interpolator unit circuit and the second phase interpolator unit circuit adopt the phase interpolator unit circuit structure as described in any of the above embodiments. The input end of the first phase interpolator unit circuit is connected with a first input clock signal phi0, for performing phase adjustment on the first input clock signal phi0, the input end of the second phase interpolator unit circuit is connected with a second input clock signal phi1, for performing phase adjustment on the second input clock signal phi0, the output end of the first phase interpolator unit circuit is connected with the output end of the second phase interpolator unit circuit, for performing signal superposition on the output signals of the first phase interpolator unit circuit and the second phase interpolator unit circuit, to generate a phase interpolation signal pho_pre. The input end of the linearity adjustment unit is connected with the output ends of the first phase interpolator unit circuit and the second phase interpolator unit circuit, for receiving the phase interpolation signal pho_pre and performing linearity adjustment on the phase interpolation signal. It is worth noting that the first input clock signal phi0 and the second input clock signal phi1 have the same frequency but different phases.
[0058] In an exemplary embodiment of the present application, please continue to refer to Figure 4 As shown, the phase interpolator circuit further comprises a driving circuit, the input end of the driving circuit is connected with the output end of the linearity adjustment unit, for providing stable driving capability to the subsequent circuit.
[0059] In an exemplary embodiment of the present application, the linearity adjustment unit comprises a plurality of capacitance control units arranged in parallel, each of the capacitance control units comprises a transmission gate and a capacitance, the first end of the transmission gate is connected with the output ends of the first phase interpolator unit circuit and the second phase interpolator unit circuit, the control end of the transmission gate is connected with a capacitance control signal, the conduction and the turn-off of the transmission gate are controlled through the capacitance control signal, the first end of the capacitance is connected with the second end of the transmission gate, and the second end of the capacitance is connected with a system ground. It is worth noting that in the present embodiment, the transmission gate is a CMOS transmission gate composed of a PMOS tube and an NMOS tube in parallel, and the capacitance includes but is not limited to MOS capacitance, MIM capacitance and MOM capacitance, etc.
[0060] Specifically, the input clock signals phi0 and phi1 with the same frequency but different phases are input into the improved parallel phase interpolator unit circuit, and the specific number of the phase interpolator unit circuits that are turned on is determined by configuring the enable control bit signals en / enb of the phase interpolator unit circuit. The output ends of these phase interpolator unit circuits are connected in parallel with each other, and by adjusting the proportion of the parallel circuit of the input clock signals phi0 and phi1 in the whole (i.e., adjusting the number of the phase interpolator units that are turned on), the precise adjustment of the phase between phi0 and phi1 is realized. In addition, according to the difference in the frequency of the input clock signals, the current control bit switch of the current control unit needs to be reasonably confirmed, and the small-capacitance control bit and the large-capacitance control bit need to be properly configured, so as to determine the actual size of the parallel capacitance, and then the effective adjustment of the linearity of the circuit is realized. The driving circuit is used for shaping the waveform of the phase interpolation signal pho_pre, so as to ensure the stability and accuracy of the signal.
[0061] It should be noted that the phase interpolator includes the phase interpolator unit circuit of any one of the above embodiments. Since the phase interpolator provided in the embodiment belongs to the same inventive concept as the phase interpolator unit circuit provided in any one of the above embodiments, it at least has the same beneficial effects, and here, it will not be described one by one.
[0062] In an exemplary embodiment of the present application, a typical phase interpolator control implementation is shown in Figure 4 and Figure 5 . In the implementation architecture, referring to Figure 4 , the phase interpolator parallel unit circuit pi_slice0 for the first input clock signal phi0 is connected with the enable control signal enb at the en pin, connected with the enable control signal en at the enb pin, connected with the current control signal hi_en0 at the hi_en pin, and connected with the current control signal hi_enb0 at the hi_enb pin. And for the phase interpolator parallel unit circuit pi_slice1 for the second input clock signal phi1, the en pin is connected with the enable control signal en, the enb pin is connected with the enable control signal enb, the hi_en pin is connected with the current control signal hi_en1, and the hi_enb pin is connected with the current control signal hi_enb1.
[0063] In the working scenario of high frequency clock, hi_en<3:0> is set as 1, wherein hi_en is a signal name, <3:0> indicates that the signal is composed of 4 binary bits, and the numbering is from the highest bit 3 to the lowest bit 0. At this time, the circuit realizes two different working states according to the combination state of en<3:0> and its inverse signal enb<3:0>. Taking the control logic of the lowest bit en<0> as an example, when en<0> = 0 and enb<0> = 1, hi_en0<0> = 1 and hi_en1<0> = 0; when en<0> = 1 and enb<0> = 0, hi_en0<0> = 0 and hi_en1<0> = 1. By reasonably configuring en<3:0>, the number of phi0 and phi1 phase interpolator unit circuit opening can be accurately controlled, and then the flexible adjustment of any phase between phi0 and phi1 can be realized. In the working scenario of low frequency clock, hi_en<3:0> is set as 0, hi_en0<3:0> = hi_en1<3:0> = 0 at this time.
[0064] In addition, please refer to Figure 5 As shown in the figure, in the low frequency working mode, hi_cen = 0, the large capacitor control bit is in the open state, and the circuit will be connected in parallel with a large capacitor. The function of the large capacitor is to adjust the linearity of the circuit. In the high frequency working mode, hi_cen = 1, the large capacitor control bit is in the closed state.
[0065] The phase interpolator design circuit proposed in the application can well meet the design requirements whether it faces low frequency clock or high frequency clock, and has high versatility. In the low frequency working state, the driving requirement is low, and the number of capacitors required for linearity is reduced, which not only effectively reduces the chip area and reduces the manufacturing cost, but also is more conducive to promoting the miniaturization of the chip.
[0066] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the application should be covered by the claims of the application.
Claims
1. A phase interpolator cell circuit, characterized by, The driving unit, the enable control unit and the current control unit are included; The input end of the driving unit is connected with an input clock signal, and the output end is connected with the input end of the enable control unit and the current control unit respectively; The control end of the enable control unit is connected with an enable control signal, and is used for opening or closing the phase interpolator unit circuit according to the enable control signal; The control end of the current control unit is connected with a current control signal, and the output end is connected with the output end of the enable control unit, and is used for adjusting the driving current of the phase interpolator unit circuit according to the frequency of the input clock signal, so as to meet the driving requirement of different frequency input clock signals.
2. The phase interpolator cell circuit of claim 1, wherein, The driving unit includes a first PMOS tube and a first NMOS tube; The control end of the first PMOS tube and the first NMOS tube is connected with the input clock signal; The source end of the first PMOS tube is connected with a system power supply, and the drain end is connected with the first input end of the enable control unit and the current control unit as the first output end of the driving unit; The source end of the first NMOS tube is connected with a system ground, and the drain end is connected with the second input end of the enable control unit and the current control unit as the second output end of the driving unit.
3. The phase interpolator cell circuit of claim 1, wherein, The enable control unit includes a second PMOS tube, a first resistor, a second resistor and a second NMOS tube; The control end of the second PMOS tube is connected with a first enable control signal, the source end is connected with the first output end of the driving unit, and the drain end is connected with the first end of the first resistor; The control end of the second NMOS tube is connected with a second enable control signal, the source end is connected with the second output end of the driving unit, and the drain end is connected with the first end of the second resistor; The second end of the first resistor and the second resistor is connected with the output end of the enable control unit and the output end of the current control unit as the output end of the enable control unit.
4. The phase interpolator cell circuit of claim 3, wherein, The first enable control signal and the second enable control signal are inverse.
5. The phase interpolator cell circuit of claim 1, wherein, The current control unit includes a third PMOS tube, a third resistor, a fourth resistor and a third NMOS tube; The control end of the third PMOS tube is connected with a first current control signal, the source end is connected with the first output end of the driving unit, and the drain end is connected with the first end of the third resistor; The control end of the third NMOS tube is connected with a second current control signal, the source end is connected with the second output end of the driving unit, and the drain end is connected with the first end of the fourth resistor; The second end of the third resistor and the fourth resistor is connected with the output end of the current control unit and the output end of the enable control unit as the output end of the current control unit.
6. The phase interpolator cell circuit of claim 5, wherein, The first current control signal and the second current control signal are inverse.
7. A phase interpolator characterized by, The first phase interpolator unit circuit, the second phase interpolator unit circuit and the linearity adjustment unit are included, wherein the first phase interpolator unit circuit and the second phase interpolator unit circuit adopt the phase interpolator unit circuit structure as claimed in any one of claims 1 to 6; The input end of the first phase interpolator unit circuit is connected with a first input clock signal, and is used for phase adjusting the first input clock signal; The output end of the second phase interpolator unit circuit is connected with a second input clock signal, and is used for phase adjusting the second input clock signal; The input end of the second phase interpolator unit circuit is connected with a second input clock signal, for phase adjustment of the second input clock signal; The output end of the first phase interpolator unit circuit is connected with the output end of the second phase interpolator unit circuit, for signal superposition of the output signals of the first phase interpolator unit circuit and the second phase interpolator unit circuit to generate a phase interpolation signal; The input end of the linearity adjustment unit is connected with the output end of the first phase interpolator unit circuit and the second phase interpolator unit circuit, for receiving the phase interpolation signal and performing linearity adjustment on the phase interpolation signal.
8. A phase interpolator as claimed in claim 7, characterized in that The phase interpolator further comprises a driving circuit, the input end of the driving circuit is connected with the output end of the linearity adjustment unit, for providing stable driving capability for the subsequent circuit.
9. The phase interpolator of claim 7, wherein, The first input clock signal and the second input clock signal have the same frequency but different phases.
10. The phase interpolator of claim 7, wherein, The linearity adjustment unit comprises a plurality of capacitance control units arranged in parallel, each capacitance control unit comprises a transmission gate and a capacitance; The first end of the transmission gate is connected with the output end of the first phase interpolator unit circuit and the second phase interpolator unit circuit, the control end of the transmission gate is connected with a capacitance control signal, and the on and off of the transmission gate is controlled by the capacitance control signal; The first end of the capacitance is connected with the second end of the transmission gate, and the second end of the capacitance is connected with a system ground.