Fault-free path selection method and system for network-on-chip

Abstract

The invention provides a fault-free path selection method and system for a network-on-chip. The method comprises the following steps: performing fault detection to search a fault node of the network-on-chip; calculating the path freedom degree of each non-fault node; calculating the ratio of the residual buffer area of the non-fault node; constructing a fault penalty factor on the basis of a preset function based on the path degree of freedom and the residual buffer area proportion; and on the basis of a preset ant colony algorithm, combining with the fault penalty factor to construct a path selection function, measuring the selection probability of each non-fault node through the path selection function, and selecting the corresponding non-fault node according to the selection probability to form an optimal fault-free path. According to the method, the congestion risk is perceived in advance according to the quantification of the path freedom on the node routing flexibility and the neighborhood association analysis of the remaining buffer area proportion, the self-optimization of the dynamic path decision of the network-on-chip in the fault state is realized, the selection probability of the fault path is remarkably reduced, and the low-delay and high-throughput transmission channel is screened out.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of network on chip, in particular to a fault-free path selection method and system of network on chip. BACKGROUND

[0002] With the evolution of car-grade computing chip towards high integration, the traditional bus architecture has shown problems such as bandwidth bottleneck when dealing with multi-core parallel communication. Under this background, network on chip (NoC) has become a new choice for intelligent driving computing chip interconnection solution due to its distributed routing architecture and adaptive traffic scheduling mechanism. As the core communication hub in the chip architecture, network on chip undertakes the key function of global data interaction. Compared with the local independence of other functional modules, the global feature of NoC makes it a high-risk area of potential single-point failure-any security defect may cause communication interruption across modules, and then lead to chip violation of safety goals. Therefore, developing a functional safety protection mechanism for NoC is one of the core challenges for the design of high-security level car-grade chips.

[0003] Existing fault-tolerant mechanisms mainly include redundancy mechanism and adaptive routing algorithm. Adaptive routing algorithm monitors network state parameters (such as link delay, bandwidth utilization and node load) in real time, then dynamically calculates the comprehensive delay of each candidate path based on the preset evaluation function, and then selects the transmission path according to the evaluation function. When detecting link abnormalities or performance degradation, trigger path recalculation and traffic migration mechanism, and avoid local congestion and node failure through load balancing strategy, finally realize the dual protection of network resource dynamic optimization and transmission reliability.

[0004] Existing adaptive routing fault-tolerant algorithm research mainly includes two kinds of reinforcement learning based and swarm optimization based. Reinforcement learning based routing algorithm has good fault-tolerant effect in network on chip due to its automatic feature learning and nonlinear modeling ability. However, its high computational overhead and reasoning delay limit its applicability in car-grade NoC scenarios with high real-time requirements. Traditional swarm optimization based fault-tolerant routing algorithm has the problems of complex parameter optimization and large computational overhead.

[0005] Existing ant colony algorithm research mainly focuses on routing table compression and traffic balancing, and less considers the fault-tolerant demand under node or link failure, which cannot fully meet the functional safety requirements of car-grade network on chip.

[0006] Therefore, there is a need for a path selection scheme for network on chip under node or link failure. SUMMARY

[0007] The present application provides a fault-free path selection method and system of network on chip to solve at least one of the above problems. The specific scheme is as follows:

[0008] A fault-free path selection method of a network-on-chip, comprising the following steps of:

[0009] determining a start node and a target node of a preset network-on-chip, and performing fault detection in a preset period to search for all fault nodes of the network-on-chip;

[0010] calculating a shortest path number and a Manhattan distance of each non-fault node to the target node while avoiding the fault nodes, and constructing a path freedom degree of the non-fault node based on the shortest path number and the Manhattan distance;

[0011] determining a next-hop node and a peripheral node of the next-hop node of each non-fault node, and calculating a residual buffer ratio reflecting an available buffer depth of the non-fault node according to a buffer state of the next-hop node and the peripheral node of each non-fault node;

[0012] constructing a fault penalty factor reflecting interference of the fault nodes on routing transmission based on a preset function and the path freedom degree and the residual buffer ratio;

[0013] constructing a path selection function based on a preset ant colony algorithm and the fault penalty factor, measuring a selection probability of each non-fault node through the path selection function, and selecting a corresponding non-fault node according to the selection probability to form an optimal fault-free path.

[0014] In some specific embodiments, the fault detection specifically comprises:

[0015] spreading in a distributed manner through virtual data packets among all nodes of the network-on-chip;

[0016] autonomously selecting an unvisited adjacent node to perform multi-branch expansion according to a topological connection relationship between adjacent nodes, a buffer congestion degree and a physical fault state;

[0017] when encountering a fault node or a high-load link, obstacle avoidance is realized through a dynamic adjustment of a diffusion direction and a path backtracking mechanism, and a global reachability topology graph is constructed based on local pheromone marking, and finally a feature record from the start node to the target node is completed.

[0018] In some specific embodiments, when the fault node is not within a rectangular range formed by the target node and the start node, the shortest path number P shortest is expressed as:

[0019]

[0020] wherein, b x is a hop distance from a local router to a destination router in an x direction, and b yThe hop distance in the y-direction is the distance from the local router to the destination router.

[0021] When the faulty node is located within the rectangle formed by the target node and the starting node, the number of shortest paths P shortest The expression is:

[0022]

[0023] P shortest =P f -P jf P fi

[0024] Among them, P jf P represents the number of shortest paths from the starting node to the failed node. fi f is the number of shortest paths from the destination node to the faulty node. x f is the hop distance from the local router to the faulty router in the x-direction. y This represents the hop distance from the local router to the faulty router in the y-direction.

[0025] In some specific embodiments, the expression for the path degree of freedom (PSF) is:

[0026] h = b x +b y

[0027]

[0028] Where h is the Manhattan distance, b x b is the hop distance from the local router to the destination router in the x-direction. y P is the hop distance in the y-direction from the local router to the destination router. shortest is the number of shortest paths, and PSF is the path degrees of freedom.

[0029] In some specific embodiments, the remaining buffer percentage is PBO. j The expression is:

[0030]

[0031] Among them, PBO j PRB represents the percentage of remaining buffer space along the path. j PRB represents the percentage of the remaining buffer space in the next hop node relative to the total buffer space. e PRB represents the percentage of the remaining buffer space of the neighboring node E of the next hop node relative to the total buffer space. s PRB is the percentage of the remaining buffer space of the neighboring node S of the next hop node relative to the total buffer space. nis the ratio of the remaining buffer of the next-hop node N to the total buffer; k is a normalization factor, which is the number of valid output channels from node J to the downstream nodes, allowed k is the current selectable output node.

[0032] In some embodiments, the failure penalty factor β j In the first quadrant, at least the following is satisfied:

[0033] β j ≥ PSF*PBO j + 1

[0034] where PBO j is the path remaining buffer ratio, and PSF is the path freedom degree.

[0035] In some embodiments, the preset function is an exponential function, and the product of the path remaining buffer ratio and the path freedom degree constitutes the argument of the exponential function.

[0036] In some embodiments, the failure penalty factor β j is expressed as:

[0037]

[0038] where PBO j is the path remaining buffer ratio, and PSF is the path freedom degree.

[0039] In some embodiments, the path selection function is expressed as:

[0040]

[0041] where Ph'(j, R i ) is the new probability value, L j is the inverse of the buffer queue length at node j, β j is the failure penalty factor, N k is the number of selectable channels of the current node, Ph(j, R i ) is the probability of selecting channel j of the data packet to reach the destination i, and α is the current information and historical information weighting coefficient of the network-on-chip, which ranges from 0 to 1.

[0042] In some embodiments, the preset period of time includes the startup period of the network-on-chip or the periodic monitoring period configured in the normal operation process of the network-on-chip.

[0043] A failure-free path selection system of a network-on-chip includes the following:

[0044] A fault screening unit is configured to determine a start node and a target node of a preset network-on-chip, and perform fault detection in a preset period to search for all fault nodes of the network-on-chip;

[0045] A path freedom degree unit is configured to calculate a shortest path number and a Manhattan distance of each non-fault node to the target node while avoiding the fault nodes, and construct a path freedom degree of the non-fault node based on the shortest path number and the Manhattan distance;

[0046] A residual buffer ratio unit is configured to determine a next-hop node and a peripheral node of the next-hop node of each non-fault node, and calculate a residual buffer ratio reflecting an available buffer depth of the non-fault node according to a buffer state of the next-hop node and the peripheral node of each non-fault node;

[0047] A fault penalty factor unit is configured to construct a fault penalty factor reflecting interference of the fault nodes on routing transmission based on the path freedom degree and the residual buffer ratio according to a preset function;

[0048] A path selection function unit is configured to construct a path selection function based on a preset ant colony algorithm and the fault penalty factor, measure a selection probability of each non-fault node through the path selection function, and select a corresponding non-fault node according to the selection probability to form an optimal fault-free path.

[0049] Beneficial effects: The application provides a fault-free path selection method and system for a network-on-chip, which comprehensively quantifies the path freedom degree of the node routing flexibility and analyzes the neighborhood correlation of the residual buffer ratio to perceive the congestion risk in advance, realizes the self-optimization of the dynamic path decision of the network-on-chip in the fault state, significantly reduces the selection probability of the fault path, screens out a transmission channel with low delay and high throughput, more effectively realizes the obstacle avoidance and flow balancing function in the obstacle scene, enhances the robustness and adaptive ability of the network-on-chip to the transient fault and local congestion, and ensures the functional safety and reliability of the chip.

[0050] In order to make the above-mentioned purposes, features and advantages of the application more obvious and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0051] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments, and it should be understood that the following drawings only show some embodiments of the application, and therefore should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0052] Figure 1 is a flowchart of the method of the application;

[0053] Figure 2 is the schematic diagram of path finding mechanism of the method of the present application;

[0054] Figure 3 is the schematic diagram of the number of shortest paths when the faulty node does not interfere;

[0055] Figure 4 is the schematic diagram of the number of shortest paths when the faulty node interferes;

[0056] Figure 5 is the schematic diagram of the selectable nodes of the route when there is no interference of the faulty node;

[0057] Figure 6 is the schematic diagram of the output channel with the faulty node;

[0058] Figure 7 is the schematic diagram of the execution flow of the ant data packet;

[0059] Figure 8a is the schematic diagram of the actual / ideal received data packet ratio comparison result in the RANDOM mode under the single point fault;

[0060] Figure 8b is the schematic diagram of the actual / ideal received data packet ratio comparison result in the Transpose1 mode under the single point fault;

[0061] Figure 8c is the schematic diagram of the actual / ideal received data packet ratio comparison result in the HOTSPOT mode under the single point fault;

[0062] Figure 8d is the schematic diagram of the actual / ideal received data packet ratio comparison result in the BIT_REVERSAL mode under the single point fault;

[0063] Figure 9a is the schematic diagram of the average delay comparison result in the RANDOM mode under the single point fault;

[0064] Figure 9b is the schematic diagram of the average delay comparison result in the Transpose1 mode under the single point fault;

[0065] Figure 9c is the schematic diagram of the average delay comparison result in the HOTSPOT mode under the single point fault;

[0066] Figure 9d is the schematic diagram of the average delay comparison result in the BIT_REVERSAL mode under the single point fault;

[0067] Figure 10a is the schematic diagram of the algorithm throughput rate comparison result in the RANDOM mode under the single point fault;

[0068] Figure 10b is a comparison result diagram of algorithm throughput rate in Transpose1 mode under single point failure;

[0069] Figure 10c is a comparison result diagram of algorithm throughput rate in HOTSPOT mode under single point failure;

[0070] Figure 10d is a comparison result diagram of algorithm throughput rate in BIT_REVERSAL mode under single point failure;

[0071] Figure 11a is a comparison result diagram of actual / ideal received data packet ratio in RANDOM mode under double point failure;

[0072] Figure 11b is a comparison result diagram of actual / ideal received data packet ratio in Transpose1 mode under double point failure;

[0073] Figure 11c is a comparison result diagram of actual / ideal received data packet ratio in HOTSPOT mode under double point failure;

[0074] Figure 11d is a comparison result diagram of actual / ideal received data packet ratio in BIT_REVERSAL mode under double point failure;

[0075] Figure 12a is a comparison result diagram of average delay in RANDOM mode under double point failure;

[0076] Figure 12b is a comparison result diagram of average delay in Transpose1 mode under double point failure;

[0077] Figure 12c is a comparison result diagram of average delay in HOTSPOT mode under double point failure;

[0078] Figure 12d is a comparison result diagram of average delay in BIT_REVERSAL mode under double point failure;

[0079] Figure 13a is a comparison result diagram of algorithm throughput rate in RANDOM mode under double point failure;

[0080] Figure 13b is a comparison result diagram of algorithm throughput rate in Transpose1 mode under double point failure;

[0081] Figure 13cis a schematic diagram of the comparison results of the algorithm throughput in the HOTSPOT mode under double-point failure;

[0082] Figure 13d is a schematic diagram of the comparison results of the algorithm throughput in the BIT_REVERSAL mode under double-point failure;

[0083] Figure 14 is a principle example diagram of the present application;

[0084] Figure 15 is a schematic diagram of a failure-free path selection system module of the present application.

[0085] Reference signs: 1-failure screening unit; 2-path freedom unit; 3-residual buffer occupancy unit; 4-failure penalty factor unit; 5-path selection function unit. DETAILED DESCRIPTION

[0086] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0087] The present application proposes a failure-free path selection method for a network on a chip, which comprehensively considers the influence of path freedom and path buffer occupancy of a network on a chip on path selection, optimizes the path selection strategy of the network on a chip, actively avoids the failure nodes and congestion areas, and guides the path decision function to dynamically select the channel with the lowest delay under the current network state. The flowchart of the failure-free path selection method is shown in the accompanying Figure 1 The specific scheme is as follows:

[0088] A failure-free path selection method for a network on a chip, comprising the following:

[0089] 101, determining the starting node and the target node of a preset network on a chip, and performing failure detection in a preset period to search for all failure nodes of the network on a chip;

[0090] 102, calculating the shortest path number and the Manhattan distance of each non-failure node to the target node under the condition of avoiding the failure nodes, and constructing the path freedom of the non-failure nodes based on the shortest path number and the Manhattan distance;

[0091] 103, determining the next hop node of each non-failure node and the peripheral nodes of the next hop node, and calculating the residual buffer occupancy reflecting the available buffer depth of each non-failure node according to the buffer state of the next hop node and the peripheral nodes of each non-failure node;

[0092] 104. Constructing a fault penalty factor reflecting the interference of the fault node on the routing transmission based on the path freedom degree and the remaining buffer occupancy ratio on the basis of the preset function;

[0093] 105. Constructing a path selection function based on the preset ant colony algorithm combined with the fault penalty factor, measuring the selection probability of each non-fault node through the path selection function, and selecting the corresponding non-fault node to form an optimal fault-free path according to the selection probability.

[0094] It should be noted that the order of steps 102 and 103 is not required, and both can be performed simultaneously or sequentially, as long as step 104 is ensured before step 104.

[0095] Traditional adaptive routing algorithms cannot respond to fault node interference in time in high-load scenarios because they do not incorporate fault information as a basis for path decision-making. Fault nodes need to be bypassed, causing their surrounding nodes to bear higher traffic loads, so surrounding nodes often form congested areas, affecting the timely transmission and reception of data packets. When making intelligent driving-related decisions on a network-on-chip, such congestion can cause data interaction delays for computing cores and affect the real-time nature of autonomous driving decisions, ultimately affecting driving safety. The present application comprehensively discusses obstacle avoidance for a network-on-chip from two dimensions of path buffer depth and shortest path diversity, and introduces a fault-aware mechanism as an adjustment parameter to improve the traditional ant colony algorithm path selection formula, and proposes a new network-on-chip routing algorithm based on the ant colony algorithm. The scheme of the present application not only optimizes network performance, but also ensures the functional safety and reliability of the chip.

[0096] Step 101 mainly involves determining the fault information of the network-on-chip. As for the fault detection time, it can be selected according to actual application. In some specific embodiments, the preset period includes the startup period of the network-on-chip or the periodic monitoring period configured during normal operation of the network-on-chip. For example, the fault information inside the chip is obtained during system warm-up, and the detection is performed quickly without affecting the operation of the network-on-chip. Periodic detection can also be performed during network-on-chip operation, and monitoring can be performed at fixed intervals (such as every 100 ms) as needed, which is suitable for dynamic faults.

[0097] In some embodiments, the fault detection specifically includes: spreading in a distributed manner among the nodes of the network-on-chip through virtual data packets; autonomously selecting unvisited adjacent nodes for multi-branch expansion according to the topological connection relationship between adjacent nodes, buffer congestion degree and physical fault state; when encountering a fault node or a high-load link, obstacle avoidance is achieved through dynamic adjustment of diffusion direction and path backtracking mechanism, and a global reachability topology graph is constructed based on local pheromone marking, and finally the feature record from the starting node to the target node is completed. Through the network-on-chip path exploration mechanism, an effective transmission path from the source node to the target node is dynamically searched, and information such as the position of the fault node is marked.

[0098] The principle of fault detection is shown in FIG. 1. Figure 2 After system initialization, integrate historical network information and load state perception module, start distributed path detection; in the detection, judge whether the path exists or contains fault nodes, if the path is feasible, update the path information and continue to explore, if a fault / unfeasible is encountered, update the information, record the fault node and back off; finally, iterate and perfect the path database, store the reachable path, fault record and link state, provide dynamic network state support for subsequent fault-free routing decision. Among them, the historical network information includes but is not limited to historical fault record, effective path library, pheromone distribution. The network state perception module can dynamically capture the fault and congestion state of the node. The path exploration mechanism spreads in a distributed manner among the nodes of the network-on-chip through virtual "ant data packets", the agent carries the path history information and real-time perceives the link state. The ant marks the path through pheromone, in this mechanism, the ant data packet simulates this behavior and marks the reachable path and fault node when spreading in the network. Based on the distributed exploration mechanism of the ant data packet, step 101 realizes the dynamic positioning of the fault node and the construction of the global reachable topology, which provides multi-dimensional data support for subsequent path freedom analysis, buffer state evaluation and intelligent routing decision, and significantly improves the fault discovery speed and topology perception ability compared with traditional detection methods.

[0099] Step 102 mainly involves the path freedom of the computing node. The fault detection of step 101 will determine the fault nodes of the network-on-chip, and the remaining nodes are non-fault nodes. It is necessary to select from the non-fault nodes to obtain an optimal path. The steps after step 102 are actually the process of selecting nodes, and the most suitable nodes are gradually selected to form a path. Step 102 is essentially the number of available shortest paths from the current node to the destination node after the Manhattan distance factor is calculated and normalized.

[0100] This application defines a quantitative index for the degree of freedom of a node's path, specifically the number of shortest paths from the current node to the destination node. The routing decision in this application prioritizes next-hop nodes with higher degrees of freedom to maintain path diversity in subsequent transmission stages; it also incorporates Manhattan distance to further quantify path selection bias and suppress detour tendencies.

[0101] Specifically, this application calculates the number of shortest paths based on the positional relationship between the source and destination nodes. In a 2D-Mesh structure, if a data packet is transmitted from the local node to the destination node, the number of shortest paths under fault-free and fully adaptive routing is shown in Equation 1:

[0102]

[0103] In the formula P f b is the number of shortest paths to the nodes. x b is the hop distance from the local router to the destination router in the x-direction. y This represents the hop distance in the y-direction from the local router to the destination router.

[0104] When NoC experiences a fault or interference, the number of shortest paths that routing packets can choose will change. Therefore, this application modifies the shortest path calculation method based on the location of the faulty node.

[0105] When the faulty node is not within the rectangle formed by the target node and the starting node, such as Figure 3 As shown, node J represents the starting router, node F represents the failed router, node I represents the destination router, and nodes W, S, E, and N represent selectable output routers. The number of shortest paths remains unchanged. The number of shortest paths P... shortest The expression is:

[0106]

[0107] Among them, b x b is the hop distance from the local router to the destination router in the x-direction. y The hop distance in the y-direction is the distance from the local router to the destination router.

[0108] When the faulty node is located within the rectangular area formed by the target node and the starting node, such as Figure 4 As shown, the number of shortest paths will change, and the number of shortest paths P shortest The expression is:

[0109]

[0110] P shortest =P f -P jf Pfi

[0111] where P jf is the number of shortest paths from the start node to the failure node, P fi is the number of shortest paths from the destination node to the failure node, f x is the hop distance from the local router to the failure router in the x direction, f y is the hop distance from the local router to the failure router in the y direction.

[0112] However, if only the number of shortest paths P shortest of the next hop of the current node is used as the basis for routing decisions, although path diversity can be enhanced, it may cause the problem of reverse transmission of data packets. The root cause lies in the fact that in a mesh topology, the path abundance in the area far from the target node is higher, which easily induces data packets to take a detour path. Therefore, this study introduces the Manhattan distance h into the evaluation model. To further quantify the path selection tendency, this paper defines the path selection factor (PSF) to reflect the joint influence of the number of shortest paths and the Manhattan distance.

[0113] In some embodiments, the expression of the path selection factor PSF is:

[0114] h = b x + b y

[0115]

[0116] where h is the Manhattan distance, b x is the hop distance from the local router to the destination router in the x direction, b y is the hop distance from the local router to the destination router in the y direction, P shortest is the number of shortest paths, and PSF is the path selection factor.

[0117] Since the reverse transmission probability is positively correlated with h, PSF can effectively suppress the detour tendency, thereby achieving a balance between path selection freedom and transmission direction rationality.

[0118] Step 103 is to calculate the buffer state of the next hop node and the available buffer capacity proportion of its adjacent nodes. When a data packet faces multiple direction transmission options, the port controller preferentially selects the input port with a lower FIFO queue occupancy rate in the downstream router as the output channel. To quantify this decision basis, this paper defines the percentage of remaining buffer (PRB), and the PRB calculation expression is:

[0119]

[0120] However, in practical applications, the data packet capacity of the on-chip network transmission often exceeds the carrying threshold of the single node buffer. For example, the size of the data packet exceeds the maximum buffer depth of the current node, at which time the neighboring nodes of the node need to be shared. To solve this problem, the application synchronously considers the buffer capacity of the neighboring nodes when evaluating the buffer state of the next hop node to predict the potential multi-hop congestion risk. Path Buffer Occupancy (PBO) is the core indicator of path selection. Specifically, the remaining buffer capacity (PRBj) of the next hop node itself directly determines the availability of the current path, and the remaining buffer capacity (PRBn, PRBs, PRBe) of the neighboring nodes (E / S / W) reflects the stability of the subsequent path. To eliminate the interference of the difference in the number of output channels of the candidate path on the buffer evaluation (for example, node J may connect different numbers of downstream nodes), the research introduces a channel number normalization factor k, which is the effective output channel number of the next hop node. Based on this, Path Buffer Occupancy (PBO) is defined as the core indicator of path selection.

[0121] The application divides the calculation of path buffer occupancy into two scenarios: if all neighboring nodes are normal nodes, then the remaining buffer occupancy of all neighboring nodes is calculated; if there is a faulty node among the neighboring nodes, then the buffer depth of the faulty node is forced to zero. As shown in Figure 5 and Figure 6 , wherein O is the source node, I is the destination node, J is the candidate next hop node, N, S, E are the peripheral nodes of the next hop node. When all neighboring nodes are normal nodes, all neighboring nodes are selected as optional nodes and the path buffer depth occupancy ratio of the optional nodes is calculated. When there is a faulty node among the neighboring nodes, the node cannot be used as the next hop target node, and its buffer factor will be set to 0.

[0122] Therefore, the expression of the remaining buffer occupancy PBO j is:

[0123]

[0124] wherein PBO j is the path remaining buffer occupancy, PRB j is the ratio of the remaining buffer occupancy of the next hop node to the total buffer, PRB e is the ratio of the remaining buffer occupancy of the peripheral node E of the next hop node to the total buffer, PRB s is the ratio of the remaining buffer occupancy of the peripheral node S of the next hop node to the total buffer, and PRB nis the ratio of the remaining buffer of the next-hop node N to the total buffer; k is a normalization factor, which is the number of valid output channels from node J to the downstream nodes, allowed k is the current selectable output node.

[0125] Step 104 is to calculate the fault penalty factor β j . The fault penalty factor represents the interference of the routing pheromone accumulation on the selected path due to congestion or failure interference. The path selection mechanism selects the appropriate output channel through the concentration of pheromones and a random greedy algorithm. In this application, the value of β j has multiple forms of influence on the ACO-FA algorithm path selection function.

[0126] Specifically, the fault penalty factor β j satisfies at least:

[0127] β j ≥ PSF*PBO j + 1

[0128] where PBO j is the path remaining buffer ratio, and PSF is the path degree of freedom.

[0129] In some specific embodiments, the preset function is an exponential function, and the product of the path remaining buffer ratio and the path degree of freedom constitutes the independent variable of the exponential function. Preferably, the expression of the fault penalty factor β j is:

[0130]

[0131] where PBO j is the path remaining buffer ratio, and PSF is the path degree of freedom.

[0132] In some specific embodiments, the expression of the path selection function is:

[0133]

[0134] where Ph'(j, R i ) is the new probability value, L j is the inverse of the buffer queue length at node j, β j is the fault penalty factor, N k is the number of selectable channels of the current node, Ph(j, R i ) is the probability of selecting channel j at the data packet to reach the destination i, and a is the current information and historical information weighting coefficient of the network on chip, which ranges from 0 to 1.

[0135] Ph(j, R i) the fault information as a direct basis for path selection through the fault penalty factor. The pheromone concentration calculation method of the congested path is optimized through the fault penalty factor, and the avoidance of faults and congestion is realized. Compared with the traditional fault-tolerant routing algorithm, the algorithm of the application is simply called ACO-FA algorithm, which has good fault perception foresight. The traditional group optimization algorithm can only indirectly infer the existence of the fault after the congestion is formed around the fault, and then make targeted path adjustment, which limits the real-time performance of path selection. The algorithm of the application can greatly speed up the response speed to the fault through the fault perception mechanism in the design stage.

[0136] The Noxim simulation platform is used for fault simulation, and the experimental results show that the proposed routing algorithm corresponds to the theoretical basis, and the feasibility of the fault-free path selection method of the network on a chip of the application is proved. Specifically as follows:

[0137] The experimental object is a network on a chip based on an 8x8 2D-Mesh topology structure. The experiment is carried out under the single-point and double-point fault injection mode respectively, and 10000 cycle simulation experiment is carried out. The performance difference of ACO-FA algorithm and XY routing algorithm in delay, network throughput and other key indicators is compared. The routing strategy parameters and other configuration information involved in the experiment are shown in Table 1.

[0138] Table 1 NoC parameter configuration table

[0139]

[0140]

[0141] Figure 7 The implementation process of the obstacle avoidance routing algorithm based on ant colony optimization in the Noxim simulation platform is shown, and the algorithm realizes the selection of fault-free path through the ant data packet.

[0142] The algorithm of the application realizes path selection through the selection function. The selection function receives two parameters of candidatechannels and Router Data for filtering routing path. Router Data includes ant data packet and information data packet. The ant data packet is divided into forward ant flit and backtracking ant flit. The ant data packet is used to explore the network topology structure and update the pheromone concentration on the path, so as to find the optimal or near-optimal routing path. As shown in Figure 7As shown, when the system is initialized, the Process Element function generates the forward ant data packet, and the routing algorithm function is responsible for receiving the ant data packet. When determining the output channel, the routing algorithm will evaluate all the optional channels and the status of the related nodes. If it is found that the current node has a fault, the system will remove the forward ant data packet on the node and generate a backward ant data packet. If the current node is running normally, the forward ant data packet will continue to transmit forward along the path until it reaches the destination node. After reaching the destination node, the forward ant data packet will be eliminated. At this time, the destination node will generate a backward ant data packet.

[0143] In the backward ant phase, the data packet will move in the opposite direction along the path that the forward ant has passed. When reaching each node, the system will check whether the node is the destination node. If it is not the destination node, the pheromone in the routing table will be updated according to the corresponding rules. When the node is the destination node, the backward ant data packet will be eliminated, indicating that its transmission period has been completed. By comparing the ACO-FA algorithm proposed in the present application with the widely used dimension-ordered XY algorithm, the simulator executes 11000 cycles. In the experiment, the first 1000 clock cycles are set as the warm-up phase to make the system reach a stable running state, thereby ensuring the reliability of subsequent data collection. After the algorithm is stable, the delay and full load throughput and other evaluation standards are compared and counted. The feasibility of the present application is verified.

[0144] Figure 8a 、 8b , 8c, 8d are respectively the actual / ideal received data packet ratio results of the dimension-ordered XY algorithm and the ACO-FA algorithm under the single-point fault model in the RANDOM, Transpose1, HOTSPOT, BIT_REVERSAL mode. The experimental data show that the actual / ideal received data packet ratio of the ACO-FA algorithm is higher than that of the dimension-ordered XY algorithm under the single-point fault of the node. The higher actual / ideal received data packet ratio proves that when the on-chip network has a single-point fault, the ACO-FA algorithm can more effectively realize the obstacle avoidance and flow balancing functions, so that the routing packet can reach the target node within a limited time.

[0145] Figure 9a 、 9b , 9c, 9d are respectively the average delay data graphs of the dimension-ordered XY algorithm and the ACO-FA algorithm under the single-point fault model in the RANDOM, Transpose1, HOTSPOT, BIT_REVERSAL mode.

[0146] The experimental data show that when the network on chip is in a high load mode, the average delay of the ACO-FA algorithm relative to the dimension-ordered XY routing algorithm shows a sustained performance advantage in three traffic injection modes of HOTSPOT, BIT_REVERSAL and Transpose1. In view of the fact that transpose traffic is commonly used for stress testing of routing algorithms, the performance difference between the two algorithms is compared and analyzed based on transpose traffic. When the injection rate is 0.011 packets / cycle / IP, the average delay of the dimension-ordered XY algorithm and the ACO-FA algorithm is similar; when the injection rate is 0.015 packets / cycle / IP, the average delay of the ACO-FA algorithm is reduced by 32.714% compared with the dimension-ordered XY routing algorithm. In the uniform random traffic mode, the delay of the ACO-FA algorithm is only 7.4%-10.1% lower than that of the dimension-ordered XY algorithm under high load.

[0147] Figure 10a 、 10b , 10c, 10d are respectively the throughput rate comparison diagrams of the routing algorithms in the RANDOM, Transpose1, HOTSPOT, BIT_REVERSAL traffic injection modes under the single-point fault model. Except for the uniform random routing, the ACO-FA is superior to the dimension-ordered XY algorithm. Due to the low overhead and no deadlock characteristics of the dimension-ordered XY routing algorithm, the advantage of the ACO-FA algorithm of the application is lower in the uniform random traffic and low load condition.

[0148] Figure 11a 、 11b , 11c, 11d are respectively the actual / ideal packet acceptance ratio data of the dimension-ordered XY algorithm and the ACO-FA algorithm in the RANDOM, Transpose1, HOTSPOT, BIT_REVERSAL modes under the double-point fault model. The experimental results show that the actual / ideal packet acceptance ratio of the ACO-FA algorithm is higher than that of the dimension-ordered XY algorithm under the node double-point fault, and compared with the single-point fault mode, the actual / ideal packet acceptance ratio of the ACO-FA algorithm is improved more when the node throughput rate is saturated. This shows that in the complex case of multiple faults, the high adaptability of the ACO-FA algorithm can more effectively avoid obstacles and ensure the functional safety of the chip.

[0149] Figure 12a 、 12b, 12c, 12d are respectively average delay data diagrams of the dimension-ordered XY algorithm and the ACO-FA algorithm under the double-point fault model under the RANDOM, Transpose1, HOTSPOT, BIT_REVERSAL traffic injection mode. The comparison experiment proves that under the high complexity mode, the average delay difference between the ACO-FA algorithm and the dimension-ordered XY routing algorithm under the four traffic modes gradually increases, and the ACO-FA algorithm shows a sustained performance advantage. Table 3 is a comparison table of average delay under different traffic under the double-point fault. The experimental data show that when the injection rate does not exceed 0.008 packets / cycle / IP, there is no obvious difference between the two algorithms in the average delay index. In the comparison experiment, when the traffic injection rate increases to 0.010 packets / cycle / IP, the average delay difference between the ACO-FA algorithm and the XY routing algorithm under the four traffic modes gradually increases, and the ACO-FA algorithm shows a sustained performance advantage.

[0150] Figure 13a 、 13b , 13c, 13d are respectively based on the double-node fault model, and the throughput rate characteristics of the dimension-ordered XY routing algorithm and the ACO-FA algorithm under the RANDOM, Transpose1, HOTSPOT, BIT_REVERSAL traffic mode are compared and analyzed. Experimental data show that in all traffic scenarios, the injection rate at which the ACO-FA algorithm reaches network saturation is higher than that of the dimension-ordered XY algorithm, and the saturation throughput rate is also higher than that of the dimension-ordered XY routing algorithm. Table 4 shows the average comparison results of the throughput rate and the delay saturation point under the double-point fault.

[0151] The principle example diagram of the present application is shown in the accompanying Figure 14 , first, the fault information inside the chip is obtained during system warm-up using built-in self-test and other technologies, and the fault information is broadcast to the remaining nodes; second, in order to increase the diversity of path selection, the path search algorithm will explore all reachable adjacent node paths when determining the candidate output channel, but will exclude those paths that have been marked as having faults; finally, the path selection mechanism will adjust the concentration of pheromones by considering the influence of fault nodes on the surrounding load and the traffic pressure of the selectable path, and finally select a more suitable output path.

[0152] The present application also proposes a fault-free path selection system for a network on a chip, and a module schematic diagram of the system is shown in the accompanying Figure 15 , the system comprises the following:

[0153] The fault screening unit 1 is used to determine the starting node and the target node of the preset network on a chip, and to detect faults in a preset period to search for all fault nodes of the network on a chip;

[0154] The path freedom degree unit 2 is configured to calculate the shortest path number and Manhattan distance of each non-faulty node to the target node while avoiding the faulty node, and construct the path freedom degree of the non-faulty node based on the shortest path number and Manhattan distance.

[0155] The residual buffer ratio unit 3 is configured to determine the next hop node of each non-faulty node and the peripheral node of the next hop node, and calculate the residual buffer ratio reflecting the available buffer depth of each non-faulty node according to the buffer state of the next hop node and the peripheral node.

[0156] The fault penalty factor unit 4 is configured to construct the fault penalty factor reflecting the interference of the faulty node on the routing transmission based on the path freedom degree and the residual buffer ratio on the basis of a preset function.

[0157] The path selection function unit 5 is configured to construct the path selection function based on the preset ant colony algorithm and in combination with the fault penalty factor, measure the selection probability of each non-faulty node through the path selection function, and select the corresponding non-faulty node to form the optimal fault-free path according to the selection probability.

[0158] The application provides a computer program product, which comprises computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to enable the computer device to perform a fault-free path selection method for a network-on-chip. The fault-free path selection method for a network-on-chip is applied to a computer program product, and thus is convenient to execute.

[0159] The application further provides a computer readable storage medium, which stores a computer program. The program is executed by a processor to implement the steps of the fault-free path selection method for a network-on-chip.

[0160] The computer storage medium of the present application can adopt any combination of one or more computer readable media. The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or apparatus, or any combination thereof. More specific examples (non-exhaustive list) of computer readable storage media include: electrical connections having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this document, the computer readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or apparatus. The present application applies a fault-free path selection method of a network-on-chip to a computer readable storage medium having a computer program stored thereon, which is executed by a processor to implement the garment simulation method steps provided by the present application, which is simple, fast and easy to store and not easy to lose.

[0161] The present application provides a fault-free path selection method and system for a network-on-chip, which comprehensively quantifies the flexibility of path and the flexibility of node routing, and analyzes the neighborhood association of the remaining buffer occupancy ratio to perceive the congestion risk in advance, realizes the self-optimization of dynamic path decision of the network-on-chip in the fault state, significantly reduces the selection probability of the fault path, filters out the transmission channel with low delay and high throughput, more effectively realizes the obstacle avoidance and flow balancing function in the obstacle scene, enhances the robustness and adaptive ability of the network-on-chip to transient faults and local congestion, and ensures the functional safety and reliability of the chip.

[0162] Those skilled in the art should understand that the modules of the present application described above can be realized by a general computing system, which can be concentrated on a single computing system or distributed on a network composed of multiple computing systems. Alternatively, they can be realized by program codes executable by a computer system, so that they can be stored in a storage system and executed by a computing system, or they can be respectively manufactured into individual integrated circuit modules, or multiple modules or steps thereof can be manufactured into a single integrated circuit module. Therefore, the present application is not limited to any specific combination of hardware and software.

[0163] Note that the above merely describes preferred embodiments of the present application and the principles of the technology applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, modifications and substitutions can be made to the present application without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the claims.

[0164] The above merely describes several specific implementation scenarios of the present application, but the present application is not limited thereto, and any changes that can be thought of by those skilled in the art should fall within the protection scope of the present application.

Claims

1. A fault-free path selection method for an on-chip network, characterized in that, Including the following: Determine the starting node and target node of the preset on-chip network, and perform fault detection within a preset time period to search for all faulty nodes of the on-chip network; Calculate the number of shortest paths and Manhattan distances from each non-faulty node to the target node while avoiding the faulty node, and construct the path degrees of freedom of the non-faulty nodes based on the number of shortest paths and Manhattan distances. Determine the next-hop node and surrounding nodes of each non-faulty node, and calculate the remaining buffer percentage reflecting the available buffer depth of the non-faulty node based on the buffer status of the next-hop node and surrounding nodes of each non-faulty node. Based on the path degrees of freedom and the proportion of remaining buffer space, a fault penalty factor reflecting the interference of faulty nodes on route transmission is constructed on the basis of a preset function. Based on the preset ant colony algorithm, a path selection function is constructed by combining the fault penalty factor. The path selection function measures the selection probability of each non-faulty node, and selects the corresponding non-faulty nodes to form the optimal fault-free path according to the selection probability.

2. The fault-free path selection method according to claim 1, characterized in that, The fault detection specifically includes: Virtual data packets are distributed among the nodes of the on-chip network in a distributed manner. Based on the topological connections between adjacent nodes, the congestion level of the buffer, and the physical fault status, it autonomously selects unvisited adjacent nodes for multi-branch expansion; When encountering faulty nodes or high-load links, obstacle avoidance is achieved by dynamically adjusting the diffusion direction and path backtracking mechanism, and a global reachability topology graph is constructed based on local pheromone marking, ultimately completing the feature recording from the starting node to the target node.

3. The fault-free path selection method according to claim 1, characterized in that, When the faulty node is not within the rectangle formed by the target node and the starting node, the number of shortest paths P shortest The expression is: Among them, b x b is the hop distance from the local router to the destination router in the x-direction. y The hop distance in the y-direction is the distance from the local router to the destination router. When the faulty node is located within the rectangle formed by the target node and the starting node, the number of shortest paths P shortest The expression is: P shortest =P f -P jf P fi Among them, P jf P represents the number of shortest paths from the starting node to the failed node. fi f is the number of shortest paths from the destination node to the faulty node. x f is the hop distance from the local router to the faulty router in the x-direction. y This represents the hop distance from the local router to the faulty router in the y-direction.

4. The fault-free path selection method according to claim 1, characterized in that, The expression for the path degrees of freedom (PSF) is: h=b x +b y Where h is the Manhattan distance, b x b is the hop distance from the local router to the destination router in the x-direction. y P is the hop distance in the y-direction from the local router to the destination router. shortest is the number of shortest paths, and PSF is the path degrees of freedom.

5. The fault-free path selection method according to claim 1, characterized in that, The remaining buffer percentage of PBO j The expression is: Among them, PBO j PRB represents the percentage of remaining buffer space along the path. j PRB represents the percentage of the remaining buffer space in the next hop node relative to the total buffer space. e PRB represents the percentage of the remaining buffer space of the neighboring node E of the next hop node relative to the total buffer space. s PRB is the percentage of the remaining buffer space of the neighboring node S of the next hop node relative to the total buffer space. n The percentage of the remaining buffer space of the next-hop node's neighboring nodes N relative to the total buffer space; k is the normalization factor, which takes the value of the number of effective output channels from node J to the downstream node, allowed. k This is the currently available output node.

6. The fault-free path selection method according to claim 1, characterized in that, The fault penalty factor β j At least the following conditions must be met in the first quadrant: b j ≥PSF*PBO j +1 Among them, PBO j The remaining buffer percentage of the path is represented by , and PSF represents the path degrees of freedom.

7. The fault-free path selection method according to claim 1, characterized in that, The preset function is an exponential function, and the product of the remaining buffer percentage of the path and the path degrees of freedom constitutes the independent variable of the exponential function.

8. The fault-free path selection method according to claim 7, characterized in that, The fault penalty factor β j The expression is: Among them, PBO j The remaining buffer percentage of the path is represented by , and PSF represents the path degrees of freedom.

9. The fault-free path selection method according to claim 1, characterized in that, The expression for the path selection function is: Where Ph′(j,R) i ) represents the new probability value, L j β is the reciprocal of the length of the buffer queue at node j. j N is the fault penalty factor. k Ph(j,R) represents the number of selectable channels for the current node. i ) represents the probability that a data packet selects channel j to reach destination i, and α is the weighting coefficient of the current and historical information of the on-chip network, ranging from 0 to 1.

10. The fault-free path selection method according to claim 1, characterized in that, The preset time period includes the periodic monitoring period configured during the startup of the on-chip network or during the normal operation of the on-chip network.

11. A fault-free path selection system for an on-chip network, characterized in that, Including the following: The fault screening unit is used to determine the starting node and target node of the preset on-chip network, and to perform fault detection within a preset time period to search for all faulty nodes of the on-chip network. The path degree of freedom unit is used to calculate the number of shortest paths and Manhattan distances from each non-faulty node to the target node while avoiding the faulty node, and to construct the path degree of freedom of the non-faulty node based on the number of shortest paths and Manhattan distances. The remaining buffer percentage unit is used to determine the next-hop node and the surrounding nodes of each non-faulty node. It calculates the remaining buffer percentage that reflects the available buffer depth of the non-faulty node based on the buffer status of the next-hop node and the surrounding nodes of each non-faulty node. The fault penalty factor unit is used to construct a fault penalty factor that reflects the interference of faulty nodes on route transmission based on the path degrees of freedom and the proportion of remaining buffer space, according to a preset function. The path selection function unit is used to construct a path selection function based on the preset ant colony algorithm and the fault penalty factor. The path selection function measures the selection probability of each non-faulty node and selects the corresponding non-faulty nodes to form the optimal fault-free path according to the selection probability.

Images