Semiconductor device having dielectric via

Abstract

A semiconductor device having a dielectric via is disclosed. A semiconductor device assembly may include a semiconductor die and a plurality of semiconductor die stacks coupled with the semiconductor die at different lateral positions. A dielectric material may be disposed at the semiconductor die between the plurality of semiconductor die stacks. The dielectric vias may extend completely through the dielectric material to the semiconductor die such that the dielectric vias are coupled with circuitry at the semiconductor die. In this manner, the dielectric vias may provide power to the semiconductor dies (e.g., other than the plurality of semiconductor die stacks).

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor device assemblies, and more particularly to a semiconductor device having a dielectric via. BACKGROUND

[0002] Microelectronic devices generally have a die (e.g., a chip) that includes integrated circuitry with a high density of very small components. Typically, the die includes an array of bond pads that are electrically coupled to the integrated circuitry. The bond pads are external electrical contacts through which voltages, signals, etc. are transmitted to and from the integrated circuitry. After the die is formed, it is “packaged” to couple the bond pads to a larger array of electrical terminals that can be more easily coupled to various power lines, signal lines, and ground lines. Conventional processes for packaging a die include electrically coupling the bond pads on the die to an array of leads, ball pads, or other types of electrical terminals, and encapsulating the die to protect it from environmental factors (e.g., moisture, particulates, static electricity, and physical shock). BRIEF DESCRIPTION OF DRAWINGS

[0003] Figure 1 A simplified schematic cross-sectional view of a semiconductor device assembly according to embodiments of the present technology is illustrated.

[0004] Figures 2 to 7 A simplified schematic cross-sectional view of a series of steps for manufacturing a semiconductor device assembly according to embodiments of the present technology is illustrated.

[0005] Figure 8 A schematic view of a system including a semiconductor device assembly configured according to embodiments of the present technology is illustrated.

[0006] Figure 9 A method of manufacturing a semiconductor device assembly according to embodiments of the present technology is illustrated. DETAILED DESCRIPTION

[0007] Multiple semiconductor dies can be packaged into a single semiconductor device to enable multiple semiconductor dies to operate in concert as a single device. Performance requirements for semiconductor devices are continually increasing while spatial constraints on these devices are decreasing. As a result, semiconductor devices are designed with increasing densities, which can introduce additional challenges. For example, high-density semiconductor devices can be at risk of overheating due to increased heat generated by the dense circuitry in the devices. As a result, semiconductor devices can benefit from thermal regulation.

[0008] One such technique that addresses this challenge and others includes implementing a dielectric via within a semiconductor device. For example, a semiconductor device can include a semiconductor die (e.g., a logic die) and a plurality of semiconductor die stacks (e.g., memory dies) coupled with the semiconductor die at different lateral locations. The semiconductor die can be implemented at the top of the semiconductor device to enable the semiconductor die to dissipate heat more efficiently. Further, the semiconductor die at the top of the semiconductor device can replace a cap (e.g., unexploited silicon), thereby limiting the cost and complexity of the semiconductor device. A dielectric material can be disposed between the plurality of semiconductor die stacks at the semiconductor die. A dielectric via can extend completely through the dielectric material to the semiconductor die, such that the dielectric via is coupled with circuitry at the semiconductor die. In this way, the dielectric via can provide power to the semiconductor die (e.g., the plurality of semiconductor die stacks excepted) even though the semiconductor die is positioned at the top of the semiconductor device.

[0009] Figure 1 A semiconductor device assembly 100 is described that includes a semiconductor die 102 (e.g., a logic die) that is (e.g., electrically and mechanically) coupled with a first semiconductor die 104 (e.g., semiconductor die 104-1 and semiconductor die 104-2) stack and a second semiconductor die 106 (e.g., semiconductor die 104-1 and semiconductor die 104-2) stack. After assembling the first semiconductor die 104 stack and the second semiconductor die 106 stack onto a wafer of semiconductor dies (e.g., logic dies), the semiconductor die 102 can be singulated from the wafer of semiconductor dies. The first semiconductor die 104 stack or the second semiconductor die 106 stack can similarly be singulated from the semiconductor wafer stack.

[0010] The semiconductor die 102 includes a metallization layer 108 with traces, wires, vias, transistors, diodes, and other circuitry at the active side of the semiconductor die 102. A dielectric material 110 (e.g., silicon oxide, silicon nitride, silicon carbide, or silicon carbonitride) can be disposed over the front side of the semiconductor die 102. The semiconductor die 102 can include contact pads 112 (e.g., contact pad 112-1, contact pad 112-2, and contact pad 112-3) disposed at the dielectric material 110 and electrically coupled with circuitry at the semiconductor die 102.

[0011] The semiconductor dies 104 stack can include metallization layers 114 (e.g., metallization layer 114-1 and metallization layer 114-2) at the active side of the semiconductor dies 104. Dielectric materials 116 (e.g., dielectric material 116-1 and dielectric material 116-2) can be disposed over the active side of the semiconductor dies 104. The semiconductor dies 104 can include contact pads 118 (e.g., contact pad 118-1 and contact pad 118-2) disposed at the dielectric materials 116 and electrically coupled with circuitry at the semiconductor dies 104. Through-silicon vias (TSVs) 120 (e.g., TSV 120-1 and TSV 120-2) can extend from the metallization layers 114 to the non-active side of the semiconductor dies 104. Dielectric materials 122 (e.g., dielectric material 122-1) can be disposed over the non-active side of the semiconductor dies 104. The TSVs 120 can be exposed through the dielectric materials 122, and contact pads 124 (e.g., contact pad 124-1) can be disposed at and electrically coupled with the TSVs 120.

[0012] The semiconductor dies 104 are coupled (e.g., hybrid bonded) to one another (e.g., in a front-to-back arrangement) to form a stack. As illustrated, the dielectric material 122-1 is directly bonded with the dielectric material 116-2, and the contact pad 124-1 and the contact pad 118-2 are coupled to form an interconnect (e.g., a metal-metal interconnect) that electrically couples the semiconductor die 104-1 and the semiconductor die 104-2. Further, the semiconductor dies 104 stack is coupled (e.g., hybrid bonded) with the semiconductor die 102 at the first lateral position. In aspects, the semiconductor die 104-1 can be bonded with the semiconductor die 102 in a face-to-face arrangement. As illustrated, the dielectric material 116-1 is directly bonded with the dielectric material 110, and the contact pad 118-1 and the contact pad 112-1 are coupled to form an interconnect (e.g., a metal-metal interconnect) that electrically couples the semiconductor die 104-1 and the semiconductor die 102.

[0013] The semiconductor dies 106 can similarly include metallization layers 126 (e.g., metallization layer 126-1 and metallization layer 126-2), dielectric materials 128 (e.g., dielectric material 128-1 and dielectric material 128-2) disposed above the metallization layers 126, and contact pads 130 (e.g., contact pad 130-1 and contact pad 130-2) disposed at the dielectric materials 128 and electrically coupled with the metallization layers 126. Further, the semiconductor dies 106 can include TSVs 132 (e.g., TSV 132-1 and TSV 132-2) extending from the metallization layers 126 to a non-active side of the semiconductor dies 106. A dielectric material 134 (e.g., dielectric material 134-1) can be disposed at the non-active side of the semiconductor dies 106. The TSVs 132 can be exposed through the dielectric material 134, and a contact pad 136 (e.g., contact pad 136-1) can be disposed on the TSVs 132.

[0014] The semiconductor dies 106 are similarly coupled (e.g., hybrid bonded) to one another (e.g., in a front-to-back arrangement) to form a stack. As illustrated, the dielectric material 134-1 is directly bonded with the dielectric material 128-2, and the contact pad 136-1 and the contact pad 130-2 are coupled to form an interconnect (e.g., a metal-metal interconnect) that electrically couples the semiconductor dies 106-1 and 106-2. Further, the semiconductor dies 106 stack can be similarly coupled (e.g., hybrid bonded) with the semiconductor die 102 at a second lateral position. In aspects, the semiconductor die 104-1 can be bonded with the semiconductor die 102 in a face-to-face arrangement. As illustrated, the dielectric material 128-1 is directly bonded with the dielectric material 110, and the contact pad 130-1 and the contact pad 112-2 are coupled to form an interconnect (e.g., a metal-metal interconnect) that electrically couples the semiconductor dies 106-1 and 102.

[0015] A dielectric material 138 (e.g., a dielectric filler) can be disposed outside of the footprint of the semiconductor dies 104 stack and the footprint of the semiconductor dies 106 stack. The dielectric material 138 can include, for example, silicon oxide, silicon nitride, silicon carbide, or silicon carbonitride. In aspects, the dielectric material 138 can be disposed between the semiconductor dies 104 stack and the semiconductor dies 106 stack. For example, the dielectric material 138 can be disposed at the semiconductor die 102 that is exposed beyond the semiconductor dies 104 stack and the footprint of the semiconductor dies 104 stack. As illustrated, the dielectric material 138 can extend above the surface of the semiconductor die 102 away from the semiconductor dies 104 stack or the semiconductor dies 106 stack.

[0016] The dielectric via 140 can extend completely through the dielectric material 138 to the semiconductor die 102. For example, the dielectric via 140 can extend from the dielectric material 138 away from a surface of the semiconductor die 102 to the semiconductor die 102. The dielectric via 140 can be electrically coupled (e.g., hybrid bonded) with the contact pad 112-3 at the semiconductor die 102 to provide power to the semiconductor die 102 through the contact pad 112-3. For example, a first end of the dielectric via 140 away from the semiconductor die 102 can be coupled with a power source, and a second end of the dielectric via 140 can be coupled with the contact pad 112-3, such that the dielectric via 140 can provide power from the power source to the first semiconductor die 102. In some cases, the contact pad 112-3 can be a buried contact (e.g., at the metallization layer 108) that is not exposed through the dielectric material 110. Thus, the dielectric via 140 can extend at least partially through the semiconductor die 102 to the buried contact, such that the dielectric via 140 is electrically coupled with the buried contact. The dielectric via 140 can be larger and have a larger aspect ratio (e.g., 10, 15, 20, 25, etc.) compared to TSVs (e.g., TSV 120 and TSV 132) between semiconductor dies. For example, the dielectric via 140 can have a width of 2 microns and a height of 30 microns, and the TSV 120 and TSV 132 can have a width of 1 micron and a height of 5 microns.

[0017] Dielectric material 142 can be disposed over dielectric material 138, the semiconductor die 104 stack, and the semiconductor die 106 stack. TSV 120-2, TSV 132-2, and dielectric via 140 can be exposed through dielectric material 142 to enable electrical contact therewith. For example, a redistribution layer 144 can be disposed over dielectric material 138, the semiconductor die 104 stack, and the semiconductor die 106 stack (e.g., at dielectric material 142). Redistribution layer 144 can include contact pads 146 (e.g., contact pad 146-1, contact pad 146-2, and contact pad 146-3) and connection circuitry (e.g., traces, wires, vias, and other connection structures) disposed in the entire dielectric material layer. Contact pads 146 can be disposed at exposed circuitry that is connected with semiconductor die 102, the semiconductor die 104 stack, and the semiconductor die 106 stack. For example, contact pad 146-1 can be electrically coupled with TSV 120-2, contact pad 146-2 can be electrically coupled with TSV 132-2, and contact pad 146-3 can be electrically coupled with dielectric via 140. Redistribution layer 144 can include connection circuitry (not shown) that connects contact pads 146 to contact pads (not shown) exposed at a surface away from semiconductor die 102. The contact pads can be connected to additional circuit components (e.g., a substrate or additional semiconductor dies) by connection structures (e.g., solder bumps 148) to provide functionality (e.g., power, ground, or input / output (I / O) signaling) for semiconductor device assembly 100.

[0018] Although not illustrated, semiconductor device assembly 100 can include additional dielectric vias that extend at least partially through dielectric material 138. For example, an additional dielectric via can extend completely through dielectric material 138 between redistribution layer 144 and semiconductor die 102. The additional dielectric via can be coupled with an additional contact pad at semiconductor die 102 to provide power, ground, or I / O signaling for semiconductor die 102. In other aspects, semiconductor device assembly 100 can include dummy dielectric vias that extend at least partially through dielectric material 138. The dummy dielectric vias can be electrically isolated from circuitry at the semiconductor device assembly (e.g., in semiconductor die 102, semiconductor die 104, and semiconductor die 106). Thus, the dummy dielectric vias do not communicate signaling to semiconductor die 102, semiconductor die 104, or semiconductor die 104. Instead, the dummy dielectric vias can be used to dissipate heat from the semiconductor device assembly. In aspects, no circuitry (e.g., traces, wires, vias, transistors, diodes, and other electrical components) is implemented between the plurality of dielectric vias. For example, dielectric material 138 between the dielectric vias is not a suitable material on which to dispose circuitry.

[0019] Although the semiconductor die 104 stack and the semiconductor die 106 stack are illustrated as two semiconductor dies, other implementations including more or fewer semiconductor dies are possible. Similarly, other implementations including the semiconductor die 104 stack or the semiconductor die 106 stack arranged differently exist. For example, the semiconductor die 104 stack or the semiconductor die 106 stack can be replaced with a semiconductor die stack assembled later to front of front (e.g., instead of front to back arrangement). Similarly, the semiconductor die 104 stack or the semiconductor die 106 stack can be coupled with the semiconductor die 102 in a back-to-back arrangement, a front-to-back arrangement, or a back-to-front arrangement (e.g., instead of face-to-face arrangement). In other aspects, the semiconductor die 104 stack or the semiconductor die 106 stack can be replaced with a single semiconductor die or a semiconductor die stack having 3, 4, 5, 6, 8, 10, 12, 14, 16, or any other number of semiconductor dies.

[0020] Although illustrated in cross-section with two semiconductor die stacks (the semiconductor die 104 stack and the semiconductor die 106 stack) electrically coupled with the semiconductor die 102, the semiconductor device assembly 100 can include any number of semiconductor die stacks. For example, the semiconductor device assembly 100 can include 3, 4, 5, 6, 8, 10, 12, 14, 16, or any other number of semiconductor die stacks electrically coupled with the semiconductor die 102. The semiconductor die stacks can be electrically coupled with the semiconductor die 102 in any number of arrangements. For example, the semiconductor die stacks can be coupled with the semiconductor die 102 in a rectangular pattern.

[0021] The present disclosure now turns to a series of steps for fabricating a semiconductor device assembly according to embodiments of the present technology. In particular, Figures 2 to 7 A simplified schematic cross-sectional view of a series of steps for fabricating a semiconductor device assembly according to embodiments of the present technology is illustrated. For ease of description, the steps are described with respect to a particular embodiment. However, steps can be performed with respect to Figures 2 to 7 The steps described are to fabricate a semiconductor device assembly according to other embodiments.

[0022] From Figure 2 Beginning at stage 200, a simplified schematic cross-sectional view of a semiconductor die 102 (e.g., a logic die) is illustrated. The semiconductor die 102 can include a metallization layer 108 with circuitry disposed thereat. A dielectric material 110 layer can be disposed over the metallization layer 108. A contact pad 112 can be disposed at the dielectric material 110 and electrically coupled with the circuitry at the metallization layer 108 to enable formation of an interconnect between the semiconductor die 102 and an additional die.

[0023] Although illustrated as a singulated semiconductor die 102, the steps with respect toFigures 2 to 7 The described steps can be performed at the wafer level to manufacture a single semiconductor device, or at the die level to manufacture multiple semiconductor devices. Figures 2 to 7 The described steps can be performed at the wafer level to manufacture a single semiconductor device, or at the die level to manufacture multiple semiconductor devices.

[0024] Figure 3 A simplified schematic cross-sectional view of stage 300 is illustrated, where the semiconductor die 104 stack and the semiconductor die 106 stack are coupled with the semiconductor die 102 at first and second lateral locations, respectively. The semiconductor die 104 stack and the semiconductor die 106 stack can be singulated from a wafer stack and coupled (e.g., stacked to wafer hybrid bonding) with the semiconductor die 102. Alternatively, each individual semiconductor die of the semiconductor die 104 stack and the semiconductor die 106 stack can be individually stacked. The semiconductor die 104 stack and the semiconductor die 106 stack can be coupled with the semiconductor die 102 by the dielectric material 110 and the contact pad 112. For example, the dielectric material 116-1 can be directly bonded with the dielectric material 110, and the contact pad 118-1 and the contact pad 112-1 can be coupled to form an interconnect electrically coupling the semiconductor die 102 and the semiconductor die 104 stack. Similarly, the dielectric material 128-1 can be directly bonded with the dielectric material 110, and the contact pad 130-1 and the contact pad 112-2 can be coupled to form an interconnect electrically coupling the semiconductor die 102 and the semiconductor die 106 stack.

[0025] Figure 4 A simplified schematic cross-sectional view of stage 400 is illustrated, where the dielectric material 138 is disposed at the semiconductor die 102 between the semiconductor die 104 stack and the semiconductor die 106 stack. In aspects, the dielectric material 138 (e.g., a dielectric filler) can be disposed at the semiconductor die 102 exposed beyond the footprint of the semiconductor die 104 stack and the footprint of the semiconductor die 106 stack. In aspects, the dielectric material 138 can mechanically support and protect the semiconductor device assembly. In other aspects, the dielectric material 138 can improve thermal regulation of the semiconductor device assembly. The dielectric material 138 can include any dielectric material, such as silicon oxide, silicon nitride, silicon carbide, or silicon carbonitride. The dielectric material 138 can similarly be disposed by any appropriate technique (e.g., dispensing, chemical vapor deposition, or physical vapor deposition).

[0026] As illustrated, dielectric material 138 can be disposed over distal ends of semiconductor die 104 stack and semiconductor die 106 stack opposite semiconductor die 102. Dielectric material 138 can be planarized (e.g., using chemical mechanical planarization (CMP) or grinding) to create a planar surface distal from semiconductor die 102. In some cases, planarization can expose (e.g., and thin) semiconductor die 104 stack and semiconductor die 106 stack (e.g., at semiconductor die 104-2 or semiconductor die 106-2). In this way, electrical contact can be made with semiconductor die 104 stack and semiconductor die 106 stack without requiring circuitry that extends through dielectric material 138. In other cases, planarization does not expose semiconductor die 104 stack and semiconductor die 106 stack, and a portion of dielectric material 138 remains over distal ends of semiconductor die 104 stack and semiconductor die 106 stack. Accordingly, a via can be disposed through dielectric material 138 to make electrical contact with semiconductor die 104-2, semiconductor die 106-2, or even semiconductor die 102, as Figure 5 illustrated in stage 500.

[0027] Figure 5 A simplified schematic cross-sectional view of stage 500 is illustrated, with a via disposed through dielectric material 138. For example, a dielectric material 142 layer (e.g., a dielectric block) can be disposed over semiconductor die 104 stack, semiconductor die 106 stack, and dielectric material 138 to protect and isolate circuitry at the same. TSV 120-2 can be implemented through dielectric material 138 and the substrate of semiconductor die 104-2, such that TSV 120-2 contacts circuitry at semiconductor die 104-2 and is exposed through dielectric material 138. For example, a via can be created (e.g., drilled or etched) through dielectric material 138 and the substrate of semiconductor die 104-2, and a conductive material can be deposited in the via to implement TSV 120-2. TSV 120-2 can be exposed through dielectric material 142 layer. In this way, electrical contact can be made with semiconductor die 104 stack through TSV 120-2. TSV 132-2 can similarly be implemented at semiconductor die 106-2 to enable electrical contact with semiconductor die 106 stack.

[0028] Furthermore, the dielectric via 140 can be implemented through the dielectric material 138 to the contact pad 112-3 at the semiconductor die 102. For example, the via can be created all the way through the dielectric material 138 to the contact pad 112-3. The via of the dielectric via 140 can be created by a process that is different than the via of the TSV 120 or the TSV 132. For example, the via of the TSV 120 or the TSV 132 can be created through the semiconductor material using a dry etch with a Bosch process. In contrast, the via of the dielectric via 140 can be dry etched through the dielectric material 138 without using a Bosch process. A conductive material can be deposited in the via to implement the dielectric via 140. Thus, the dielectric via 140 can be electrically coupled with the semiconductor die 102 through the contact pad 112-3 and exposed at a distal end opposite the semiconductor die through the dielectric material 138 (e.g., and the dielectric material 142). In contrast to the TSV 120 or the TSV 132, the dielectric via 140 need not be surrounded by a dielectric liner disposed in the via, for example, because the dielectric via 140 extends through the dielectric material 138 and not through a semiconductive material. Thus, the dielectric via 140 can not have the same stress, isolation, or diffusion problems as a TSV disposed through a semiconductor material. In aspects, the dielectric via 140 can be used to deliver power or other signals (e.g., ground or I / O signals) to circuitry at the semiconductor die 102.

[0029] Although specific embodiments have been illustrated and described herein Figures 3 to 5 for purposes of the embodiments, other such embodiments are possible. For example, although the semiconductor die 104 stack and the semiconductor die 106 stack are described as being mounted to the semiconductor die 102 as a stack, the semiconductor die 104 stack and the semiconductor die 106 stack can instead be mounted to the semiconductor die 102 by wafer-to-wafer bonding. In particular, the semiconductor die 104 stack, the semiconductor die 106 stack, and the dielectric material 138 can collectively form a reconstituted wafer that is bonded to the semiconductor die 102.

[0030] In some cases, the reconstituted wafer can be formed by adhering the semiconductor die 104 stack and the semiconductor die 106 stack to a carrier wafer, and disposing the dielectric material 138 between the semiconductor die 104 stack and the semiconductor die 106 stack (e.g., at a portion of the carrier wafer that is exposed beyond the semiconductor die 104 stack and the semiconductor die 106 stack). In aspects, adhering the semiconductor die 104 stack and the semiconductor die 106 stack to the carrier wafer as singulated die stacks enables testing of the semiconductor, the semiconductor die 104 stack, and the semiconductor die 106 stack and selection of them as "known good cubes," which can improve yield.

[0031] In other cases, the semiconductor die 104 stack and the semiconductor die 106 stack can be adhered to a carrier wafer as a wafer stack. The wafer stack can be sawn between the semiconductor die 104 stack and the semiconductor die 106 stack to remove portions of the wafer stack between the die stacks while leaving the semiconductor die 104 stack and the semiconductor die 106 stack adhered to the carrier. Then, the dielectric material 138 can be disposed between the semiconductor die 104 stack and the semiconductor die 106 stack (e.g., at a portion of the carrier wafer exposed by the semiconductor die 104 stack and the semiconductor die 106 stack).

[0032] Once the dielectric material 138 is disposed, the semiconductor die 104 stack, the semiconductor die 106 stack, and the dielectric material 138 can collectively form a reconstructed wafer that is bonded to the semiconductor die 102. Wafer-level processes can be performed on the reconstructed wafer. For example, the reconstructed wafer can be bonded to the semiconductor die 102 (e.g., a wafer including the semiconductor die 102) by wafer-level processes, which can have improved quality over stack-level or die-level processes. For example, wafer-level processes can result in semiconductor devices with higher yields or with better aligned interconnects.

[0033] In view of the wafer-level processing that can be performed on the reconstructed wafer, in some cases, the dielectric via 140 can be generated through the dielectric material 138 (e.g., to the carrier wafer) prior to the reconstructed wafer being bonded to the semiconductor die 102. For example, the via can be generated entirely through the dielectric material 138 on the reconstructed wafer, and a conductive material can be disposed in the via to implement the dielectric via. In this way, the dielectric via 140 can be exposed at a coupling surface of the reconstructed wafer such that, when the reconstructed wafer is bonded to the semiconductor die 102, the dielectric via 140 can be electrically coupled with the contact pad 112-3 (e.g., a hybrid bond). Alternatively, the dielectric via 140 can be generated after the reconstructed wafer is coupled with the semiconductor die 102.

[0034] Although illustrated in cross-section such that only two semiconductor die stacks are shown, additional die stacks can be stacked on the wafer of semiconductor dies 206. For example, the semiconductor device assembly can include 4, 8, 12, 30, 50, 100, or any other number of semiconductor die stacks. Similarly, although only two iterations of die stacks are illustrated, additional semiconductor die layers can be stacked onto the semiconductor device assembly by repeating the operations described with respect to Figure 5 and 6. Thus, the total number of semiconductor dies in each semiconductor die stack coupled to the wafer of semiconductor dies 206 can equal 2, 3, 4, 5, 6, 8, 10, 12, 14, 16, or any other number of semiconductor dies.

[0035] Turning next toFigure 6A A simplified schematic cross-sectional view of the semiconductor device assembly at stage 600A is illustrated. At stage 600A, a redistribution layer 144 is formed at a distal end opposite the semiconductor die 102. The redistribution layer 144 can be formed from layers of conductive material (e.g., copper, gold, or silver) and insulating material (e.g., dielectric material, polymer, or photosensitive dielectric material). The conductive material and insulating material can be disposed on the coupling surface by any suitable method. In aspects, the redistribution layer 144 can be formed by sputtering, plating, photolithography, etching, spin coating, or any other suitable technique.

[0036] The conductive material can be used to create a contact pad 146-1 corresponding to the exposed portion of the TSV 120-2, a contact pad 146-2 corresponding to the exposed portion of the TSV 132-2, and a contact pad 146-3 corresponding to the exposed portion of the dielectric via 140. The insulating material can be disposed to separate the conductive material and implement separate components. For example, layers of conductive material can be disposed to implement a wiring layer having internal circuitry connected to the contact pads 146. Dielectric layers can be disposed between the wiring layers to separate these layers. Contacts (illustrated in combination with the contact pads 146 for simplicity) can similarly be disposed at a surface of the redistribution layer 144 distal from the semiconductor die 102 (e.g., in a ball grid array (BGA)). The contacts can be electrically coupled with one or more external circuit components (e.g., a substrate and additional semiconductor dies) by solder bumps 148 or other connection structures to provide functionality (e.g., power, ground, I / O signaling) to the semiconductor die 104 stack, the semiconductor die 106 stack, and the semiconductor die 102 through the TSV 120-2, the TSV 132-2, and the dielectric via 140.

[0037] As discussed above, the semiconductor device assembly can be fabricated at the wafer level such that multiple semiconductor devices are fabricated on a single wafer. For example, the semiconductor die 102 can be a single semiconductor die on a wafer of semiconductor dies. Thus, the wafer of semiconductor dies including the semiconductor die 102 can be sawn between adjacent dies to singulate the semiconductor device assembly into multiple semiconductor device assemblies (e.g., including the illustrated assembly implemented on the semiconductor die 102). Although not illustrated, the dielectric material 138 can be disposed between different semiconductor dies on the wafer of semiconductor dies including the semiconductor die 102. Thus, singulating the wafer of semiconductor dies can include sawing through the dielectric material 138 between different semiconductor dies. Thus, the illustrated singulated semiconductor device assembly can include dielectric sidewalls at least partially surrounding the semiconductor die 104 stack or the semiconductor die 106 stack. Upon singulation, the semiconductor device assembly can be assembled onto a substrate as illustrated in Figure 7

[0038] Figure 6B ​Another embodiment of a semiconductor device assembly at stage 600B is illustrated. As with Figure 6A In contrast, Figure 6B The contact pad 112-3 illustrated in stage 600B is a buried contact pad (e.g., a back end of line contact pad) embedded in the semiconductor die 102. As such, the dielectric via 140 can extend at least partially through the semiconductor die 102 to the contact pad 112-3 such that electrical contact can be made with the contact pad 112-3. The semiconductor die 102 can include dummy pads 150 that improve the planarity of the semiconductor die 102 or the bonding of the semiconductor die 102 to the dielectric material 138.

[0039] Figure 6C Another embodiment of a semiconductor device assembly at stage 600C is illustrated in which one or more additional dielectric vias can be disposed through the dielectric material 138. For example, an additional dielectric via 152 can be disposed through the dielectric material 138 to an additional contact pad 112-4 (e.g., a buried contact pad or a surface contact pad) at the semiconductor die 102. The additional dielectric via 152 can provide an additional signal (e.g., a power, ground, or I / O signal) to the semiconductor die 102. In some cases, the additional dielectric via 152 can provide a direct signal path from the redistribution layer 144 to the semiconductor die 102 (e.g., except for the semiconductor die 104 stack or the semiconductor die 106 stack). In this way, other components on a package level substrate (not shown) attached to the redistribution layer 144 by solder bumps 148 can communicate with the semiconductor die 102 through the additional dielectric via 152. In other aspects, a dummy dielectric via can be created that extends at least partially through the dielectric material 138. The dummy dielectric via can be electrically isolated from circuitry at the semiconductor die 102 and thus cannot carry signals to or from the semiconductor die 102. Instead, the dummy dielectric via can be used to dissipate heat from the semiconductor device assembly or to improve the bonding between various device components (e.g., the semiconductor die 104 stack and the semiconductor die 102).

[0040] Figure 7 A simplified schematic cross-sectional view of a semiconductor device assembly at stage 700 is illustrated in which Figure 6AThe singulated semiconductor devices described in the foregoing example embodiments are assembled onto a package-level substrate 702 (e.g., a printed circuit board (PCB), an interposer, etc.) and packaged. For example, the redistribution layer 144 of the singulated semiconductor devices is coupled with the package-level substrate 702 through the solder bumps 148 such that the semiconductor die 102 is positioned above the semiconductor die 104 stack and the semiconductor die 106 stack. The package-level substrate 702 can include wiring circuitry that connects contacts (not shown) at an upper surface at which the solder bumps 148 are coupled to contacts (not shown) at a lower surface at which the connection structures 704 are disposed. The package-level substrate 702 can be coupled with external circuitry components (e.g., a host board) through the connection structures 704 to provide functionality (e.g., power, ground, I / O signaling) for the device assembly.

[0041] An underfill material 706 (e.g., a capillary underfill) can be provided between the singulated semiconductor devices and the package-level substrate 702 to provide electrical isolation of the connection structures (e.g., the solder bumps 148) and structurally support the assembly. The semiconductor device assembly can further include an encapsulant material 708 (e.g., a molding resin compound) that at least partially encapsulates the semiconductor die 102, the semiconductor die 104 stack, the semiconductor die 106 stack, and the package-level substrate 702 to prevent electrical contact therewith and to provide mechanical strength and protection for the assembly.

[0042] Although in the foregoing example embodiments, semiconductor device assemblies have been described and depicted as including particular configurations of semiconductor dies, in other embodiments, the assemblies can be provided with different configurations of semiconductor dies. For example, a vertical semiconductor die stack or a single semiconductor die can be employed to implement the semiconductor device assemblies described in any of the foregoing examples, with appropriate modifications.

[0043] According to one aspect of the disclosure, in Figures 1 to 7The semiconductor devices illustrated in the assemblies of FIGS. 1-3 can include memory dies, such as dynamic random access memory (DRAM) dies, NAND memory dies, or NOR memory dies, magnetic random access memory (MRAM) dies, phase change memory (PCM) dies, ferroelectric random access memory (FeRAM) dies, static random access memory (SRAM) dies, or the like. In embodiments in which multiple dies are disposed in a single assembly, the semiconductor devices can include the same kind of memory dies (e.g., both NAND, both DRAM, etc.) or different kinds of memory dies (e.g., one DRAM and one NAND, etc.). According to another aspect of the disclosure, the semiconductor dies of the assemblies illustrated and described above can be logic dies (e.g., controller dies, processor dies, etc.), or a mix of logic dies and memory dies (e.g., a memory controller die and memory dies controlled thereby). In some embodiments, the semiconductor device assemblies can communicate using a tightly coupled memory (TCM) protocol.

[0044] Any of the semiconductor devices and semiconductor device assemblies described above with respect to Figures 1 to 7 may be incorporated into any of a vast number of larger and / or more complex systems, representative examples of which are Figure 8 the system 800 illustratively shown in FIG. 8. The system 800 can include a semiconductor device assembly 802 (e.g., a discrete semiconductor device), a power supply 804, a driver 806, a processor 808, and / or other subsystems or components 810. The semiconductor device assembly 802 can include features generally similar to those of the semiconductor device assemblies described above with respect to Figures 1 to 7 The resulting system 800 can perform any of a wide

[0045] Figure 9 An example method 900 for fabricating a semiconductor device assembly according to embodiments of the present technology is illustrated. Although illustrated in a particular configuration, one or more operations of the method 900 can be omitted, repeated, or reorganized. Additionally, the method 900 can include other operations not illustrated in Figure 9 , such as operations detailed in one or more other methods described herein.

[0046] At 902, a first semiconductor die is provided. The first semiconductor die has a first contact, a second contact, and a third contact coupled with circuitry at the first semiconductor die. At 904, a first semiconductor die stack and a second semiconductor die stack are provided. At 906, the first semiconductor die stack is coupled with the first semiconductor die at a first lateral location through the first contact. At 908, the second semiconductor die stack is coupled with the first semiconductor die at a second lateral location through the second contact. At 910, a dielectric material is disposed between the first semiconductor die stack and the second semiconductor die stack. At 912, a dielectric via is created that extends completely through the dielectric material. At 914, the dielectric via is coupled with the first semiconductor die through the third contact such that the dielectric via is configured to provide power to the circuitry at the first semiconductor die through the third contact. In so doing, a semiconductor device with a dielectric via can be implemented.

[0047] Specific details of several embodiments of semiconductor devices, and related systems and methods are described above. Depending upon the context, the term "substrate" can refer either to a wafer- scale substrate or to a singulated, die-scale substrate. Further, structures disclosed herein can be formed using conventional semiconductor fabrication techniques, unless otherwise indicated. Materials can be deposited, for example, using chemical vapor deposition, physical vapor deposition, plating, electroless plating, spin-coating, and / or other suitable techniques. Similarly, materials can be removed, for example, using plasma etching, wet etching, CMP, or other suitable techniques.

[0048] The technology disclosed herein relates to semiconductor devices, systems having semiconductor devices, and related methods for manufacturing semiconductor devices. The term "semiconductor device" generally refers to a solid-state device that includes one or more semiconductor materials. Examples of semiconductor devices include, among others, logic devices, memory devices, and diodes. Further, the term "semiconductor device" can refer to a finished device or to assemblies or other structures at various processing stages before becoming a finished device. Depending upon the context in which the term "substrate" is used, the term "substrate" can refer to a structure that supports electronic components, such as a die, e.g., a PCB or a wafer-scale substrate, a die-scale substrate, or another die for a die stack or 3DI application.

[0049] The devices discussed herein, including memory devices, can be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be an epitaxial layer of semiconductor material on an insulator (such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during initial formation or growth of the substrate, or by any other doping means.

[0050] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the disclosure and appended claims. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations.

[0051] As used herein, including in the claims, “or” as used in a list of items (for example, a list of items prefaced by a phrase such as “at least one of’ or “one or more of’) indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an example step that is described as “based on condition A” can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0052] As used herein, the terms “vertical,” “lateral,” “upper,” “lower,” “over,” and “under” can refer to the relative directions or positions of features in a semiconductor device in view of the orientation shown in the figures. For example, “upper” or “uppermost” can refer to a feature positioned closer to the top of the page than another feature. However, these terms should be construed broadly to include semiconductor devices having other orientations (e.g., inverted or tilted orientations), where top / bottom, over / under, above / below, upward / downward, and left / right can be interchanged depending on the orientation.

[0053] From the foregoing, it will be appreciated that specific embodiments of the application have been described herein for purposes of illustration, but that various modifications can be made without deviating from the scope of the application. In particular, although many of the examples presented herein involve specific combinations of method acts or system elements, it should be understood that those acts and those elements can be combined in other ways to accomplish the same objectives. Accordingly, the descriptions and representations are to be considered as illustrative and not restrictive.

Claims

1. A semiconductor device assembly comprising: a first semiconductor die having a first contact, a second contact, and a third contact coupled with circuitry at the first semiconductor die; a first semiconductor die stack coupled with the first semiconductor die at a first lateral location through the first contact, the first semiconductor die stack including a second semiconductor die, the second semiconductor die being distal from the first semiconductor die and having a fourth contact coupled with circuitry at the second semiconductor die, the fourth contact being exposed at a first distal end of the first semiconductor die stack opposite the first semiconductor die; a second semiconductor die stack coupled with the first semiconductor die at a second lateral location through the second contact, the second semiconductor die stack including a third semiconductor die, the third semiconductor die being distal from the first semiconductor die and having a fifth contact coupled with circuitry at the third semiconductor die, the fifth contact being exposed at a second distal end of the second semiconductor die stack opposite the first semiconductor die; a dielectric material disposed at a portion of the first semiconductor die exposed beyond a first footprint of the first semiconductor die stack and a second footprint of the second semiconductor die stack; and a dielectric via extending completely through the dielectric material to the third contact and configured to provide power to the circuitry at the first semiconductor die.

2. The semiconductor device assembly of claim 1, wherein: the fourth contact includes a through-silicon via extending through the second semiconductor die; and the fifth contact includes an additional through-silicon via extending through the third semiconductor die.

3. The semiconductor device assembly of claim 1, wherein: the third contact comprises a buried contact; and the dielectric via extends at least partially through the first semiconductor die to the buried contact.

4. The semiconductor device assembly of claim 1, further comprising: a sixth contact coupled with the circuitry at the first semiconductor die; and an additional dielectric via extending completely through the dielectric material to the sixth contact, the additional dielectric via configured to communicate signaling to or from the circuitry at the first semiconductor die.

5. The semiconductor device assembly of claim 1, further comprising a dummy dielectric via extending at least partially through the dielectric material, the dummy dielectric via being electrically isolated from the circuitry at the first semiconductor die.

6. The semiconductor device assembly of claim 1, further comprising a redistribution layer disposed over the first semiconductor die stack, the second semiconductor die stack, and the dielectric material, the redistribution layer being coupled with the fourth contact, the fifth contact, and the dielectric via.

7. The semiconductor device assembly of claim 1, wherein: ​ ​ The dielectric material is disposed over the first distal end of the first semiconductor die stack and the second distal end of the second semiconductor die stack; and The fourth contact and the fifth contact are exposed through the dielectric material.

8. The semiconductor device assembly of claim 1, wherein: The first semiconductor die comprises a logic die; and The first semiconductor die stack and the second semiconductor die stack comprise memory dies.

9. A method for manufacturing a semiconductor device assembly, comprising: providing a first semiconductor die having a first contact, a second contact, and a third contact coupled with circuitry at the first semiconductor die; providing a first semiconductor die stack and a second semiconductor die stack; coupling the first semiconductor die stack with the first semiconductor die at a first lateral location through the first contact; coupling the second semiconductor die stack with the first semiconductor die at a second lateral location through the second contact; disposing a dielectric material between the first semiconductor die stack and the second semiconductor die stack; creating a dielectric via extending completely through the dielectric material; and coupling the dielectric via with the first semiconductor die through the third contact such that the dielectric via is configured to provide power to the circuitry at the first semiconductor die through the third contact.

10. The method of claim 9, further comprising: coupling a plurality of wafers of semiconductor dies to create a semiconductor wafer stack; and singulating the first semiconductor die stack from the semiconductor wafer stack.

11. The method of claim 9, further comprising, after coupling the first semiconductor die stack and the second semiconductor die stack with the first semiconductor die, disposing the dielectric material at the first semiconductor die between the first semiconductor die stack and the second semiconductor die stack.

12. The method of claim 9, further comprising: adhering the first semiconductor die stack to a carrier wafer; adhering the second semiconductor die stack to the carrier wafer; disposing the dielectric material at the carrier wafer between the first semiconductor die stack and the second semiconductor die stack to form a reconstituted wafer including the first semiconductor die stack, the second semiconductor die stack, and the dielectric material; and coupling the reconstituted wafer to the first semiconductor die such that the first semiconductor die stack is coupled with the first semiconductor die at the first lateral location through the first contact and the second semiconductor die stack is coupled with the first semiconductor die at the second lateral location through the second contact.

13. The method of claim 12, further comprising: coupling a plurality of wafers of semiconductor dies to create a semiconductor wafer stack including the first semiconductor die stack and the second semiconductor die stack, the semiconductor wafer stack adhered to the carrier wafer; and removing a portion of the semiconductor die stack between the first semiconductor die stack and the second semiconductor die stack.

14. The method of claim 12, further comprising: generating the via through the dielectric material before coupling the reconstituted wafer to the first semiconductor die; and coupling the reconstituted wafer to the first semiconductor die such that the via is coupled to the first semiconductor die through the third contact.

15. The method of claim 9, wherein the third contact is a buried contact, the method further comprising: generating a via extending completely through the dielectric material and at least partially through the first semiconductor die to the buried contact; and disposing conductive material in the via to implement the via coupled to the buried contact.

16. The method of claim 9, further comprising: disposing the dielectric material over the first semiconductor die stack and the second semiconductor die stack; generating a second via extending at least partially through the dielectric material to circuitry at a second semiconductor die of the first semiconductor die stack; and generating a third via extending through the dielectric material to circuitry at a third semiconductor die of the second semiconductor die stack.

17. The method of claim 9, further comprising disposing a redistribution layer over the first semiconductor die stack, the second semiconductor die stack, and the dielectric material, the redistribution layer coupled to the first semiconductor die stack, the second semiconductor die stack, and the via.

18. The method of claim 9, wherein the first semiconductor die includes a fourth contact coupled to the circuitry at the first semiconductor die, the method further comprising: generating an additional via extending completely through the dielectric material; and coupling the additional via to the first semiconductor die through the fourth contact such that the additional via is configured to provide communication signaling to or from the circuitry at the first semiconductor die through the fourth contact.

19. The method of claim 9, further comprising generating a dummy via extending at least partially through the dielectric material, the dummy via electrically isolated from the circuitry at the first semiconductor die.

20. A semiconductor device assembly, comprising: a redistribution layer; a first semiconductor die stack coupled to the redistribution layer at a first lateral location; a second semiconductor die stack coupled to the redistribution layer at a second lateral location; a first semiconductor die having a footprint greater than the first semiconductor die stack and the second semiconductor die stack combined, the first semiconductor die coupled to the first semiconductor die stack and the second semiconductor die stack at a distal end opposite the redistribution layer; a dielectric material disposed between the redistribution layer, the first semiconductor die stack, the second semiconductor die stack, and the first semiconductor die; and a dielectric via extending through the dielectric material between the redistribution layer and the first semiconductor die, the dielectric via configured to provide power from the redistribution layer to the first semiconductor die.

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