Display module, driving method thereof and display device

Abstract

The invention provides a display module, a driving method thereof and a display device. The display module comprises a display panel, a driving chip and a flexible circuit board, the flexible circuit board is provided with a memory, the driving chip comprises a first binding area, and the first binding area comprises a first binding pin group and a second binding pin group which are electrically connected with a data interface of the driving chip. The first binding pin group and the second binding pin group have a set interval in a first direction, the first direction is the arrangement direction of the binding pins in the first binding area, and the flexible circuit board comprises a third binding pin group and a fourth binding pin group which are electrically connected with the memory respectively; the first binding pin group and the third binding pin group are respectively bound with the display panel to realize electric connection, and the second binding pin group and the fourth binding pin group are respectively bound with the display panel to realize electric connection. According to the embodiment, the signal transmission interruption risk between the driving chip and the memory can be reduced, and the robustness of signal transmission is improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology. More specifically, it relates to a display module and its driving method, and a display device. Background Technology

[0002] For example, in display modules such as Organic Light Emitting Diodes (OLEDs), compensation data is typically stored in the module's memory to optimize display performance. This compensation data includes parameters such as gamma correction and demura parameters. After the display module is powered on, the display driver IC (DIC) reads the compensation data from the memory and uses it to compensate for the image to be displayed. The inventors discovered that compensation failures frequently occur during reliability testing of display modules, affecting the display performance of the product. Summary of the Invention

[0003] The purpose of this disclosure is to provide a display module and its driving method, as well as a display device, to solve at least one of the problems existing in the prior art.

[0004] To achieve the above objectives, the present disclosure adopts the following technical solution: The first aspect of this disclosure provides a display module, including a display panel, a driver chip, and a flexible circuit board. The flexible circuit board is provided with a memory. The driver chip includes a first bonding area, which includes a first bonding pin group and a second bonding pin group electrically connected to the data interface of the driver chip, respectively. The first bonding pin group and the second bonding pin group are spaced apart in a first direction, which is the arrangement direction of the bonding pins in the first bonding area. The flexible circuit board includes a third bonding pin group and a fourth bonding pin group electrically connected to the memory, respectively. The first bonding pin group and the third bonding pin group are electrically connected to the display panel by bonding, and the second bonding pin group and the fourth bonding pin group are electrically connected to the display panel by bonding.

[0005] Optionally, the number of bonding pins between the first bonding pin group and the second bonding pin group is greater than or equal to 10.

[0006] Optionally, the number of bonding pins between the first bonding pin group and the second bonding pin group is less than or equal to 100.

[0007] Optionally, the first and second binding pin groups are equidistant from the data interface in the first direction.

[0008] Optionally, the driver chip includes a data selection circuit, wherein the first binding pin group is electrically connected to the first input terminal group of the data selection circuit, the second binding pin group is electrically connected to the second input terminal group of the data selection circuit, and the output terminal group of the data selection circuit is electrically connected to the data interface of the driver chip.

[0009] Optionally, the driver chip is configured to control the data selection circuit to connect the first input group or the second input group to the output group based on data read from the memory.

[0010] Optionally, the driver chip is configured to control the data selection circuit to connect at least one first input terminal in the first input terminal group or at least one second input terminal in the second input terminal group to the output terminal group in response to an external instruction.

[0011] Optionally, the data selection circuit is a multiplexer.

[0012] Optionally, the driver chip is configured to control the multiplexer via registers.

[0013] A second aspect of this disclosure provides a display device, including the display module provided in the first aspect of this disclosure.

[0014] A third aspect of this disclosure provides a driving method for a display module, applied to the display module provided in the first aspect of this disclosure, the driving method comprising: The driver chip determines whether the data read from the memory is normal. If not, it controls the data selection circuit to switch one input group currently connected to the output group to another input group. The first input group is one of the first input group and the second input group, and the other input group is the other of the first input group and the second input group; or In response to an external command, the driver chip controls the data selection circuit to connect at least one first input terminal in the first input terminal group or at least one second input terminal in the second input terminal group to the output terminal group.

[0015] The beneficial effects of this disclosure are as follows: The technical solution described in this disclosure reduces the risk that the high-voltage, high-frequency signal accelerating the electrochemical corrosion at the bonding connection between the driver chip and the display panel and / or the bonding connection between the flexible circuit board and the display panel may cause the driver chip to be unable to read compensation data from the memory. This reduces the risk of signal transmission interruption between the driver chip and the memory, improves the robustness of signal transmission, and helps the display product pass reliability tests and extend the lifespan of the display product. Attached Figure Description

[0016] The specific embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0017] Figure 1 A schematic diagram of a display module in the related art is shown.

[0018] Figure 2 The image shows an electron microscope (EM) image of the film layer detached from the bonding area between the driver chip and the display panel.

[0019] Figure 3 A schematic diagram of a display module provided in an embodiment of this disclosure is shown.

[0020] Figure 4 A schematic diagram of a multiplexer is shown. Detailed Implementation

[0021] The terms “on”, “formed on”, and “set on” used in this disclosure can indicate that one layer is directly formed or set on another layer, or that one layer is indirectly formed or set on another layer, meaning that there are other layers between the two layers.

[0022] It should be noted that although the terms "first," "second," etc., may be used herein to describe various components, members, elements, regions, layers, and / or parts, these components, members, elements, regions, layers, and / or parts should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and / or part from another. Thus, for example, the first component, first member, first element, first region, first layer, and / or first part discussed below may be referred to as a second component, second member, second element, second region, second layer, and / or second part without departing from the teachings of this disclosure.

[0023] In this disclosure, unless otherwise stated, the term "co-layer arrangement" means that two layers, components, members, elements, or portions can be formed by the same fabrication process (e.g., patterning process), and that the two layers, components, members, elements, or portions are generally formed of the same material. For example, co-layer arrangement of two or more functional layers means that these co-layer functional layers can be formed using the same material layer and the same fabrication process, thereby simplifying the fabrication process of the display substrate.

[0024] In this disclosure, unless otherwise stated, the term "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping. The term "one-step patterning process" refers to a process that uses a photomask to form patterned layers, components, or parts.

[0025] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description of this disclosure and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in this disclosure may be appropriately replaced as appropriate.

[0026] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0027] In this disclosure, "parallel" can be broadly defined as the state in which two straight lines form an angle of -10° or more and less than 10°, and therefore also includes the state in which the angle is -5° or more and less than 5°. In addition, "perpendicular" can be broadly defined as the state in which two straight lines form an angle of 80° or more and less than 100°, and therefore also includes the state in which the angle is 85° or more and less than 95°.

[0028] In this disclosure, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined, but can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, and chamfers, curved edges, and other deformations are possible.

[0029] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0030] In this disclosure, “equal” includes absolute equality and approximate equality, wherein an acceptable deviation of approximate equality may be, for example, the difference between the two equals being less than or equal to 5% of either one.

[0031] For example, in display modules such as OLEDs, the driver chip is bonded to the display panel using a COP (Chip On Panel) bonding process, and the flexible printed circuit board (FPC) is bonded to the display panel using a FOP (Flexible On Panel) bonding process. For example, the FLASH memory is mounted on the flexible printed circuit board. Related display modules include... Figure 1 As shown, the system includes a display panel 110, a driver chip 120, and a flexible circuit board 130. For example, a FLASH memory 1301 is disposed on the flexible circuit board 130. The signal channels between the driver chip 120 and the memory 1301, which use SPI communication, include a clock signal transmission channel CLK, a master output / slave input signal transmission channel MOSI, a master input / slave output signal transmission channel MISO, and a chip select signal transmission channel CS, for a total of four signal transmission channels. Each signal transmission channel from the memory 1301 to the data interface 1201 of the driver chip 120 includes a flexible circuit board lead, an FOP bonding part (composed of a bonding pin of a flexible circuit board and a bonding pin of a display panel), a display panel lead, a COP bonding part (composed of a bonding pin of a driver chip and a bonding pin of a display panel), and a driver chip lead, which are connected in sequence.

[0032] Regarding the compensation failure problem that often occurs in the reliability testing of display modules, the inventors discovered that the high-voltage, high-frequency signal from which the driver chip reads compensation data from the memory located on the flexible circuit board accelerates the electrochemical corrosion at the bonding connection between the driver chip and the display panel (COP bonding area) and / or the bonding connection between the flexible circuit board and the display panel (FOP bonding area). This corrosion is particularly accelerated by the high-temperature and high-humidity environment of reliability testing, leading to film peeling at the bonding area. Figure 2 As shown. Consequently, the signal channel between the driver chip and the memory is disconnected, and the driver chip cannot read compensation data from the memory. Display products often fail reliability tests due to this problem, and this issue also affects the lifespan of the display product.

[0033] In view of the above, one embodiment of this disclosure provides a display module including a display panel, a driver chip, and a flexible circuit board. The flexible circuit board is provided with a memory. The driver chip includes a first bonding area, which includes a first bonding pin group and a second bonding pin group that are electrically connected to the data interface of the driver chip, respectively. The first bonding pin group and the second bonding pin group are spaced apart in a first direction, which is the arrangement direction of the bonding pins in the first bonding area. The flexible circuit board includes a third bonding pin group and a fourth bonding pin group that are electrically connected to the memory, respectively. The first bonding pin group and the third bonding pin group are electrically connected to the display panel by bonding, and the second bonding pin group and the fourth bonding pin group are electrically connected to the display panel by bonding.

[0034] This embodiment reduces the risk of the driver chip being unable to read compensation data from the memory due to the electrochemical corrosion at the bonding connection between the driver chip and the display panel and / or the bonding connection between the flexible circuit board and the display panel caused by the high-voltage, high-frequency signal accelerating the driver chip's reading of compensation data from the memory. This also reduces the risk of signal transmission interruption between the driver chip and the memory, improves the robustness of signal transmission, helps the display product pass reliability tests, and extends the lifespan of the display product.

[0035] The display module provided in this embodiment includes various types of display panels, which can be selected and set according to actual needs. For example, it can be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, or a mini / micro light-emitting display (MLED) display panel, etc. This embodiment does not make specific limitations here.

[0036] In a specific example, for example Figure 3As shown, the display module provided in this embodiment includes a display panel 310, a driver chip 320, and a flexible circuit board 330. The flexible circuit board 330 is provided with a memory 3301, such as FLASH. Taking the display panel 310 as an OLED display panel as an example, it includes a display area AA and a border area. The display area AA includes multiple sub-pixels arranged in an array, multiple scan lines (or gate lines) extending along a first direction (e.g., row direction) and spaced along a second direction (e.g., column direction), and multiple data lines extending along the second direction and spaced along the first direction. The sub-pixels include thin-film transistors (TFTs), anodes, and OLED light-emitting layers. The gate of the thin-film transistor is connected to the scan line, the first electrode (e.g., source electrode) is connected to the data line, and the second electrode (e.g., drain electrode) is the anode. The display area AA also includes other film layers such as a buffer layer, a pixel boundary layer, a cathode, and an encapsulation layer, which will not be described in detail here.

[0037] The display area AA side of the display panel 310 (e.g.) Figure 3 The lower side (as shown) border area includes a first bonding area for bonding the display panel to the driver chip 320 and a second bonding area for bonding the display panel to the flexible circuit board. The first bonding area includes a plurality of first bonding pins of the display panel arranged along a first direction, and the second bonding area includes a plurality of second bonding pins of the display panel arranged along the first direction, which is the extending direction of the lower side edge of the display panel. Figure 3 The horizontal direction in the middle.

[0038] The driver chip 320 includes a driver chip bonding area (i.e., a first bonding area), which includes a plurality of driver chip bonding pins arranged along a first direction. Some of the driver chip bonding pins form a first bonding pin group and a second bonding pin group that are electrically connected to the data interface of the driver chip.

[0039] Taking the driver chip 320 and memory 3301 using SPI communication as an example: As shown in Example 3, the first bonding pin group includes four driver chip bonding pins, namely, a driver chip bonding pin that is bonded to a first bonding pin of a display panel to form a first COP bonding section 3401 belonging to the first CLK signal transmission channel; a driver chip bonding pin that is bonded to a first bonding pin of a display panel to form a second COP bonding section 3402 belonging to the first CS signal transmission channel; a driver chip bonding pin that is bonded to a first bonding pin of a display panel to form a third COP bonding section 3403 belonging to the first MOSI signal transmission channel; and a driver chip bonding pin that is bonded to a first bonding pin of a display panel to form a third COP bonding section 3403 belonging to the first MOSI signal transmission channel. The driver chip bonding pins of the four COP bonding units 3404 are as follows: the driver chip bonding pin of the first COP bonding unit 3401 is electrically connected to the data interface 3201 of the driver chip 320 via the first driver chip lead 3501; the driver chip bonding pin of the second COP bonding unit 3402 is electrically connected to the data interface 3201 via the second driver chip lead 3502; the driver chip bonding pin of the third COP bonding unit 3403 is electrically connected to the data interface 3201 via the third driver chip lead 3503; and the driver chip bonding pin of the fourth COP bonding unit 3404 is electrically connected to the data interface 3201 via the fourth driver chip lead 3504. For example... Figure 3 As shown, the bonding structure and routing of the second bonding pin group are similar to those of the first bonding pin group, and will not be described again here.

[0040] The flexible circuit board 330 includes a flexible circuit board bonding area, which includes a plurality of flexible circuit board bonding pins arranged along a first direction. Some of these flexible circuit board bonding pins constitute a third bonding pin group and a fourth bonding pin group electrically connected to the memory 3301. For example, as shown in Figure 3, the third bonding pin group includes four flexible circuit board bonding pins: a first FOP bonding portion 3601 bonded to a second bonding pin of a display panel to form a first CLK signal transmission channel; a second FOP bonding portion 3602 bonded to a second bonding pin of a display panel to form a first CS signal transmission channel; a third FOP bonding portion 3603 bonded to a second bonding pin of a display panel to form a first MOSI signal transmission channel; and a fourth FOP bonding portion 3604 bonded to a second bonding pin of a display panel to form a first MISO signal transmission channel. The first FOP bonding portion... The second bonding pin of the display panel of the fixed part 3601 is electrically connected to the first bonding pin of the display panel of the first COP bonding part 3401 through the first display panel lead 3701. The second bonding pin of the display panel of the second FOP bonding part 3602 is electrically connected to the first bonding pin of the display panel of the second COP bonding part 3402 through the second display panel lead 3702. The second bonding pin of the display panel of the third FOP bonding part 3603 is electrically connected to the first bonding pin of the display panel of the third COP bonding part 3403 through the third display panel lead 3703. The second bonding pin of the display panel of the fourth FOP bonding part 3604 is electrically connected to the first bonding pin of the display panel of the fourth COP bonding part 3404 through the fourth display panel lead 3704. The flexible circuit board bonding pins of the first FOP bonding section 3601, the second FOP bonding section 3602, the third FOP bonding section 3603, and the fourth FOP bonding section 3604 are electrically connected to the CLK signal port, CS signal port, MOSI signal port, and MISO signal port of the memory 3301 respectively via independent flexible circuit board leads. Figure 3 As shown, the bonding structure and routing of the fourth bonding pin group are similar to those of the third bonding pin group, and will not be described again here.

[0041] It should be noted that, as Figure 3 As shown, the flexible circuit board leads electrically connected to the flexible circuit board bonding pins of the first FOP bonding section 3601 belonging to the first CLK signal transmission channel in the third bonding pin group, and the flexible circuit board leads electrically connected to the flexible circuit board bonding pins of the FOP bonding section belonging to the second CLK signal transmission channel in the fourth bonding pin group, can be connected in parallel to the CLK signal port of the memory 3301 inside the flexible circuit board, or for example... Figure 3 The flexible circuit board lead belonging to the first CLK signal transmission channel, electrically connected to the first FOP bonding part 3601 in the third bonding pin group on the left, and the flexible circuit board lead belonging to the second CLK signal transmission channel, electrically connected to the FOP bonding part in the fourth bonding pin group on the right, are shorted together near the memory 3301 to form a single flexible circuit board lead connected to the CLK signal port of the memory 3301. That is, the first and second CLK signal transmission channels are paralleled inside the flexible circuit board. The other three signal transmission channels are similar. Figure 3 The driver chip 320 shown includes a data selection circuit 3202. On the side of the data selection circuit 3202 connected to the data interface 3201, the first CLK signal transmission channel and the second CLK signal transmission channel are paralleled. On the side of the data selection circuit 3202 connected to the driver chip's bonding pins, the leads of the first CLK signal transmission channel and the second CLK signal transmission channel are independent so that the data selection circuit 3202 can switch the signal transmission channels. If the data selection circuit 3202 is not provided, the first CLK signal transmission channel and the second CLK signal transmission channel are paralleled inside the driver chip.

[0042] As can be seen, in the display module provided in this embodiment, two independent signal transmission channels are formed between the driver chip and the memory, at the bonding connection between the driver chip and the display panel, and at the bonding connection between the flexible circuit board and the display panel. Figure 3 The first group of signal transmission channels 3801 and the second group of signal transmission channels 3802 shown can reduce the risk that the high voltage and high frequency signals accelerating the electrochemical corrosion at the bonding connection between the driver chip and the display panel and / or the bonding connection between the flexible circuit board and the display panel may cause the driver chip to be unable to read the compensation data from the memory. This reduces the risk of signal transmission interruption between the driver chip and the memory, improves the robustness of signal transmission, helps the display product pass the reliability test, and helps extend the life of the display product.

[0043] In one possible implementation, the number of bonding pins spaced between the first bonding pin group and the second bonding pin group is greater than or equal to 10. Therefore, this implementation, by limiting the number of bonding pins spaced between the first bonding pin group and the second bonding pin group, defines the distance between the first bonding pin group and the second bonding pin group in a first direction (the direction of the bonding pin arrangement). Figure 3The horizontal spacing can prevent the first and second bonding pin groups from being too close, which could cause a film layer to detach at the bonding connection between the driver chip and the display panel, or a film layer to detach at the bonding connection between the flexible circuit board and the display panel. This would interrupt both signal transmission channels simultaneously, further reducing the risk of signal transmission interruption between the driver chip and the memory, and further improving the robustness of signal transmission.

[0044] In one possible implementation, the number of bonded pins between the first bonded pin group and the second bonded pin group is less than or equal to 100. This avoids the problem of excessively long lead traces in the two signal transmission channels, thus helping to ensure signal quality.

[0045] In one possible implementation, the first and second bonding pin groups are equidistant from the data interface in the first direction. This ensures that the lead lengths of the two signal transmission channels remain consistent, thus guaranteeing the synchronization of the signals transmitted by the two signal transmission channels.

[0046] Continuing with the previous example, for example Figure 3 As shown, the data interface 3201 is located in the first direction of the driver chip 320 ( Figure 3 In the middle position (horizontal direction), the first binding pin group and the second binding pin group are symmetrically located on the left and right sides of the data interface 3201 in the first direction, and are equidistant from the data interface 3201 in the first direction.

[0047] In one possible implementation, the driver chip includes a data selection circuit. The first bonding pin group is electrically connected to the first input terminal group of the data selection circuit, the second bonding pin group is electrically connected to the second input terminal group of the data selection circuit, and the output terminal group of the data selection circuit is electrically connected to the data interface of the driver chip. Thus, by switching the signal transmission channels of the data selection circuit, only one of the two signal transmission channels can transmit signals at any given time. This avoids the phenomenon where both signal transmission channels transmit signals simultaneously, causing both channels to simultaneously generate high-voltage, high-frequency signals that accelerate the electrochemical corrosion of the bonding connection between the driver chip and the display panel (COP bonding area) and / or the bonding connection between the flexible circuit board and the display panel (FOP bonding area).

[0048] Continuing with the previous example, for example Figure 3As shown, the driver chip 320 includes a data selection circuit 3202. A first bonding pin group is electrically connected to the first input terminal group of the data selection circuit 3202 through a first lead group (the first lead group includes a first driver chip lead 3501, a second driver chip lead 3502, a third driver chip lead 3503, and a fourth driver chip lead 3504). A second bonding pin group is electrically connected to the second input terminal group of the data selection circuit 3202 through a second lead group. The output terminal group of the data selection circuit 3202 is electrically connected to the data interface 3201 through a third lead group.

[0049] In one possible implementation, the data selection circuit is a multiplexer.

[0050] Continuing with the previous example, the data selection circuit 3202 is, for example... Figure 4 The multiplexer shown is... Figure 4 As shown, for the clock signal transmission channel CLK, the master output slave input signal transmission channel MOSI, the master input slave output signal transmission channel MISO, and the chip select signal transmission channel CS, the multiplexer uses logic gate circuits including NOT gates, AND gates, and OR gates to switch the signal transmission channels.

[0051] Taking the clock signal transmission channel CLK as an example, CLK_1 is a memory 3301 that contains the clock signal transmission channel CLK_1. Figure 3 The CLK signal transmitted through the first CLK signal transmission channel of the first COP bonding section 3401 and the first FOP bonding section 3601 on the left side of the multiplexer is transmitted to the first CLK input terminal in the first input terminal group of the multiplexer. CLK_2 is the CLK signal transmitted through the memory 3301 via the first CLK signal transmission channel of the first COP bonding section 3401 and the first FOP bonding section 3601. Figure 3 The second CLK signal transmission channel of the COP binding section and FOP binding section on the right side transmits the CLK signal to the second CLK input terminal in the second input terminal group of the multiplexer. Figure 3 and Figure 4In the diagram, CLK_S is the control signal for the CLK logic gate circuit. When CLK_S is 0, after passing through NOT gate 401, CLK_S makes the signal input to the second input terminal of the first AND gate 402 1. If the CLK_1 signal of the first CLK signal transmission channel is 0, the output signal of the first AND gate 402 is 0; if the CLK_1 signal of the first CLK signal transmission channel is 1, the output signal of the first AND gate 402 is 1. CLK_S with the CLK_1 signal of the first CLK signal transmission channel being 0 is directly input to the first input terminal of the second AND gate 403. Regardless of whether the CLK_2 signal of the second CLK signal transmission channel is 0 or 1, the second AND gate 403 outputs a signal of 0. The output signals of the first AND gate 402 and the second AND gate 403 are respectively output to the two input terminals of the OR gate 404, and the output of the OR gate 404... The CLK output terminal of the CLK logic gate circuit of the multiplexer is used as the CLK output terminal. When the CLK_1 signal of the first CLK signal transmission channel is 0, the output signal of the CLK output terminal of the multiplexer is 0. When the CLK_1 signal of the first CLK signal transmission channel is 1, the output signal of the CLK output terminal of the multiplexer is 1. That is, the signal CLK_OUT output by the CLK output terminal of the multiplexer is determined by the CLK_1 signal of the first CLK signal transmission channel, or in other words, the signal CLK_OUT output by the CLK output terminal of the multiplexer is the CLK_1 signal of the first CLK signal transmission channel. Conversely, when CLK_S is 1, the signal CLK_OUT output by the CLK output terminal of the CLK logic gate circuit of the multiplexer is the CLK_2 signal of the second CLK signal transmission channel. Thus, the two signal transmission channels of the CLK signal can be controlled or switched by the control signal CLK_S. Similarly, the two signal transmission channels of the MOSI signal, MISO signal, and CS signal can be controlled or switched by the control signals MOSI_S, MISO signal, and CS signal, respectively.

[0052] In one possible implementation, the driver chip is configured to control the multiplexer via registers.

[0053] In one possible implementation, the driver chip is configured to control the data selection circuit to connect the first input group or the second input group to the output group based on data read from the memory.

[0054] Continuing with the previous example, the data selection circuit 3202 is, for example... Figure 4The multiplexer MUX shown assumes that the current control signals CLK_S, MOSI_S, MISO_S, and CS_S are all set to 0. The data interface 3201 of the driver chip 320 reads the compensation data from the memory 3301 through the first signal transmission channel (including the first CLK signal transmission channel, the first MOSI signal transmission channel, the first MISO signal transmission channel, and the first CS signal transmission channel). The driver chip 320 determines whether the compensation data read from the memory 3301 is normal. For example, it can determine that the read compensation data is abnormal when it receives an all-0 or all-F signal according to the communication settings, thereby determining that the first signal transmission channel has been interrupted. The control signals CLK_S, MOSI_S, MISO_S, and CS_S are changed to all set to 1 to switch to the second signal transmission channel (including the second CLK signal transmission channel, the second MOSI signal transmission channel, the second MISO signal transmission channel, and the second CS signal transmission channel) to read the compensation data from the memory 3301. Conversely, assuming that the current control signals CLK_S, MOSI_S, MISO_S, and CS_S are all set to 1, if the driver chip 320 determines that the second signal transmission channel has been interrupted, it can change the control signals CLK_S, MOSI_S, MISO_S, and CS_S to all set to 0, so as to switch to the first signal transmission channel to read the compensation data in the memory 3301.

[0055] As can be seen, this method enables the display module to automatically switch signal transmission channels.

[0056] In one possible implementation, the driver chip is configured to control the data selection circuit to connect at least one first input terminal in the first input terminal group or at least one second input terminal in the second input terminal group to the output terminal group in response to an external instruction.

[0057] Continuing with the previous example, the data selection circuit 3202 is, for example... Figure 4 The multiplexer shown assumes that the current control signals CLK_S, MOSI_S, MISO_S, and CS_S are all set to 0. The driver chip 320's data interface 3201 reads compensation data from memory 3301 through the first signal transmission channels (including the first CLK signal transmission channel, the first MOSI signal transmission channel, the first MISO signal transmission channel, and the first CS signal transmission channel). If an abnormality in the display compensation is detected by an external detection device, or if a testing personnel or user discovers an abnormality in the display compensation, an external command can be sent to the driver chip 320 through the external detection device or human-machine interface device. This causes the driver chip 320 to respond to external commands by setting the control signals CLK_S, MOSI_S, MISO_S, and CS_S to all 1, thereby switching to the second signal transmission channel (including the second CLK signal transmission channel, the second MOSI signal transmission channel, the second MISO signal transmission channel, and the second CS signal transmission channel) to read the compensation data from the memory 3301; or This causes the driver chip 320 to respond to external commands by sequentially setting the control signals CLK_S, MOSI_S, MISO_S, and CS_S to 1, and waiting for the next external command after each change. If the display compensation error disappears after setting CLK_S to 1, it indicates that only the first CLK signal transmission channel is interrupted. Afterwards: you can continue switching the MOSI, MISO, and CS signal transmission channels, allowing the driver chip 320 to read the compensation data from memory 3301 through the second signal transmission channels (including the second CLK, second MOSI, second MISO, and second CS signal transmission channels); or you can choose not to continue switching the MOSI, MISO, and CS signal transmission channels, allowing the driver chip 320 to read the compensation data from memory 3301 through the second CLK, first MOSI, first MISO, and first CS signal transmission channels. If the display compensation abnormally disappears after setting MOSI_S to 1, it indicates that the first MOSI_S signal transmission channel is interrupted. Afterwards: you can continue switching the MISO and CS signal transmission channels, allowing the driver chip 320 to read the compensation data from memory 3301 through the second signal transmission channels (including the second CLK, second MOSI, second MISO, and second CS signal channels); or you can choose not to continue switching the MISO and CS signal transmission channels, allowing the driver chip 320 to read the compensation data from memory 3301 through the second CLK, second MOSI, first MISO, and first CS signal channels; or you can set CLK_S to 0 again to determine if the first CLK signal transmission channel is interrupted.

[0058] As can be seen, this method can partially switch and locate interrupted signal transmission channels, thereby further improving the robustness of signal transmission. The order in which the control signals are set to 1 is not limited to the above "CLK_S—MOSI_S—MISO_S—CS_S", but can also be set to other sequences such as "MOSI_S—CLK_S—CS_S—MISO_S".

[0059] Conversely, if the current control signals CLK_S, MOSI_S, MISO_S, and CS_S are all set to 1, and the driver chip 320 determines that the second signal transmission channel has been interrupted, it can change the control signals CLK_S, MOSI_S, MISO_S, and CS_S to all 0 to switch to the first signal transmission channel to read the compensation data in the memory 3301.

[0060] Another embodiment of this disclosure provides a driving method for a display module, applied to the display module provided in the above embodiments, the driving method including step S1 or step S2: Step S1 is as follows: The driver chip determines whether the data read from the memory is normal. If not, it controls the data selection circuit to switch one input terminal group currently connected to the output terminal group to another input terminal group. The one data terminal group is one of the first input terminal group and the second input terminal group, and the other input terminal group is the other of the first input terminal group and the second input terminal group.

[0061] Step S2 is as follows: In response to an external instruction, the driver chip controls the data selection circuit to connect at least one first input terminal in the first input terminal group or at least one second input terminal in the second input terminal group to the output terminal group.

[0062] In a specific example, for step S1, referring to the example of the above embodiment, the data selection circuit 3202 is, for example... Figure 4 The multiplexer MUX shown assumes that the current control signals CLK_S, MOSI_S, MISO_S, and CS_S are all set to 0. The data interface 3201 of the driver chip 320 reads the compensation data from the memory 3301 through the first signal transmission channel (including the first CLK signal transmission channel, the first MOSI signal transmission channel, the first MISO signal transmission channel, and the first CS signal transmission channel). The driver chip 320 determines whether the compensation data read from the memory 3301 is normal. For example, it can determine that the read compensation data is abnormal when it receives an all-0 or all-F signal according to the communication settings, thereby determining that the first signal transmission channel has been interrupted. The control signals CLK_S, MOSI_S, MISO_S, and CS_S are changed to all set to 1 to switch to the second signal transmission channel (including the second CLK signal transmission channel, the second MOSI signal transmission channel, the second MISO signal transmission channel, and the second CS signal transmission channel) to read the compensation data from the memory 3301.

[0063] In a specific example, for step S2, referring to the example of the above embodiment, the data selection circuit 3202 is, for example... Figure 4The multiplexer shown assumes that the current control signals CLK_S, MOSI_S, MISO_S, and CS_S are all set to 0. The driver chip 320's data interface 3201 reads compensation data from memory 3301 through the first signal transmission channels (including the first CLK signal transmission channel, the first MOSI signal transmission channel, the first MISO signal transmission channel, and the first CS signal transmission channel). If an abnormality in the display compensation is detected by an external detection device, or if a testing personnel or user discovers an abnormality in the display compensation, an external command can be sent to the driver chip 320 through the external detection device or human-machine interface device. This causes the driver chip 320 to respond to external commands by setting the control signals CLK_S, MOSI_S, MISO_S, and CS_S to all 1, thereby switching to the second signal transmission channel (including the second CLK signal transmission channel, the second MOSI signal transmission channel, the second MISO signal transmission channel, and the second CS signal transmission channel) to read the compensation data from the memory 3301; or This causes the driver chip 320 to respond to external commands by sequentially setting the control signals CLK_S, MOSI_S, MISO_S, and CS_S to 1, and waiting for the next external command after each change.

[0064] It should be noted that the driving method provided in this embodiment is similar to the driving principle and workflow of the display module provided in the above embodiments. The relevant parts can be referred to the above description, and will not be repeated here.

[0065] Another embodiment of this disclosure provides a display device including the above-described display module. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator; this embodiment does not limit the scope of the application.

[0066] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.

Claims

1. A display module, characterized in that, The device includes a display panel, a driver chip, and a flexible circuit board. The flexible circuit board has a memory. The driver chip includes a first bonding area, which includes a first bonding pin group and a second bonding pin group that are electrically connected to the data interface of the driver chip. The first bonding pin group and the second bonding pin group are spaced apart in a first direction, which is the arrangement direction of the bonding pins in the first bonding area. The flexible circuit board includes a third bonding pin group and a fourth bonding pin group that are electrically connected to the memory. The first bonding pin group and the third bonding pin group are electrically connected to the display panel by bonding, and the second bonding pin group and the fourth bonding pin group are electrically connected to the display panel by bonding.

2. The display module according to claim 1, characterized in that, The number of bonded pins between the first bonded pin group and the second bonded pin group is greater than or equal to 10.

3. The display module according to claim 1 or 2, characterized in that, The number of bonded pins between the first bonded pin group and the second bonded pin group is less than or equal to 100.

4. The display module according to claim 1, characterized in that, The first and second bonded pin groups are equidistant from the data interface in the first direction.

5. The display module according to claim 1, characterized in that, The driver chip includes a data selection circuit. The first binding pin group is electrically connected to the first input terminal group of the data selection circuit, the second binding pin group is electrically connected to the second input terminal group of the data selection circuit, and the output terminal group of the data selection circuit is electrically connected to the data interface of the driver chip.

6. The display module according to claim 5, characterized in that, The driver chip is configured to control the data selection circuit to connect the first input group or the second input group to the output group based on data read from the memory.

7. The display module according to claim 5, characterized in that, The driver chip is configured to control the data selection circuit in response to an external command to connect at least one first input terminal in the first input terminal group or at least one second input terminal in the second input terminal group to the output terminal group.

8. The display module according to claim 5, characterized in that, The data selection circuit is a multiplexer.

9. A display device, characterized in that, The display module includes any one of claims 1-8.

10. A driving method for a display module as described in any one of claims 1-8, characterized in that, include: The driver chip determines whether the data read from the memory is normal. If not, it controls the data selection circuit to switch one input terminal group currently connected to the output terminal group to another input terminal group. The one data terminal group is one of the first input terminal group and the second input terminal group, and the other input terminal group is the other of the first input terminal group and the second input terminal group. or In response to an external command, the driver chip controls the data selection circuit to connect at least one first input terminal in the first input terminal group or at least one second input terminal in the second input terminal group to the output terminal group.

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