Ion trap chip for stabilizing a large-scale two-dimensional ion crystal and method for manufacturing the same

Abstract

The application discloses an ion trap chip for stably confining a large-scale two-dimensional ion crystal and a manufacturing method thereof. The ion trap chip comprises a substrate, a trench and an ion confinement channel penetrating through the substrate in a thickness direction are arranged on the substrate, and a metalized plating layer. The trench separates the metalized plating layer into a radio frequency electrode and a plurality of direct current electrodes. A cross section of the trench perpendicular to a length direction of the trench comprises a longitudinal deep portion, a horizontal portion and two back bending portions. The longitudinal deep portion extends from an opening of the trench along the thickness direction of the substrate. The horizontal portion extends from the longitudinal deep portion to both sides of the longitudinal deep portion along a horizontal direction. The back bending portions extend from the horizontal portion to a surface where the opening of the trench is located and are spaced apart from the surface. The two back bending portions are respectively located on both sides of the longitudinal deep portion. The ion trap chip for stably confining a large-scale two-dimensional ion crystal according to the embodiment of the application can stably capture and operate the two-dimensional ion crystal, and has the advantages of a large ion confinement scale, high stability, small noise and high voltage resistance.

Description

Technical Field

[0001] This invention relates to the field of ion trap chip manufacturing technology, and more specifically, to an ion trap chip for stably trapping large-scale two-dimensional ion crystals and its manufacturing method. Background Technology

[0002] Ion trap technology is a method that uses an electric field to capture, store, and manipulate ions. It has wide applications in fields such as quantum computing, precision measurement, and atomic physics.

[0003] Current ion trap quantum computing and quantum simulation schemes focus on one-dimensional ion chain crystals and movable linear ion arrays, lacking research on two-dimensional planar ion crystals. Furthermore, one-dimensional ion chains, occupying the same volume, cannot expand the number of ions as effectively as two-dimensional planar ion crystals. While some ion trap structures in these technologies can trap two-dimensional ion crystals at room temperature, their stability is insufficient; increasing the ion size immediately affects the lifetime of individual ions. Although placing them in cold traps can trap larger numbers of ions, the temperature changes and vibrations introduced by the cold traps themselves also affect the stability of the ion crystal, limiting the development of quantum computing and quantum simulation on ion crystals.

[0004] Some ion trap chips in related technologies utilize laser ablation technology to first deposit a metal film on an alumina substrate and then ablate the electrode structure. This can be used to trap and manipulate small-scale planar two-dimensional ion crystals. However, the flatness after ablation is poor and residues are easily left behind, which reduces the withstand voltage of the ion trap chip and makes it prone to breakdown. Moreover, after ablation, the insulating dielectric is exposed, and ions can easily approach the non-conductive surface, resulting in uneven electric field and electrostatic charge noise. Summary of the Invention

[0005] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes an ion trap chip for stably trapping large-scale two-dimensional ion crystals. This ion trap chip can stably capture and manipulate two-dimensional ion crystals, and has the advantages of large ion trapping scale, high stability, low noise, and high voltage tolerance.

[0006] The present invention also proposes a method for manufacturing an ion trap chip for stably trapping large-scale two-dimensional ion crystals.

[0007] To achieve the above objective, according to an embodiment of the first aspect of the present invention, an ion trap chip for stably trapping a large-scale two-dimensional ion crystal is provided. The ion trap chip for stably trapping a large-scale two-dimensional ion crystal includes: a substrate, wherein the substrate has trenches and ion trapping channels extending through the substrate along the thickness direction; a metallization coating, wherein the metallization coating is disposed on the surface of the substrate, the trenches separating the metallization coating into radio frequency electrodes and a plurality of DC electrodes, the radio frequency electrodes being located on the inner circumferential surface of the ion trapping channel, the plurality of DC electrodes being respectively disposed on both sides of the width direction of the ion trapping channel, the trenches having a cross-section perpendicular to the length direction of the trenches including a depth portion, a horizontal portion and two curved portions, the depth portion extending from the opening of the trenches along the thickness direction of the substrate, the horizontal portion extending from the depth portion along the horizontal direction to both sides of the depth portion, the curved portions extending from the horizontal portion to the surface where the opening of the trenches is located and spaced apart from the surface, and the two curved portions being respectively located on both sides of the depth portion.

[0008] The ion trap chip for stably trapping large-scale two-dimensional ion crystals according to embodiments of the present invention can stably capture and manipulate two-dimensional ion crystals, and has the advantages of large ion trapping scale, high stability, low noise, and high voltage tolerance.

[0009] In addition, the ion trap chip for stably trapping large-scale two-dimensional ion crystals according to the above embodiments of the present invention may also have the following additional technical features:

[0010] According to one embodiment of the present invention, the substrate has a front side and a back side in the thickness direction, the trench includes a front side trench and a back side trench, the front side trench and the back side trench are spaced apart in the thickness direction of the substrate, the front side trench is located on the front side of the substrate and separates the metallized plating on the front side of the substrate into a front RF electrode and a plurality of front DC electrodes, the back side trench is located on the back side of the substrate and separates the metallized plating on the back side of the substrate into a back RF electrode and a plurality of back DC electrodes, the front RF electrode and the back RF electrode are connected at the ion trapping channel.

[0011] According to one embodiment of the present invention, the front trench also separates the metallized plating on the front side of the substrate into a reverse electrode connection portion, and the reverse electrode connection portion is electrically connected to the reverse DC electrode through a tapered hole provided on the substrate.

[0012] According to one embodiment of the present invention, the front trench further separates the metallized coating on the front side of the substrate into a front ground electrode, and the back trench further separates the metallized coating on the back side of the substrate into a back ground electrode. The front ground electrode and the back ground electrode are electrically connected through a tapered hole provided on the substrate and the edge of the substrate.

[0013] According to one embodiment of the present invention, the front trench further separates the metallized coating on the front side of the substrate into a radio frequency (RF) wiring area, which is electrically connected to the front RF electrode. The back trench further separates the metallized coating on the back side of the substrate into a measurement wiring area, which is electrically connected to the back RF electrode.

[0014] According to one embodiment of the present invention, the width of the depth gradually decreases from the end near the opening to the end away from the opening.

[0015] According to one embodiment of the present invention, the width of the ion trapping channel gradually increases from the middle to both ends in the thickness direction of the substrate.

[0016] According to one embodiment of the present invention, the substrate is a fused silica material, and the metallization coating includes a chromium substrate layer and a gold film layer.

[0017] According to one embodiment of the present invention, the substrate is provided with positioning through holes.

[0018] According to an embodiment of the second aspect of the present invention, a method for manufacturing an ion trap chip for stably trapping a large-scale two-dimensional ion crystal according to an embodiment of the first aspect of the present invention is provided, comprising the following steps:

[0019] Provide substrate raw materials;

[0020] The trenches are selectively etched into the substrate material using a laser to obtain the substrate.

[0021] The metallization coating is deposited on the substrate by vacuum evaporation or magnetron sputtering.

[0022] The method for manufacturing an ion trap chip for stably trapping a large-scale two-dimensional ion crystal according to an embodiment of the present invention has advantages such as good electrode independence, large ion trapping scale, high stability, low noise, and high voltage withstand capability by utilizing the ion trap chip for stably trapping a large-scale two-dimensional ion crystal according to the first aspect of the present invention.

[0023] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0024] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0025] Figure 1This is a front structural schematic diagram of an ion trap chip for stably trapping large-scale two-dimensional ion crystals according to an embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of the reverse side of an ion trap chip for stably trapping large-scale two-dimensional ion crystals according to an embodiment of the present invention.

[0027] Figure 3 This is a partial cross-sectional view of an ion trap chip for stably trapping large-scale two-dimensional ion crystals according to an embodiment of the present invention.

[0028] Figure 4 This is a partial cross-sectional view of an ion trap chip for stably trapping large-scale two-dimensional ion crystals according to an embodiment of the present invention.

[0029] Figure 5 This is a partial cross-sectional view of an ion trap chip for stably trapping large-scale two-dimensional ion crystals according to an embodiment of the present invention.

[0030] Figure 6 This is a schematic diagram of the process for manufacturing an ion trap chip for stably trapping a large-scale two-dimensional ion crystal according to an embodiment of the present invention.

[0031] Figure 7 This is a flowchart of a method for manufacturing an ion trap chip for stably trapping a large-scale two-dimensional ion crystal according to an embodiment of the present invention.

[0032] Reference numerals: Ion trap chip for stable trapping of large-scale two-dimensional ion crystals 1, trench 10, depth portion 11, horizontal portion 12, convex portion 13, front trench 14, reverse trench 15, ion trapping through-slot 20, radio frequency electrode 30, front radio frequency electrode 31, reverse radio frequency electrode 32, DC electrode 40, front DC electrode 41, reverse DC electrode 42, reverse electrode wiring portion 50, conical hole 60, front ground electrode 71, reverse ground electrode 72, radio frequency wiring area 81, measurement wiring area 82, positioning through-hole 90. Detailed Implementation

[0033] This application is based on the findings and understanding of the following facts and issues:

[0034] Ion trap technology is a method that uses an electric field to capture, store, and manipulate ions. It has wide applications in fields such as quantum computing, precision measurement, and atomic physics.

[0035] Current ion trap quantum computing and quantum simulation schemes focus on one-dimensional ion chain crystals and movable linear ion arrays, lacking research on two-dimensional planar ion crystals. Furthermore, one-dimensional ion chains, occupying the same volume, cannot expand the number of ions as effectively as two-dimensional planar ion crystals. While some ion trap structures in these technologies can trap two-dimensional ion crystals at room temperature, their stability is insufficient; increasing the ion size immediately affects the lifetime of individual ions. Although placing them in cold traps can trap larger numbers of ions, the temperature changes and vibrations introduced by the cold traps themselves also affect the stability of the ion crystal, limiting the development of quantum computing and quantum simulation on ion crystals.

[0036] Some ion trap chips in related technologies utilize laser ablation technology to first deposit a metal film on an alumina substrate and then ablate the electrode structure. This can be used to trap and manipulate small-scale planar two-dimensional ion crystals. However, the flatness after ablation is poor and residues are easily left behind, which reduces the withstand voltage of the ion trap chip and makes it prone to breakdown. Moreover, after ablation, the insulating dielectric is exposed, and ions can easily approach the non-conductive surface, resulting in uneven electric field and electrostatic charge noise.

[0037] Specifically, in some ion trap chips in related technologies, if the trenches are first ablated and then coated, the coating will penetrate deep into the trenches, causing short circuits between electrodes and affecting the independence of the electrodes.

[0038] In addition, there are various other ion trap structures in related technologies, such as blade traps and quadrupole ion traps, which require assembly and face the problem of low assembly precision, thus limiting the application capabilities of ion trap technology.

[0039] Silicon ion trap chips based on semiconductor micro-nano fabrication technology face several challenges, including severe microwave absorption loss by semiconductor materials such as silicon, leading to chip heating; a small bandgap that makes it difficult for visible light to propagate, limiting the chip's light transmittance; and the difficulty for narrow-bandgap semiconductors to withstand high voltages, with ion trapping stability affected by stray electric fields. These issues result in numerous limitations in practical applications.

[0040] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0041] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, features defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0042] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0043] The following description, with reference to the accompanying drawings, describes an ion trap chip 1 for stably trapping large-scale two-dimensional ion crystals according to an embodiment of the present invention.

[0044] like Figures 1-7 As shown, the ion trap chip 1 for stably trapping large-scale two-dimensional ion crystals according to an embodiment of the present invention includes a substrate and a metallized coating.

[0045] The substrate has a trench 10 and an ion trapping channel 20 extending through the substrate along its thickness direction. The metallization coating is disposed on the surface of the substrate. The trench 10 separates the metallization coating into a radio frequency electrode 30 and a plurality of DC electrodes 40. The radio frequency electrode 30 is located on the inner circumferential surface of the ion trapping channel 20, and the plurality of DC electrodes 40 are respectively disposed on both sides of the ion trapping channel 20 in the width direction.

[0046] The trench 10 has a cross section perpendicular to its length direction, including a depth portion 11, a horizontal portion 12, and two curved portions 13. The depth portion 11 extends from the opening of the trench 10 along the thickness direction of the substrate. The horizontal portion 12 extends from the depth portion 11 in a horizontal direction to both sides of the depth portion 11. The curved portions 13 extend from the horizontal portion 12 to the surface where the opening of the trench 10 is located and are spaced apart from that surface. The two curved portions 13 are located on both sides of the depth portion 11.

[0047] It is important to understand here that "the section of the trench 10 perpendicular to the length of the trench 10" refers to the horizontal extension direction, and the trench 10 can be regarded as being formed by extending this section horizontally.

[0048] The trench 10 is a blind trench, in other words, the trench 10 does not penetrate the substrate along the thickness direction.

[0049] Specifically, the substrate is an insulating material, and the metallized plating layer is a conductive material.

[0050] Multiple DC electrodes 40 on each side of the ion trapping channel 20 in the width direction can be spaced apart along the length direction of the ion trapping channel 20.

[0051] The depth portion 11, the horizontal portion 12, and the back portion 13 can have a certain width to ensure sufficient distance between electrodes and a sufficiently high breakdown voltage, and to prevent short circuits caused by metal accumulation peaks during metallization coating at the bottom of the trench 10.

[0052] The trench 10 may include, for example Figure 3 The DC-DC trenches shown are spaced apart by two DC electrodes 40 and are as follows: Figure 4 The RF-DC trench shown is for the spaced RF electrode 30 and DC electrode 40. Both the DC-DC trench and the RF-DC trench include a depth 11, a horizontal portion 12 and a convex portion 13, but their specific dimensions and shapes may differ.

[0053] For example, the RF-DC trench needs to be spaced at a sufficient distance from the circumference of the ion trapping channel 20 to ensure structural strength. The size of the RF-DC trench can be smaller than that of the DC-DC trench while ensuring insulation to accommodate the small space around the ion trapping channel 20. The opening and the backrest 13 of the RF-DC trench can be set at an angle to adapt to the shape of the ion trapping channel 20.

[0054] According to an embodiment of the present invention, an ion trap chip 1 for stably trapping large-scale two-dimensional ion crystals is provided. By setting an ion trapping channel 20, an RF electrode 30 is located on the inner circumferential surface of the ion trapping channel 20, and multiple DC electrodes 40 are spaced apart outside the RF electrode 30. Compared with the ion trap structure in the related art that can only target one-dimensional ion chains, the RF electrode 30 and DC electrodes 40 can apply an electric field to the ion trapping channel 20, and use the electric field to capture, store and manipulate ions in the ion trapping channel 20. The DC electrodes 40 on both sides of the ion trapping channel 20 can synchronously increase the voltage so that the ion crystal is in a two-dimensional plane parallel to the plane of the ion trap chip 1, and eliminate micro-vibrations perpendicular to the plane direction. This can be used to stably form two-dimensional ion crystals, improve the fidelity of quantum operations, and eliminate the need for a cold trap, thus avoiding the influence of temperature changes on the stability of the ion crystal. It has been verified that the two-dimensional ion crystal that can be stably trapped at room temperature is an order of magnitude larger than that of the ion trap chips in the related art.

[0055] Furthermore, by including a depth portion 11, a horizontal portion 12, and a curved portion 13 in the trench 10, during the metallization process of the substrate, after metal atoms enter the depth portion 11, they are less likely to further enter the horizontal portion 12 and the curved portion 13. Even if metal atoms enter the horizontal portion 12 and the curved portion 13, they will not form a continuous metal layer, thereby avoiding short circuits between adjacent electrodes and ensuring the independence of adjacent electrodes. Therefore, trenches 10 can be formed on the substrate first, and then metallization coating can be performed on the substrate with trenches 10 to form the metallization coating. This can also achieve isolation between electrodes and maintain the independence of the electrodes. Compared with the method of metallization followed by ablation in related technologies, on the one hand, since the formation of trenches 10 only needs to act on the substrate material and not on the metal material, there is no need to use an ablation process. Trenches 10 can be formed in a gentler way, such as laser selective etching. This can not only effectively improve the surface flatness of the processed surface to reduce the electric field non-uniformity noise induced by the tip, but also avoid ablation residue to improve the withstand voltage of the chip well and prevent breakdown. On the other hand, by etching before metallization, the surface of the insulating dielectric on the substrate can be effectively avoided, ensuring that the surface near the captured ions is a conductor and reducing the electrostatic charge noise excited by ultraviolet laser.

[0056] Therefore, the ion trap chip 1 for stably trapping large-scale two-dimensional ion crystals according to the embodiments of the present invention can stably capture and operate two-dimensional ion crystals, and has the advantages of large ion trapping scale, high stability, low noise, and high voltage tolerance.

[0057] The following description, with reference to the accompanying drawings, describes an ion trap chip 1 for stably trapping large-scale two-dimensional ion crystals according to a specific embodiment of the present invention.

[0058] In some specific embodiments of the present invention, such as Figures 1-7 As shown, the ion trap chip 1 for stably trapping large-scale two-dimensional ion crystals according to an embodiment of the present invention includes a substrate and a metallized coating.

[0059] Specifically, such as Figure 1 and Figure 2 As shown, the substrate has a front side and a back side in the thickness direction. The trench 10 includes a front trench 14 and a back trench 15, which are spaced apart in the thickness direction of the substrate. The front trench 14 is located on the front side of the substrate and separates the metallized plating on the front side of the substrate into a front radio frequency electrode 31 and a plurality of front DC electrodes 41. The back trench 15 is located on the back side of the substrate and separates the metallized plating on the back side of the substrate into a back radio frequency electrode 32 and a plurality of back DC electrodes 42. The front radio frequency electrode 31 and the back radio frequency electrode 32 are connected at the ion trapping channel 20. This facilitates the formation of radio frequency electrodes 30 around the ion trapping channel 20 and the formation of a plurality of DC electrodes 40 on both sides of the ion trapping channel 20. It also facilitates the application of voltage through the DC electrodes 40 on both sides of the ion trapping channel 20 to trap the ion crystal within the ion trapping channel 20, thus facilitating the trapping and manipulation of the two-dimensional ion crystal.

[0060] Advantageously, such as Figure 1 , Figure 2 and Figure 5 As shown, the front trench 14 also separates the metallized plating on the front side of the substrate into a reverse electrode connection portion 50. The reverse electrode connection portion 50 is electrically connected to the reverse DC electrode 42 through a tapered hole 60 provided on the substrate. Specifically, the tapered hole 60 penetrates the substrate so that the metallized plating on both sides of the substrate can be connected to achieve a low-resistance connection between the electrodes on both sides. In this way, the electrical connection with the reverse DC electrode 42 can be achieved by wiring at the reverse electrode connection portion 50, so that both the front DC electrode 41 and the reverse DC electrode 42 can be wired only on the front side of the substrate, which facilitates the implementation of single-sided wiring in the ion trap chip 1.

[0061] More specifically, such as Figure 1 , Figure 2 and Figure 5 As shown, the front trench 14 further separates the metallized coating on the front side of the substrate to form a front ground electrode 71, and the back trench 15 further separates the metallized coating on the back side of the substrate to form a back ground electrode 72. The front ground electrode 71 and the back ground electrode 72 are electrically connected through a tapered hole 60 provided on the substrate and the edge of the substrate. Specifically, the front ground electrode 71 and the back ground electrode 72 are located outside the RF electrode 30 and the DC electrode 40. This facilitates the grounding of the ion trap chip 1, and the electrical connection between the front and back sides reduces ground loops.

[0062] Furthermore, such as Figure 1 and Figure 2 As shown, the front trench 14 further separates the metallized coating on the front side of the substrate into an RF wiring area 81, which is electrically connected to the front RF electrode 31. The back trench 15 further separates the metallized coating on the back side of the substrate into a measurement wiring area 82, which is electrically connected to the back RF electrode 32. The RF wiring area 81 facilitates the wiring of the RF electrode 30, and the measurement wiring area 82 can be used for probe contact during testing of the ion trap chip 1.

[0063] Figures 1-4 An ion trap chip 1 for stably trapping a large-scale two-dimensional ion crystal is shown according to some examples of the present invention. Figure 3 As shown, the width of the depth portion 11 gradually decreases from the end near the opening to the end away from the opening. This facilitates the adhesion of the metallization coating to the depth portion 11, thus preventing the insulation material of the substrate from being exposed, and further makes it difficult for metal atoms to enter the horizontal portion 12 and the curved portion 13.

[0064] Advantageously, such as Figure 4 As shown, the width of the ion trapping channel 20 gradually increases from the middle to both ends in the thickness direction of the substrate. This facilitates the adhesion of the metallization plating layer within the ion trapping channel 20, facilitates the formation of the radio frequency electrode 30, avoids exposure of the insulating material, and helps reduce noise.

[0065] Optionally, the substrate is made of fused silica. This gives the substrate good structural strength, processability, and a low coefficient of thermal expansion, as well as some light transmittance to facilitate integration with optical waveguides. The metallized coating includes a chromium substrate layer and a gold film layer. This helps ensure the adhesion, conductivity, and oxidation resistance of the metallized coating.

[0066] Specifically, the substrate is provided with positioning through holes 90. Specifically, the positioning through holes 90 are adapted to accommodate insulating gaskets and screws. This facilitates the installation and positioning of the ion trap chip 1.

[0067] The following is for reference. Figure 6 and Figure 7 A method for manufacturing an ion trap chip 1 for stably trapping a large-scale two-dimensional ion crystal according to an embodiment of the present invention is described, comprising the following steps:

[0068] Provide substrate raw materials;

[0069] The substrate is obtained by selectively etching trenches 10 on the substrate material using a laser, as shown below. Figure 6 As shown in (a);

[0070] The metallization layer is deposited on the substrate by vacuum evaporation or magnetron sputtering, such as... Figure 6 As shown in (b).

[0071] The method for manufacturing an ion trap chip 1 for stable trapping of large-scale two-dimensional ion crystals according to an embodiment of the present invention, by utilizing the ion trap chip 1 for stable trapping of large-scale two-dimensional ion crystals according to the above embodiment of the present invention, can process trenches before metallization while ensuring electrode independence, thereby avoiding problems such as reduced withstand voltage and high noise caused by metallization followed by ablation. This results in an ion trap chip with advantages such as good electrode independence, large ion trapping scale, high stability, low noise, and high withstand voltage.

[0072] Other components and operations of the ion trap chip 1 for stably trapping large-scale two-dimensional ion crystals according to embodiments of the present invention and its manufacturing method are known to those skilled in the art and will not be described in detail here.

[0073] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0074] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. An ion trap chip for stably trapping large-scale two-dimensional ion crystals, characterized in that, include: A substrate having trenches and ion trapping channels penetrating the substrate along its thickness direction; A metallized coating is disposed on the surface of the substrate. The trench separates the metallized coating into radio frequency electrodes and multiple DC electrodes. The radio frequency electrodes are located on the inner circumferential surface of the ion trapping channel. The multiple DC electrodes are respectively disposed on both sides of the width direction of the ion trapping channel. The trench has a cross-section perpendicular to the length direction of the trench, including a depth portion, a horizontal portion, and two curved portions. The depth portion extends from the opening of the trench along the thickness direction of the substrate. The horizontal portion extends from the depth portion in a horizontal direction to both sides of the depth portion. The curved portions extend from the horizontal portion to the surface where the opening of the trench is located and are spaced apart from the surface. The two curved portions are respectively located on both sides of the depth portion.

2. The ion trap chip for stably trapping large-scale two-dimensional ion crystals according to claim 1, characterized in that, The substrate has a front side and a back side in the thickness direction. The trench includes a front side trench and a back side trench. The front side trench and the back side trench are spaced apart in the thickness direction of the substrate. The front side trench is located on the front side of the substrate and separates the metallized plating on the front side of the substrate into a front RF electrode and a plurality of front DC electrodes. The back side trench is located on the back side of the substrate and separates the metallized plating on the back side of the substrate into a back RF electrode and a plurality of back DC electrodes. The front RF electrode and the back RF electrode are connected at the ion trapping channel.

3. The ion trap chip for stably trapping large-scale two-dimensional ion crystals according to claim 2, characterized in that, The front trench also separates the metallized plating on the front side of the substrate into a reverse electrode connection portion, which is electrically connected to the reverse DC electrode through a tapered hole provided on the substrate.

4. The ion trap chip for stably trapping large-scale two-dimensional ion crystals according to claim 2, characterized in that, The front trench also separates the metallized film on the front side of the substrate into a front ground electrode, and the back trench also separates the metallized film on the back side of the substrate into a back ground electrode. The front ground electrode and the back ground electrode are electrically connected through a tapered hole provided on the substrate and the edge of the substrate.

5. The ion trap chip for stably trapping large-scale two-dimensional ion crystals according to claim 2, characterized in that, The front trench also separates the metallized coating on the front side of the substrate into an RF wiring area, which is electrically connected to the front RF electrode. The back trench also separates the metallized coating on the back side of the substrate into a measurement wiring area, which is electrically connected to the back RF electrode.

6. The ion trap chip for stably trapping large-scale two-dimensional ion crystals according to claim 1, characterized in that, The width of the depth portion gradually decreases from the end closest to the opening to the end furthest from the opening.

7. The ion trap chip for stably trapping large-scale two-dimensional ion crystals according to claim 1, characterized in that, The width of the ion trapping channel gradually increases from the middle to both ends in the thickness direction of the substrate.

8. The ion trap chip for stably trapping large-scale two-dimensional ion crystals according to claim 1, characterized in that, The substrate is made of fused silica material, and the metallized coating includes a chromium substrate layer and a gold film layer.

9. The ion trap chip for stably trapping large-scale two-dimensional ion crystals according to claim 1, characterized in that, The substrate is provided with positioning through holes.

10. A method for manufacturing an ion trap chip for stably trapping large-scale two-dimensional ion crystals according to any one of claims 1-9, characterized in that, Includes the following steps: Provide substrate raw materials; The trenches are selectively etched into the substrate material using a laser to obtain the substrate. The metallization coating is deposited on the substrate by vacuum evaporation or magnetron sputtering.

Images