Data encryption device and memory encryption and decryption system, chip

Abstract

The application relates to the technical field of data encryption, and discloses a data encryption device, a memory encryption and decryption system and a chip. The device comprises an address input end, a password root output end, a key generation circuit for generating a first key and a second key with n bits, and a data encryption logic circuit comprising a four-round encryption module. Four-round encryption units in the four-round encryption module comprise an interleaver with n bits, four 64-bit round function components arranged on both sides of the interleaver, and two sub-circuits for encrypting residual data and residual keys. The data encryption logic circuit is connected with the address input end, the password root output end and the key generation circuit, is used for performing alignment processing on a memory access address, and performs interleaving encryption processing on the n-bit aligned address, the first key and the second key obtained through the alignment processing on the basis of the four-round encryption module to generate a password root with n bits. The encryption device is used for encrypting write data on the basis of the password root, and the decryption device is used for decrypting read data on the basis of the password root.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data encryption, and in particular to a data encryption device, a memory encryption and decryption system, and a chip. BACKGROUND

[0002] A block cipher algorithm is a symmetric cipher algorithm that divides plaintext data into groups according to a fixed length (referred to as a “block length”) and independently encrypts or decrypts each group of data. It is often used for encryption and decryption operations on memory data, but such operations usually have two limitations: 1. Commonly used block cipher algorithms have too long encryption and decryption times for data, which seriously affects the data throughput rate of the memory; and 2. Commonly used block cipher algorithms are encrypted and decrypted in data bit widths of 64 bits, 128 bits, 256 bits, etc., and cannot match flexible memory bit widths. SUMMARY

[0003] The present application aims to at least partially solve one of the technical problems in the related art. To this end, one object of the present application is to provide a data encryption device that has low encryption and decryption latency and supports flexible memory encryption characteristics.

[0004] A second object of the present application is to provide a memory encryption and decryption system.

[0005] A third object of the present application is to provide a chip.

[0006] To achieve the above objects, a data encryption device according to an embodiment of the first aspect of the present application is provided for a memory, the data bit width of the memory being n and the address bit width of the memory being m, n and m being integers, and the data encryption device comprising: an address input terminal connected to an address terminal of the memory, for receiving an access address transmitted to the address terminal of the memory; a cipher root output terminal connected to an encryption device of a write data terminal of the memory and a decryption device of a read data terminal of the memory, respectively, for outputting an n-bit cipher root; a key generation circuit for generating an n-bit first key and an n-bit second key; and a data encryption logic circuit comprising a four-round encryption module, wherein a four-round encryption unit in the four-round encryption module comprises an n-bit interleaver and four 64-bit round function components and two sub-circuits for encrypting remaining data and remaining keys, which are arranged on both sides of the interleaver, and the data encryption logic circuit is connected to the address input terminal, the cipher root output terminal, and the key generation circuit, for performing alignment processing on the access address, performing interleaving encryption processing on the n-bit aligned address obtained by the alignment processing, the first key, and the second key based on the four-round encryption module, and generating the n-bit cipher root, so that the encryption device encrypts write data based on the cipher root and the decryption device decrypts read data based on the cipher root.

[0007] The data encryption device according to the embodiment of the present application realizes low-latency encryption and decryption of data in a data stage by using a password root generated in advance, realizes flexible bit-width encryption and decryption capability by using four round encryption units in the four round encryption module to perform data bit interleaving, and thus completes high-speed flexible memory encryption and decryption operation, and guarantees the security of data storage. The data encryption device according to the embodiment of the present application has low encryption and decryption latency and supports flexible bit-width memory encryption characteristics.

[0008] In addition, the data encryption device according to the above embodiment of the present application can further have the following additional technical features.

[0009] According to one embodiment of the present application, the data encryption logic circuit further comprises: an address alignment sub-circuit, an input end of the address alignment sub-circuit being connected with the address input end, for performing alignment processing on the m-bit memory access address to obtain the n-bit aligned address; a first XOR sub-circuit, a first input end of the first XOR sub-circuit being connected with an output end of the address alignment sub-circuit, a second input end of the first XOR sub-circuit being connected with a first output end of the key generation circuit, for performing XOR operation on the aligned address and the first key to obtain a first XOR result, wherein a first input end of the four round encryption module is connected with an output end of the first XOR circuit, a second input end of the four round encryption module is connected with a second output end of the key generation circuit, the four round encryption module comprises k four round encryption units connected in series, for performing 4k times of encryption operation on the first XOR result and the second key to obtain a target encryption result, wherein k>=1, k is an integer; a key conversion sub-circuit, an input end of the key conversion sub-circuit being connected with the first output end of the key generation circuit, for converting the first key; a second XOR sub-circuit, a first input end of the second XOR sub-circuit being connected with an output end of the four round encryption module, a second input end of the second XOR sub-circuit being connected with an output end of the key conversion sub-circuit, an output end of the second XOR circuit being connected with the password root output end, for performing XOR operation on the target encryption result and the converted first key to obtain the password root.

[0010] According to one embodiment of the present application, four 64-bit round function components corresponding to the interleaver on both sides are arranged, which are a first column of 64-bit round function components, a second column of 64-bit round function components, a third column of 64-bit round function components and a fourth column of 64-bit round function components, two sub-circuits for encrypting the remaining data and the remaining key corresponding to the interleaver on both sides, which are a third XOR sub-circuit and a fourth XOR sub-circuit, wherein the first input end of the first column of 64-bit round function components is connected to the input end of the four-round encryption unit, the second input end of the first column of 64-bit round function components is connected to the second output end of the key generation circuit, and the 64-bit round function components in each row of the first column of 64-bit round function components are used to encrypt the 64-bit data in the corresponding group of the input data by using the 64-bit key in the corresponding group of the second key, to obtain a first encryption result; the first input end of the second column of 64-bit round function components is connected to the output end of the first column of 64-bit round function components, the second input end of the second column of 64-bit round function components is connected to the second output end of the key generation circuit, and the 64-bit round function components in each row of the second column of 64-bit round function components are used to encrypt the 64-bit data in the corresponding group of the first encryption result by using the 64-bit key in the corresponding group of the second key, to obtain a second encryption result; the first input end of the third XOR sub-circuit is connected to the input end of the four-round encryption unit, the second input end of the third XOR sub-circuit is connected to the second output end of the key generation circuit, and the third XOR sub-circuit is used to perform XOR operation on the remaining key in the second key and the remaining data in the input data, to obtain a third XOR result; the input end of the interleaver is connected to the output end of the second column of 64-bit round function components and the output end of the third XOR sub-circuit, respectively, and the interleaver is used to perform data bit interleaving arrangement on the second encryption result or the data composed of the second encryption result and the third XOR result, to obtain interleaved data; the first input end of the third column of 64-bit round function components is connected to the output end of the interleaver, the second input end of the third column of 64-bit round function components is connected to the second output end of the key generation circuit, and the 64-bit round function components in each row of the third column of 64-bit round function components are used to encrypt the 64-bit data in the corresponding group of the interleaved data by using the 64-bit key in the corresponding group of the second key, to obtain a third encryption result; the first input end of the fourth column of 64-bit round function components is connected to the output end of the third column of 64-bit round function components, the second input end of the fourth column of 64-bit round function components is connected to the second output end of the key generation circuit, the output end of the fourth column of 64-bit round function components is connected to the output end of the four-round encryption unit, and the 64-bit round function components in each row of the fourth column of 64-bit round function components are used to encrypt the 64-bit data in the corresponding group of the third encryption result by using the 64-bit key in the corresponding group of the second key, to obtain a fourth encryption result.The first input end of the fourth exclusive OR sub-circuit is connected with the output end of the interleaver, the second input end of the fourth exclusive OR sub-circuit is connected with the second output end of the key generation circuit, and the output end of the fourth exclusive OR sub-circuit is connected to the output end of the four-round encryption unit, for performing exclusive OR operation on the remaining data in the interleaved data and the remaining key in the second key to obtain a fourth exclusive OR result, wherein the four-time encryption result or the data composed of the four-time encryption result and the fourth exclusive OR result is the encryption result output by the four-round encryption unit.

[0011] According to an embodiment of the present application, the number of 64-bit round function components in each column is determined by the integer part of the quotient of the data bit width n of the memory divided by 64.

[0012] According to an embodiment of the present application, the interleaver is configured to fill the input data into a preset square matrix row by row in descending order, and mark a vacancy if there is a position in the preset square matrix after filling the data that has not been filled with data, wherein the number of rows r of the preset square matrix satisfies (r-1) 2 ≤ n≤ r 2 wherein r represents the number of rows of the preset square matrix, and n represents the data bit width of the memory; transpose the preset square matrix after filling the data, and take out the data row by row in ascending order, and discard the vacancy when the bit of the taken data is the vacancy.

[0013] According to an embodiment of the present application, the 64-bit round function component comprises an S-box transformation layer, a linear transformation M layer, a constant addition operation layer and a key addition operation layer connected in sequence.

[0014] According to an embodiment of the present application, when n>m, the address alignment sub-circuit repeatedly expands the memory access address of m bits, and takes the low n bits after the bit width of the expanded memory access address is greater than or equal to n.

[0015] According to an embodiment of the present application, the key conversion sub-circuit comprises a shift layer and / or an S-box transformation layer.

[0016] To achieve the above object, the second aspect of the present application provides a memory encryption and decryption system, comprising: a memory, the data bit width of the memory is n, the address bit width of the memory is m, n and m are integers; an encryption device connected with the write data end of the memory; a decryption device connected with the read data end of the memory; the data encryption device provided by the first aspect of the present application is connected with the address end of the memory, the encryption device and the decryption device respectively, and is used for performing alignment processing on the memory access address transmitted to the address end of the memory, performing interleaving encryption processing on the n-bit aligned address obtained through the alignment processing, the first key and the second key, and generating the n-bit password root, so that the encryption device encrypts the write data according to the password root, and the decryption device decrypts the read data according to the password root.

[0017] To achieve the above object, the third aspect of the present application provides a chip, comprising the memory encryption and decryption system provided by the second aspect of the present application.

[0018] Additional aspects and advantages of the present application will be made apparent by the following description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a schematic diagram of the data encryption device of one embodiment of the present application;

[0020] Figure 2 is a schematic diagram of the data encryption device of one specific embodiment of the present application;

[0021] Figure 3 is a schematic diagram of the four-round encryption unit of one embodiment of the present application;

[0022] Figure 4 is a schematic diagram of the 64-bit round function component of one embodiment of the present application;

[0023] Figure 5 is a schematic diagram of the memory encryption and decryption system of one embodiment of the present application;

[0024] Figure 6 is a schematic diagram of the chip of one embodiment of the present application. DETAILED DESCRIPTION

[0025] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are intended to explain the present application, and cannot be understood as a limitation of the present application.

[0026] In a general MCU (Micro Controller Unit) or ASIC (Application-Specific Integrated Circuit) chip system, SRAM (Static Random-Access Memory), Flash, OTP (One-Time Programmable Memory) and other memories are important components that store important information such as software code, system running data, private data, etc. for short or long term, and the security of their data is closely related to the security of the system and the safety of the user's property.

[0027] Memory encryption is an important data security measure that uses encryption technology to encrypt data written to memory and manages keys to ensure that only authorized users can correctly decrypt and obtain the original data when reading the memory. This management usually involves the use of advanced encryption algorithms and key management strategies to effectively prevent data from being accessed, tampered with, or leaked by unauthorized personnel or systems. Compared with SRAM and other volatile memories, Flash, OTP and other non-volatile memories are more vulnerable to attacks because, in general, even if the chip is powered off, most non-volatile memories can save the stored data for more than 10 years, and attackers can easily scan all stored content and extract valuable information.

[0028] To solve the problem of long encryption and decryption time of block cipher algorithms and the inability to match flexible and diverse memory bit widths, embodiments of the present application provide a data encryption device and a memory encryption and decryption system and chip. The data encryption device and memory encryption and decryption system of the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0029] The data encryption device of the embodiments of the present application is used for a memory, the data bit width of the memory is n, the address bit width of the memory is m, and n and m are integers. Figure 1 is a schematic diagram of the data encryption device of an embodiment of the present application. As shown in Figure 1 , the data encryption device can include:

[0030] The address input end is connected with the address end of the memory and is used for receiving the memory access address transmitted to the address end of the memory;

[0031] The password root output end is connected with the encryption device of the write data end and the decryption device of the read data end of the memory, respectively, and is used for outputting an n-bit password root;

[0032] The key generation circuit is used for generating an n-bit first key and an n-bit second key;

[0033] The data encryption logic circuit comprises a four-round encryption module, four-round encryption units in the four-round encryption module comprise an n-bit interleaver and four 64-bit round function components and two sub-circuits for encrypting residual data and residual keys which are correspondingly arranged on both sides of the interleaver, are connected with an address input end, a password root output end and a key generation circuit, are used for performing alignment processing on a memory access address, performing interleaving encryption processing on the n-bit aligned address obtained through the alignment processing, the first key and the second key based on the four-round encryption module, and generating an n-bit password root, so that the encryption device encrypts the write data according to the password root, and the decryption device decrypts the read data according to the password root.

[0034] It should be noted that the data bit width of the memory in the embodiment of the application is n, and the address bit width is m. The first key generated by the key generation circuit and the bit width of the first key are the same as the data bit width of the memory, that is, the bit width of the first key and the first key are both n.

[0035] The address input end of the data encryption device is connected with the address end of the memory, and the password root output end of the data encryption device is connected with the encryption device at the write data end of the memory and the decryption device at the read data end of the memory respectively. The data encryption device can generate an n-bit password root based on an m-bit memory access address in the addressing stage, so that the encryption device connected at the write data end of the memory or the decryption device connected at the read data end can encrypt or decrypt n-bit write data or n-bit read data based on the n-bit password root generated in advance. It should be noted that in a general processor system, the addressing stage is usually at least one clock cycle earlier than the data stage. Therefore, the password root for encryption and decryption is generated in the addressing stage, and the generated password root can be directly used to encrypt or decrypt data in the data stage, so as to shorten the encryption and decryption time and improve the data throughput rate of the memory.

[0036] The data encryption device in the embodiment of the application generates an n-bit password root based on an m-bit memory access address and the first key and the second key of n bits generated by the key generation circuit through the data encryption logic circuit.

[0037] Specifically, the key generation circuit in the data encryption device generates a first key of n bits and a second key of n bits. The data encryption logic circuit in the data encryption device comprises a four-round encryption module, and four-round encryption units in the four-round encryption module comprise an n-bit interleaver and four 64-bit round function components and two sub-circuits for encrypting residual data and residual keys which are correspondingly arranged on both sides of the interleaver. The four-round encryption units in the four-round encryption module are used to realize data encryption and decryption of 64-bit multiples and non-64-bit multiples, and realize memory encryption of different data bit widths.

[0038] The input end of the data encryption logic circuit is connected with the address input end and the key generation circuit respectively, and is used for receiving the m-bit memory access address input by the address input end and the n-bit first key and the n-bit second key generated by the key generation circuit. The data encryption logic circuit performs alignment processing on the received m-bit memory access address to obtain an n-bit aligned address. After performing exclusive OR operation processing on the n-bit aligned address and the first key, the data encryption logic circuit performs interleaving encryption processing on the exclusive OR operation result and the second key by using the four-round encryption module, and performs again exclusive OR operation processing on the interleaving encryption processing result and the first key to generate an n-bit password root.

[0039] The output end of the data encryption logic circuit is connected with the password root output end, and is used for inputting the generated n-bit password root to the encryption device connected at the memory write data end or the decryption device connected at the read data end through the password root output end. Therefore, if the memory is written with data, the encryption device can encrypt the write data based on the password root, and the encrypted write data can be stored to the memory access address. If the memory is read with data, the decryption device can decrypt the data stored at the memory access address based on the password root.

[0040] It should be noted that the four-round encryption units in the four-round encryption module can realize data encryption and decryption of 64-bit multiples and non-64-bit multiples, and can support memory encryption of different data bit widths, and have better convenience than commonly used block encryption algorithms, so that the data encryption device of the embodiment of the present application meets the flexible requirement of data encryption of various data bit width memories.

[0041] The data encryption device in the embodiment of the present application realizes low-latency encryption and decryption by using the password root generated in advance to encrypt and decrypt data in the data stage, realizes flexible bit width encryption and decryption capability by using the four-round encryption units in the four-round encryption module to perform data bit interleaving, thereby completing high-speed flexible memory encryption and decryption operation and ensuring the security of data storage. The data encryption device of the embodiment of the present application has the characteristics of low encryption and decryption latency and supporting flexible bit width memory encryption.

[0042] The data encryption logic circuit in the embodiment of the present application mainly includes an address alignment sub-circuit, a first exclusive OR sub-circuit, a four-round encryption module, a key conversion sub-circuit and a second exclusive OR sub-circuit.

[0043] In a general processor system, the addressing stage is usually at least one clock cycle earlier than the data stage. The embodiment of the present application uses the memory access address of the memory as the input signal of the data encryption logic circuit, and can generate the password root used for data encryption in advance.

[0044] In one specific embodiment of the present application, as shown in Figure 2 The data encryption logic circuit can include:

[0045] An address alignment sub-circuit, an input end of the address alignment sub-circuit is connected with the address input end, and the address alignment sub-circuit is configured to perform alignment processing on the memory access address of m bits to obtain an aligned address of n bits.

[0046] In practice, when n>m, the address alignment sub-circuit performs repeated expansion on the memory access address of m bits, and takes the low n bits of the expanded memory access address when the bit width of the expanded memory access address is greater than or equal to n.

[0047] Specifically, when the memory access address of m bits and the data of n bits do not match in bit width, the address alignment sub-circuit performs alignment processing on the received memory access address of m bits. When n>m, the memory access address of m bits is repeatedly expanded, and the low n bits of the expanded memory access address are taken as the aligned address of n bits when the bit width of the expanded memory access address is greater than or equal to n.

[0048] It should be noted that when the memory access address of m bits and the data of n bits match in bit width, the address alignment sub-circuit can not be set, and the first XOR sub-circuit is directly used to perform XOR operation on the memory access address and the first key.

[0049] A first XOR sub-circuit, a first input end of the first XOR sub-circuit is connected with an output end of the address alignment sub-circuit, a second input end of the first XOR sub-circuit is connected with a first output end of the key generation circuit, and the first XOR sub-circuit is configured to perform XOR operation on the aligned address and the first key to obtain a first XOR result.

[0050] Specifically, the first XOR sub-circuit performs input-level XOR operation on the input n-bit aligned address using the first key to obtain the first XOR result. It should be noted that the bit-wise XOR operation can be represented by "⊕", see Figure 2 .

[0051] A four-round encryption module, a first input end of the four-round encryption module is connected with an output end of the first XOR circuit, a second input end of the four-round encryption module is connected with a second output end of the key generation circuit, and the four-round encryption module includes k four-round encryption units connected in series, and the four-round encryption module is configured to perform 4k times of encryption operation on the first XOR result and the second key to obtain a target encryption result (interleaved encryption processing result), where k≥1, k is an integer.

[0052] The four-round encryption module in the embodiment of the application performs encryption on the n-bit input to generate n-bit output.

[0053] Specifically, the four-round encryption module includes at least one four-round encryption unit, and a plurality (equal to or greater than 2) of four-round encryption units are connected in series. The four-round encryption unit in the embodiment of the application mainly includes four columns of same 64-bit round function components, an n-bit data interleaver located at a center position, and two exclusive OR sub-circuits (a third exclusive OR sub-circuit and a fourth exclusive OR sub-circuit) of remaining data bits and remaining key bits. The second key generated by the key generation circuit is used as an encryption key of the four-round encryption unit. One four-round encryption unit can perform 4 times of encryption operations. The number of four-round encryption units used by the four-round encryption module can be selected according to the security level of data. For example, 4 serial four-round encryption units are selected as encryption subjects, and 16 rounds of depth of encryption operations can be realized. The four-round encryption module receives the first exclusive OR result output by the first exclusive OR circuit and the second key output by the key generation circuit, and can use the enabled four-round encryption units to perform 4k times of encryption operations on the first exclusive OR result and the second key to obtain a target encryption result.

[0054] It should be noted that the number of four-round encryption units enabled in the four-round encryption module can be pre-set fixedly, or an enabling sub-circuit can be arranged to enable and control the four-round encryption units in the four-round encryption module according to the actual required security level, and the embodiment of the application does not limit this.

[0055] The key conversion sub-circuit is connected with the first output end of the key generation circuit, and is used to convert the first key.

[0056] It should be noted that the key conversion sub-circuit can also not be arranged, and the first key can be directly used to encrypt the target encryption result to generate the password root. In order to improve the encryption effect, the key conversion sub-circuit is arranged in the embodiment of the application.

[0057] Specifically, the key conversion sub-circuit converts the first key, so that the keys used in the input stage exclusive OR and the output stage exclusive OR in the data encryption logic circuit are not completely the same. In a specific embodiment, the key conversion sub-circuit can include a shift layer and / or an S-box conversion layer.

[0058] Specifically, the key conversion sub-circuit can only include a shift layer or only include an S-box conversion layer. The key conversion sub-circuit can also be composed of a shift layer and an S-box conversion layer.

[0059] The second exclusive OR sub-circuit is connected with the output end of the four-round encryption module at a first input end, is connected with the output end of the key conversion sub-circuit at a second input end, and is connected with the password root output end at an output end, and is used to perform exclusive OR operation on the target encryption result and the converted first key to obtain the password root.

[0060] Specifically, the second XOR sub-circuit performs XOR operation on the input target encryption result by using the converted first key to obtain the password root.

[0061] It should be noted that the first key generated by the key generation circuit in the embodiment of the present application is used for whitening operation on the main body of the data encryption logic circuit. That is, the first key can be used for input-level XOR operation on the input n-bit aligned address, and the first key can also be used for output-level XOR operation on the input target encryption result. In order to ensure the diversity and attack resistance of the whitening operation, the key conversion sub-circuit is arranged to convert the first key input into the second XOR sub-circuit, so that the keys used in the input-level XOR operation and the output-level XOR operation are not exactly the same.

[0062] The four-round encryption unit in the embodiment of the present application mainly consists of four columns of same 64-bit round function components, an n-bit data interleaver arranged at the center position, and two XOR sub-circuits (third XOR sub-circuit and fourth XOR sub-circuit) for the remaining data bits and the remaining key bits. The number of 64-bit round function components in each column of 64-bit round function components is determined by the integer part of the quotient obtained by dividing the data bit width n of the memory by 64.

[0063] The n-bit second key generated by the key generation circuit in the embodiment of the present application is an encryption key of the n-bit four-round encryption unit, and is input into the 64-bit round function component in the same column as the round key. The four-round encryption unit uses the n-bit second key to perform encryption processing on the n-bit input data.

[0064] Specifically, the n-bit input data is grouped by 64 bits and the n-bit second key by bit. The 64-bit round function component in each row of the four columns of 64-bit round function components uses the 64-bit key of the corresponding group to perform encryption processing on the 64-bit data of the corresponding group.

[0065] It should be noted that for the first four-round encryption unit in the four-round encryption module, the input data of the first column of 64-bit round function components in the four-round encryption unit is the n-bit aligned address. For the non-first four-round encryption unit in the four-round encryption module, the input data of the first column of 64-bit round function components in the four-round encryption unit is the data output by the previous four-round encryption unit.

[0066] In one embodiment of the present application, as shown in Figure 3

[0067] ​The first input end of the first column of 64-bit round function components is connected to the input end of the four-round encryption unit, the second input end of the first column of 64-bit round function components is connected to the second output end of the key generation circuit, and the 64-bit round function components in each row of the first column of 64-bit round function components are used to encrypt the corresponding group of 64-bit data in the input data by using the corresponding group of 64-bit keys in the second key, to obtain a first encryption result;

[0068] The first input end of the second column of 64-bit round function components is connected to the output end of the first column of 64-bit round function components, the second input end of the second column of 64-bit round function components is connected to the second output end of the key generation circuit, and the 64-bit round function components in each row of the second column of 64-bit round function components are used to encrypt the corresponding group of 64-bit data in the first encryption result by using the corresponding group of 64-bit keys in the second key, to obtain a second encryption result;

[0069] The first input end of the third XOR sub-circuit is connected to the input end of the four-round encryption unit, the second input end of the third XOR sub-circuit is connected to the second output end of the key generation circuit, and is used to perform XOR operation on the remaining keys in the second key and the remaining data in the input data, to obtain a third XOR result;

[0070] The input end of the interleaver is connected to the output end of the second column of 64-bit round function components and the output end of the third XOR sub-circuit respectively, and is used to perform data bit interleaving arrangement on the second encryption result, or the data composed of the second encryption result and the third XOR result, to obtain interleaved data;

[0071] The first input end of the third column of 64-bit round function components is connected to the output end of the interleaver, the second input end of the third column of 64-bit round function components is connected to the second output end of the key generation circuit, and the 64-bit round function components in each row of the third column of 64-bit round function components are used to encrypt the corresponding group of 64-bit data in the interleaved data by using the corresponding group of 64-bit keys in the second key, to obtain a third encryption result;

[0072] The first input end of the fourth column of 64-bit round function components is connected to the output end of the third column of 64-bit round function components, the second input end of the fourth column of 64-bit round function components is connected to the second output end of the key generation circuit, the output end of the fourth column of 64-bit round function components is connected to the output end of the four-round encryption unit, and the 64-bit round function components in each row of the fourth column of 64-bit round function components are used to encrypt the corresponding group of 64-bit data in the third encryption result by using the corresponding group of 64-bit keys in the second key, to obtain a fourth encryption result;

[0073] The first input end of the fourth XOR sub-circuit is connected with the output end of the interleaver, the second input end of the fourth XOR sub-circuit is connected with the second output end of the key generation circuit, and the output end of the fourth XOR sub-circuit is connected to the output end of the four-round encryption unit, for performing XOR operation on the remaining keys in the second keys and the remaining data in the interleaved data, to obtain a fourth XOR result, wherein the encryption result output by the four-round encryption unit is data composed of the four-time encryption result and the fourth XOR result.

[0074] The four-round encryption unit of the embodiment of the present application can be used for data encryption and decryption of the memory with data bit width of 64 integer multiples and non-64 integer multiples.

[0075] When the data bit width of the memory is an integer multiple of 64, the input data and the second keys are grouped by 64 bits. Since the data bit width of the memory is an integer multiple of 64, there is no remainder when the input data and the second keys are grouped by 64 bits, so the four-round encryption unit only uses the four-column 64-bit round function assembly and the interleaver when encrypting the input data, without using the third XOR sub-circuit and the fourth XOR sub-circuit. Specifically, the first column 64-bit round function assembly and the second column 64-bit round function assembly successively encrypt 64-bit data using the corresponding group of 64-bit keys, without using the third XOR sub-circuit. The interleaver arranges the data bits of the second column 64-bit round function assembly output twice-encrypted result, and then successively encrypts the interleaved data using the third column 64-bit round function assembly and the fourth column 64-bit round function assembly, and the four-time encryption result output by the fourth column 64-bit round function assembly is used as the encryption result output by the four-round encryption unit, without using the fourth XOR sub-circuit.

[0076] When the data bit width of the memory is not an integer multiple of 64, the input data and the second key are grouped by 64 bits. Since the data bit width of the memory is not an integer multiple of 64, there is a remainder when the input data and the second key are grouped by 64 bits, so the third exclusive OR sub-circuit and the fourth exclusive OR sub-circuit are used to perform exclusive OR operation on the remaining key and the remaining data bit by bit when the four-round encryption unit encrypts the input data. Specifically, the first column of 64-bit round function assemblies and the second column of 64-bit round function assemblies encrypt the 64-bit data by using the corresponding group of 64-bit keys in turn, the third exclusive OR sub-circuit performs exclusive OR operation on the remaining key and the remaining data bit by bit, and the second encryption result output by the second column of 64-bit round function assemblies and the third exclusive OR result output by the third exclusive OR sub-circuit are both input into the interleaver, which performs data bit interleaving arrangement on the data composed of the second encryption result and the third exclusive OR result bit by bit. The interleaved data output by the interleaver is grouped by 64 bits and output to the third column of 64-bit round function assemblies and the fourth column of 64-bit round function assemblies in the subsequent stage for processing in turn, and the remaining data bits and the remaining input key are processed by the fourth exclusive OR sub-circuit bit by bit, and the fourth encryption result output by the fourth column of 64-bit round function assemblies and the fourth exclusive OR result output by the fourth exclusive OR sub-circuit are used as the encryption result output by the four-round encryption unit.

[0077] It should be noted that the basic bit width of group encryption is usually 64 bits, 128 bits or 256 bits, and in order to support flexible memory bit width, the encryption unit based on the 64-bit round function assembly is used in the embodiment of the present application. The number of columns of the 64-bit round function assembly is fixed, and the number of rows of the 64-bit round function assembly is related to the data bit width of the memory. When the memory bit width is equal to or lower than 64 bits, a single row of 64-bit round unit is used for encryption; when the memory bit width is greater than 64 bits, the number of rows of the 64-bit round unit is equal to the integer part of the quotient obtained by dividing the memory bit width by 64.

[0078] For example, when the data bit width of the memory is 136, the integer part of the quotient obtained by dividing 136 by 64 is 2. Therefore, when the data bit width of the memory is 136, two rows of 64-bit round function assemblies are arranged in each column of 64-bit round function assemblies in the four-round encryption unit. When the input data with a data bit width of 136 is encrypted by using the four-round encryption unit, the input data with a data bit width of 136 and the second key are grouped to obtain three groups of data. The data bit width of the first group and the second group is 64, and the data bit width of the third group is 8, which is the remaining data bit width. Each column of 64-bit round function assemblies in each column of 64-bit round function assemblies encrypts the corresponding group of 64-bit data in the input data by using the corresponding group of 64-bit keys in the second key. The remaining key and the remaining input data are encrypted by using the exclusive OR sub-circuit.

[0079] In one embodiment of the present application, the interleaver is used to fill the input data into a preset square matrix row by row in descending order, and mark the empty positions in the preset square matrix after filling the data as empty positions, and the number of rows r of the preset square matrix satisfies (r-1) 2 ≤ n≤ r 2 , wherein r represents the number of rows of the preset square matrix, and n represents the data bit width of the memory.

[0080] The preset square matrix after filling the data is transposed, and the data is taken out row by row in ascending order, and the empty positions are discarded when the data bits are empty positions.

[0081] The interleaver in the embodiment of the present application does not perform any logical operation, and its main function is to arrange the n-bit input data in a data bit interleaving manner, and then output the n-bit interleaved data.

[0082] In practice, the interleaving algorithm of the interleaver can be implemented by the matrix transposition method, specifically, the number of rows r of the preset square matrix is determined according to the data bit width n of the memory, wherein r satisfies (r-1) 2 ≤ n ≤ r 2 The n-bit input data line is filled into the preset square matrix A row by row in descending order, and if there are remaining positions not filled with data in the preset square matrix A, the positions are marked as empty positions. The preset square matrix A is transposed, and the data line is taken out row by row in ascending order, and if an empty position is encountered, the empty position is discarded.

[0083] The data interleaving implemented by the matrix transposition method of the embodiment of the present application can separate the adjacent data of the original input to the maximum distance, the distance between any adjacent data is greater than r-1, and a better interleaving effect can be achieved.

[0084] In one embodiment of the present application, as Figure 4 shown, the 64-bit round function component can include an S-box transformation layer, a linear transformation M layer, a constant addition operation layer, and a key addition operation layer connected in sequence.

[0085] Specifically, the 64-bit round function component is composed of four steps of S-box transformation layer, linear transformation M layer, constant addition, and key addition, and can refer to the round function of a general 64-bit block cipher, such as DES, PRINCE, etc. The embodiment of the present application does not make special limitations on the 64-bit round function component.

[0086] It should be noted that the added encryption and decryption circuit and the XOR logic in the embodiment of the present application are pure digital logic designs, and the hardware overhead is small, and easy to implement in circuit design.

[0087] It should be noted that the bit width of the key generation circuit, the first exclusive or sub-circuit, the key conversion sub-circuit, the second exclusive or sub-circuit, the third exclusive or sub-circuit, the fourth exclusive or sub-circuit, the 64-bit round function component and the interleaver in the embodiment of the application is the same as the data bit width of the memory.

[0088] The data encryption device in the embodiment of the application generates a password root in advance, and realizes encryption and decryption of memory data in a low-latency manner, thereby effectively reducing the influence of encryption and decryption operation on the throughput of memory access. The data encryption device in the embodiment of the application generates a password root in advance, and realizes encryption and decryption of memory data in a low-latency manner, thereby effectively reducing the influence of encryption and decryption operation on the throughput of memory access.

[0089] In chip design, the circuit of the data encryption device involved in the application can be integrated.

[0090] The application provides a memory encryption and decryption system.

[0091] Figure 5 FIG. 1 is a schematic diagram of a memory encryption and decryption system according to an embodiment of the application. Figure 5 As shown in FIG. 1, the memory encryption and decryption system can include:

[0092] The memory has a data bit width of n and an address bit width of m, where n and m are integers.

[0093] The encryption device is connected to the write data end of the memory.

[0094] The decryption device is connected to the read data end of the memory.

[0095] The data encryption device described above is connected to the address end, the encryption device and the decryption device of the memory, respectively, and is used to perform alignment processing on the access address transmitted to the address end of the memory, perform interleaving encryption processing on the n-bit aligned address obtained through the alignment processing, the first key and the second key, and generate an n-bit password root, so that the encryption device encrypts the write data according to the password root and the decryption device decrypts the read data according to the password root.

[0096] The main circuit of the memory encryption and decryption system in the embodiment of the application includes the memory, the encryption device, the decryption device and the data encryption device.

[0097] The data encryption device of the embodiment of the present application can generate an n-bit password root based on an m-bit memory access address in the addressing stage, so that the encryption device connected to the memory write data end or the decryption device connected to the read data end can encrypt or decrypt the n-bit write data or the n-bit read data based on the n-bit password root generated in advance in the data stage. It should be noted that in a general processor system, the addressing stage is usually at least one clock cycle earlier than the data stage. Therefore, the password root for encryption and decryption is generated in the addressing stage, and the generated password root can be directly used to encrypt or decrypt the data in the data stage, so as to shorten the encryption and decryption time and improve the data throughput rate of the memory.

[0098] In an embodiment of the present application, the encryption device and the decryption device are exclusive OR logical operation circuits.

[0099] The encryption device and the decryption device can be implemented as exclusive OR logical operation circuits, and the bit width of the exclusive OR logical operation circuits is the same as the bit width of the memory input and output data.

[0100] The memory encryption and decryption system of the embodiment of the present application can solve the problem of low memory access rate caused by long encryption and decryption time of memory data, and can generate a password root in advance in the addressing stage, and realize encryption and decryption by exclusive OR operation on the memory input and output data.

[0101] The memory encryption and decryption system of the embodiment of the present application can solve the problem of large hardware overhead of the encryption and decryption circuit, and use the same password root generation circuit for data decryption and data encryption, without the need for additional decryption circuit, thereby effectively saving the hardware overhead of encryption and decryption.

[0102] The memory encryption and decryption system of the embodiment of the present application can meet the flexible requirement of data encryption for various bit width memories, and can realize non-64-bit multiple data encryption and decryption through data interleaving and other methods, thereby supporting memory encryption of different data bit widths and having better convenience than the commonly used block encryption algorithm.

[0103] The memory encryption and decryption system of the embodiment of the present application can realize low-delay encryption and decryption characteristics by generating a password root in advance and performing bit-wise exclusive OR on data, and can realize flexible bit width encryption and decryption capability through data bit interleaving, thereby completing high-speed and flexible memory encryption and decryption operation, ensuring the security of data storage, and having low encryption and decryption delay and flexible bit width memory encryption characteristics.

[0104] The present application provides a chip.

[0105] Figure 6 FIG. 1 is a schematic diagram of a memory encryption and decryption system according to an embodiment of the present application. As shown in FIG. 1, the chip includes the memory encryption and decryption system. Figure 6 As shown in FIG. 1, the chip includes the memory encryption and decryption system.

[0106] The chip has low encryption and decryption delay and supports flexible bit width memory encryption.

[0107] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0108] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0109] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise explicitly specified and limited.

[0110] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0111] In the present application, unless otherwise explicitly specified and limited, a first feature is "on" or "under" a second feature can mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature is "over", "above" and "on top of" the second feature can mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. The first feature is "under", "below" and "underneath" the second feature can mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is horizontally lower than the second feature.

[0112] Although the embodiments of the present application have been shown and described above, it is to be understood that the above-described embodiments are exemplary only, and are not to be construed as limiting the present application, and that changes, modifications, substitutions and variations can be made thereto by those skilled in the art without departing from the scope of the present application.

Claims

1. A data encryption device, characterized by comprising: A memory for storing data, the memory having a data bit width of n and an address bit width of m, n and m being integers, comprising: an address input terminal connected to an address terminal of the memory for receiving an access address transmitted to the address terminal of the memory; a password root output terminal connected to an encryption device of a write data terminal and a decryption device of a read data terminal of the memory respectively for outputting an n-bit password root; a key generation circuit for generating a first key and a second key of n bits; a data encryption logic circuit comprising a four-round encryption module, each four-round encryption unit in the four-round encryption module comprising an n-bit interleaver and four 64-bit round function components and two sub-circuits for encrypting residual data and residual keys arranged on both sides of the interleaver, the data encryption logic circuit being connected to the address input terminal, the password root output terminal and the key generation circuit, for performing alignment processing on the access address, performing interleaving encryption processing on the n-bit aligned address obtained by the alignment processing, the first key and the second key based on the four-round encryption module, and generating the n-bit password root, so that the encryption device encrypts the write data based on the password root and the decryption device decrypts the read data based on the password root.

2. The data encryption apparatus according to claim 1, wherein The data encryption logic circuit further comprises: an address alignment sub-circuit, an input terminal of the address alignment sub-circuit being connected to the address input terminal, for performing alignment processing on the m-bit access address to obtain the n-bit aligned address; a first XOR sub-circuit, a first input terminal of the first XOR sub-circuit being connected to an output terminal of the address alignment sub-circuit, a second input terminal of the first XOR sub-circuit being connected to a first output terminal of the key generation circuit, for performing XOR operation on the aligned address and the first key to obtain a first XOR result, wherein a first input terminal of the four-round encryption module is connected to an output terminal of the first XOR circuit, a second input terminal of the four-round encryption module is connected to a second output terminal of the key generation circuit, the four-round encryption module comprising k four-round encryption units connected in series, for performing 4k encryption operations on the first XOR result and the second key to obtain a target encryption result, wherein k≥1, k being an integer; a key conversion sub-circuit, an input terminal of the key conversion sub-circuit being connected to the first output terminal of the key generation circuit, for converting the first key; a second XOR sub-circuit, a first input terminal of the second XOR sub-circuit being connected to an output terminal of the four-round encryption module, a second input terminal of the second XOR sub-circuit being connected to an output terminal of the key conversion sub-circuit, an output terminal of the second XOR circuit being connected to the password root output terminal, for performing XOR operation on the target encryption result and the converted first key to obtain the password root.

3. The data encryption apparatus according to claim 1 or 2, characterized by Corresponding to the four-column 64-bit round function components arranged on both sides of the interleaver, a first-column 64-bit round function component, a second-column 64-bit round function component, a third-column 64-bit round function component and a fourth-column 64-bit round function component are arranged respectively, and corresponding to the two sub-circuits for encrypting the remaining data and the remaining key arranged on both sides of the interleaver, a third XOR sub-circuit and a fourth XOR sub-circuit are arranged respectively, wherein, a first input end of the first-column 64-bit round function component is connected to an input end of the four-round encryption unit, a second input end of the first-column 64-bit round function component is connected to a second output end of the key generation circuit, and the 64-bit round function components in each row of the first-column 64-bit round function component are used to encrypt the 64-bit data in a corresponding group in the input data by using the 64-bit key in a corresponding group in the second key, to obtain a first encryption result; a first input end of the second-column 64-bit round function component is connected to an output end of the first-column 64-bit round function component, a second input end of the second-column 64-bit round function component is connected to the second output end of the key generation circuit, and the 64-bit round function components in each row of the second-column 64-bit round function component are used to encrypt the 64-bit data in a corresponding group in the first encryption result by using the 64-bit key in a corresponding group in the second key, to obtain a second encryption result; a first input end of the third XOR sub-circuit is connected to the input end of the four-round encryption unit, a second input end of the third XOR sub-circuit is connected to the second output end of the key generation circuit, and the third XOR sub-circuit is used to perform XOR operation on the remaining key in the second key and the remaining data in the input data, to obtain a third XOR result; an input end of the interleaver is connected to an output end of the second-column 64-bit round function component and an output end of the third XOR sub-circuit respectively, and the interleaver is used to perform data bit interleaving arrangement on the second encryption result or the data composed of the second encryption result and the third XOR result, to obtain interleaved data; a first input end of the third-column 64-bit round function component is connected to an output end of the interleaver, a second input end of the third-column 64-bit round function component is connected to the second output end of the key generation circuit, and the 64-bit round function components in each row of the third-column 64-bit round function component are used to encrypt the 64-bit data in a corresponding group in the interleaved data by using the 64-bit key in a corresponding group in the second key, to obtain a third encryption result; a first input end of the fourth-column 64-bit round function component is connected to an output end of the third-column 64-bit round function component, a second input end of the fourth-column 64-bit round function component is connected to the second output end of the key generation circuit, an output end of the fourth-column 64-bit round function component is connected to an output end of the four-round encryption unit, and the 64-bit round function components in each row of the fourth-column 64-bit round function component are used to encrypt the 64-bit data in a corresponding group in the third encryption result by using the 64-bit key in a corresponding group in the second key, to obtain a fourth encryption result. The first input end of the fourth XOR sub-circuit is connected with the output end of the interleaver, the second input end of the fourth XOR sub-circuit is connected with the second output end of the key generation circuit, and the output end of the fourth XOR sub-circuit is connected to the output end of the four-round encryption unit, for performing XOR operation on the remaining data in the interleaved data and the remaining key in the second key to obtain a fourth XOR result, wherein the four-time encryption result or the data composed of the four-time encryption result and the fourth XOR result is the encryption result output by the four-round encryption unit.

4. The data encryption apparatus according to claim 3, wherein The number of 64-bit round function components in each column is determined by the integer part of the quotient of the data bit width n of the memory divided by 64.

5. The data encryption apparatus according to claim 3, wherein The interleaver is configured to fill the input data into a preset square matrix row by row in descending order, and mark an empty position as a vacancy if there is an empty position in the preset square matrix after filling the data, wherein the number of rows r of the preset square matrix satisfies (r-1) 2 ≤ n≤ r 2 , wherein r represents the number of rows of the preset square matrix, and n represents the data bit width of the memory. The filled preset square matrix is transposed, and data is taken out row by row in descending order, and the empty bit is discarded when the data bit is the empty bit.

6. The data encryption apparatus according to claim 3, wherein The 64-bit round function component comprises an S-box transformation layer, a linear transformation M layer, a constant addition operation layer and a key addition operation layer connected in sequence.

7. The data encryption apparatus according to claim 2, wherein When n>m, the address alignment sub-circuit repeatedly extends the memory access address of m bits, and takes the low n bits after the extended memory access address bit width is greater than or equal to n.

8. The data encryption apparatus according to claim 2, wherein The key conversion sub-circuit comprises a shift layer and / or an S-box transformation layer.

9. A memory encryption / decryption system, characterized by, Comprise: a memory, the data bit width of the memory is n, the address bit width is m, n and m are integers; an encryption device connected with the write data end of the memory; a decryption device connected with the read data end of the memory; The data encryption device of any one of claims 1-8 is connected with the address end of the memory, the encryption device and the decryption device respectively, for performing alignment processing on the memory access address transmitted to the address end of the memory, performing interleaving encryption processing on the n-bit aligned address obtained by alignment processing, the first key and the second key, and generating the n-bit password root, so that the encryption device encrypts the write data according to the password root, and the decryption device decrypts the read data according to the password root.

10. A chip, characterized by The memory encryption and decryption system of claim 9 is included. The memory encryption and decryption system of claim 9 is included.

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