Display panel and display device

Abstract

The application discloses a display panel and a display device. The display panel comprises an array substrate and a counter substrate. The array substrate comprises a substrate and a plurality of thin film transistors, a passivation layer and a first transparent conductive layer. The thin film transistor comprises a gate, a gate insulating layer, an active layer and an electrode layer. The electrode layer comprises a first electrode and a second electrode which are spaced from each other, and the second electrode is close to a display area. The first metal layer comprises a common electrode trace and a metal electrode trace which are spaced from each other. The common electrode trace is close to the display area, and the metal electrode trace forms the gate. The common electrode trace and the gate are connected to different electrical signals. The first transparent conductive layer comprises a first conductive part and a second conductive part which are spaced from each other. The first conductive part is electrically connected to the first electrode via a via hole, and the second conductive part is electrically connected to the second electrode via a via hole. The second electrode of the thin film transistor closest to the display area is electrically connected to the common electrode trace via the second conductive part via hole. Through the above arrangement, the problem that the metal trace is prone to corrosion is solved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] TFT-LCD (Thin Film Transistor Liquid Crystal Display) holds an unshakeable position in the field of large, medium, and small flat panel displays due to the following characteristics: low voltage and low power consumption; flat panel structure; passive display (no glare, no eye strain, independently controlled dedicated light source for adjustable brightness); large display information capacity; easy to colorize; no electromagnetic radiation; and long lifespan. As consumer demands continue to rise, TFT-LCD products need constant upgrades. For example, TFT-LCD products are moving towards narrower bezel designs, and narrow or bezel-less designs place even stricter requirements on the high temperature and humidity testing of the LCD panel.

[0003] For narrow-bezel or borderless products, the alignment film can easily spread to the frame adhesive coating area and exceed the frame adhesive boundary due to the narrow bezel. Since the bonding ability between the alignment film and the frame adhesive is poor, and the moisture resistance of the alignment film is weakened under high temperature and high humidity conditions, moisture can easily enter the display panel through the bonding area between the alignment film and the frame adhesive during high temperature and high humidity tests. This can lead to corrosion of the metal traces and affect the performance of the display panel. Summary of the Invention

[0004] This application provides a display panel and display device to solve the problem that the metal traces of narrow-bezel or borderless display panels are easily corroded in the related art.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a display panel, including an array substrate and a counter substrate disposed opposite to each other, and a frame adhesive connecting the array substrate and the counter substrate; the display panel includes a display area and a non-display area disposed around the periphery of the display area;

[0006] The array substrate includes a substrate and a plurality of thin-film transistors disposed on one side of the substrate, the plurality of thin-film transistors being disposed in the non-display area; each thin-film transistor includes a gate, a gate insulating layer, an active layer and an electrode layer stacked sequentially; the electrode layer includes a first electrode and a second electrode spaced apart from each other, the second electrode being located on the side of the first electrode closer to the display area; one of the first electrode and the second electrode is a source electrode and the other is a drain electrode;

[0007] The array substrate includes a first metal layer and a second metal layer; the first metal layer is located between the gate insulating layer and the substrate; the first metal layer includes a common electrode trace and a metal electrode trace spaced apart from each other, the metal electrode trace is located on the side of the common electrode trace away from the display area, the metal electrode trace is disposed corresponding to the active layer and forms the gate; the common electrode trace is connected to a different electrical signal from the gate; the second metal layer includes the electrode layer;

[0008] The array substrate further includes a passivation layer and a first transparent conductive layer sequentially disposed on the side of the electrode layer away from the substrate. The passivation layer covers the plurality of thin film transistors. The first transparent conductive layer includes a first conductive portion and a second conductive portion spaced apart from each other. The first conductive portion is disposed corresponding to the first electrode and is electrically connected to the first electrode through a via. The second conductive portion is disposed corresponding to the second electrode and is electrically connected to the second electrode through a via.

[0009] In the direction from the non-display area to the display area, the second electrode of the thin-film transistor closest to the display area is electrically connected to the common electrode trace through a corresponding second conductive via.

[0010] The substrate includes a second transparent conductive layer, which is electrically connected to the second conductive portion corresponding to the thin-film transistor closest to the display area.

[0011] In some embodiments, the first electrode is not electrically connected to the metal electrode trace; or,

[0012] The first electrode is electrically connected to the metal electrode trace through the first conductive portion via.

[0013] In some embodiments, the plurality of thin-film transistors are arranged circumferentially along the array substrate;

[0014] The gates of the plurality of thin-film transistors are electrically connected to each other; and / or, the second electrodes of the plurality of thin-film transistors are electrically connected to each other and are all electrically connected to the common electrode trace;

[0015] And / or, the first electrodes of the plurality of thin-film transistors are electrically connected to each other.

[0016] In some embodiments, the plurality of thin-film transistors are arranged circumferentially along the array substrate;

[0017] In the plurality of thin-film transistors, the gates of the odd-numbered thin-film transistors are electrically connected to each other and connected to a first electrical signal; the gates of the even-numbered thin-film transistors are electrically connected to each other and connected to a second electrical signal.

[0018] The second electrodes of the plurality of thin-film transistors are all electrically connected to the common electrode trace;

[0019] The first electrodes of the plurality of thin-film transistors are electrically connected to each other; or, the first electrodes of any two adjacent thin-film transistors are spaced apart from each other, and among the plurality of thin-film transistors, the first electrodes of the odd-numbered thin-film transistors are electrically connected to each other, and the first electrodes of the even-numbered thin-film transistors are electrically connected to each other.

[0020] In some embodiments, N thin-film transistors are disposed in the direction from the display area to the non-display area, where N is a positive integer greater than 1;

[0021] In the direction from the display area to the non-display area, the gates of any two adjacent thin-film transistors are spaced apart from each other and connected to different electrical signals; wherein, in the direction from the display area to the non-display area, the gates of N thin-film transistors are connected to the first electrical signal to the Nth electrical signal in a one-to-one correspondence.

[0022] In the direction from the display area to the non-display area, in any two adjacent thin-film transistors, the second electrode of the thin-film transistor on the side away from the display area is electrically connected to the first electrode of the thin-film transistor on the side closer to the display area.

[0023] In some embodiments, N thin-film transistors are disposed in the direction from the non-display area to the display area, where N is a positive integer greater than 1;

[0024] In the direction from the non-display area to the display area, the gates of any two adjacent thin-film transistors are spaced apart from each other and connected to different electrical signals; wherein, in the direction from the non-display area to the display area, the gates of N thin-film transistors are connected to the first electrical signal to the Nth electrical signal in a one-to-one correspondence.

[0025] In the direction from the non-display area to the display area, in any two adjacent thin-film transistors, the second electrode of the thin-film transistor on the side away from the display area is not electrically connected to the first electrode of the thin-film transistor on the side closer to the display area.

[0026] In the direction from the non-display area to the display area, only the second electrode of the thin-film transistor whose gate is connected to the Nth electrical signal is electrically connected to the common electrode trace through the corresponding second conductive portion via; the second electrodes of the remaining thin-film transistors are electrically connected to the corresponding gate through the corresponding second conductive portion via.

[0027] In some embodiments, the array substrate includes a first metal layer, an insulating layer, a semiconductor layer, and a second metal layer stacked sequentially; the first metal layer includes the common electrode trace and a plurality of gate electrodes; the insulating layer includes a plurality of interconnected gate insulating layers and covers the first metal layer; the semiconductor layer includes a plurality of spaced-apart active layers; the second metal layer includes a plurality of electrode layers; and the passivation layer covers the second metal layer.

[0028] The non-display area includes a first protection zone and a second protection zone, with the second protection zone located on the side of the first protection zone closer to the display area; the thin-film transistor is located in the second protection zone.

[0029] The second metal layer further includes a protective metal disposed in the first protected area, and the first transparent conductive layer further includes a third conductive portion disposed in the first protected area; the protective metal is spaced apart from the electrode layer, and the first conductive portion and the second conductive portion are spaced apart from the third conductive portion; the third conductive portion and the protective metal are electrically connected through a via.

[0030] In some embodiments, the first metal layer further includes a sacrificial metal disposed in the first protected area, the sacrificial metal being connected to the gate of the thin-film transistor closest to the edge of the display panel, or the sacrificial metal being spaced apart from the gate of the thin-film transistor;

[0031] The third conductive portion is electrically connected to the sacrificial metal through a via contact.

[0032] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a display device, comprising:

[0033] Any of the display panels described above;

[0034] A backlight module is disposed on one side of the display panel and is used to provide backlight for the display panel.

[0035] In some implementations, a temperature sensor and control circuitry are also included;

[0036] The temperature sensor is disposed on the array substrate and is used to detect the temperature of the common electrode trace;

[0037] The control circuit is electrically connected to the temperature sensor and the gates of the plurality of thin-film transistors. The control circuit is used to control the on / off state of the thin-film transistors according to the temperature of the common electrode trace detected by the temperature sensor.

[0038] In some embodiments, the control circuit is configured to control all the thin-film transistors to turn off in response to the temperature of the common electrode trace being less than or equal to a first preset threshold.

[0039] And / or, in response to the temperature of the common electrode trace being greater than the first preset threshold and less than or equal to the second preset threshold, the plurality of thin-film transistors connected to the first electrical signal are controlled to turn on, and the plurality of thin-film transistors connected to the second electrical signal are controlled to turn off; wherein the second preset threshold is greater than the first preset threshold;

[0040] And / or, in response to the temperature of the common electrode trace being greater than the second preset threshold, control the multiple thin-film transistors connected to the first electrical signal and the multiple thin-film transistors connected to the second electrical signal to be turned on.

[0041] In some embodiments, the control circuit is configured to control all the thin-film transistors to turn off in response to the temperature of the common electrode trace being less than or equal to a first preset threshold.

[0042] And / or, in response to the temperature of the common electrode trace being greater than a (M-1)th preset threshold and less than or equal to an Mth preset threshold, the thin-film transistors connected to the first electrical signal to the (M-1)th electrical signal are controlled to turn on, and the thin-film transistors connected to the Mth electrical signal to the Nth electrical signal are controlled to turn off; wherein M is a positive integer greater than or equal to 2 and less than or equal to N; wherein the first preset threshold to the Nth preset threshold increases sequentially;

[0043] And / or, in response to the temperature of the common electrode trace being greater than the Nth preset threshold, control all of the thin-film transistors connected to the first electrical signal to the Nth electrical signal to be turned on.

[0044] The beneficial effects of this application are as follows: Unlike the prior art, this application discloses a display panel and a display device. The display panel includes an array substrate and a counter substrate disposed opposite each other, and a frame adhesive connecting the array substrate and the counter substrate. The display panel includes a display area and a non-display area disposed around the display area. The array substrate includes a substrate and a plurality of thin-film transistors disposed on one side of the substrate, with the plurality of thin-film transistors disposed in the non-display area. Each thin-film transistor includes a gate, a gate insulating layer, an active layer, and an electrode layer stacked sequentially. The electrode layer includes a first electrode and a second electrode spaced apart from each other, with the second electrode located on the side of the first electrode closer to the display area. One of the first electrode and the second electrode is a source, and the other is a drain. The array substrate includes a first metal layer and a second metal layer. The first metal layer is located between the gate insulating layer and the substrate. The first metal layer includes a common electrode trace and a metal electrode trace spaced apart from each other. The traces are located on the side of the common electrode trace away from the display area. The metal electrode traces are disposed corresponding to the active layer and form the gate. The common electrode traces and the gate are connected to different electrical signals. The second metal layer includes an electrode layer. The array substrate also includes a passivation layer and a first transparent conductive layer disposed sequentially on the side of the electrode layer away from the substrate. The passivation layer covers multiple thin-film transistors. The first transparent conductive layer includes a first conductive portion and a second conductive portion spaced apart from each other. The first conductive portion is disposed corresponding to the first electrode and is electrically connected to the first electrode through a via. The second conductive portion is disposed corresponding to the second electrode and is electrically connected to the second electrode through a via. In the direction from the non-display area to the display area, the second electrode of the thin-film transistor closest to the display area is electrically connected to the common electrode trace through the via of the second conductive portion. The substrate includes a second transparent conductive layer, and the second transparent conductive layer is electrically connected to the second conductive portion corresponding to the thin-film transistor closest to the display area.

[0045] By setting multiple thin-film transistors in the non-display area, with the first and second electrodes of the thin-film transistors spaced apart, and since the second electrode is located on the side of the first electrode closer to the display area, and the first conductive portion is positioned corresponding to the first electrode and electrically connected to the first electrode through a via, even if moisture enters the non-display area along the alignment film, it will first undergo electrochemical corrosion at the via corresponding to the first electrode, where the first conductive portion, moisture, and the first electrode come into contact, thus consuming most of the moisture. Furthermore, because the first and second electrodes are spaced apart, and the first and second conductive portions of the first transparent conductive layer are also spaced apart, even if the first electrode and the first conductive portion are corroded, the corrosion is less likely to spread to the second electrode side, effectively preventing corrosion of the second conductive portion, the second electrode, and the common electrode traces on the side closer to the display area. Simultaneously, since the first metal layer includes spaced-apart common electrode traces and metal electrode traces... The metal electrode trace serves as the gate of the thin-film transistor (TFT). Since the gate and the common electrode trace are connected to different electrical signals, the on / off state of the TFT can be independently controlled by the gate. Furthermore, the voltage of the gate can be set higher than the voltage of the common electrode trace, facilitating better conduction of the TFT and thus improving corrosion resistance. Moreover, corrosion of the TFT gate does not affect the common electrode trace separated from it. The common electrode trace closer to the display area is less prone to corrosion, preventing moisture from affecting the common electrode trace and other components within the display area. This effectively solves the problem of easy corrosion of metal traces in narrow-bezel or borderless display panels in related technologies, improving the performance of the display panel. It also ensures that a sufficient area of ​​the common electrode trace is electrically connected to the second transparent conductive layer of the substrate through the second conductive portion, guaranteeing the conductivity between the array substrate and the substrate. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0047] Figure 1 This is a top view of an embodiment of the display panel provided in the first embodiment of this application;

[0048] Figure 2 yes Figure 1 A partially enlarged schematic diagram of area S of the provided display panel according to the first embodiment;

[0049] Figure 3 yes Figure 2A cross-sectional schematic diagram of an embodiment of the provided display panel (A1-A2);

[0050] Figure 4 yes Figure 2 A cross-sectional schematic diagram of another embodiment of the provided display panel, A1-A2;

[0051] Figure 5 yes Figure 2 A cross-sectional schematic diagram of an embodiment of the provided display panel (A3-A4);

[0052] Figure 6 yes Figure 2 A schematic diagram of the electrical connections of multiple thin-film transistors in a first embodiment of the array substrate of the provided display panel;

[0053] Figure 7 yes Figure 6 A schematic diagram of the distribution structure of multiple thin-film transistors in one embodiment is provided;

[0054] Figure 8 yes Figure 6 A schematic diagram of the distribution structure of another embodiment of the provided thin-film transistors;

[0055] Figure 9 yes Figure 2 A schematic diagram of the electrical connections of multiple thin-film transistors in a second embodiment of the array substrate of the provided display panel;

[0056] Figure 10 yes Figure 9 A schematic diagram of the distribution structure of multiple thin-film transistors in one embodiment is provided;

[0057] Figure 11 yes Figure 9 A schematic diagram of the distribution structure of another embodiment of the provided thin-film transistors;

[0058] Figure 12 yes Figure 2 A schematic diagram of the electrical connections of multiple thin-film transistors in a third embodiment of the array substrate of the provided display panel;

[0059] Figure 13 yes Figure 1 A partially enlarged schematic diagram of area S of the provided display panel according to the second embodiment;

[0060] Figure 14 yes Figure 13 A cross-sectional schematic diagram of an embodiment of the provided display panel (A1-A2);

[0061] Figure 15 yes Figure 13 A cross-sectional schematic diagram of an embodiment of the provided display panel (A3-A4);

[0062] Figure 16 yes Figure 1 A partially enlarged schematic diagram of area S of the provided display panel in the third embodiment;

[0063] Figure 17 yes Figure 16 A cross-sectional schematic diagram of the first embodiment of the provided display panel (A1-A2);

[0064] Figure 18 yes Figure 16 A cross-sectional schematic diagram of the second embodiment of the provided display panel, A1-A2;

[0065] Figure 19 yes Figure 16 A schematic diagram of the electrical connections of multiple thin-film transistors in an embodiment of the array substrate of the provided display panel;

[0066] Figure 20 yes Figure 16 A schematic diagram of the electrical connections of multiple thin-film transistors in another embodiment of the array substrate of the provided display panel;

[0067] Figure 21 yes Figure 16 A cross-sectional schematic diagram of the third embodiment of the provided display panel (A1-A2);

[0068] Figure 22 This is a schematic diagram of an embodiment of the display device provided in the second embodiment of this application;

[0069] Figure 23 This is a schematic diagram of another embodiment of the display device provided in the second embodiment of this application.

[0070] Icon labels:

[0071] 400, Display device; 300, Control circuit; 200, Backlight module; 100, Display panel; 1, Array substrate; 11, Substrate; 12, Thin-film transistor; 13, First metal layer; 131, Gate; 132, Common electrode trace; 133, Metal electrode trace; 134, Sacrificial metal; 14, Insulating layer; 141, Gate insulating layer; 15, Semiconductor layer; 151, Active layer; 16, Second metal layer; 161, Electrode layer; 162, First electrode... 1621, First part; 1622, Second part; 163, Second electrode; 164, Protective metal; 17, Passivation layer; 18, First transparent conductive layer; 181, First conductive part; 182, Second conductive part; 183, Third conductive part; 19, Alignment film; 2, Alignment substrate; 3, Frame adhesive; 4, Circuit board; 5, Temperature sensor; X, Display area; F, Non-display area; F1, First protection zone; F2, Second protection zone; B, Bonding area. Detailed Implementation

[0072] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0073] The terms "first," "second," and "third" used in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0074] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0075] See Figures 1 to 21 , Figure 1 This is a top view schematic diagram of an embodiment of the display panel provided in the first embodiment of this application. Figure 2 yes Figure 1 A partially enlarged schematic diagram of area S of the provided display panel according to the first embodiment. Figure 3 yes Figure 2 A cross-sectional schematic diagram of an embodiment of the provided display panel, A1-A2. Figure 4 yes Figure 2 A cross-sectional schematic diagram of another embodiment of the provided display panel, A1-A2. Figure 5 yes Figure 2 The provided display panel, A3-A4, is a cross-sectional schematic diagram of one embodiment. Figure 6 yes Figure 2 A schematic diagram of the electrical connections of multiple thin-film transistors in the array substrate of the provided display panel according to a first embodiment.Figure 7 yes Figure 6 A schematic diagram of the distribution structure of multiple thin-film transistors in one embodiment is provided. Figure 8 yes Figure 6 A schematic diagram of the distribution structure of multiple thin-film transistors in another embodiment is provided. Figure 9 yes Figure 2 A schematic diagram of the electrical connections of multiple thin-film transistors in the array substrate of the provided display panel according to a second embodiment. Figure 10 yes Figure 9 A schematic diagram of the distribution structure of multiple thin-film transistors in one embodiment is provided. Figure 11 yes Figure 9 A schematic diagram of the distribution structure of multiple thin-film transistors in another embodiment is provided. Figure 12 yes Figure 2 A schematic diagram of the electrical connections of multiple thin-film transistors in the array substrate of the provided display panel according to a third embodiment. Figure 13 yes Figure 1 A partially enlarged schematic diagram of area S of the provided display panel in the second embodiment. Figure 14 yes Figure 13 A cross-sectional schematic diagram of an embodiment of the provided display panel, A1-A2. Figure 15 yes Figure 13 The provided display panel, A3-A4, is a cross-sectional schematic diagram of one embodiment. Figure 16 yes Figure 1 A partially enlarged schematic diagram of area S of the provided display panel in the third embodiment. Figure 17 yes Figure 16 A cross-sectional schematic diagram of the first embodiment of the provided display panel, A1-A2. Figure 18 yes Figure 16 A cross-sectional schematic diagram of the second embodiment of the provided display panel, A1-A2. Figure 19 yes Figure 16 A schematic diagram of the electrical connections of multiple thin-film transistors in an embodiment of the array substrate of the provided display panel. Figure 20 yes Figure 16 A schematic diagram of the electrical connections of multiple thin-film transistors in another embodiment of the array substrate of the provided display panel. Figure 21 yes Figure 16 A cross-sectional schematic diagram of the third embodiment of the provided display panel, A1-A2.

[0076] See Figures 1 to 21 The first embodiment of this application provides a display panel 100, which includes an array substrate 1 and a counter substrate 2 disposed opposite to each other, and a frame adhesive 3 connecting the array substrate 1 and the counter substrate 2. The display panel 100 includes a display area X and a non-display area F disposed around the display area X. Specifically, as shown... Figure 1As shown, in one embodiment, the size of the array substrate 1 is larger than the size of the counter substrate 2, and one side of the array substrate 1 protrudes from the counter substrate 2 to form a bonding area B, which is used to bond other components such as the circuit board 4.

[0077] See Figures 1 to 21 In the non-display area F, the array substrate 1 includes a substrate 11 and a plurality of thin-film transistors (TFTs) disposed on one side of the substrate 11. Each TFT includes a gate 131, a gate insulator 141 (GI), an active semiconductor layer 151 (AS), and an electrode layer 161 stacked sequentially. The electrode layer 161 includes a first electrode 162 and a second electrode 163 spaced apart from each other. The second electrode 163 is located on the side of the first electrode 162 closer to the display area X, and both the first electrode 162 and the second electrode 163 are at least partially in contact with the active layer 151. One of the first electrode 162 and the second electrode 163 is the source and the other is the drain. For example, the first electrode 162 is the source and the second electrode 163 is the drain.

[0078] Specifically, the display panel 100 includes a first metal layer 13 and a second metal layer 16. The first metal layer 13 is located between the gate insulating layer 141 and the substrate 11. The first metal layer 13 includes a common electrode trace 132 and a metal electrode trace 133 spaced apart from each other. The metal electrode trace 133 is located on the side of the common electrode trace 132 away from the display area X. The metal electrode trace 133 corresponds to the active layer 151 and forms the gate 131 of the thin-film transistor 12. The common electrode trace 132 and the gate 131, i.e., the metal electrode trace 133, are connected to different electrical signals. That is, the gate 131 is formed by the metal electrode trace 133 spaced apart from the common electrode trace 132. The gate 131 of the thin-film transistor 12 and the common electrode trace 132 are disconnected and not connected to each other, and they are connected to different electrical signals. In some specific embodiments, the gate 131, i.e., the metal electrode trace 133, can be connected to the SW (Switch) signal, which can be used to control the on / off state of the thin-film transistor 12, and the common electrode trace 132 is connected to the VCOM signal.

[0079] The second metal layer 16 includes the aforementioned electrode layer 161, that is, the gate electrode 131 is formed on the first metal layer 13, and the source and drain electrodes are formed on the second metal layer 16. Specifically, the second metal layer 16 can be made of conductive metal materials such as titanium or aluminum, and the active layer 151 can be made of amorphous silicon or oxide semiconductor materials. Amorphous silicon or oxide semiconductor materials have strong corrosion resistance, and the active layer 151 is not easily corroded by moisture.

[0080] Specifically, the array substrate 1 further includes a passivation layer 17 (PV) and a first transparent conductive layer 18 sequentially disposed on the side of the electrode layer 161 away from the substrate 11. The passivation layer 17 covers a plurality of thin-film transistors 12, and the first transparent conductive layer 18 is disposed on the side of the passivation layer 17 away from the substrate 11. Figure 3 , Figure 4 , Figure 14 As shown, the first transparent conductive layer 18 includes a first conductive portion 181 and a second conductive portion 182 spaced apart from each other, i.e., the first conductive portion 181 and the second conductive portion 182 are disconnected. The first conductive portion 181 is disposed corresponding to the first electrode 162 and is electrically connected to the first electrode 162 through a via, and the second conductive portion 182 is disposed corresponding to the second electrode 163 and is electrically connected to the second electrode 163 through a via. Specifically, the passivation layer 17 can be made of silicon nitride or silicon oxide, and the material of the first transparent conductive layer 18 is indium tin oxide (ITO) or zinc tin oxide (ZTO), etc. In some embodiments, an alignment film 19 is further disposed on the side of the first transparent conductive layer 18 of the array substrate 1 away from the substrate 11, and the alignment film 19 extends to the non-display area F.

[0081] In this configuration, from the non-display area F towards the display area X, the second electrode 163 of the thin-film transistor 12 closest to the display area X is electrically connected to the common electrode trace 132 of the first metal layer 13 through a via of the second conductive portion 182. That is, the second electrode 163 of the thin-film transistor 12 closest to the display area X is electrically connected to the common electrode trace 132 through the second conductive portion 182. The second electrode 163 of the thin-film transistor 12 and the common electrode trace 132 are connected to the same electrical signal. In some specific embodiments, the second electrode 163 is electrically connected to the common electrode trace 132 through the second conductive portion 182, thereby connecting the second electrode 163 to the VCOM signal. The second electrode 163 is not connected to the gate 131, i.e., the metal electrode trace 133; that is, the second electrode 163 of the thin-film transistor 12 and the gate 131 are connected to different electrical signals.

[0082] The substrate 2 of the display panel 100 includes a second transparent conductive layer (not shown). The second transparent conductive layer is electrically connected to the second conductive portion 182 corresponding to the thin film transistor 12 closest to the display area X in the direction from the non-display area F to the display area X. That is, the second conductive portion 182 of the first transparent conductive layer 18 closest to the thin film transistor 12 of the display area X is electrically connected to the common electrode trace 132 through a via. The second transparent conductive layer is electrically connected to the second conductive portion 182 corresponding to the thin film transistor 12 closest to the display area X, and connected to the via of the common electrode trace 132 through the second conductive portion 182. The second transparent conductive layer and the common electrode trace 132 are connected by the second conductive portion 182 corresponding to the thin film transistor 12 closest to the display area X, so that the VCOM signal of the common electrode trace 132 is conducted to the second transparent conductive layer of the opposing substrate 2 through the second conductive portion 182 corresponding to the thin film transistor 12 closest to the display area X. This facilitates the control of the deflection of liquid crystal molecules in the liquid crystal layer (not shown) between the array substrate 1 and the opposing substrate 2 of the display panel 100, thereby realizing the image display function.

[0083] Specifically, the second transparent conductive layer of the substrate 2 and the second conductive portion 182 of the first transparent conductive layer 18 corresponding to the thin film transistor 12 closest to the display area X of the array substrate 1 can be electrically connected by conductive components such as conductive gold balls. Alternatively, a color resist stack layer can be provided on the substrate 2 at the position corresponding to the second conductive portion 182 of the thin film transistor 12 closest to the display area X, and the second transparent conductive layer can be disposed on the surface of the color resist stack layer, so that the second transparent conductive layer of the substrate 2 and the second conductive portion 182 of the first transparent conductive layer 18 of the array substrate 1 can be in direct contact, thereby achieving electrical connection.

[0084] It is understood that in this embodiment of the application, by setting multiple thin-film transistors 12 in the non-display area F, and the first electrode 162 and the second electrode 163 of the thin-film transistors 12 are spaced apart from each other, a portion of the first metal layer 13 of the array substrate 1, namely the metal electrode trace 133, forms the gate 131 of the thin-film transistor 12. Since the second electrode 163 is located on the side of the first electrode 162 close to the display area X, the first conductive portion 181 is set corresponding to the first electrode 162 and is electrically connected to the first electrode 162 through a via. When the thin-film transistor 12 is turned on, even if water vapor enters the non-display area F along the alignment film 19, it will first be electrochemically corroded at the via corresponding to the first electrode 162 by the contact of the first conductive portion 181, water vapor and the first electrode 162, thereby consuming most of the water vapor. Furthermore, since the first electrode 162 and the second electrode 163 are spaced apart, the first conductive portion 181 and the second conductive portion 182 of the first transparent conductive layer 18 are spaced apart from each other. At the same time, the active layer 151 is made of amorphous silicon or oxide semiconductor material, and the active layer 151 is not easily corroded. Even if the first electrode 162 and the first conductive portion 181 are corroded at the via location, the corrosion is not likely to extend to the second electrode 163 side. The corrosion of the first electrode 162 will not affect the second electrode 163 and the common electrode trace 132. This can effectively prevent the second conductive portion 182, the second electrode 163 and the common electrode trace 132 of the first metal layer 13 from being corroded near the display area X side, effectively blocking the extension of the corrosion path. The spaced arrangement of the first conductive portion 181 and the second conductive portion 182, as well as the spaced arrangement of the first electrode 162 and the second electrode 163, limits the corrosion range.

[0085] Meanwhile, since the first metal layer 13 includes mutually spaced common electrode traces 132 and metal electrode traces 133, and the metal electrode traces 133 serve as the gate 131 of the thin-film transistor 12, the gate 131 (i.e., the metal electrode trace 133) and the common electrode trace 132 are connected to different electrical signals. The on / off state of the thin-film transistor 12 can be independently controlled by the gate 131. The voltage of the gate 131 can be set to be greater than the voltage of the common electrode trace 132, facilitating better conduction of the thin-film transistor 12 and thus better achieving the corrosion resistance function. Furthermore, the gate 133 of the thin-film transistor 12... Whether or not it is corroded will not affect the common electrode trace 132 separated from it. The common electrode trace 132 closer to the display area X is less susceptible to corrosion, which effectively avoids the influence of moisture on the common electrode trace 132 of the first metal layer 13 and other components in the display area X. It effectively solves the problem that the metal traces of narrow bezel or frameless display panels 100 are easily corroded in related technologies, significantly improves the reliability of narrow bezel or frameless display panels 100 in high temperature and high humidity environments, reduces display abnormality problems caused by metal corrosion, and improves the performance of display panels 100.

[0086] Simultaneously, when the thin-film transistor 12 is turned on, the gate 131 of the first metal layer 13, i.e., the metal electrode trace 133, also generates heat. The heat generated by the metal electrode trace 133 of the first metal layer 13 can heat the remaining film layer structure of the thin-film transistor 12 located on top of it, which is beneficial to improve the reaction rate between the first electrode 162 and water vapor, increase the water vapor consumption rate, and thus improve the corrosion resistance of the display panel 100. Moreover, the structure of the common electrode trace 132 of the first metal layer 13 does not require special design, ensuring that the common electrode trace 132 with a sufficient area is electrically connected to the second transparent conductive layer of the opposing substrate 2 through the second conductive portion 182 corresponding to the thin-film transistor 12 closest to the display area X, ensuring the conduction effect between the array substrate 1 and the opposing substrate 2, and corrosion is not easily diffused along the second conductive portion 182 to the second transparent conductive layer of the opposing substrate 2.

[0087] Specifically, in some embodiments, the alignment film 19 is at least partially located between the frame adhesive 3 and the substrate 11, that is, the alignment film 19 extends to the coating position of the frame adhesive 3. The material of the alignment film 19 is PI (Polyimide). The display panel 100 can be a narrow-bezel or frameless display panel. Since the bezel of the display panel 100 is narrow, when the alignment film 19 is coated using a coating equipment with lower precision, the alignment film 19 easily spreads to the connection position between the frame adhesive 3 and the array substrate 1 in the non-display area F and exceeds the boundary of the frame adhesive 3. That is, the alignment film 19 easily spreads to the side of the frame adhesive 3 away from the display area X. The alignment film 19 is a low-hygroscopic material. Under high temperature and high humidity conditions, the moisture absorption capacity of the alignment film 19 weakens. That is, the moisture absorption capacity of the alignment film 19 is enhanced in the high temperature and high humidity environment, and it easily absorbs water vapor. When the display panel 100 is subjected to high temperature and high humidity testing, water vapor easily comes into contact with the alignment film 19 and enters the display panel 100. In this embodiment, even if moisture enters the display panel 100 along the alignment film 19, it will only corrode the first electrode 162 and the first conductive portion 181 at the via position corresponding to the first electrode 162 of the thin film transistor 12 in the non-display area F, due to an electrochemical reaction. The first electrode 162 is spaced apart from the second electrode 163, and the first conductive portion 181 is spaced apart from the second conductive portion 182. Therefore, the second electrode 163 and the second conductive portion 182 are not easily corroded, and the common electrode trace 132 of the first metal layer 13 is also not easily corroded. The remaining traces in the display area X will not be corroded. By sacrificing only the first electrode 162 and the first conductive portion 181, the corrosion resistance of the narrow bezel or bezel-less display panel 100 can be improved, and the display performance of the display panel 100 can be improved.

[0088] Therefore, for narrow-bezel or borderless display panels 100, by setting the array substrate 1 to the above structure, the alignment film 19 can be coated using a low-precision coating equipment. Even if the alignment film 19 spreads to the coating position of the frame adhesive 3, it will not have a significant impact on the corrosion resistance of the narrow-bezel or borderless display panel 100. This can effectively reduce the precision requirements of the alignment film 19 coating equipment, reduce production costs, and optimize and improve the design. It solves the limitation of large fluctuations in the coating of the alignment film 19 for narrow-bezel or borderless products using PI Inject equipment, and realizes that the alignment film 19 can be coated using PI Inject equipment for narrow-bezel or borderless products.

[0089] In some implementations, such as Figure 3 As shown, the first electrode 162 of the thin-film transistor 12 may not be electrically connected to the metal electrode trace 133 of the first metal layer 13. That is, the first electrode 162 and the gate 131, i.e., the metal electrode trace 133, are spaced apart and insulated by the gate insulating layer 141, and the first conductive portion 181 of the first transparent conductive layer 18 at the position corresponding to the first electrode 162 is only electrically connected to the via of the first electrode 162, and is not electrically connected to the gate 131, i.e., the metal electrode trace 133. When the gate 131, i.e., the metal electrode trace 133 of the thin-film transistor 12 is connected to the SW signal, and the thin-film transistor 12 is turned on, the VCOM signal connected to the second electrode 163 of the thin-film transistor 12 closest to the display area X is transmitted to the first electrode 162 through the active layer 151. The signal at the first electrode 162 of the thin-film transistor 12 is also a VCOM signal. Moisture is first consumed by contact with the first conductive portion 181 and the first electrode 162. In this embodiment, the gate 131 of the thin-film transistor 12, i.e., the metal electrode trace 133, is not electrically connected to the first electrode 162. Therefore, corrosion of the first electrode 162 is unlikely to affect the gate 131, i.e., the metal electrode trace 133, and the gate 131, i.e., the metal electrode trace 133, is not easily corroded. Moreover, the signal at the first electrode 162 and the signal at the gate 131 of the thin-film transistor 12 will not affect each other and will not affect the conduction state of the thin-film transistor 12.

[0090] In other implementations, such as Figure 4As shown, the first electrode 162 of the thin-film transistor 12 can also be electrically connected to the gate 131, i.e., the metal electrode trace 133, through the via of the first conductive portion 181. Specifically, the first conductive portion 181 of the first transparent conductive layer 18 is electrically connected to the first electrode 162 and the gate 131 via, respectively, thereby electrically connecting the first electrode 162 and the gate 131 through the first conductive portion 181. Therefore, when the gate 131, i.e., the metal electrode trace 133, of the thin-film transistor 12 is connected to the SW signal and the thin-film transistor 12 is turned on, water vapor can not only be consumed by electrochemical reaction with the first conductive portion 181 and the first electrode 162, but also be consumed by the electrochemical reaction between the first conductive portion 181 and the gate 131, i.e., the metal electrode trace 133. The first electrode 162 and gate 131 of the thin-film transistor 12 can be corroded to consume water vapor, thereby increasing the water vapor consumption path and consumption rate, which is beneficial to further improve the corrosion resistance of the display panel 100. At the same time, since the gate 131, i.e., the metal electrode trace 133, and the common electrode trace 132 are spaced apart, the corrosion of the gate 131, i.e., the metal electrode trace 133, will not affect the common electrode trace 132, effectively avoiding the corrosion of the common electrode trace 132 and other traces or components in the display area X.

[0091] In some implementations, such as Figure 3 and Figure 4 As shown, the first electrode 162 of the thin-film transistor 12 is at least partially overlapped with the active layer 151. For example, the first electrode 162 of the thin-film transistor 12 includes a first portion 1621 and a second portion 1622 connected to each other. The first portion 1621 of the first electrode 162 of the thin-film transistor 12 overlaps with the active layer 151, and the second portion 1622 of the first electrode 162 extends to the side of the active layer 151 away from the display area X. The projection of the metal electrode trace 133 of the first metal layer 13 onto the substrate 11 at least partially overlaps with the projection of the second portion 1622 of the first electrode 162 onto the substrate 11. That is, the end of the gate 131, i.e., the metal electrode trace 133, away from the display area X can extend to the side of the active layer 151 away from the display area X. The projection of the active layer 151 of the thin-film transistor 12 onto the substrate 11 is located within the projection of the gate 131, i.e., the metal electrode trace 133, onto the substrate 11, thereby ensuring that the thin-film transistor 12 can be effectively turned on. The metal electrode trace 133 can be made of aluminum, copper or their alloys, and the common electrode trace 132 and the metal electrode trace 133 of the first metal layer 13 can be formed using the same process.

[0092] It is understood that the first portion 1621 of the first electrode 162 of the thin-film transistor 12 overlaps with the active layer 151, and the projection of the gate 131, i.e. the metal electrode trace 133, onto the substrate 11 at least partially overlaps with the projection of the second portion 1622 of the first electrode 162 onto the substrate 11. This ensures that the thin-film transistor 12 can be effectively turned on. At the same time, it also ensures that when the thin-film transistor 12 is turned on, the heat generated by the gate 131, i.e. the metal electrode trace 133, can heat the first portion 1621 of the first electrode 162 located on top of it and the second portion 1622 that overlaps with it, thereby further accelerating the reaction rate of the first electrode 162 with water vapor, increasing the water vapor consumption rate, further improving the corrosion resistance of the display panel 100, and effectively preventing water vapor from spreading to the second electrode 163 side.

[0093] In some embodiments, the projection of the gate 131, i.e., the metal electrode trace 133, onto the substrate 11 only partially overlaps with the projection of the second portion 1622 of the first electrode 162 onto the substrate 11 (e.g., Figure 3 (As shown). The above arrangement can ensure that the gate 131, i.e. the metal electrode trace 133, has sufficient distance from the edge of the array substrate 1, so as to prevent external moisture from reacting with the gate 131, i.e. the metal electrode trace 133, and corroding the gate 131 when it enters the display panel 100, and to prevent moisture from spreading to the display area X side. At the same time, the heat generated by the gate 131 can also heat the first part 1621 of the first electrode 162 located on top of it and the second part 1622 that overlaps with it, thereby accelerating the consumption of moisture.

[0094] In other embodiments, the projection of the second portion 1622 of the first electrode 162 onto the substrate 11 lies within the projection of the gate 131 onto the substrate 11 (e.g., Figure 4 (As shown). That is, the end of the gate 131, i.e., the metal electrode trace 133, away from the display area X is located on the side of the first electrode 162 away from the display area X, and the second portion 1622 of the first electrode 162 does not extend beyond the edge of the gate 131, i.e., the metal electrode trace 133. It can be understood that in this embodiment, the projection of the first electrode 162 of the thin film transistor 12 on the substrate 11 is completely located within the projection of the gate 131, i.e., the metal electrode trace 133, on the substrate 11. When the gate 131 is connected to the SW signal and the thin film transistor 12 is turned on, the heat generated by the gate 131 can heat the first portion 1621 and all the second portions 1622 of the first electrode 162 located on top of it, thereby further improving the water vapor consumption rate of the first electrode 162 and further improving the corrosion resistance of the display panel 100.

[0095] In one specific embodiment, the end of the gate 131, i.e., the metal electrode trace 133, away from the display area X can be located on the side of the gate insulating layer 141 away from the display area X. That is, the side of the gate 131, i.e., the metal electrode trace 133 away from the display area X, can be uncovered or unencased by the gate insulating layer 141, exposing the end of the gate 131, i.e., the metal electrode trace 133. When moisture enters the display panel 100, it can be consumed by a chemical or electrochemical reaction between the moisture and the gate 131, i.e., the metal electrode trace 133, thereby further increasing the moisture consumption rate and improving the corrosion resistance of the display panel 100. In other embodiments, the end of the gate 131, i.e., the metal electrode trace 133, away from the display area X can be covered by the gate insulating layer 141, which can be designed as needed.

[0096] In other embodiments, the projection of the gate 131, i.e., the metal electrode trace 133, onto the substrate 11 may not overlap with the projection of the second portion 1622 of the first electrode 162 onto the substrate 11. For example, the end of the gate 131, i.e., the metal electrode trace 133, away from the display area X may be flush with the end of the active layer 151 away from the display area X. That is, the end of the gate 131, i.e., the metal electrode trace 133, away from the display area X may be located at the junction of the first portion 1621 and the second portion 1622 of the first electrode 162. It can be understood that the non-overlapping projection of the gate 131, i.e., the metal electrode trace 133, onto the substrate 11 and the projection of the second portion 1622 of the first electrode 162 onto the substrate 11, and the larger distance between the gate 131, i.e., the metal electrode trace 133 and the edge of the array substrate 1, can effectively prevent external moisture from reacting with the gate 131, i.e., the metal electrode trace 133, and corroding the gate 131 when it enters the display panel 100, and prevent moisture from spreading to the display area X side.

[0097] See Figure 1 , Figure 2 and Figure 13 In some embodiments, a plurality of thin-film transistors 12 in the non-display area F of the array substrate 1 are arranged along the circumference of the array substrate 1. That is, the plurality of thin-film transistors 12 are arranged only along the circumference of the array substrate 1, and only one thin-film transistor 12 is arranged in the direction from the display area X to the non-display area F.

[0098] See Figures 6 to 8 In some embodiments, the gates 131 of the plurality of thin-film transistors 12 are electrically connected to each other; in some embodiments, the second electrodes 163 of the plurality of thin-film transistors 12 are electrically connected to each other and are all electrically connected to the common electrode trace 132; in some embodiments, the first electrodes 162 of the plurality of thin-film transistors are electrically connected to each other.

[0099] For details, see Figure 6In one specific embodiment, the gates 131 of multiple thin-film transistors 12 are electrically connected to each other and are all connected to the SW signal. Specifically, the gates 131 of multiple thin-film transistors 12 are electrically connected to the same SW signal line, and the SW signal is transmitted to the gates 131 of the multiple thin-film transistors 12 of the display panel 100 from the same SW signal line. It can be understood that since the gates 131 of multiple thin-film transistors 12 are all connected to the same SW signal, the on / off state of the multiple thin-film transistors 12 of the display panel 100 can be controlled simultaneously. Controlling multiple thin-film transistors 12 to conduct simultaneously is more convenient and can also provide anti-corrosion effect for multiple positions in the circumferential direction of the display panel 100.

[0100] In one specific embodiment, the second electrodes 163 of a plurality of thin-film transistors 12 are electrically connected to each other. Since the plurality of thin-film transistors 12 are arranged along the circumference of the array substrate 1, and only one thin-film transistor 12 is arranged in the direction from the display area X to the non-display area F, that is, only one row of thin-film transistors 12 is arranged at one side position corresponding to the display panel 100, and the second electrodes 163 of the thin-film transistors 12 are electrically connected to the common electrode trace 132 through the second conductive portion 182, the second electrodes 163 of the plurality of thin-film transistors 12 are all electrically connected to the common electrode trace 132.

[0101] In one specific implementation, such as Figure 7 As shown, the gates 131 of two adjacent thin-film transistors 12 can be spaced apart from each other, that is, the gates 131 of two adjacent thin-film transistors 12 do not contact each other, and the gates 131 of multiple thin-film transistors 12 can be respectively connected to the same SW signal line, so that the gates 131 of multiple thin-film transistors 12 are electrically connected to each other by the same SW signal line.

[0102] In another specific implementation, such as Figure 8 As shown, the gates 131 of multiple thin-film transistors 12 can be directly contacted and electrically connected, and the SW signal line can be contacted and electrically connected to the gate 131 of any one of the thin-film transistors 12, thereby ensuring that the gates 131 of multiple thin-film transistors 12 are all electrically connected to the same SW signal line. The way in which the gates 131 of multiple thin-film transistors 12 are connected to the SW signal can be designed as needed, and this embodiment does not limit this.

[0103] In some embodiments, the second electrodes 163 of multiple thin-film transistors 12 are electrically connected to each other and all are electrically connected to a common electrode trace 132. In one specific embodiment, the second electrodes 163 of the multiple thin-film transistors 12 can be directly contacted and electrically connected to each other. Any one of the second electrodes 163 of the thin-film transistors 12 is electrically connected to the common electrode trace 132 through a via of the second conductive portion 182 of the first transparent conductive layer 18, thereby achieving electrical connection between the second electrodes 163 of the multiple thin-film transistors 12 and the common electrode trace 132. In another specific embodiment, the second electrodes 163 of the multiple thin-film transistors 12 can also be spaced apart from each other, that is, the second electrodes 163 of adjacent thin-film transistors 12 do not contact each other. Each second electrode 163 of the thin-film transistors 12 is electrically connected to a different location on the common electrode trace 132 through a corresponding via of the second conductive portion 182, thereby achieving mutual electrical connection between the second electrodes 163 of the multiple thin-film transistors 12. The method by which the second electrodes 163 of the multiple thin-film transistors 12 are electrically connected to the common electrode trace 132 can be designed as needed, and this application embodiment does not limit this.

[0104] In some embodiments, the first electrodes 162 of the plurality of thin-film transistors 12 are electrically connected to each other. Specifically, the first electrodes 162 of the plurality of thin-film transistors 12 can be directly contacted and electrically connected to each other. When the gate 131 of the plurality of thin-film transistors 12 is connected to the SW signal and the thin-film transistors 12 are turned on, the VCOM signal on the common electrode trace 132 is conducted to the second electrode 163 through the second conductive portion 182, and then conducted to the first electrode 162 of the thin-film transistor 12 through the active layer 151. The first electrodes 162 of the plurality of thin-film transistors 12 are all VCOM signals.

[0105] It is understood that by directly contacting and electrically connecting the first electrodes 162 of multiple thin-film transistors 12, the corrosion path of the first electrodes 162 can be extended in the circumferential direction of the array substrate 1. This allows the first electrodes 162 of the thin-film transistors 12 at some locations to undergo an electrochemical reaction with the first conductive portion 181 and water vapor, and then diffuse along the circumferential direction of the array substrate 1 and along the extension path of the first electrodes 162 to the positions of the first electrodes 162 of other thin-film transistors 12, thereby further consuming water vapor. The contact and electrical connection of the first electrodes 162 of multiple thin-film transistors 12 is beneficial to extending the water vapor consumption path, further increasing the water vapor consumption rate, and preventing water vapor from diffusing to the second electrode 163 side, thus making it more effective to prevent the second electrode 163 and the common electrode trace 132 from being corroded.

[0106] In other embodiments, the first electrodes 162 of the plurality of thin-film transistors 12 may not be electrically connected to each other. Specifically, the first electrodes 162 of the plurality of thin-film transistors 12 are spaced apart from each other, and the first electrodes 162 of two adjacent thin-film transistors 12 do not contact each other. The signal at the first electrodes 162 of the plurality of thin-film transistors 12 is still the VCOM signal conducted through the active layer 151. It can be understood that by spaced apart from each other, when the first electrode 162 of one thin-film transistor 12 comes into contact with moisture and reacts, it will not affect the first electrodes 162 of other thin-film transistors 12. Moisture is not easily diffused along the already corroded first electrode 162 of the thin-film transistor 12 to the first electrodes 162 of other thin-film transistors 12, thereby avoiding the influence of moisture on other thin-film transistors 12. This allows the first electrodes 162 of the thin-film transistors 12 at multiple positions in the circumferential direction of the display panel 100 to effectively react with and consume the moisture when moisture enters, further improving the corrosion resistance of the display panel 100.

[0107] See Figures 9 to 12 In some embodiments, a plurality of thin-film transistors 12 are arranged along the circumference of the array substrate 1, and only one thin-film transistor 12 is arranged in the direction from the display area X to the non-display area F.

[0108] Specifically, in some implementation methods, such as Figures 9 to 12 As shown, among the multiple thin-film transistors 12, the gates 131 of the odd-numbered thin-film transistors 12 are electrically connected to each other and are all connected to a first electrical signal, which is the SW1 signal; the gates 131 of the even-numbered thin-film transistors 12 are electrically connected to each other and are all connected to a second electrical signal, which is the SW2 signal.

[0109] That is, along the circumference of the array substrate 1, the gates 131 of two adjacent thin-film transistors 12 are connected to different electrical signals, and the gates 131 of two adjacent thin-film transistors 12 are controlled by different signal lines. This allows multiple thin-film transistors 12 to be divided into two groups. Specifically, the odd-numbered thin-film transistors 12 form one group, and the even-numbered thin-film transistors 12 form another group. The two groups of thin-film transistors 12 are independently controlled by different signal lines, which facilitates the control of the conduction state of the two groups of thin-film transistors 12 based on different temperature, humidity and other conditions. This ensures the corrosion resistance of the display panel 100 at various positions in the circumference and also effectively avoids energy waste.

[0110] Specifically, based on specific usage scenarios and environments, only one set of thin-film transistors 12 can be controlled to conduct, or both sets of thin-film transistors 12 can be controlled to conduct simultaneously. This allows the display panel 100 to have different corrosion resistance capabilities, meeting different corrosion resistance requirements under different environments, thereby improving the performance and application range of the display panel 100. For example, when both sets of thin-film transistors 12 are conducting, the display panel 100 has the strongest corrosion resistance, meeting the corrosion resistance requirements under higher humidity or temperature conditions. Conversely, when the temperature or humidity is lower, controlling only one set of thin-film transistors 12 to conduct is sufficient to meet the corrosion resistance requirements under those conditions, which helps save energy.

[0111] In some embodiments, the gates 131 of any two adjacent thin-film transistors 12 are spaced apart. In one specific embodiment, the gates 131 of the multiple thin-film transistors 12 are all spaced apart and do not contact each other. The gates 131 of the odd-numbered thin-film transistors 12 are electrically connected to the first electrical signal line, i.e., the SW1 signal line, thereby connecting the gates 131 of the odd-numbered thin-film transistors 12 to the first electrical signal, so that the gates 131 of the odd-numbered thin-film transistors 12 are electrically connected to each other through the first electrical signal line. Similarly, the gates 131 of the even-numbered thin-film transistors 12 are electrically connected to the second electrical signal line, i.e., the SW2 signal line, thereby connecting the gates 131 of the even-numbered thin-film transistors 12 to the second electrical signal, so that the gates 131 of the even-numbered thin-film transistors 12 are electrically connected to each other through the second electrical signal line.

[0112] In one specific embodiment, the gates 131 of the plurality of thin-film transistors 12 can be arranged without misalignment in the direction from the non-display F to the display area X, such as... Figure 10 As shown, the first electrical signal line (i.e., SW1 signal line) and the second electrical signal line (i.e., SW2 signal line) can be located on opposite sides of the thin-film transistor 12, so that the gates 131 of multiple odd-numbered thin-film transistors 12 are electrically connected to each other by the first electrical signal line, and the gates 131 of multiple even-numbered thin-film transistors 12 are electrically connected to each other by the second electrical signal line. The fact that the first and second electrical signal lines are located on opposite sides of the thin-film transistor 12 facilitates the electrical connection between the gates 131 of the odd-numbered thin-film transistors 12 and the first electrical signal line, and between the gates 131 of the even-numbered thin-film transistors 12 and the second electrical signal line, avoiding mutual interference between the first and second electrical signal lines.

[0113] In another specific implementation, such as Figure 11As shown, the gates 131 of adjacent thin-film transistors 12 can also be staggered in the direction from the non-display F to the display area X. That is, the gates 131 of the two sets of thin-film transistors 12 are staggered in the direction from the non-display F to the display area X. The gates 131 of multiple thin-film transistors 12 in each set of thin-film transistors 12 can be directly contacted and electrically connected to each other, or they can be spaced apart from each other. The first electrical signal line (i.e., SW1 signal line) and the second electrical signal line (i.e., SW2 signal line) can be located on the same side of the thin-film transistor 12.

[0114] The specific connection method between the gate 131 of the thin-film transistor 12 and the electrical signal can be designed as needed, as long as the gate 131 of the odd-numbered thin-film transistor 12 is connected to the first electrical signal and the gate 131 of the even-numbered thin-film transistor 12 is connected to the second electrical signal. This application embodiment does not make specific limitations in this regard.

[0115] See Figures 9 to 12 In some embodiments, the second electrodes 163 of the plurality of thin-film transistors 12 are all electrically connected to the common electrode trace 132. In some specific embodiments, such as Figure 9 and Figure 10 As shown, the second electrodes 163 of the multiple thin-film transistors 12 can be arranged at intervals, that is, the second electrodes 163 of two adjacent thin-film transistors 12 can not contact each other. The second electrode 163 of each thin-film transistor 12 is electrically connected to the corresponding second conductive portion 182 through a via, and can be electrically connected to the common electrode trace 132 of the first metal layer 13 through the corresponding second conductive portion 182 via, so that the second electrodes 163 of the multiple thin-film transistors 12 are electrically connected to the common electrode trace 132 through the corresponding second conductive portion 182.

[0116] In other embodiments, the second electrodes 163 of the plurality of thin-film transistors 12 can also be electrically connected to each other. The second conductive portion 182 corresponding to any one of the second electrodes 163 of the thin-film transistor 12 can be electrically connected to the common electrode trace 132 of the first metal layer 13 via, thus achieving electrical connection between the second electrodes 163 of the plurality of thin-film transistors 12 and the common electrode trace 132. The specific connection method between the second electrodes 163 of the plurality of thin-film transistors 12 and the common electrode trace 132 can be designed as needed, and this application does not impose specific limitations on it.

[0117] In some implementations, such as Figure 9 As shown, the first electrodes 162 of any two adjacent thin-film transistors 12 are spaced apart from each other and do not contact each other. Among the multiple thin-film transistors 12, the first electrodes 162 of the odd-numbered thin-film transistors 12 are electrically connected to each other, and the first electrodes 162 of the even-numbered thin-film transistors 12 are electrically connected to each other.

[0118] In one specific embodiment, the first electrodes 162 of a plurality of thin-film transistors 12 in the same group can be directly contacted and electrically connected. That is, the first electrodes 162 of the odd-numbered thin-film transistors 12 can be directly contacted and electrically connected, and the first electrodes 162 of the even-numbered thin-film transistors 12 can be directly contacted and electrically connected. Alternatively, the first electrodes 162 of a plurality of thin-film transistors 12 in the same group can be electrically connected to each other through other wiring or structures. For example, the first conductive portions 181 of the plurality of thin-film transistors 12 in the same group can be contacted and electrically connected to each other, thereby realizing the mutual electrical connection of the first electrodes 162 of a plurality of thin-film transistors 12 in the same group. Alternatively, two separate wirings can be provided to electrically connect the first electrodes 162 of a plurality of thin-film transistors 12 in the same group.

[0119] It is understood that since the gates 131 of two adjacent thin-film transistors 12 are connected to different electrical signals, the conduction state of the two adjacent thin-film transistors 12 can be controlled independently. By setting the first electrodes 162 of the two adjacent thin-film transistors 12 at intervals, when one of the thin-film transistors 12 is turned on, when water vapor comes into contact with the first electrode 162 and the corresponding first conductive part 181 of the thin-film transistor 12 and undergoes an electrochemical reaction, it will not affect the other adjacent thin-film transistor 12 that is not yet turned on. Water vapor will not diffuse along the first electrode 162 of the already turned-on thin-film transistor 12 to the first electrode 162 of the adjacent unturned thin-film transistor 12, thus avoiding the corrosion of the first electrode 162 of the thin-film transistor 12 when it is not turned on, which would affect the design of different corrosion resistance gradients of the display panel 100 and help improve the performance of the display panel 100. Meanwhile, the first electrodes 162 of multiple thin-film transistors 12 in the same group are electrically connected to each other. Since the gates 131 of multiple thin-film transistors 12 in the same group are connected to the same electrical signal, the thin-film transistors 12 in the same group can be turned on simultaneously. By electrically connecting the first electrodes 162 of multiple thin-film transistors 12 in the same group to each other, water vapor can be corroded along the distribution position of the first electrodes 162 of multiple thin-film transistors 12 in the same group. The corrosion path of the first electrode 162 can be extended in the circumferential direction of the array substrate 1, extending the water vapor consumption path and further increasing the water vapor consumption rate. This effectively prevents water vapor from diffusing to the second electrode 163 side, avoids corrosion of the second electrode 163 and the common electrode trace 132, and improves corrosion resistance.

[0120] In another embodiment, such as Figure 12As shown, the first electrodes 162 of multiple thin-film transistors 12 can also be electrically connected to each other. Specifically, the first electrodes 162 of two adjacent thin-film transistors 12 can be spaced apart from each other, and the first electrodes 162 of two sets of thin-film transistors 12 can be electrically connected through other traces and structures. For example, the first conductive portions 181 corresponding to two adjacent thin-film transistors 12 can be electrically connected to each other through contact, and the first electrodes 162 of multiple thin-film transistors 12 can be electrically connected to each other through the vias of the first conductive portions 181; or, the first electrodes 162 of multiple thin-film transistors 12 can also be electrically connected to each other by setting separate traces; or, the first electrodes 162 of multiple thin-film transistors 12 can also be directly connected through contact. It can be understood that the mutual electrical connection of the first electrodes 162 of multiple thin-film transistors 12 can further extend the corrosion path of water vapor along the circumferential direction of the array substrate 1, further increase the water vapor consumption rate, and more effectively prevent water vapor from diffusing to the second electrode 163 side, thus preventing the common electrode trace 132 from being corroded.

[0121] See Figures 16 to 19 In some embodiments, N thin-film transistors 12 are provided in the direction from the display area X to the non-display area F, where N is a positive integer greater than 1. For example, N can take the value of any positive integer such as two, three, four, five, six, etc.

[0122] In this embodiment, multiple thin-film transistors 12 can still be provided along the circumference of the array substrate 1, that is, multiple thin-film transistors 12 are provided both along the circumference of the array substrate 1 and in the direction from the display area X to the non-display area F. Specifically, the multiple thin-film transistors 12 in the non-display area F of the array substrate 1 can be divided into N groups, each group having multiple thin-film transistors 12 distributed along the circumference of the array substrate 1. That is, each side of the array substrate 1 is provided with N rows of thin-film transistors 12, and each row of thin-film transistors 12 has multiple thin-film transistors 12. In other embodiments, the multiple thin-film transistors 12 may also be provided only along the direction from the display area X to the non-display area F, without multiple thin-film transistors 12 being provided along the circumference of the array substrate 1.

[0123] Specifically, in this embodiment, in the direction from the display area X to the non-display area F, the gates 131 of any two adjacent thin-film transistors 12 are spaced apart from each other and do not contact each other. Specifically, the gates 131 of two adjacent thin-film transistors 12 can be aligned in the circumferential direction of the array substrate 1 or staggered in the circumferential direction of the array substrate 1.

[0124] In this embodiment, in the direction from the display area X to the non-display area F, the gates 131 of any two adjacent thin-film transistors 12 are connected to different electrical signals. Specifically, in the direction from the display area X to the non-display area F, the gates 131 of N thin-film transistors 12 are connected one-to-one with the first electrical signal to the Nth electrical signal; that is, the gates 131 of the N thin-film transistors 12 are sequentially connected to the first electrical signal, the second electrical signal, ..., the (N-1)th electrical signal, and the Nth electrical signal. In other words, in this embodiment, the gate 131 of the thin-film transistor 12 closest to the display area X is connected to the first electrical signal, while the gate 131 of the thin-film transistor 12 furthest from the display area X, i.e., closest to the edge, is connected to the Nth electrical signal. In a specific embodiment, the first electrical signal is SW1, the second electrical signal is SW2, and so on, with the (N-1)th electrical signal being SW(N-1) and the Nth electrical signal being SWN. In this embodiment, in the direction from the display area X to the non-display area F, the gates 131 of any two adjacent thin-film transistors 12 are connected to different electrical signals, which can divide the multiple thin-film transistors 12 into N groups. The thin-film transistors 12 in different groups are controlled by different electrical signals. The conduction state of multiple groups of thin-film transistors 12 can be controlled independently, so that the display panel 100 can have multiple different corrosion resistance gradients, thereby facilitating the satisfaction of more corrosion resistance requirements and effectively avoiding energy waste while ensuring corrosion resistance.

[0125] For example, such as Figures 16 to 19 As shown, two thin-film transistors 12 are disposed in the direction from the display area X to the non-display area F, that is, the value of N is two. The multiple thin-film transistors 12 in the non-display area F of the array substrate 1 can be divided into two groups, each group having multiple thin-film transistors 12 distributed circumferentially along the array substrate 1. Each side of the array substrate 1 has two rows of thin-film transistors 12. In the direction from the display area X to the non-display area F, the gates 131 of adjacent rows of thin-film transistors 12 are spaced apart. In the direction from the display area X to the non-display area F, the gates 131 of the multiple thin-film transistors 12 in the first row are all connected to a first electrical signal, specifically, the first electrical signal is the SW1 signal. The gates 131 of the multiple thin-film transistors 12 in the second row are all connected to a second electrical signal, the second electrical signal is the SW2 signal. The gates 131 of the two sets of thin-film transistors 12 are respectively connected to the first electrical signal and the second electrical signal. The two sets of thin-film transistors 12 can be independently controlled by the first electrical signal and the second electrical signal, and the conduction state of the two sets of thin-film transistors 12 can be independently controlled, thereby facilitating the satisfaction of different corrosion resistance requirements.

[0126] In some implementations, such as Figure 17 and Figure 18As shown, in the direction from the display area X to the non-display area F, in any two adjacent thin-film transistors 12, the second electrode 163 of the thin-film transistor 12 on the side furthest from the display area X is electrically connected to the first electrode 162 of the thin-film transistor 12 on the side closest to the display area X. In the direction from the display area X to the non-display area F, except for the second electrode 163 of the thin-film transistor 12 closest to the display area X, which is electrically connected to the common electrode trace 132 of the first metal layer 13, the first electrodes 162 and second electrodes 163 of the other thin-film transistors 12 are not electrically connected to the common electrode trace 132 to ensure that the common electrode trace 132 is not corroded and to prevent corrosion from spreading to the display area X. With the above configuration, since the second electrode 163 of the thin-film transistor 12 closest to the display area X is electrically connected to the common electrode trace 132 through the second conductive portion 182 via, and the common electrode trace 132 is connected to the VCOM signal, the second electrode 163 of the thin-film transistor 12 closest to the display area X is also connected to the VCOM signal. After the thin-film transistor 12 closest to the display area X is turned on, that is, after the multiple thin-film transistors 12 connected to the first electrical signal are turned on, the VCOM signal of its second electrode 163 is transmitted to the first electrode 162 through the active layer 151.

[0127] Since the second electrode 163 of any two adjacent thin-film transistors 12, located away from the display area X, is electrically connected to the first electrode 162 of the thin-film transistor 12 located closer to the display area X, the VCOM signal at the first electrode 162 of the thin-film transistor 12 closest to the display area X (i.e., the thin-film transistor 12 connected to the first electrical signal) is transmitted to the second electrode 163 of the next thin-film transistor 12 electrically connected to it (i.e., the thin-film transistor 12 connected to the second electrical signal). When the temperature or humidity of the display panel 100 is high, and moisture is more likely to diffuse and cause corrosion, and the display panel 100 requires strong corrosion resistance, the multiple thin-film transistors 12 connected to the first electrical signal can be turned on first, followed by the multiple thin-film transistors 12 connected to the second electrical signal. After the thin-film transistor 12 connected to the second electrical signal is turned on, the VCOM signal of its second electrode 163 is transmitted through its active layer 151 to its first electrode 162. This process can be repeated to control the sequential turning on of N rows of thin-film transistors 12 along the direction from the display area X to the non-display area F.

[0128] Specifically, in this embodiment, since only the second electrode 163 of the thin-film transistor 12 closest to the display area X, i.e., the thin-film transistor 12 connected to the first electrical signal, is electrically connected to the common electrode trace 132 through the second conductive portion 182 via, and in the direction from the display area X to the non-display area F, among two adjacent thin-film transistors 12, the second electrode 163 of the thin-film transistor 12 furthest from the display area X is electrically connected to the first electrode 162 of the thin-film transistor 12 closest to the display area X, and the VCOM signal connected at the second electrode 163 of the thin-film transistor 12 is transmitted sequentially from the display area X to the non-display area F, in this embodiment, it is necessary to first control the thin-film transistor 12 closest to the display area X, i.e., the thin-film transistor 12 connected to the first electrical signal, to be turned on, and then, based on the conduction of the thin-film transistor 12 connected to the first electrical signal, further control the remaining thin-film transistors 12 from the display area X to the non-display area F to be turned on sequentially, so that the display panel 100 can have different corrosion resistance capabilities.

[0129] For example, such as Figure 19 As shown, in this embodiment, only the multiple thin-film transistors 12 connected to the first electrical signal can be turned on, so that the first electrode 162 of the multiple thin-film transistors 12 connected to the first electrical signal reacts with water vapor and corrodes, thereby consuming the water vapor. If water vapor remains after the first electrode 162 of the multiple thin-film transistors 12 connected to the first electrical signal is corroded, or if the temperature or humidity of the display panel 100 is high and the first electrode 162 of the multiple thin-film transistors 12 connected to the first electrical signal cannot meet the corrosion resistance requirements, the multiple thin-film transistors 12 connected to the first electrical signal and the multiple thin-film transistors 12 connected to the second electrical signal can be turned on simultaneously, so that the first electrode 162 of both the multiple thin-film transistors 12 connected to the first electrical signal and the multiple thin-film transistors 12 connected to the second electrical signal can have the ability to consume water vapor. The water vapor can react with the first electrode 162 of the multiple thin-film transistors 12 connected to the second electrical signal on the side away from the display area X and be consumed first, thereby more effectively preventing water vapor from spreading to the display area X and meeting different usage requirements.

[0130] Because of the above-described connection method of the thin-film transistors 12 in this embodiment, it is not possible to control the conduction of only the multiple thin-film transistors 12 connected to the second electrical signal. If the multiple thin-film transistors 12 connected to the first electrical signal are not conducted, the VCOM signal cannot be effectively transmitted to the second electrode 163 of the multiple thin-film transistors 12 connected to the second electrical signal. Therefore, there is no electrical signal at the second electrode 163 of the multiple thin-film transistors 12 connected to the second electrical signal. Consequently, the first electrode 162 of the multiple thin-film transistors 12 connected to the second electrical signal will also be unable to undergo an effective electrochemical reaction with water vapor and the first conductive part 181, and water vapor will not be effectively consumed.

[0131] In one specific implementation, such as Figure 17 As shown, in the direction from the display area X to the non-display area F, among two adjacent thin-film transistors 12, the second electrode 163 of the thin-film transistor 12 on the side away from the display area X is electrically connected to the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X. That is, the second electrode 163 of the thin-film transistor 12 on the side away from the display area X is directly connected to the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X, and the second electrode 163 of the thin-film transistor 12 on the side away from the display area X and the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X belong to a continuous extension of the same film.

[0132] In this embodiment, in the direction from the non-display area F to the display area X, the second conductive portion 182 corresponding to the thin film transistor 12 on the side away from the display area X is electrically connected to the first conductive portion 181 corresponding to the thin film transistor 12 on the side closer to the display area X, and is electrically connected to the second electrode 163 and the first electrode 162 of the corresponding two adjacent thin film transistors 12 through a via, so that water vapor can react with the second electrode 163 and the first electrode 162 of the two adjacent thin film transistors 12 at the via at the connection position of the second electrode 163 and the first electrode 162 of the two adjacent thin film transistors 12, thereby consuming water vapor.

[0133] In another specific implementation, such as Figure 18As shown, in the direction from the display area X to the non-display area F, among two adjacent thin-film transistors 12, the second electrode 163 of the thin-film transistor 12 on the side away from the display area X is spaced apart from the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X. That is, the second electrode 163 of the thin-film transistor 12 on the side away from the display area X and the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X are not in direct contact. Specifically, in this embodiment, the passivation layer 17 has vias at the positions corresponding to the second electrode 163 of the thin-film transistor 12 on the side away from the display area X and the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X. The second conductive portion 182 corresponding to the thin-film transistor 12 on the side away from the display area X is in contact with and electrically connected to the first conductive portion 181 corresponding to the thin-film transistor 12 on the side closer to the display area X, and extends into the corresponding vias. The second electrode 163 of the thin film transistor 12 on the side away from the display area X is electrically connected to the first electrode 162 of the thin film transistor 12 on the side close to the display area X through a second conductive portion 182 and a first conductive portion 181 that are interconnected and extend into the corresponding vias, respectively.

[0134] It can be understood that, in the direction from the display area X to the non-display area F, the second electrode 163 of the thin film transistor 12 on the side away from the display area X and the first electrode 162 of the thin film transistor 12 on the side closer to the display area X are spaced apart from each other and are not directly connected. They are only electrically connected through the first transparent conductive layer 18. This can further slow down the rate at which water vapor diffuses to the first electrode 162 of the thin film transistor 12 on the side closer to the display area X, thereby more effectively preventing water vapor from diffusing to the display area X.

[0135] In other implementations, such as Figure 16 and Figure 20 , Figure 21 As shown, N thin-film transistors 12 are disposed in the direction from the non-display area F to the display area X, where N is a positive integer greater than 1. For example, N can take any positive integer value such as two, three, four, five, or six. In this embodiment, multiple thin-film transistors 12 can still be disposed along the circumference of the array substrate 1. The multiple thin-film transistors 12 in the non-display area F of the array substrate 1 can be divided into N groups, each group having multiple thin-film transistors 12 distributed along the circumference of the array substrate 1. That is, each side of the array substrate 1 is correspondingly provided with N rows of thin-film transistors 12, and each row of thin-film transistors 12 is provided with multiple thin-film transistors 12. In other embodiments, the multiple thin-film transistors 12 can also be disposed only along the direction from the non-display area F to the display area X, without multiple thin-film transistors 12 disposed along the circumference of the array substrate 1.

[0136] In the direction from the non-display area F to the display area X, the gates 131 of any two adjacent thin-film transistors 12 are spaced apart and connected to different electrical signals. Specifically, in this embodiment, in the direction from the non-display area F to the display area X, the gates 131 of N thin-film transistors 12 are connected one-to-one with the first electrical signal to the Nth electrical signal. That is, the gates 131 of the N thin-film transistors are sequentially connected to the first electrical signal, the second electrical signal, ..., the (N-1)th electrical signal, and the Nth electrical signal. In other words, in this embodiment, the gate 131 of the thin-film transistor 12 closest to the display area X is connected to the Nth electrical signal, while the gate 131 of the thin-film transistor 12 furthest from the display area X, i.e., closest to the edge, is connected to the first electrical signal. Specifically, the first electrical signal is SW1, the second electrical signal is SW2, and so on, the (N-1)th electrical signal is SW(N-1), and the Nth electrical signal is SWN.

[0137] like Figure 20 and Figure 21 As shown, in this embodiment, in the direction from the non-display area F to the display area X, in any two adjacent thin-film transistors 12, the second electrode 163 of the thin-film transistor 12 on the side away from the display area X is not electrically connected to the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X. That is, the second electrode 163 of the thin-film transistor 12 on the side away from the display area X and the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X are spaced apart from each other and are not electrically connected to each other through the first transparent conductive layer 18.

[0138] In this embodiment, in the direction from the non-display area F to the display area X, only the gate 131 of the thin-film transistor 12 of the Nth electrical signal is connected to the second electrode 163. That is, only the second electrode 163 of the thin-film transistor 12 closest to the display area X is electrically connected to the common electrode trace 132 through the corresponding second conductive portion 182 via. The second electrodes 163 of the remaining thin-film transistors 12 are electrically connected to the corresponding gate 131, i.e., the metal electrode trace 133, through the corresponding second conductive portion 182 via. In this embodiment, in the direction from the non-display area F to the display area X, the gate 131, first electrode 162, and second electrode 163 of each thin-film transistor 12 are spaced apart from each other and are not electrically connected. Each thin-film transistor 12 can be independently controlled. Through the above arrangement, multiple thin-film transistors 12 in the direction from the non-display area F to the display area X can be independently controlled. The conduction state of multiple thin-film transistors 12 can be specifically controlled as needed, so that the display panel 100 can have different corrosion resistance capabilities, thereby meeting different usage requirements.

[0139] For example, such as Figure 20 and Figure 21As shown, two thin-film transistors 12 are disposed in the direction from the non-display area F to the display area X, that is, the value of N is two. The multiple thin-film transistors 12 in the non-display area F of the array substrate 1 can be divided into two groups, each group having multiple thin-film transistors 12 distributed circumferentially along the array substrate 1, and each side of the array substrate 1 has two rows of thin-film transistors 12. In the direction from the non-display area F to the display area X, the gates 131 of adjacent rows of thin-film transistors 12 are spaced apart from each other. The gates 131 of the multiple thin-film transistors 12 in the first row, that is, the ones closest to the edge, are all connected to a first electrical signal, which is the SW1 signal. The second electrodes 163 of the multiple thin-film transistors 12 in the first row are electrically connected to the corresponding gates 131 through the corresponding second conductive portions 182 vias. That is, the second electrodes 163 of the multiple thin-film transistors 12 in the first row are also connected to the SW1 signal, and their gates 131 and second electrodes 163 are connected to the same electrical signal. When the multiple thin-film transistors 12 in the first row are turned on, the SW1 signal of their second electrode 163 is transmitted to their first electrode 162 through the active layer 151, causing an electrochemical reaction between the first electrode 162, water vapor, and the corresponding first conductive portion 181, thus consuming the water vapor. The gates 131 of the multiple thin-film transistors 12 in the second row, closest to the display area X, are all connected to a second electrical signal, which is the SW2 signal. The second electrodes 163 of the multiple thin-film transistors 12 in the second row are connected to the common electrode trace 132, meaning the second electrodes 163 of the multiple thin-film transistors 12 in the second row are connected to the VCOM signal. Since the gates 131 and second electrodes 163 of the thin-film transistors 12 in the second row are connected to different electrical signals, the thin-film transistors 12 are more easily turned on. When the multiple thin-film transistors 12 in the second row are turned on, the VCOM signal connected to their second electrode 163 is transmitted to their first electrode 162 through the active layer 151, causing an electrochemical reaction between the first electrode 162, water vapor, and the corresponding first conductive portion 181, thus consuming the water vapor. In other implementations, N can also be any positive integer greater than two.

[0140] Specifically, in this embodiment, in the direction from the non-display area F to the display area X, the second electrode 163 of any two adjacent thin-film transistors 12, on the side farther from the display area X, is not electrically connected to the first electrode 162 of the thin-film transistor 12 on the side closer to the display area X. Furthermore, except for the thin-film transistor 12 closest to the display area X, the second electrodes 163 of the remaining thin-film transistors 12 are electrically connected to the corresponding gate 131 (i.e., the metal electrode trace 133) through the corresponding second conductive portion 182 via. The gate 131 of each row of thin-film transistors 12 can be independently controlled, and the second electrodes 163 of each row of thin-film transistors 12 are connected to different electrical signals. Therefore, the conduction of each row of thin-film transistors 12 and the transmission of the electrical signal from its second electrode 163 to the first electrode 162 do not affect each other. Thus, the conduction of each row of thin-film transistors 12 can be independently controlled, without needing to conduct other thin-film transistors 12 on top of controlling the conduction of the thin-film transistor 12 closest to the display area X. For example, the thin-film transistor 12 connected to the first electrical signal can be turned on only, or the thin-film transistor 12 connected to the second electrical signal can be turned on only, or the thin-film transistor 12 connected to the first electrical signal and the thin-film transistor 12 connected to the second electrical signal can be turned on simultaneously, which can be designed as needed.

[0141] In one embodiment, the thin-film transistor 12 connected to the first electrical signal that is furthest from the display area X (i.e., closest to the edge) can be turned on first. This allows the first electrode 162 of the thin-film transistor 12 connected to the first electrical signal to react with and consume the moisture, thereby more effectively preventing moisture from diffusing towards the display area X. When the temperature or humidity of the display panel 100 is high, moisture is more likely to diffuse and cause corrosion. When the display panel 100 requires strong corrosion resistance, any other row or multiple rows of thin-film transistors 12 can be turned on simultaneously. This effectively increases the corrosion path and corrosion area of ​​the moisture, thereby improving the corrosion resistance of the display panel 100.

[0142] In one specific embodiment, the thin-film transistors 12 connected to the first electrical signal to the Nth electrical signal can be turned on sequentially. That is, multiple thin-film transistors 12 can be turned on sequentially along the direction from the non-display area F to the display area X. The thin-film transistors 12 near the edge can be turned on first, so that the corrosion path of water vapor can extend sequentially from the edge to the display area X. Most of the water vapor can be consumed near the edge, thereby more effectively preventing water vapor from spreading to the display area X and more effectively preventing the common electrode trace 132 and the other metal traces of the display area X from being corroded.

[0143] In this embodiment, from the non-display area F to the display area X, the gates 131 and electrode layers 161 of the N thin-film transistors are disconnected from each other. The multiple thin-film transistors 12 in the non-display area F can each serve as independent consumption paths, which is beneficial to increasing the water vapor consumption path and the metal area that can absorb water vapor, thereby further improving the water vapor consumption rate. Moreover, after the gate 131 and electrode layer 161 of a single thin-film transistor 12 are corroded, it will not affect other thin-film transistors 12. Water vapor is less likely to diffuse towards the display area X, which is more conducive to enhancing the corrosion resistance of the display panel 100 and more effectively preventing water vapor from diffusing towards the second electrode 163 and the common electrode trace 132 of the thin-film transistor 12 closest to the display area X, thus effectively preventing the common electrode trace 132 from being corroded.

[0144] See Figure 1 , Figure 2 , Figure 5 , Figure 13 and Figure 15 In some embodiments, the array substrate 1 includes a first metal layer 13, an insulating layer 14, a semiconductor layer 15, and a second metal layer 16 stacked sequentially. The first metal layer 13 includes a common electrode trace 132 and a plurality of gate electrodes 131, i.e., metal electrode traces 133. The insulating layer 14 includes a plurality of gate insulating layers 141, which are interconnected and cover the first metal layer 13. The semiconductor layer 15 includes a plurality of active layers 151, which are spaced apart from each other. The second metal layer 16 includes a plurality of electrode layers 161, and a passivation layer 17 covers the second metal layer 16.

[0145] The non-display area F includes a first protection zone F1 and a second protection zone F2. The second protection zone F2 is located on the side of the first protection zone F1 that is close to the display area X. The thin film transistor 12 of the array substrate 1 is located in the second protection zone F2. That is, the thin film transistor 12 is not disposed in the first protection zone F1.

[0146] For details, see Figure 2 , Figure 5 , Figure 13 and Figure 15The second metal layer 16 also includes a protective metal 164 disposed in the first protective zone F1, and the first transparent conductive layer 18 also includes a third conductive portion 183 disposed in the first protective zone F1. The protective metal 164 is disposed at a distance from the electrode layer 161, and the first conductive portion 181 and the second conductive portion 182 are both disposed at a distance from the third conductive portion 183. The third conductive portion 183 and the protective metal 164 are electrically connected through a via. It is understood that by setting the thin-film transistor 12 in the second protection zone F2, further setting the first protection zone F1 on the side of the second protection zone F2 away from the display area X, and setting a protective metal 164 independent of the electrode layer 161 and a third conductive part 183 independent of the first conductive part 181 and the second conductive part 182 in the first protection zone F1, and electrically connecting the third conductive part 183 with the through hole of the protective metal 164, when water vapor enters the display panel 100, it can react with the protective metal 164 and the third conductive part 183 located in the outermost first protection zone F1 at the through hole position. The water vapor first corrodes the protective metal 164 and the third conductive part 183, thereby further enhancing the corrosion resistance of the display panel 100. Most of the water vapor is first consumed and absorbed by the protective metal 164 and the third conductive part 183 in the first protection zone F1, and is less likely to diffuse to the display area X side, effectively preventing the first metal layer 13 and other components in the display area X from being corroded.

[0147] In one specific implementation, such as Figure 2 and Figure 5 As shown, the gate 131 of the thin-film transistor 12, i.e. the metal electrode trace 133, does not need to extend into the first protection zone F1. The first metal layer 13 does not need to be provided in the first protection zone F1. The water vapor can be consumed directly by reacting with the protective metal 164 and the third conductive part 183 at the via location.

[0148] In another specific implementation, such as Figure 13 and Figure 15 As shown, the first metal layer 13 also includes a sacrificial metal 134 disposed in the first protected area F1. The sacrificial metal 134 can be connected to the gate 131 of the thin-film transistor 12 closest to the edge of the display panel 100, or the sacrificial metal 134 can be disposed at a distance from the gate 131 of the thin-film transistor 12. That is, the sacrificial metal 134 can be formed by extending the gate 131 of the thin-film transistor 12 closest to the edge into the first protected area F1, or it can be a metal trace disposed independently of the gate 131 of the thin-film transistor 12, which can be designed as needed. In this embodiment, the third conductive portion 183 can also be electrically connected to the sacrificial metal 134 through a via contact.

[0149] It is understandable that sacrificial metal 134 and protective metal 164 are simultaneously installed in the first protection zone F1. The third conductive part 183 is electrically connected to both sacrificial metal 134 and protective metal 164 through holes. Most of the water vapor can be consumed and absorbed by the protective metal 164, sacrificial metal 134 and third conductive part 183 in the first protection zone F1, which is more conducive to increasing the corrosion path and corrosion area of ​​water vapor and further enhancing the consumption rate of water vapor. Moreover, the protective metal 164 is set on top of the sacrificial metal 134. The heat generated by the sacrificial metal 134 can heat the protective metal 164 located on top of it in the first protection zone F1, which is more conducive to accelerating the reaction of water vapor with the protective metal 164 and the third conductive part 183, and is more conducive to accelerating the consumption of water vapor, thereby further preventing water vapor from spreading to the display area X side.

[0150] See Figures 22 to 23 , Figure 22 This is a schematic diagram of an embodiment of the display device provided in the second embodiment of this application. Figure 23 This is a schematic diagram of another embodiment of the display device provided in the second embodiment of this application.

[0151] See Figure 22 and Figure 23 The second embodiment of this application provides a display device 400, which includes a display panel 100 and a backlight module 200. The backlight module 200 is disposed on one side of the display panel 100 and is used to provide backlight for the display panel 100 so that the display panel 100 can realize the screen display function.

[0152] Specifically, the specific structure of the display panel 100 can be any of the display panels 100 described in the above embodiments, and can be designed or selected as needed.

[0153] In some implementations, see Figure 23 The display panel 100 includes a temperature sensor 5, and the display device 400 also includes a control circuit 300. The temperature sensor 5 is disposed on the array substrate 1 and is used to detect the temperature of the common electrode trace 132 of the first metal layer 13 of the array substrate 1. The control circuit 300 is electrically connected to the temperature sensor 5 and the gates 131 of the plurality of thin film transistors 12. The control circuit 300 is used to control the on / off state of the thin film transistors 12 according to the temperature of the common electrode trace 132 detected by the temperature sensor 5.

[0154] In some embodiments, the display panel 100 can be as follows: Figures 9 to 12In any of the display panels 100 shown, specifically, a plurality of thin-film transistors 12 are arranged along the circumference of the array substrate 1. Among the plurality of thin-film transistors 12, the gates 131 of the odd-numbered thin-film transistors 12 are electrically connected to each other and are all connected to a first electrical signal (i.e., SW1 signal), while the gates 131 of the even-numbered thin-film transistors 12 are electrically connected to each other and are all connected to a second electrical signal (i.e., SW2 signal). The second electrodes 163 of the plurality of thin-film transistors 12 are all electrically connected to a common electrode trace 132. In one specific embodiment, as shown... Figure 12 As shown, the first electrodes 162 of the plurality of thin-film transistors 12 are electrically connected to each other, or, in another specific embodiment, as Figure 9 As shown, the first electrodes 162 of any two adjacent thin-film transistors 12 are spaced apart from each other. Among the multiple thin-film transistors 12, the first electrodes 162 of the odd-numbered thin-film transistors 12 are electrically connected to each other, and the first electrodes 162 of the even-numbered thin-film transistors 12 are electrically connected to each other.

[0155] Specifically, in one embodiment, the control circuit is configured to turn off all thin-film transistors 12 in response to the temperature of the common electrode trace 132 being less than or equal to a first preset threshold. And / or, in some embodiments, the control circuit is configured to turn on a plurality of thin-film transistors 12 connected to a first electrical signal and turn off a plurality of thin-film transistors 12 connected to a second electrical signal in response to the temperature of the common electrode trace 132 being greater than the first preset threshold and less than or equal to a second preset threshold, wherein the second preset threshold is greater than the first preset threshold. And / or, in some embodiments, the control circuit is configured to turn on both a plurality of thin-film transistors 12 connected to the first electrical signal and a plurality of thin-film transistors 12 connected to the second electrical signal in response to the temperature of the common electrode trace 132 being greater than the second preset threshold. Specifically, the specific values ​​or ranges of the first and second preset thresholds can be set based on experience or actual needs.

[0156] Through the above settings, the conduction states of multiple thin-film transistors 12 connected to the first electrical signal and multiple thin-film transistors 12 connected to the second electrical signal can be controlled separately. This allows for the control of different numbers of thin-film transistors 12 to conduct when the common electrode trace 132 is at different temperature thresholds. This facilitates the implementation of different moisture consumption paths and rates at different temperatures, meeting various corrosion resistance requirements. Consequently, the display panel 100 can have different corrosion resistance gradients, ensuring that more thin-film transistors 12 are conducted at higher temperatures, faster moisture diffusion rates, and faster corrosion rates. Furthermore, the first electrodes 162 of multiple thin-film transistors 12 collectively consume moisture, preventing moisture from diffusing towards the X side of the display. Under conditions where the temperature is not high but moisture diffusion and corrosion still occur, controlling only a portion of the thin-film transistors 12 to conduct, and using only the first electrodes 162 of those transistors to consume moisture, can meet the corrosion resistance requirements within that temperature range, avoiding unnecessary energy waste caused by all thin-film transistors 12 being turned on. Conversely, at lower temperatures, where moisture diffusion is less likely and corrosion is less probable, all thin-film transistors 12 can be turned off to avoid energy waste. Through this method, the corrosion resistance can be more intelligently and effectively controlled based on the temperature of the common electrode trace 132 of the display panel 100, meeting different usage requirements.

[0157] In some embodiments, the display panel 100 can be as follows: Figures 16 to 21 In any of the display panels 100 shown, specifically, N thin-film transistors 12 are arranged in the direction from the non-display area F to the display area X, where N is a positive integer greater than 1. For example, N can take any positive integer value such as two, three, four, five, or six. In the direction from the non-display area F to the display area X, the gates 131 of any two adjacent thin-film transistors 12 are arranged at intervals and connected to different electrical signals.

[0158] Specifically, in one embodiment, the control circuit is used to control all thin-film transistors 12 to turn off in response to the temperature of the common electrode trace 132 being less than or equal to a first preset threshold.

[0159] And / or, in some embodiments, the control circuit is used to, in response to the temperature of the common electrode trace 132 being greater than a (M-1)th preset threshold and less than or equal to an Mth preset threshold, control the thin-film transistor 12 connected to the first electrical signal to the (M-1)th electrical signal to be turned on, and control the thin-film transistor 12 connected to the Mth electrical signal to the Nth electrical signal to be turned off; wherein M is a positive integer greater than or equal to 2 and less than or equal to N, and the first preset threshold to the Nth preset threshold increase sequentially. For example, M can be any positive integer such as 2, 3, 4, 5, (N-2), (N-1), N, etc. That is, in response to the temperature of the common electrode trace 132 being greater than a first preset threshold and less than or equal to a second preset threshold, the thin-film transistor 12 connected to the first electrical signal is turned on, and the thin-film transistors 12 connected to the second electrical signal to the Nth electrical signal are turned off; and so on, in response to the temperature of the common electrode trace 132 being greater than a (N-1)th preset threshold and less than or equal to the Nth preset threshold, the thin-film transistors 12 connected to the first electrical signal to the (N-1)th electrical signal are turned on, and the thin-film transistor 12 connected to the Nth electrical signal is turned off. Wherein, the first preset threshold is less than the second preset threshold, the second preset threshold is less than the third preset threshold, and so on, with the (N-1)th preset threshold being less than the Nth preset threshold.

[0160] And / or, in some embodiments, the control circuit is used to control all thin-film transistors 12 connected to the first electrical signal to the Nth electrical signal to conduct in response to the temperature of the common electrode trace 132 being greater than the Nth preset threshold. It is understood that the above arrangement allows N rows of thin-film transistors 12 to conduct as needed under N different temperature ranges along the direction from the non-display area F to the display area X, thereby meeting more diverse corrosion resistance requirements and giving the display panel 100 more gradients in corrosion resistance. This facilitates smarter, more precise, and more efficient moisture consumption, improving the corrosion resistance of the display panel 100. Specifically, the specific values ​​or ranges of the first preset threshold to the Nth preset threshold can be set based on experience or actual needs.

[0161] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display panel, comprising an array substrate and a counter substrate disposed opposite to each other, and a frame adhesive connecting the array substrate and the counter substrate; the display panel comprising a display area and a non-display area disposed around the periphery of the display area; characterized in that, The array substrate includes a substrate and a plurality of thin-film transistors disposed on one side of the substrate, the plurality of thin-film transistors being disposed in the non-display area; each thin-film transistor includes a gate, a gate insulating layer, an active layer and an electrode layer stacked sequentially; the electrode layer includes a first electrode and a second electrode spaced apart from each other, the second electrode being located on the side of the first electrode closer to the display area; one of the first electrode and the second electrode is a source electrode and the other is a drain electrode; The array substrate includes a first metal layer and a second metal layer; the first metal layer is located between the gate insulating layer and the substrate; the first metal layer includes a common electrode trace and a metal electrode trace spaced apart from each other, the metal electrode trace is located on the side of the common electrode trace away from the display area, the metal electrode trace is disposed corresponding to the active layer and forms the gate; the common electrode trace is connected to a different electrical signal from the gate; the second metal layer includes the electrode layer; The array substrate further includes a passivation layer and a first transparent conductive layer sequentially disposed on the side of the electrode layer away from the substrate. The passivation layer covers the plurality of thin film transistors. The first transparent conductive layer includes a first conductive portion and a second conductive portion spaced apart from each other. The first conductive portion is disposed corresponding to the first electrode and is electrically connected to the first electrode through a via. The second conductive portion is disposed corresponding to the second electrode and is electrically connected to the second electrode through a via. In the direction from the non-display area to the display area, the second electrode of the thin-film transistor closest to the display area is electrically connected to the common electrode trace through a corresponding second conductive via. The substrate includes a second transparent conductive layer, which is electrically connected to the second conductive portion corresponding to the thin-film transistor closest to the display area.

2. The display panel according to claim 1, characterized in that, The first electrode is not electrically connected to the metal electrode trace; or... The first electrode is electrically connected to the metal electrode trace through the first conductive portion via.

3. The display panel according to claim 1, characterized in that, The plurality of thin-film transistors are arranged along the circumferential direction of the array substrate; The gates of the plurality of thin-film transistors are electrically connected to each other; and / or, the second electrodes of the plurality of thin-film transistors are electrically connected to each other and are all electrically connected to the common electrode trace; And / or, the first electrodes of the plurality of thin-film transistors are electrically connected to each other.

4. The display panel according to claim 1, characterized in that, The plurality of thin-film transistors are arranged along the circumferential direction of the array substrate; In the plurality of thin-film transistors, the gates of the odd-numbered thin-film transistors are electrically connected to each other and connected to a first electrical signal; the gates of the even-numbered thin-film transistors are electrically connected to each other and connected to a second electrical signal. The second electrodes of the plurality of thin-film transistors are all electrically connected to the common electrode trace; The first electrodes of the plurality of thin-film transistors are electrically connected to each other; or, the first electrodes of any two adjacent thin-film transistors are spaced apart from each other, and among the plurality of thin-film transistors, the first electrodes of the odd-numbered thin-film transistors are electrically connected to each other, and the first electrodes of the even-numbered thin-film transistors are electrically connected to each other.

5. The display panel according to claim 1, characterized in that, N thin-film transistors are disposed in the direction from the display area to the non-display area, where N is a positive integer greater than 1; In the direction from the display area to the non-display area, the gates of any two adjacent thin-film transistors are spaced apart from each other and connected to different electrical signals; wherein, in the direction from the display area to the non-display area, the gates of N thin-film transistors are connected to the first electrical signal to the Nth electrical signal in a one-to-one correspondence. In the direction from the display area to the non-display area, in any two adjacent thin-film transistors, the second electrode of the thin-film transistor on the side away from the display area is electrically connected to the first electrode of the thin-film transistor on the side closer to the display area.

6. The display panel according to claim 1, characterized in that, N thin-film transistors are disposed in the direction from the non-display area to the display area, where N is a positive integer greater than 1; In the direction from the non-display area to the display area, the gates of any two adjacent thin-film transistors are spaced apart from each other and connected to different electrical signals; wherein, in the direction from the non-display area to the display area, the gates of N thin-film transistors are connected to the first electrical signal to the Nth electrical signal in a one-to-one correspondence. In the direction from the non-display area to the display area, in any two adjacent thin-film transistors, the second electrode of the thin-film transistor on the side away from the display area is not electrically connected to the first electrode of the thin-film transistor on the side closer to the display area. In the direction from the non-display area to the display area, only the second electrode of the thin-film transistor whose gate is connected to the Nth electrical signal is electrically connected to the common electrode trace through the corresponding second conductive portion via; the second electrodes of the remaining thin-film transistors are electrically connected to the corresponding gate through the corresponding second conductive portion via.

7. The display panel according to any one of claims 1-6, characterized in that, The array substrate includes a first metal layer, an insulating layer, a semiconductor layer, and a second metal layer stacked sequentially; the first metal layer includes the common electrode trace and a plurality of gate electrodes; the insulating layer includes a plurality of interconnected gate insulating layers and covers the first metal layer; the semiconductor layer includes a plurality of spaced-apart active layers; the second metal layer includes a plurality of electrode layers; and the passivation layer covers the second metal layer. The non-display area includes a first protection zone and a second protection zone, with the second protection zone located on the side of the first protection zone closer to the display area; the thin-film transistor is located in the second protection zone. The second metal layer further includes a protective metal disposed in the first protected area, and the first transparent conductive layer further includes a third conductive portion disposed in the first protected area; the protective metal is spaced apart from the electrode layer, and the first conductive portion and the second conductive portion are spaced apart from the third conductive portion; the third conductive portion and the protective metal are electrically connected through a via.

8. The display panel according to claim 7, characterized in that, The first metal layer further includes a sacrificial metal disposed in the first protected area, the sacrificial metal being connected to the gate of the thin-film transistor closest to the edge of the display panel, or the sacrificial metal being spaced apart from the gate of the thin-film transistor; The third conductive portion is electrically connected to the sacrificial metal through a via contact.

9. A display device, characterized in that, include: The display panel as described in any one of claims 1-8; A backlight module is disposed on one side of the display panel and is used to provide backlight for the display panel.

10. The display device according to claim 9, characterized in that, It also includes temperature sensors and control circuitry; The temperature sensor is disposed on the array substrate and is used to detect the temperature of the common electrode trace; The control circuit is electrically connected to the temperature sensor and the gates of the plurality of thin-film transistors. The control circuit is used to control the on / off state of the thin-film transistors according to the temperature of the common electrode trace detected by the temperature sensor.

11. The display device according to claim 10, characterized in that, The display panel is the display panel as described in claim 4; The control circuit is used to control all the thin-film transistors to turn off in response to the temperature of the common electrode trace being less than or equal to a first preset threshold. And / or, in response to the temperature of the common electrode trace being greater than the first preset threshold and less than or equal to the second preset threshold, the plurality of thin-film transistors connected to the first electrical signal are controlled to turn on, and the plurality of thin-film transistors connected to the second electrical signal are controlled to turn off; wherein the second preset threshold is greater than the first preset threshold; And / or, in response to the temperature of the common electrode trace being greater than the second preset threshold, control the multiple thin-film transistors connected to the first electrical signal and the multiple thin-film transistors connected to the second electrical signal to be turned on.

12. The display device according to claim 10, characterized in that, The display panel is the display panel as described in claim 5 or 6; The control circuit is used to control all the thin-film transistors to turn off in response to the temperature of the common electrode trace being less than or equal to a first preset threshold. And / or, in response to the temperature of the common electrode trace being greater than a (M-1)th preset threshold and less than or equal to an Mth preset threshold, the thin-film transistors connected to the first electrical signal to the (M-1)th electrical signal are controlled to turn on, and the thin-film transistors connected to the Mth electrical signal to the Nth electrical signal are controlled to turn off; wherein, M is a positive integer greater than or equal to 2 and less than or equal to N; the first preset threshold to the Nth preset threshold increase sequentially; And / or, in response to the temperature of the common electrode trace being greater than the Nth preset threshold, control all of the thin-film transistors connected to the first electrical signal to the Nth electrical signal to be turned on.

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