Processor and cross-die access method for processor

Abstract

The present application relates to a processor and a cross-die access method for the processor. Based on the present application, cross-die access of any die of the processor to target data cached in another die can trigger replication of the target data from the another die to the die due to a miss detection of the target data in the die, and subsequent cross-die access of the die to the target data can be converted to in-die access to the target data replicated to the local cache of the die, so that the actual occurrence of cross-die access can be reduced. Moreover, when the target data cached in the another die is updated, the target data cached locally due to the replication can be deleted and replicated again due to a miss detection, so that the consistency of the target data in different dies can be taken into account. Furthermore, the efficiency of cross-die access in a processor packaged with at least two dies can be improved without loss of consistency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of artificial intelligence chips, in particular to a processor and a cross-die access method for the processor. BACKGROUND

[0002] Chiplet technology can package at least two dies as a processor, for example, as a processor with a SoC (System-on-Chip). Among them, the processor packaged with at least two dies can be referred to as a multi-die processor, and compared with the processor packaged with only one die, the processor packaged with at least two dies has higher computing power and storage capacity.

[0003] Specifically, in the processor packaged with at least two dies, each die has a processing core and a memory. Among them, the processing core of each die can not only access the memory of the die, but also realize cross-die access to the memory of other dies, that is, the memory of each die can be accessed by the processing core of all dies. Thus, multi-die fusion is realized.

[0004] However, the bandwidth of the D2D (Die to Die, die-to-die interconnect) bus between different dies is limited, thereby resulting in low efficiency of cross-die access.

[0005] As can be seen from the above, how to improve the efficiency of cross-die access in the processor packaged with at least two dies has become a technical problem to be solved in the related art. SUMMARY

[0006] The present application provides a processor and a cross-die access method for the processor, which helps to improve the efficiency of cross-die access in the processor packaged with at least two dies.

[0007] In an embodiment of the present application, a processor is provided, comprising:

[0008] a first die having a plurality of first-die-side processing cores and a plurality of first-die-side cache units, and a plurality of first-die-side main memories are respectively and one-to-one mapped to the plurality of first-die-side cache units;

[0009] a second die having a plurality of second-die-side processing cores and a plurality of second-die-side cache units, and a plurality of second-die-side main memories are respectively and one-to-one mapped to the plurality of second-die-side cache units;

[0010] The plurality of first die-side cache units and the plurality of second die-side cache units are configured to be one-to-one corresponding through a preset corresponding relationship between the plurality of first die-side main memories and the plurality of second die-side main memories, and any one of the first die-side cache units is configured to:

[0011] In response to a read request initiated by any one of the first die-side processing cores on the target data, performing hit detection on the target data in the address space of the corresponding first die-side main memory;

[0012] If the hit detection fails, a failure response is generated, which is used to copy and transport the target data to the first die-side cache unit when the access address of the target data is located in the address space of the corresponding second die-side main memory;

[0013] If the hit detection succeeds, a read response carrying the hit target data is generated, which is used to be transmitted to the first die-side processing core initiating the read request;

[0014] In response to data update of the target data in the address space of the corresponding second die-side main memory, the target data copied and transported to the first die-side cache unit is invalidated.

[0015] In some examples, optionally, the first die further has a cross-routing switch, and the cross-routing switch is configured to: route and forward, according to the access address of the target data, the read request initiated by any one of the first die-side processing cores to the corresponding first die-side cache unit; if any one of the first die-side cache units generates a failure response due to the hit detection failure on the target data and the access address of the target data is located in the address space of the corresponding second die-side main memory, route and forward the read request initiated on the target data to the corresponding second die-side cache unit, so that the target data is copied and transported from the corresponding second die-side cache unit to the first die-side cache unit; if any one of the first die-side cache units generates a read response due to the hit detection success on the target data, transmit the read response to the first die-side processing core initiating the request on the target data.

[0016] In some examples, optionally, any one of the second die-side cache units is configured to: in response to data update of the target data in the second die-side cache unit, generate an invalidation request to the corresponding first die-side cache unit, so that the corresponding first die-side cache unit invalidates the target data copied and transported from the second die-side cache unit to the corresponding first die-side cache unit according to the invalidation request generated by the second die-side cache unit.

[0017] In some examples, optionally, the first die and the second die are interconnected through a D2D bus, the copy migration of the target data is implemented through a cross-die transmission based on the D2D bus, and a monitoring bus independent of the D2D bus is further connected between the first die and the second die; any one of the second-die-side cache units is specifically configured to generate an invalidation request to the corresponding first-die-side cache unit through the monitoring bus.

[0018] In some examples, optionally, any one of the second-die-side cache units is further configured to, in response to completion of the copy migration of the target data, set a sharing identifier of the tag information corresponding to the target data and maintained in the second-die-side cache unit to an effective state; and in response to the target data being subjected to a data update in the second-die-side cache unit, set the sharing identifier of the tag information corresponding to the target data and maintained in the second-die-side cache unit to an ineffective state.

[0019] In some examples, optionally, any one of the second-die-side cache units is specifically configured to, in response to a state change of the sharing identifier of the tag information corresponding to the target data and maintained in the second-die-side cache unit from the effective state to the ineffective state, generate an invalidation request to the corresponding first-die-side cache unit.

[0020] In some examples, optionally, the target data is associated with a currently running kernel of the first-die-side processing core that initiates the read request; any one of the first-die-side cache units is further configured to, in response to termination of the running of the kernel associated with the target data, invalidate the target data copied to the first-die-side cache unit.

[0021] In some examples, optionally, any one of the first-die-side cache units is further configured to, in response to completion of the copy migration of the target data, set a copy identifier of the tag information corresponding to the target data and maintained in the first-die-side cache unit to an effective state; and in response to termination of the running of the kernel associated with the target data, invalidate the target data copied to the first-die-side cache unit according to the copy identifier in the effective state.

[0022] In some examples, optionally, the tag information corresponding to the target data and respectively maintained in the first-die-side cache units further includes a kernel identifier corresponding to the kernel associated with the target data, and the operation of invalidating the target data is further based on the kernel identifier.

[0023] In some examples, optionally, the target data is a plurality of target data, a plurality of tag information corresponding to the plurality of target data is respectively maintained in any one of the first-die-side cache units, and the operation of invalidating the target data includes invalidating the plurality of target data copied to the first-die-side cache unit in batches.

[0024] In some examples, optionally, any one of the second-die-side cache units is further configured to: in response to completion of the copy migration of the target data, set a sharing identifier of the tag information corresponding to the target data maintained in the second-die-side cache unit to an active state; and in response to the target data copied to the corresponding first-die-side cache unit being invalidated, set the sharing identifier of the tag information corresponding to the target data maintained in the second-die-side cache unit to an inactive state.

[0025] In some examples, optionally, any one of the first-die-side cache units is further configured to: in response to the target data copied to the first-die-side cache unit being invalidated, generate an invalidation request to the corresponding second-die-side cache unit, so that the corresponding second-die-side cache unit sets a sharing identifier of the tag information corresponding to the target data maintained in the corresponding second-die-side cache unit to an inactive state according to the invalidation request generated by the first-die-side cache unit.

[0026] In some examples, optionally, the first die and the second die are interconnected through a D2D bus, the copy migration of the target data is implemented through a cross-die transmission based on the D2D bus, and a monitoring bus independent of the D2D bus is further connected between the first die and the second die; any one of the first-die-side cache units is further configured to generate an invalidation request to the corresponding second-die-side cache unit through the monitoring bus.

[0027] In some examples, optionally, any one of the first-die-side cache units includes a main memory mapping region and a cross-die mapping region, the main memory mapping region of the first-die-side cache unit is used for address space mapping of the first-die-side main memory, and the cross-die mapping region of the first-die-side cache unit is independent of the main memory mapping region.

[0028] In another embodiment of the present application, a cross-die access method for a processor is provided, the processor including a first die and a second die, the first die having a plurality of first-die-side processing cores and a plurality of first-die-side cache units, a plurality of first-die-side main memories being one-to-one mapped to the plurality of first-die-side cache units respectively, the second die having a plurality of second-die-side processing cores and a plurality of second-die-side cache units, a plurality of second-die-side main memories being one-to-one mapped to the plurality of second-die-side cache units respectively, the plurality of first-die-side cache units and the plurality of second-die-side cache units being configured to be one-to-one corresponding through a preset corresponding relationship between the plurality of first-die-side main memories and the plurality of second-die-side main memories, and the cross-die access method including the following steps performed by any one of the first-die-side cache units:

[0029] in response to a read request initiated by any one of the first-die-side processing cores on the target data, performing a hit detection on the target data in the address space of the corresponding first-die-side main memory;

[0030] if the hit detection fails, generating a failure response, which is used to cause the target data to be copied and carried to the first-die-side cache unit when the access address of the target data is located in the address space of the corresponding second-die-side main memory;

[0031] if the hit detection succeeds, generating a read response carrying the hit target data, which is used to be transmitted to the first-die-side processing core that initiates the read request;

[0032] in response to a data update of the target data in the address space of the corresponding second-die-side main memory, invalidating the target data copied and carried to the first-die-side cache unit.

[0033] In some examples, optionally, the first die further has a cross-routing switch, and the cross-die access method further includes the following steps performed by the cross-routing switch: routing and forwarding, according to the access address of the target data, the read request initiated by any one of the first-die-side processing cores to the corresponding first-die-side cache unit; if any one of the first-die-side cache units generates a failure response due to a failure of the hit detection on the target data, and the access address of the target data is located in the address space of the corresponding second-die-side main memory, routing and forwarding the read request initiated on the target data to the corresponding second-die-side cache unit, so that the target data is copied and carried from the corresponding second-die-side cache unit to the first-die-side cache unit; if any one of the first-die-side cache units generates a read response due to a success of the hit detection on the target data, transmitting the read response to the first-die-side processing core that initiates the request on the target data.

[0034] In some examples, optionally, the cross-die access method further includes the following steps performed by any one of the second-die-side cache units: in response to a data update of the target data in the second-die-side cache unit, generating an invalidation request to the corresponding first-die-side cache unit, so that the corresponding first-die-side cache unit invalidates the target data copied and carried from the second-die-side cache unit to the corresponding first-die-side cache unit according to the invalidation request generated by the second-die-side cache unit.

[0035] In some examples, optionally, the first die and the second die are interconnected through a D2D bus, the copying and carrying of the target data is implemented through cross-die transmission based on the D2D bus, and a monitoring bus independent of the D2D bus is further connected between the first die and the second die; generating the invalidation request to the corresponding first-die-side cache unit includes generating the invalidation request to the corresponding first-die-side cache unit through the monitoring bus.

[0036] In some examples, optionally, the cross-die access method further comprises the following steps performed by any one of the second-die-side cache units: in response to the copy migration of the target data being completed, setting the sharing identifier of the tag information corresponding to the target data maintained in the second-die-side cache unit to an active state; and in response to the target data being updated by the execution data in the second-die-side cache unit, setting the sharing identifier of the tag information corresponding to the target data maintained in the second-die-side cache unit to an inactive state.

[0037] In some examples, optionally, in response to the data update of the target data in the second-die-side cache unit, generating the invalidation request to the corresponding first-die-side cache unit comprises: in response to the state change of the sharing identifier of the tag information corresponding to the target data maintained in the second-die-side cache unit from the active state to the inactive state, generating the invalidation request to the corresponding first-die-side cache unit.

[0038] In some examples, optionally, the target data is associated with a currently running kernel of the first-die-side processing core that initiates the read request; and the cross-die access method further comprises the following steps performed by any one of the first-die-side cache units: in response to the running of the kernel associated with the target data being ended, invalidating the target data copied to the first-die-side cache unit.

[0039] In some examples, optionally, the cross-die access method further comprises the following steps performed by any one of the first-die-side cache units: in response to the copy migration of the target data being completed, setting the copy identifier of the tag information corresponding to the target data maintained in the first-die-side cache unit to an active state; and in response to the running of the kernel associated with the target data being ended, invalidating the target data copied to the first-die-side cache unit according to the copy identifier in the active state.

[0040] In some examples, optionally, the tag information corresponding to the target data respectively maintained in the first-die-side cache units further comprises a kernel identifier corresponding to the kernel associated with the target data, and the operation of invalidating the target data is further based on the kernel identifier.

[0041] In some examples, optionally, the target data is a plurality of target data, a plurality of tag information corresponding to the plurality of target data respectively maintained in any one of the first-die-side cache units, and the operation of invalidating the target data comprises: invalidating the plurality of target data copied to the first-die-side cache unit in batches.

[0042] In some examples, optionally, the cross-die access method further comprises the following steps performed by any one of the second die-side cache units: in response to completion of the copy migration of the target data, setting the sharing identifier of the tag information corresponding to the target data maintained in the second die-side cache unit to an active state; and in response to the target data copied to the corresponding first die-side cache unit being invalidated, setting the sharing identifier of the tag information corresponding to the target data maintained in the second die-side cache unit to an inactive state.

[0043] In some examples, optionally, the cross-die access method further comprises the following steps performed by any one of the first die-side cache units: in response to the target data copied to the first die-side cache unit being invalidated, generating an invalidation request to the corresponding second die-side cache unit, so that the corresponding second die-side cache unit sets the sharing identifier of the tag information corresponding to the target data maintained in the corresponding second die-side cache unit to an inactive state according to the invalidation request generated by the first die-side cache unit.

[0044] In some examples, optionally, the first die and the second die are interconnected through a D2D bus, the copy migration of the target data is implemented through cross-die transmission based on the D2D bus, and a monitoring bus independent of the D2D bus is further connected between the first die and the second die; generating the invalidation request to the corresponding second die-side cache unit comprises generating the invalidation request to the corresponding second die-side cache unit through the monitoring bus.

[0045] In some examples, optionally, any one of the first die-side cache units comprises a main memory mapping region and a cross-die mapping region, the main memory mapping region of the first die-side cache unit is used for address space mapping of the first die-side main memory, and the cross-die mapping region of the first die-side cache unit is independent of the main memory mapping region.

[0046] As can be seen above, based on the embodiments of the present application, the cross-die access of any die of the processor to the target data cached in another die can cause the copy transfer of the target data from the other die to the die due to the miss detection of the target data in the die, and the subsequent cross-die access of the die to the target data can be converted into the in-die access to the target data copied to the local cache of the die, so that the actual occurrence of the cross-die access limited by the bandwidth of the D2D bus can be reduced. Moreover, when the target data cached in the other die is updated, the target data cached locally due to the copy transfer can be deleted, and thereafter, the target data updated can be copied again due to the miss detection, so that the coherency of the target data in different dies can be considered. Furthermore, the efficiency of the cross-die access in the processor with at least two dies can be improved without loss of coherency. BRIEF DESCRIPTION OF DRAWINGS

[0047] The following drawings only schematically illustrate and explain the present application and do not limit the scope of the present application:

[0048] Figure 1 An exemplary structure schematic diagram of the internal architecture of the processor in the embodiments of the present application;

[0049] Figure 2 A schematic diagram of the cross-die access principle of the processor in the embodiments of the present application;

[0050] Figure 3 A schematic diagram of the cross-die access instance of the processor in the embodiments of the present application;

[0051] Figure 4 An exemplary structure schematic diagram of the cache unit of each die of the processor in the embodiments of the present application;

[0052] Figure 5 A working instance schematic diagram of the cache unit of each die of the processor in the embodiments of the present application;

[0053] Figure 6 An exemplary flow schematic diagram of the cross-die access method for the processor in the embodiments of the present application. DETAILED DESCRIPTION

[0054] To make the objects, technical solutions and advantages of the present application clearer, further detailed description will be made to the present application with reference to the accompanying drawings and embodiments.

[0055] Exemplarily, in the embodiments of the present application, the processor can be any one of integrated circuit chips suitable for artificial intelligence, such as GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural network Processing Unit), DPU (Deep learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Units).

[0056] Figure 1 An exemplary structure schematic diagram of the internal architecture of the processor in the embodiments of the present application. Please refer to Figure 1 In the embodiments of the present application, the processor can include a first die D_p and a second die D_q, and the first die D_p and the second die D_q can be interconnected through a D2D bus.

[0057] Exemplarily, in the embodiments of the present application, the first die D_p can have a plurality of first die side processing cores A_p_1~A_p_n, and the second die D_q can have a plurality of second die side processing cores A_q_1~A_q_n. Wherein, n represents the number of the first die side processing cores A_p_1~A_p_n and the number of the plurality of second die side processing cores A_q_1~A_q_n, and n can be a positive integer greater than 1. It can be understood that the embodiments of the present application use n to represent the same number of the first die side processing cores A_p_1~A_p_n and the plurality of second die side processing cores A_q_1~A_q_n for ease of expression, but the number of the first die side processing cores A_p_1~A_p_n and the plurality of second die side processing cores A_q_1~A_q_n can also be different.

[0058] Exemplarily, in the embodiments of the present application, each of the first die D_p and the second die D_q can include one or more streaming processor clusters (SPCs) for kernel computing, and any one or each of the streaming processor clusters can include a plurality of processing cores. In this case, the plurality of first-die-side processing cores A_p_1~A_p_n can include processing cores in at least one (e.g., one or all) streaming processor cluster of the first die D_p, and the plurality of second-die-side processing cores A_q_1~A_q_n can include processing cores in at least one (e.g., one or all) streaming processor cluster of the second die D_q.

[0059] Exemplarily, in the embodiments of the present application, each of the plurality of first-die-side processing cores A_p_1~A_p_n and the plurality of second-die-side processing cores A_q_1~A_q_n can implement data processing by running a kernel, and the kernel run by any one of the plurality of first-die-side processing cores A_p_k or the plurality of second-die-side processing cores A_q_k is a software kernel run by an instruction.

[0060] Exemplarily, in the embodiments of the present application, the plurality of first-die-side processing cores A_p_1~A_p_n and the plurality of second-die-side processing cores A_q_1~A_q_n can implement data processing for artificial intelligence, in which case each of the plurality of first-die-side processing cores A_p_1~A_p_n and the plurality of second-die-side processing cores A_q_1~A_q_n can be referred to as an artificial intelligence core (AI core), k being a positive integer greater than or equal to 1 and less than or equal to n.

[0061] Exemplarily, in the embodiments of the present application, the data processing implemented by the plurality of first-die-side processing cores A_p_1~A_p_n and the plurality of second-die-side processing cores A_q_1~A_q_n can be controlled by a dispatcher through task dispatching. Accordingly, the first die D_p can further have a first-die-side dispatcher DP_p, which can be configured to dispatch task indications based on the kernel running to the plurality of first-die-side processing cores A_p_1~A_p_n, and receive task responses generated by the plurality of first-die-side processing cores A_p_1~A_p_n respectively at the end of the respective kernel running. Similarly to the first die D_p, the second die D_q can further have a second-die-side dispatcher DP_q, which can be configured to dispatch task indications based on the kernel running to the plurality of second-die-side processing cores A_q_1~A_q_n, and receive task responses generated by the plurality of second-die-side processing cores A_q_1~A_q_n respectively at the end of the respective kernel running.

[0062] Exemplarily, in the embodiments of the present application, the first die D_p can further have a plurality of first-die-side cache units C_p_1~C_p_m, and the address spaces of the plurality of first-die-side main memories M_p_1~M_p_m can be respectively and one-to-one mapped to the plurality of first-die-side cache units C_p_1~C_p_m, i.e., the data in any one of the first-die-side main memories M_p_i can be dynamically cached in the corresponding first-die-side cache unit C_p_i, and the complete data consistency between any one of the first-die-side main memories M_p_i and the corresponding first-die-side cache unit C_p_i can not be required to be maintained. Wherein, m represents the number of the plurality of first-die-side cache units C_p_1~C_p_m and the number of the plurality of first-die-side main memories M_p_1~M_p_m whose address spaces are respectively mapped to the plurality of first-die-side cache units C_p_1~C_p_m, m can be a positive integer greater than 1, m can be the same as or different from n, and i is a positive integer greater than or equal to 1 and less than or equal to m.

[0063] Exemplarily, in the embodiments of the present application, the plurality of first-die-side processing cores A_p_1~A_p_n and the plurality of first-die-side cache units C_p_1~C_p_m can all be located in the first die D_p, and the plurality of first-die-side main memories M_p_1~M_p_m as the main memory can be located in the first die D_p or can also be independent of the first die D_p. But no matter what physical form the plurality of first-die-side main memories M_p_1~M_p_m has, the interconnection between the plurality of first-die-side main memories M_p_1~M_p_m and the plurality of first-die-side cache units C_p_1~C_p_m does not depend on the D2D bus (for example, all bypass the D2D bus).

[0064] Exemplarily, in the embodiments of the present application, the plurality of first-die-side processing cores A_p_1~A_p_n and the plurality of first-die-side cache units C_p_1~C_p_m can be interconnected through a Routing Crossbar-based Network on Chip (NOC). In this case, the first die D_p can also have at least one first-die-side Routing Crossbar RCB_p, which can be interconnected with the plurality of first-die-side cache units C_p_1~C_p_m through a first-die-side Network on Chip NOC_p in the first die D_p, and the interconnection between the first-die-side Routing Crossbar RCB_p and the plurality of first-die-side processing cores A_p_1~A_p_n can not depend on the first-die-side Network on Chip NOC_p.

[0065] Exemplarily, in embodiments of the present application, the second die D_q can also have a plurality of second-die-side cache units C_q_1~C_q_m, and the address spaces of the plurality of second-die-side main memories M_q_1~M_q_m can be respectively and one-to-one mapped to the plurality of second-die-side cache units C_q_1~C_q_m, i.e., the data in any one of the second-die-side main memories M_q_i can be dynamically cached in the corresponding second-die-side cache unit C_q_i, and the complete data consistency between any one of the second-die-side main memories M_q_i and the corresponding second-die-side cache unit C_q_i can not be required to be maintained. It can be understood that, in embodiments of the present application, although the number of the plurality of second-die-side cache units C_q_1~C_q_m and the number of the plurality of second-die-side main memories M_q_1~M_q_m whose address spaces are respectively mapped to the plurality of second-die-side cache units C_q_1~C_q_m are both denoted by m, embodiments of the present application do not exclude the case that the number of the plurality of first-die-side cache units C_p_1~C_p_m is different from the number of the plurality of second-die-side cache units C_q_1~C_q_m, and the number of the plurality of first-die-side main memories M_p_1~M_p_m is different from the number of the plurality of second-die-side main memories M_q_1~M_q_m.

[0066] Exemplarily, in embodiments of the present application, similar to the first die D_p, the plurality of second-die-side processing cores A_q_1~A_q_n and the plurality of second-die-side cache units C_q_1~C_q_m of the second die D_q can all be located in the second die D_q, and the plurality of second-die-side main memories M_q_1~M_q_m can be located in the second die D_q or can also be independent of the second die D_q. Regardless of the physical form of the plurality of second-die-side main memories M_q_1~M_q_m, the interconnection between the plurality of second-die-side main memories M_q_1~M_q_m and the plurality of second-die-side cache units C_q_1~C_q_m does not depend on the D2D bus (e.g., bypasses the D2D bus).

[0067] Exemplarily, in embodiments of the present application, similar to the first die D_p, the second die D_q can also have at least one second-die-side crossbar switch RCB_q, the second-die-side crossbar switch RCB_q can be interconnected with the plurality of second-die-side cache units C_q_1~C_q_m through the second-die-side on-die network NOC_q in the second die D_q, and the interconnection between the second-die-side crossbar switch RCB_q and the plurality of second-die-side processing cores A_q_1~A_q_n can not depend on the second-die-side on-die network NOC_q.

[0068] Exemplarily, in the embodiments of the present application, the processor can realize the multi-die fusion by packaging the first die D_p and the second die D_q, and the multi-die fusion can include the processing capability fusion of the plurality of first die side processing cores A_p_1~A_p_n and the plurality of second die side processing cores A_q_1~A_q_n, and the storage capability fusion of the plurality of first die side main memories M_p_1~M_p_m and the plurality of second die side main memories M_q_1~M_q_m.

[0069] Exemplarily, in the embodiments of the present application, there can be a preset correspondence between the storage capability fusion of the plurality of first die side main memories M_p_1~M_p_m and the plurality of second die side main memories M_q_1~M_q_m, for example, the storage capability fusion of the plurality of first die side main memories M_p_1~M_p_m and the plurality of second die side main memories M_q_1~M_q_m can be configured in pairs in one-to-one correspondence. In this case, the address spaces of the main memories with the correspondence can be uniformly addressed, for example, the address spaces of any pair of corresponding first die side main memory M_p_i and second die side main memory M_q_i can be uniformly addressed, so that there is no address overlap in the address spaces of the corresponding first die side main memory M_p_i and second die side main memory M_q_i.

[0070] Exemplarily, in the embodiments of the present application, the plurality of first die side cache units C_p_1~C_p_m and the plurality of second die side cache units C_q_1~C_q_m can be configured in one-to-one correspondence through the preset correspondence between the plurality of first die side main memories M_p_1~M_p_m and the plurality of second die side main memories M_q_1~M_q_m. For example, if the plurality of first die side main memories M_p_1~M_p_m and the plurality of second die side main memories M_q_1~M_q_m are configured in pairs in one-to-one correspondence, then the plurality of first die side cache units C_p_1~C_p_m and the plurality of second die side cache units C_q_1~C_q_m can also be configured in pairs in one-to-one correspondence.

[0071] Exemplarily, in the embodiments of the present application, any one first die side cache unit C_p_i can be configured to:

[0072] In response to a read request initiated by any one first die side processing core A_p_k for target data, a hit-miss detection is performed on the address space of the corresponding first die side main memory M_p_i for the target data, that is, a hit-miss detection is performed on the target data in the first die side cache unit C_p_i and the corresponding first die side main memory M_p_i;

[0073] If the hit detection of the target data in the first die-side cache unit C_p_i and the corresponding first die-side main memory M_p_i fails, a failure response is generated, which can be used to cause the target data to be copied (e.g., from the corresponding second die-side cache unit C_q_i) to the first die-side cache unit C_p_i when the access address of the target data is located in the address space of the corresponding second die-side main memory M_q_i (i.e., the target data is a cross-die access data currently located in the corresponding second die-side main memory M_q_i or currently located in both the corresponding second die-side cache unit C_q_i and the corresponding second die-side main memory M_q_i).

[0074] If the hit detection of the target data in the first die-side cache unit C_p_i and the corresponding first die-side main memory M_p_i succeeds, e.g., the access address of the target data is located in the address space of the corresponding first die-side main memory M_p_i (i.e., the target data is an in-die access data currently located in the corresponding first die-side main memory M_p_i or currently located in both the first die-side cache unit C_p_i and the corresponding first die-side main memory M_p_i), or the target data is a cross-die access data copied from the second die D_p to the first die-side cache unit C_p_i, a read response carrying the hit target data (e.g., in-die access data or data copied through cross-die access) is generated, which is used to be transmitted to the first die-side processing core A_p_k that initiates the read request.

[0075] In response to a data update of the target data in the address space of the corresponding second die-side main memory M_q_i (e.g., the data update can occur in the corresponding second die-side cache unit C_q_i), the target data copied to the first die-side cache unit C_p_i is invalidated so that the copied target data can be deleted from the first die-side cache unit C_p_i (e.g., any data invalidated can be deleted from the first die-side cache unit C_p_i at a time when a preset condition is met).

[0076] As can be seen from the above, based on the embodiments of the present application, the cross-die access of any die (e.g., the first die D_p) of the processor to the target data cached in another die (e.g., the second die D_q) can trigger the copy of the target data from the other die (e.g., the second die D_q) to the die (e.g., the first die D_p) due to the miss detection of the target data in the die (e.g., the first die D_p), and the subsequent cross-die access of the die (e.g., the first die D_p) to the target data can be converted into the in-die access to the target data cached locally in the die (e.g., the first die D_p), so that the actual number of cross-die accesses subject to the delay due to the bandwidth limitation of the D2D bus can be reduced. Moreover, when the target data cached in the other die (e.g., the second die D_q) is updated, the target data cached locally in the die (e.g., the first die D_p) due to the copy can be deleted, and thereafter, the target data in the other die (e.g., the second die D_q) updated can be copied again to the die (e.g., the first die D_p) due to the miss detection, so that the consistency of the target data in different dies can be taken into account. Furthermore, the efficiency of the cross-die access in the processor with at least two dies can be improved without loss of consistency.

[0077] Figure 2 A schematic diagram of the cross-die access principle of the processor in the embodiments of the present application is shown in FIG. 1. Please refer to FIG. 1. Figure 2 In the embodiments of the present application, the first-die-side cross-routing switch RCB_p can be configured to:

[0078] According to the access address of the target data, the read request (e.g., ① in FIG. 2) initiated by any one of the first-die-side processing cores A_p_k is routed and forwarded to the corresponding first-die-side cache unit C_p_i (e.g., ② in FIG. 2); Figure 2 Figure 2 If the failure response (e.g., ② in FIG. 2) is generated by any one of the first-die-side cache units C_p_i due to the miss detection of the target data, and the access address of the target data is located in the address space of the corresponding second-die-side main memory M_q_i (i.e., the target data is currently located in the corresponding second-die-side main memory M_q_i, or is currently located in both the corresponding second-die-side cache unit C_q_i and the corresponding second-die-side main memory M_q_i), the read request initiated to the target data is routed and forwarded to the corresponding second-die-side cache unit C_q_i (e.g., ③ in FIG. 2), so that the target data is copied from the corresponding second-die-side cache unit C_q_i to the first-die-side cache unit C_p_i (e.g., ④ in FIG. 2).

[0079] Figure 2 Figure 2 Figure 2 ​​​​(4) in (1) above;

[0080] If any one of the first-die-side cache units C_p_i generates a read response due to a hit detection success of the target data, for example, generates a read response due to a successful hit of the target data copied and carried from the second-die D_q to the first-die-side cache unit C_p_i, the read response is transmitted to the first-die-side processing core A_p_k that initiates the request for the target data (as Figure 2 (5) in (1) above.

[0081] Exemplarily, still referring to Figure 2 In embodiments of the present application, the target data in the address space of the corresponding second-die-side main memory M_q_i can be executed data update in the corresponding second-die-side cache unit C_q_i (as Figure 2 For example, the target data in the corresponding second-die-side cache unit C_q_i can be executed data update by the write operation initiated by any one of the second-die-side processing cores A_q_k.

[0082] Exemplarily, still referring to Figure 2 In embodiments of the present application, any one of the second-die-side cache units C_q_i can be configured to generate an invalid request Inv_req_q to the corresponding first-die-side cache unit C_p_i in response to the data update of the target data in the second-die-side cache unit C_q_i (as Figure 2 (6) in (1) above, so that the corresponding first-die-side cache unit C_p_i invalidates the target data copied and carried from the second-die-side cache unit C_q_i to the corresponding first-die-side cache unit C_p_i according to the invalid request Inv_req_q generated by the second-die-side cache unit C_q_i.

[0083] Exemplarily, in embodiments of the present application, if the target data in the corresponding second-die-side cache unit C_q_i is executed data update due to the write operation initiated by any one of the second-die-side processing cores A_q_k, the second-die-side dispatcher DP_q can be further configured to generate an invalid command Inv_cmd_q to the second-die-side cache unit C_q_i where the target data is located when receiving a task response generated by any one of the second-die-side processing cores A_q_k due to the completion of the write operation on the target data, so that the second-die-side cache unit C_q_i generates an invalid request Inv_req_q to the corresponding first-die-side cache unit C_p_i in response to the received invalid command Inv_cmd_q.

[0084] Exemplarily, still referring to Figure 2In the embodiments of the present application, a monitoring bus SN independent of the D2D bus can also be connected between the first die D_p and the second die D_q, which can be used for the first die side cache unit C_p_i and the second die side cache unit C_q_i corresponding to each other to monitor (snoop) the status of the target data at the opposite end. Therefore, any one of the second die side cache units C_q_i can be specifically configured to generate an invalid request Inv_req_q to the corresponding first die side cache unit C_p_i through the monitoring bus, so that the corresponding first die side cache unit C_p_i can monitor or determine the data update of the target data in the second die side cache unit C_q_i.

[0085] Exemplarily, in the embodiments of the present application, the monitoring bus SN can also be regarded as another D2D bus, but the bandwidth of the monitoring bus SN can be smaller than the D2D bus based on which the target data is copied and transported.

[0086] Exemplarily, in the embodiments of the present application, if the target data is associated with the currently running kernel of the first die side processing core A_p_k that initiates the read request, any one of the first die side cache units C_p_i can be further configured to, in response to the end of the running of the kernel associated with the target data, invalidate the target data copied and transported to the first die side cache unit C_p_i (such as Figure 2 ⑧ in the above).

[0087] Exemplarily, in the embodiments of the present application, the first die side dispatcher DP_p can be further configured to, when receiving the task response generated by any one of the first die side processing cores A_p_k due to the end of the running of the kernel associated with the target data, generate an invalid command Inv_cmd_p to the first die side cache unit C_p_i where the target data is located, so that the first die side cache unit C_p_i invalidates the target data copied and transported to the first die side cache unit C_p_i in response to the received invalid command Inv_cmd_p.

[0088] Exemplarily, in the embodiments of the present application, after the target data copied and carried to the first die side cache unit C_p_i is invalidated due to the end of the running of the kernel, the first die side processing core A_p_k which has run the kernel before can start the running of the next kernel, the running of the next kernel can also be associated with the target data but the assignment to the target data can be different (i.e. for the same target data associated with multiple kernels, it can have configurable values respectively adapted to different kernels), and the target data in the corresponding second die side cache unit C_q_i can be updated in the initial stage of the running of the next kernel by the first die side processing core A_p_k, and then the copied and carried target data can be reused (for example, the process of ①~⑧ in Figure 3 can be restarted) to improve the efficiency of cross-die access, and enable the target data to adapt to the differentiated requirements of different kernels on data consistency.

[0089] Figure 3 A schematic diagram of the cross-die access instance of the processor in the embodiments of the present application. Please refer to Figure 3 ( Figure 2 correspond to ①~⑧ shown in Figure 3 ), in the embodiments of the present application, in any one of the first die side cache unit C_p_i and the corresponding second die side cache unit C_q_i, tag information can be maintained for any data, the tag information can be used for hit detection of the corresponding data, and the tag information corresponding to any data (for example, target data) can include: a tag used to represent the access address of the data (for example, target data), a valid flag used to represent the validity or invalidity of the data (for example, target data), a dirty flag used to represent whether the data (for example, target data) needs to be synchronized to the corresponding first die side main memory M_p_i or second die side main memory M_q_i, and a kernel id used to represent the corresponding kernel of the kernel which causes the data (for example, target data) to be cached in the first die side cache unit C_p_i or second die side cache unit C_q_i. Wherein, the operation of invalidating any data (for example, target data) can be realized by setting the valid flag to a digital level representing invalidity.

[0090] Exemplarily, as Figure 3As shown, in embodiments of the present application, the tag information corresponding to any data (e.g. target data) maintained by the second die side cache unit C_q_i can further include a sharing flag, and the sharing flag is used to represent whether the data is shared with other dies (e.g. the first die D_p) by being copied (e.g. as target data) to the corresponding first die side cache unit C_p_i. Wherein, in this case, any one of the second die side cache units C_q_i can be further configured to:

[0091] in response to completion of the copying of the target data (e.g. as in ④ of Figure 3 ), set the sharing flag of the tag information corresponding to the target data maintained in the second die side cache unit C_q_i to an effective state, to represent that the target data is currently shared with the first die D_p by being copied to the corresponding first die side cache unit C_p_i; and,

[0092] in response to the target data being executed data update in the second die side cache unit C_q_i, set the sharing flag of the tag information corresponding to the target data maintained in the second die side cache unit C_q_i to an invalid state, to represent that the sharing of the target data with the first die D_p before data update is ended, i.e. to avoid the target data shared with the first die D_p from losing consistency due to the occurrence of data update, the sharing of the target data with the first die D_p before data update is ended.

[0093] Exemplarily, in embodiments of the present application, the invalid request Inv_req_q (e.g. as in ⑦ of Figure 3 ) generated by any one of the second die side cache units C_q_i to the corresponding first die side cache unit C_p_i can be enabled when the sharing flag of the tag information corresponding to the target data maintained in the second die side cache unit C_q_i is in the effective state.

[0094] Exemplarily, in embodiments of the present application, any one of the second die side cache units C_q_i can be specifically configured to: in response to the invalid command Inv_cmd_q received from the second die side dispatcher DP_q, set the sharing flag of the tag information corresponding to the target data maintained in the second die side cache unit C_q_i to an invalid state (e.g. as in ⑥ of Figure 3 ).

[0095] Exemplarily, in embodiments of the present application, any one second die side cache unit C_q_i can be specifically configured to generate (e.g. generate to the corresponding first die side cache unit C_p_i through the monitoring bus SN) an invalid request Inv_req_q to the corresponding first die side cache unit C_p_i in response to the state change of the sharing identifier of the tag information corresponding to the target data maintained in the second die side cache unit C_q_i from the effective state to the invalid state, as shown in (vi) of Figure 3

[0096] Exemplarily, as shown in Figure 3 , in embodiments of the present application, the tag information corresponding to any data (e.g. target data) maintained by any one first die side cache unit C_p_i can further include a copy flag, and the copy flag is used to represent whether the data is copied (e.g. copied as target data) to the first die side cache unit C_p_i from other dies (e.g. second dies D_q). In this case, any one first die side cache unit C_p_i can be further configured to:

[0097] in response to the completion of the copy of the target data (as shown in (iv) of Figure 3 ), set the copy identifier of the tag information corresponding to the target data maintained in the first die side cache unit C_p_i to the effective state, to represent that the target data is copied to the first die side cache unit C_p_i from the corresponding second die side cache unit C_q_i; and,

[0098] in response to the end of the running of the kernel associated with the target data, for example, in response to the task response of the first die side dispatcher DP_p due to the end of the running of the kernel associated with the target data (as shown in (vii) of Figure 3 ), set the target data copied to the first die side cache unit C_p_i to be invalid according to the effective copy identifier, so that the target data copied to the first die side cache unit C_p_i is deleted from the first die side cache unit C_p_i due to the end of the running of the associated kernel.

[0099] Exemplarily, in embodiments of the present application, the operation of setting the target data to be invalid can be further according to the kernel identifier, that is, in response to the end of the running of the kernel associated with the target data, any one first die side cache unit C_p_i can set the target data copied to the first die side cache unit C_p_i to be invalid according to the kernel identifier corresponding to the running end kernel and the effective copy identifier, so that the target data copied to the first die side cache unit C_p_i is deleted from the first die side cache unit C_p_i due to the end of the running of the associated kernel. ​

[0100] Exemplarily, in the embodiments of the present application, the target data associated with any one of the cores can be multiple, in which case, the first die-side cache unit C_p_i that caches the multiple target data through copy-on-write can respectively maintain multiple tag information corresponding to the multiple target data, and according to the core identifier corresponding to the running-end core and the copy identifier in the effective state, the first die-side cache unit C_p_i can include the operation of invalidating the target data copied and written into the first die-side cache unit C_p_i, which can include invalidating the multiple target data in batches.

[0101] Exemplarily, in the embodiments of the present application, any one of the second die-side cache units C_q_i can be further configured to, in response to the target data copied and written into the corresponding first die-side cache unit C_p_i being invalidated, invalidate the shared identifier of the tag information corresponding to the target data maintained in the second die-side cache unit C_q_i.

[0102] Exemplarily, in the embodiments of the present application, any one of the first die-side cache units C_p_i can be further configured to, in response to the target data copied and written into the first die-side cache unit C_p_i being invalidated, generate an invalidation request Inv_req_p to the corresponding second die-side cache unit C_q_i (such as Figure 4 Exemplarily, in the embodiments of the present application, any one of the first die-side cache units C_p_i can be further configured to, in response to the target data copied and written into the first die-side cache unit C_p_i being invalidated, generate an invalidation request Inv_req_p to the corresponding second die-side cache unit C_q_i (such as

[0103] Therefore, if the invalidation request Inv_req_q generated by any one of the second die-side cache units C_q_i to the corresponding first die-side cache unit C_p_i is configured to be enabled when the shared identifier is in the effective state, by invalidating the shared identifier after the target data copied and written into the first die-side cache unit C_p_i is invalidated, unnecessary invalidation request Inv_req_q can be avoided in the subsequent data update of the target data in the second die-side cache unit C_q_i.

[0104] Figure 5 An exemplary structure diagram of the cache units of the dies of the processor in the embodiments of the present application. Figure 4 An exemplary working instance diagram of the cache units of the dies of the processor in the embodiments of the present application. Please refer toFigure 5 and Figure 5 In the embodiments of this application, any first die-side cache unit C_p_i or second die-side cache unit C_q_i may include a multiplexer, a splitter, a hit detection channel connected between the multiplexer and the splitter, a tag cache medium connected to the hit detection channel, a cache queue connected between the splitter and the corresponding first die-side main memory M_p_i or second die-side main memory M_q_i, and a data cache medium connected to the cache queue.

[0105] For example, in embodiments of this application, the multiplexer of any first die-side cache unit C_p_i or second die-side cache unit C_q_i may include three input terminals and one output terminal, wherein:

[0106] The first input terminal is used to receive read / write requests from any first die-side cache unit C_p_i via the first die-side on-chip network NOC_p, or to receive read / write requests from any first die-side cache unit C_p_i via the second die-side on-chip network NOC_q. Figure 4 (The connection structure related to the first input terminal is omitted in the text).

[0107] The second input terminal is used to receive invalid commands Inv_cmd_p or Inv_cmd_p generated by the first die-side dispatcher DP_p or the second die-side dispatcher DP_q;

[0108] The third input is used to receive invalid requests Inv_cmd_p or Inv_cmd_p transmitted via the monitoring bus SN.

[0109] For example, in the embodiments of this application, the splitter of any first die-side cache unit C_p_i or second die-side cache unit C_q_i may include an input terminal and two output terminals. The input terminal is connected to the hit detection channel, and one output terminal is connected to the cache queue, and the other output terminal generates an invalid request Inv_req_p or Inv_req_p through the monitoring bus SN.

[0110] For example, in the embodiments of this application, the data caching medium of any one of the first die-side cache unit C_p_i or the second die-side cache unit C_q_i is used to store the data (including target data) cached in the first die-side cache unit C_p_i or the second die-side cache unit C_q_i.

[0111] Exemplarily, in the embodiments of the present application, the cache queue of any one of the first-die-side cache units C_p_i or the second-die-side cache units C_q_i is used for data synchronization between the data cache medium and the corresponding first-die-side main memory M_p_i or the second-die-side main memory M_q_i.

[0112] Exemplarily, in the embodiments of the present application, the tag cache medium of any one of the first-die-side cache units C_p_i or the second-die-side cache units C_q_i is used for storing the tag information maintained correspondingly for the data (including the target data) in the data cache medium.

[0113] Exemplarily, in the embodiments of the present application, the hit detection channel of any one of the first-die-side cache units C_p_i or the second-die-side cache units C_q_i is used for hit detection by using the received read-write request, so as to generate a read-write response to the splitter when the hit detection succeeds, or generate a failure response to the splitter when the hit detection fails, so that the read-write response or the failure response enters the cache queue through the splitter, thereby, the read-write response entering the cache queue can allow the hit data in the data cache medium to be read-write accessed by any one of the first-die-side cache units C_p_i through the first-die-side on-die network NOC_p, or by any one of the second-die-side cache units C_q_i through the second-die-side on-die network NOC_q. Figure 5 and Figure 4 The specific connection structure related to the read-write access is omitted in the above description), and the failure response entering the cache queue can be fed back to the first-die-side routing crossbar RCB_p or the second-die-side routing crossbar RCB_q through the first-die-side on-die network NOC_p or the second-die-side on-die network NOC_q.

[0114] Exemplarily, in the embodiments of the present application, the above description is exemplarily described only by taking the cross-die access of the first die D_p to the second die D_q as an example, but it can be understood that the cross-die access of the second die D_q to the first die D_p can be in the same way, that is, the execution subject related to the first die D_p side in the above description is transposed with the execution subject related to the second die D_q side, so as to obtain the description related to the cross-die access of the second die D_q to the first die D_p. Therefore, Figure 4 The reference signs in the above description are represented by “ / ” in the meaning of “or”, thereby representing that Figure 6 The figures in the above description are universal for the first die D_p and the second die D_q.

[0115] Exemplarily, in the embodiments of the present application, any one of the first-die-side cache units C_p_i can include a main memory mapping region and a cross-die mapping region, the main memory mapping region of the first-die-side cache unit C_p_i can be used for address space mapping of the first-die-side main memory M_p_i, and the cross-die mapping region of the first-die-side cache unit C_p_i is used to store target data copied from the corresponding second-die-side cache unit C_q_i, and the cross-die mapping region of the first-die-side cache unit C_p_i is independent of the main memory mapping region of the first-die-side cache unit C_p_i. Similarly, if the second die D_q adopts the same cross-die access mode to the first die D_p, any one of the second-die-side cache units C_q_i can include a main memory mapping region and a cross-die mapping region, the main memory mapping region of the second-die-side cache unit C_q_i can be used for address space mapping of the second-die-side main memory M_q_i, and the cross-die mapping region of the second-die-side cache unit C_q_i is used to store target data copied from the corresponding first-die-side cache unit C_p_i, and the cross-die mapping region of the second-die-side cache unit C_q_i is independent of the main memory mapping region of the second-die-side cache unit C_q_i.

[0116] Exemplarily, in the embodiments of the present application, the dies included by the processor can not be limited to the first die D_p and the second die D_q shown in the drawings, i.e., the processor can also include other dies in addition to the first die D_p and the second die D_q, in which case, cross-die access can be implemented between each two of the at least two dies included by the processor in the manner described above for the first die D_p and the second die D_q.

[0117] In another embodiment of the present application, a cross-die access method for a processor is also provided, and the processor to which the cross-die access method is applicable can have the same or similar structure as the processor having the first die and the second die described above. For example, the processor to which the cross-die access method is applicable includes a first die and a second die, the first die has a plurality of first-die-side processing cores and a plurality of first-die-side cache units, and the address spaces of a plurality of first-die-side main memories are respectively and one-to-one mapped to the plurality of first-die-side cache units, the second die has a plurality of second-die-side processing cores and a plurality of second-die-side cache units, and a plurality of second-die-side main memories are respectively and one-to-one mapped to the plurality of second-die-side cache units, and the plurality of first-die-side cache units and the plurality of second-die-side cache units are configured to be one-to-one corresponding through the preset corresponding relationship between the plurality of first-die-side main memories and the plurality of second-die-side main memories.

[0118] Figure 6An exemplary flowchart of a cross-die access method for a processor in an embodiment of the present application is shown in FIG. 6. Referring to FIG. 6, the cross-die access method can include the following steps performed by any one of the first-die side cache units: ​ In an embodiment of the present application, the cross-die access method can include the following steps performed by any one of the first-die side cache units:

[0119] S610: In response to a read request initiated by any one of the first-die side processing cores for target data, performing a hit detection for the target data in the address space of the corresponding first-die side main memory. For example, S610 can perform the hit detection for the target data in the first-die side cache unit and the corresponding first-die side main memory.

[0120] If the hit detection for the target data in the first-die side cache unit and the corresponding first-die side main memory fails, a failure response is generated by performing S630, which can be used to cause the target data to be copied (e.g., copied from the corresponding second-die side cache unit) to the first-die side cache unit when the access address of the target data is located in the address space of the corresponding second-die side main memory (i.e., the target data is cross-die access data currently located in the corresponding second-die side main memory or currently located in both the corresponding second-die side cache unit and the corresponding second-die side main memory). For example, the copying of the target data can be achieved by a cross-die transmission based on the D2D bus.

[0121] If the hit detection for the target data in the first-die side cache unit and the corresponding first-die side main memory succeeds, for example, the access address of the target data is located in the address space of the corresponding first-die side main memory (i.e., the target data is in-die access data currently located in the corresponding first-die side main memory or located in both the first-die side cache unit and the corresponding first-die side main memory), or the target data is cross-die access data copied from the second die to the first-die side cache unit, a read response carrying the hit target data (e.g., in-die access data or cross-die access data) is generated by performing S650, which is used to be transmitted to the first-die side processing core that initiates the read request.

[0122] S670: In response to a data update (e.g., the data update can occur in the corresponding second-die side cache unit) of the target data in the address space of the corresponding second-die side main memory, invalidating the target data copied to the first-die side cache unit, so that the target data can be deleted (e.g., any data invalidated can be deleted from the first-die side cache unit at a time when a preset condition is met) from the first-die side cache unit.

[0123] As can be seen from the above, based on the embodiments of the present application, the cross-die access of any die (e.g., the first die) of the processor to the target data cached in another die (e.g., the second die) can trigger the copy of the target data from the other die (e.g., the second die) to the die (e.g., the first die) due to the miss of the hit detection of the target data in the die (e.g., the first die), and the subsequent cross-die access of the die (e.g., the first die) to the target data can be converted into the in-die access to the target data cached locally in the die (e.g., the first die), so that the actual number of cross-die accesses subject to the delay due to the bandwidth limitation of the D2D bus can be reduced. Moreover, when the target data cached in the other die (e.g., the second die) is updated, the target data cached locally in the die (e.g., the first die) due to the copy can be deleted, and thereafter, the target data updated in the other die (e.g., the second die) can be copied again to the die (e.g., the first die) due to the miss of the hit detection, so that the consistency of the target data in different dies can be taken into account. Furthermore, the efficiency of the cross-die access in the processor with at least two dies can be improved without loss of consistency.

[0124] Exemplarily, in the embodiments of the present application, the cross-die access method for the processor can further include the following steps performed by the first-die-side cross-routing switch:

[0125] Before S610, the read request initiated by any first-die-side processing core is routed and forwarded to the corresponding first-die-side cache unit according to the access address of the target data;

[0126] If any first-die-side cache unit generates a failure response due to the miss of the hit detection of the target data, and the access address of the target data is located in the address space of the corresponding second-die-side main memory (i.e., the target data is currently located in the corresponding second-die-side main memory, or is currently located in both the corresponding second-die-side cache unit and the corresponding second-die-side main memory), then after S650, the read request initiated for the target data is routed and forwarded to the corresponding second-die-side cache unit, so that the target data is copied from the corresponding second-die-side cache unit to the first-die-side cache unit;

[0127] If any first-die-side cache unit generates a read response due to the success of the hit detection of the target data, for example, generates a read response due to the success of the hit of the target data copied from the second die to the first-die-side cache unit, then after S630, the read response is transmitted to the first-die-side processing core that initiates the request for the target data.

[0128] Exemplarily, in the embodiments of the present application, the cross-die access method for the processor can further comprise the following steps performed by any one of the second die-side cache units before S670:

[0129] In response to the data update of the target data in the second die-side cache unit, an invalidation request is generated to the corresponding first die-side cache unit (e.g. the invalidation request is generated to the corresponding first die-side cache unit through the monitoring bus) to cause the corresponding first die-side cache unit to invalidate the target data copied from the second die-side cache unit to the corresponding first die-side cache unit according to the invalidation request generated by the second die-side cache unit by performing S670.

[0130] Exemplarily, in the embodiments of the present application, the cross-die access method for the processor can further comprise the following steps performed by any one of the second die-side cache units:

[0131] In response to the completion of the copy of the target data, the shared identifier of the tag information corresponding to the target data maintained in the second die-side cache unit is set to an effective state; and,

[0132] In response to the data update of the target data in the second die-side cache unit, the shared identifier of the tag information corresponding to the target data maintained in the second die-side cache unit is set to an invalid state.

[0133] Exemplarily, in the embodiments of the present application, the process of generating the invalidation request by any one of the second die-side cache units to the corresponding first die-side cache unit in the cross-die access method for the processor can comprise: in response to the state change of the shared identifier of the tag information corresponding to the target data maintained in the second die-side cache unit from the effective state to the invalid state, generating the invalidation request to the corresponding first die-side cache unit.

[0134] Exemplarily, in the embodiments of the present application, if the target data is associated with the current running kernel of the first die-side processing core initiating the read request, the cross-die access method for the processor can further comprise the following steps performed by any one of the first die-side cache units: in response to the end of the running of the kernel associated with the target data, invalidating the target data copied to the first die-side cache unit.

[0135] Exemplarily, in the embodiments of the present application, the cross-die access method for the processor can further comprise the following steps performed by any one of the first die-side cache units:

[0136] In response to the completion of the copy of the target data, the copy identifier of the tag information corresponding to the target data maintained in the first die-side cache unit is set to an effective state; and,

[0137] In response to the end of the running of the kernel associated with the target data, the target data copied to the first die-side cache unit is invalidated according to the replication identifier of the effective state, or further according to the kernel identifier when invalidating the target data.

[0138] For example, in the embodiments of the present application, if the target data is multiple, and multiple tag information corresponding to the multiple target data is maintained in any one of the first die-side cache units, the operation of invalidating the target data includes: invalidating the multiple target data copied to the first die-side cache unit in batches.

[0139] For example, in the embodiments of the present application, the cross-die access method for the processor can further include the following steps performed by any one of the second die-side cache units: in response to the target data copied to the corresponding first die-side cache unit being invalidated, invalidating the shared identifier of the tag information corresponding to the target data maintained in the second die-side cache unit.

[0140] For example, in the embodiments of the present application, the cross-die access method for the processor can further include the following steps performed by any one of the first die-side cache units:

[0141] In response to the target data copied to the first die-side cache unit being invalidated, an invalidation request is generated to the corresponding second die-side cache unit, for example, an invalidation request is generated to the corresponding second die-side cache unit through a monitoring bus, so that the corresponding second die-side cache unit invalidates the shared identifier of the tag information corresponding to the target data maintained in the corresponding second die-side cache unit according to the invalidation request generated by the first die-side cache unit.

[0142] It can be understood that in the embodiments of the present application, the parts of the exemplary description can be in a "and / or" relationship. In this paper, the meaning of "and / or" is that there can be a "and" common definition relationship or also a "or" alternative definition relationship between the context connected by it. Therefore, the parts of the content with "and / or" relationship can be understood as including different case combinations of "and / or" respectively representing "and" common definition relationship or "or" alternative definition relationship between each two parts of the content, and this different case combination can be considered as substantially equivalent to the definition range of "at least one of the parts".

[0143] The above only describes the preferred embodiments of the present application and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A processor, characterized in that, include: The first die has multiple first die-side processing cores and multiple first die-side cache units, and the address spaces of the multiple first die-side main memory are mapped one-to-one to the multiple first die-side cache units. The second die has multiple second die-side processing cores and multiple second die-side cache units, and the multiple second die-side main memory are mapped one-to-one to the multiple second die-side cache units respectively; Among them, multiple first-die-side cache units and multiple second-die-side cache units are configured to correspond one-to-one with each other through a preset correspondence between multiple first-die-side main memory units and multiple second-die-side main memory units, and any one of the first-die-side cache units is configured as follows: In response to any read request initiated by the first die-side processing to check the target data, a hit detection of the target data is performed in the address space of the corresponding first die-side main memory; If the hit detection fails, a failure response is generated. This failure response is used to cause the target data to be copied and moved to the first die-side cache unit when the access address of the target data is located in the address space of the corresponding second die-side main memory. If the hit detection is successful, a read response carrying the hit target data is generated, which is then transmitted to the first die-side processing core that initiated the read request. In response to a data update of the target data in the address space of the corresponding second die-side main memory, the target data that has been copied and moved to the first die-side cache unit is invalidated.

2. The processor according to claim 1, characterized in that, The first die also has a cross-routing switch, and the cross-routing switch is configured as follows: Based on the access address of the target data, any read request initiated by any first die-side processing core is routed and forwarded to the corresponding first die-side cache unit; If any first die-side cache unit generates a failure response due to a failure to detect a hit with the target data, and the access address of the target data is located in the address space of the corresponding second die-side main memory, then the read request initiated for the target data will be routed and forwarded to the corresponding second die-side cache unit so that the target data is copied and moved from the corresponding second die-side cache unit to the first die-side cache unit. If any of the first die-side cache units generates a read response due to a successful hit detection of the target data, the read response is transmitted to the first die-side processing core that initiated the request for the target data.

3. The processor according to claim 1, characterized in that, Any second die-side buffer unit is configured as follows: In response to a data update of the target data in the second die-side cache unit, an invalidation request is generated to the corresponding first die-side cache unit, so that the corresponding first die-side cache unit invalidates the target data copied and moved from the second die-side cache unit to the corresponding first die-side cache unit based on the invalidation request generated by the second die-side cache unit.

4. The processor according to claim 3, characterized in that, The first and second dies are interconnected via a D2D bus. The copying and transfer of target data is achieved through cross-dies transmission based on the D2D bus. Furthermore, a monitoring bus independent of the D2D bus is also connected between the first and second dies. Any second die-side cache unit is specifically configured to generate an invalidation request to the corresponding first die-side cache unit via the monitoring bus.

5. The processor according to claim 3, characterized in that, Any second die-side cache unit is further configured as follows: In response to the completion of the copying and transfer of the target data, the shared identifier of the tag information corresponding to the target data maintained in the second bare die side buffer unit is set to the active state; as well as, In response to the target data being updated in the second die-side cache unit, the shared identifier of the tag information corresponding to the target data maintained in the second die-side cache unit is set to invalid state.

6. The processor according to claim 5, characterized in that, Any second die-side cache unit is specifically configured as follows: In response to the change in the state of the shared identifier of the tag information maintained for the target data in the second die-side cache unit from the active state to the invalid state, an invalidation request is generated to the corresponding first die-side cache unit.

7. The processor according to claim 1, characterized in that, The target data is associated with the currently running kernel of the first die-side processing core that initiated the read request; Any first die-side cache unit is further configured to invalidate the target data that has been copied and moved to the first die-side cache unit in response to the end of kernel operation associated with the target data.

8. The processor according to claim 7, characterized in that, Any one of the first die-side cache units is further configured as follows: In response to the completion of the copying and transfer of the target data, the copying flag of the tag information corresponding to the target data maintained in the first bare die side buffer unit is set to the active state; as well as, In response to the termination of the kernel operation associated with the target data, the target data that has been copied and moved to the first die-side cache unit is invalidated based on the copy identifier of the effective status.

9. The processor according to claim 8, characterized in that, The tag information maintained by the first bare die side cache unit for the target data also includes the kernel identifier corresponding to the kernel associated with the target data, and the operation of invalidating the target data is further based on the kernel identifier.

10. The processor according to claim 8, characterized in that, There are multiple target data, and each of the first bare die side cache units maintains multiple tag information corresponding to the multiple target data. Furthermore, the operation of invalidating the target data includes: batch invalidating the multiple target data that have been copied and moved to the first bare die side cache unit.

11. The processor according to claim 7, characterized in that, Any second die-side cache unit is further configured as follows: In response to the completion of the copying and transfer of the target data, the shared identifier of the tag information corresponding to the target data maintained in the second bare die side buffer unit is set to the active state; as well as, In response to invalidating the target data copied and moved to the corresponding first die-side cache unit, the shared identifier of the tag information maintained for the target data in the second die-side cache unit is set to invalid.

12. The processor according to claim 11, characterized in that, Any one of the first die-side cache units is further configured as follows: In response to the invalidation of the target data copied and moved to the first die-side cache unit, an invalidation request is generated to the corresponding second die-side cache unit, so that the corresponding second die-side cache unit, based on the invalidation request generated by the first die-side cache unit, will set the shared identifier of the tag information maintained for the target data in the corresponding second die-side cache unit to an invalid state.

13. The processor according to claim 12, characterized in that, The first and second dies are interconnected via a D2D bus. The copying and transfer of target data is achieved through cross-dies transmission based on the D2D bus. Furthermore, a monitoring bus independent of the D2D bus is also connected between the first and second dies. Any of the first die-side cache units is further configured to: generate an invalidation request to the corresponding second die-side cache unit via the monitoring bus.

14. The processor according to any one of claims 1 to 12, characterized in that, Any first die-side cache unit includes a main memory mapping region and a cross-die mapping region. The main memory mapping region of the first die-side cache unit is used for address space mapping of the first die-side main memory, and the cross-die mapping region of the first die-side cache unit is independent of the main memory mapping region.

15. A method for cross-die access of a processor, characterized in that, The processor includes a first die and a second die. The first die has multiple first die-side processing cores and multiple first die-side cache units. The address spaces of the multiple first die-side main memories are mapped one-to-one to the multiple first die-side cache units. The second die has multiple second die-side processing cores and multiple second die-side cache units. The multiple second die-side main memories are mapped one-to-one to the multiple second die-side cache units. The multiple first die-side cache units and the multiple second die-side cache units are configured to correspond one-to-one through a preset correspondence between the multiple first die-side main memories and the multiple second die-side main memories. Furthermore, the cross-die access method includes the following steps performed by any one of the first die-side cache units: In response to any read request initiated by the first die-side processing to check the target data, a hit detection of the target data is performed in the address space of the corresponding first die-side main memory; If the hit detection fails, a failure response is generated. This failure response is used to cause the target data to be copied and moved to the first die-side cache unit when the access address of the target data is located in the address space of the corresponding second die-side main memory. If the hit detection is successful, a read response carrying the hit target data is generated, which is then transmitted to the first die-side processing core that initiated the read request. In response to a data update of the target data in the address space of the corresponding second die-side main memory, the target data that has been copied and moved to the first die-side cache unit is invalidated.

Images