Digital-to-analog conversion circuit and conversion method

Abstract

The invention discloses a digital-to-analog conversion circuit and a conversion method, and belongs to the field of circuit design. In order to solve the problems that the output amplitude of an existing digital-to-analog converter is fixed, and the resolution needs to be sacrificed or an additional circuit needs to be added during amplitude adjustment, the invention provides a novel circuit structure. On the basis that the circuit comprises a digital output module, a switch module and a weight circuit module, a high-level adjustable reference source and a low-level adjustable reference source are innovatively introduced. The switch module selectively connects the input node of the weight circuit module to the two adjustable reference sources according to the control signal of the digital output module. Therefore, the amplitude and the direct current bias of the output analog signal are directly determined by the voltage values of the two reference sources. According to the invention, the output signal range can be dynamically and flexibly adjusted on the premise that the resolution is not lost, and the bipolar signal can be conveniently generated, so that the system design is simplified, and the cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to a universal circuit design, in particular, a digital-to-analog conversion circuit and conversion method. BACKGROUND

[0002] A digital-to-analog converter (DAC) is a key module connecting the digital and analog world, and its performance (such as resolution, linearity) is crucial. Please refer to Figure 1 , resistive DAC, especially the classic R-2R structure, is widely used in medium and low speed and precision applications due to its simple structure, low cost and easy integration, and can be directly driven by the GPIO of the MCU.

[0003] However, this traditional GPIO-driven R-2R DAC has the following defects:

[0004] Limited output range and only single polarity: the output voltage is hard locked by the GPIO level, and cannot generate negative voltage or bipolar signal.

[0005] Amplitude adjustment sacrifices resolution: if you want to reduce the output range, you can only limit the digital input range by software, resulting in a decrease in effective resolution and loss of accuracy.

[0006] Another common solution is to use an on-chip integrated DAC with a high-end MCU or a dedicated chip, which usually has higher accuracy and resolution. However, they have the following defects:

[0007] High cost: the price of chips with integrated high-performance DACs is much higher than that of general-purpose MCUs.

[0008] Amplitude modulation is difficult: the output voltage is also limited by the supply voltage or fixed reference source.

[0009] It is not easy to change the reference voltage: the internal reference voltage is usually fixed; the range of external reference voltage is limited, and additional complex circuitry is required to obtain negative voltage.

[0010] Sacrifice resolution like R-2R: limiting digital input still results in loss of accuracy.

[0011] High cost of post-amplifier: increases cost, power consumption, PCB size, noise and non-linear distortion, offsetting the advantages of the DAC itself.

[0012] The existing DAC solution generally has the problem of fixed output amplitude and difficulty in flexible adjustment. The existing adjustment scheme either sacrifices resolution or requires the introduction of expensive and complex external circuitry, resulting in increased cost, power consumption, poor design flexibility, and difficulty in adapting to changing load conditions. SUMMARY

[0013] The present application aims to overcome the defects in the background art, and aims to solve the problems of fixed output amplitude of the existing digital-to-analog conversion circuit, and the need to sacrifice resolution or introduce complex and high-cost external circuits when adjusting the amplitude. Specifically, the present application is dedicated to providing a low-cost, high-resolution, and high-flexibility digital-to-analog conversion circuit, which can realize dynamic and continuous adjustment of the full-scale range (i.e. amplitude and bias) of the output analog signal without losing the original digital resolution during the adjustment process.

[0014] To achieve the above-mentioned purpose, the present application discloses a digital-to-analog conversion circuit with dynamically adjustable amplitude. The circuit is fundamentally innovative based on the traditional DAC structure, and its core technical solutions include:

[0015] A digital-to-analog conversion circuit includes a digital output module, a switching module, and a weight circuit module. The circuit further includes:

[0016] A high-level adjustable reference source for generating a dynamically adjustable high reference level;

[0017] And a low-level adjustable reference source for generating a dynamically adjustable low reference level;

[0018] The switching module selectively connects multiple input nodes of the weight circuit module to the high-level adjustable reference source or the low-level adjustable reference source according to the control signal of the digital output module;

[0019] The weight circuit module is used to weight process the high reference level or the low reference level selectively accessed by the switching module to generate an analog output signal corresponding to the control signal of the digital output module.

[0020] Further, the weight circuit module is an R-2R ladder resistance network structure;

[0021] The R-2R ladder resistance network structure includes a plurality of resistors with resistance R and resistors with resistance 2R, and has a plurality of input nodes connected to the switching module and an output end generating the analog output signal;

[0022] The switching module connects the corresponding input node to the high-level adjustable reference source or the low-level adjustable reference source according to each bit of the digital control signal of the digital output module.

[0023] Further, the weight circuit module is a binary weighted resistance network structure, which includes:

[0024] A set of weight resistors with resistance varying according to binary weights R, 2R, 4R,..., 2^(n-1)R;

[0025] and a summing operational amplifier;

[0026] wherein one end of each weight resistor is connected to a corresponding output terminal of the switch module as an input node, and the other end is commonly connected to a summing input terminal of the summing operational amplifier, and an output terminal of the summing operational amplifier generates the analog output signal.

[0027] Further, the weight circuit module is a resistor string network structure, which comprises:

[0028] a resistor voltage divider chain composed of a plurality of resistors with the same resistance value connected in series;

[0029] a top end of the resistor voltage divider chain is connected to the high-level adjustable reference source, and a bottom end of the resistor voltage divider chain is connected to the low-level adjustable reference source;

[0030] a multiplexer, a plurality of input terminals of the multiplexer are respectively connected to each connection node of the resistor voltage divider chain; and a digital code output by the digital output module is used as an address signal to control the multiplexer to select one of a plurality of voltage divider levels as the analog output signal.

[0031] Further, the weight circuit module is a current source adder structure, which comprises:

[0032] a constant current source array with binary weighted output currents;

[0033] a common output summing branch;

[0034] the switch module controls the output currents of each weight current source to selectively flow to the common output summing branch according to the digital code of the digital output module;

[0035] all the selected currents are collected in the common output summing branch, and an analog output signal proportional to the digital code is generated through a load element;

[0036] wherein the output current values of each constant current source in the constant current source array are changed in proportion under the control of the level of the high-level adjustable reference source and / or the low-level adjustable reference source.

[0037] Further, the high-level adjustable reference source and the low-level adjustable reference source are adjustable constant voltage sources or adjustable constant current sources.

[0038] Further, the adjustable constant voltage source is implemented in at least one of the following manners:

[0039] a pulse width modulation signal combined with a low-pass filter;

[0040] an adjustable linear voltage regulator;

[0041] A combination of a digital potentiometer and an operational amplifier voltage follower;

[0042] Another digital-to-analog converter is combined with a buffered operational amplifier;

[0043] Dedicated programmable power supply chip.

[0044] Furthermore, the amplitude of the output analog signal is controlled by adjusting the voltage difference between the high reference level and the low reference level.

[0045] Furthermore, the low reference level can be adjusted to a positive voltage, zero voltage, or a negative voltage.

[0046] This application also discloses a method for performing digital-to-analog conversion using a circuit, which specifically includes the following steps:

[0047] Based on the amplitude requirements of the target output signal, set the output voltage of the high-level adjustable reference source and the output voltage of the low-level adjustable reference source;

[0048] The digital code is provided by the digital output module;

[0049] The switching module controls each weight bit of the weighting circuit module to connect to the output voltage of the high-level adjustable reference source or the output voltage of the low-level adjustable reference source according to the digital code.

[0050] The weighting circuit module outputs an analog signal whose dynamic range is limited by the output voltage of the high-level adjustable reference source and the output voltage of the low-level adjustable reference source.

[0051] Beneficial effects of this invention:

[0052] Compared with the prior art, the present invention, by introducing an adjustable dual reference source, has the following significant advantages:

[0053] This invention enables flexible and dynamic adjustment of the output amplitude. It allows for dynamic changes during system operation. and The value of the reference voltage is used to set the full-scale range of the output signal. For example, the output range can be switched from 0~5V to ±2V. This structure can achieve amplitude adjustment without relying on the subsequent programmable gain amplifier circuit, which helps to improve the flexibility, integration and adaptability of the circuit to different application scenarios.

[0054] The digital resolution of the DAC is maintained while adjusting the amplitude. Unlike the traditional method of adjusting the amplitude by reducing the digital input range, in this invention, when... and Once the value is set within the valid range, the input n-digit code will always be within... to "new" full-scale range is effective. The voltage step value corresponding to the least significant bit (LSB) of the digital code will be scaled proportionally with the change of the full-scale range, but the total number of step levels remains unchanged. This achieves compatibility between amplitude control and digital resolution retention.

[0055] It is capable of directly outputting bipolar signals, which helps to simplify system design. By setting the reference voltage to be a negative voltage, setting the reference voltage to be a positive voltage, the circuit of the present application can directly generate a bipolar output signal that crosses zero. This helps to avoid the need to add a charge pump, an inverting amplifier or a negative power supply system in order to generate a negative voltage in the traditional scheme, thereby reducing the complexity and cost of system design.

[0056] The structure and implementation method are flexible. The core weight circuit of the present application can use the mature R-2R resistor network structure. The added adjustable reference source part can be implemented using various schemes such as PWM + filtering, auxiliary DAC or adjustable linear voltage regulator according to different requirements of precision and response speed of applications. Compared with the scheme of "high-performance on-chip DAC + external PGA / VGA", the present application provides a technical approach to balance between structure implementation and functional flexibility. BRIEF DESCRIPTION OF DRAWINGS

[0057] Figure 1 It is a structural schematic diagram of an R-2R digital-to-analog conversion circuit directly driven by a GPIO in the prior art.

[0058] Figure 2 It is a structural schematic diagram of the amplitude-dynamically-adjustable digital-to-analog conversion circuit proposed by the present application.

[0059] Figure 3 It is a circuit structure diagram of the first embodiment of the present application, in which the weight circuit module specifically adopts an R-2R ladder network structure.

[0060] Figure 4 It is a circuit structure diagram of the second embodiment of the present application, in which the weight circuit module specifically adopts a binary-weighted resistor network structure.

[0061] Figure 5 It is a circuit structure diagram of the third embodiment of the present application, in which the weight circuit module specifically adopts a resistor string network structure.

[0062] Figure 6 It is a circuit structure diagram of the fourth embodiment of the present application, in which the weight circuit module specifically adopts a current source adder structure.

[0063] Figure 7 ​​The circuit structure diagram of a specific implementation of one adjustable reference source in the fifth embodiment of the present application is shown in Figure 6, which adopts a combination of a PWM signal and a low-pass filter.

[0064] Figure 8 The circuit structure diagram of a specific implementation of another adjustable reference source in the fifth embodiment of the present application is shown in Figure 7, which is based on an adjustable linear voltage regulator.

[0065] Figure 9 The circuit structure diagram of a specific implementation of another adjustable reference source in the fifth embodiment of the present application is shown in Figure 8, which adopts a series / parallel structure of a Zener diode.

[0066] Figure 10 The circuit structure diagram of a specific implementation of another adjustable reference source in the fifth embodiment of the present application is shown in Figure 9, which adopts a combination of an auxiliary DAC and a buffer operational amplifier.

[0067] Figure 11 The circuit structure diagram of a specific implementation of another adjustable reference source in the fifth embodiment of the present application is shown in Figure 10, which adopts a combination of a digital potentiometer and an operational amplifier follower.

[0068] Figure 12 The circuit structure diagram of a specific implementation of another adjustable reference source in the fifth embodiment of the present application is shown in Figure 11, which adopts a combination of an analog adder / weighted operational amplifier.

[0069] Figure 13 The circuit structure diagram of a specific implementation of another adjustable reference source in the fifth embodiment of the present application is shown in Figure 12, which is an adjustable constant current source structure. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solutions and advantages of the present application clearer and more apparent, the digital-to-analog conversion circuit and conversion method of the present application are further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0071] In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more; the orientations or positional relationships indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "left", "right", "inner", "outer", "front end", "rear end", "head", "tail", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientations or positional relationships shown in the drawings, which are only for the purpose of facilitating the description of the present application and simplifying the description, and are not intended to indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third", etc. are only for the purpose of description and cannot be understood as indicating or implying relative importance.

[0072] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integral connection; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium, or internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0073] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the description of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0074] Embodiment one

[0075] This embodiment details a kind of amplitude dynamic adjustable digital-to-analog conversion circuit based on R-2R ladder resistance network, its structure is as shown in Figure 2 And Figure 3 . Figure 2 It is a system level function block diagram, Figure 3 It is the specific circuit implementation of the scheme on 4 bit R-2R DAC.

[0076] Referring to Figure 2 , the circuit of this embodiment includes:

[0077] Digital output module 46: the module is usually realized by the parallel port of microcontroller (MCU), FPGA, DSP or special integrated circuit. It is responsible for generating an n-bit digital code signal according to the instruction of the upper application, for example, for 4-bit DAC, D3, D2, D1, D0.

[0078] High-level adjustable reference source 43 ( ): the module is a voltage source, and the output voltage of the module can be accurately controlled and adjusted during system operation. It provides high reference level for the whole DAC circuit.

[0079] Low-level adjustable reference source 44 ( ): similar to , the module is a voltage source, and the output voltage of the module can be accurately controlled and adjusted during system operation. It provides low reference level for the whole DAC circuit. The voltage value of the module can be set to positive voltage, zero voltage or negative voltage.

[0080] Switching module 45: This module consists of n independent single-pole double-throw analog switches. In this embodiment, switches S3, S2, S1, and S0 correspond to the digital signals D3, D2, D1, and D0, respectively. The control terminal of each switch is connected to the corresponding bit of the digital output module. When a certain bit Di is logic '1', the corresponding switch Si connects the corresponding node of the weighting circuit to... When Di is logic '0', Si connects the node to... .

[0081] Weighted circuit module 47: In this embodiment, this module adopts an R-2R ladder resistor network structure, such as... Figure 3 As shown, this network consists of resistors with values ​​of R and 2R, ensuring that the Thevenin equivalent resistance seen from any node is R, thus achieving precise binary weight allocation. The final output of the network is... .

[0082] A key characteristic of R-2R ladder networks is their output voltage. It is the weighted average of the voltages connected to all the switches. For an n-bit R-2R DAC, its output voltage is... The general calculation formula is:

[0083]

[0084] Where D is the decimal value corresponding to the input n-bit digital code. For example, for binary 1011, D=11.

[0085] The technical effects of the present invention will be illustrated below through a specific numerical example. Assume this embodiment is an 8-bit DAC (n=8) with a digital input range D of 0~255.

[0086] Scenario A: Analog traditional unipolar DAC.

[0087] The output of the high-level adjustable reference source 43 Set to +5.0V, and set the output of the low-level adjustable reference source 44. Set to 0.0V.

[0088] Operations and Results:

[0089] When the digital input D=0 (binary 00000000), all switches are closed to... According to the formula, .

[0090] When the digital input D=255 (binary 11111111), all switches are closed to... . .

[0091] When the digital input D = 128 (binary 10000000), .

[0092] Under this setting, the behavior of the circuit is exactly the same as a conventional 8-bit DAC with a full-scale range of 0~5V.

[0093] Scenario B: Implementing bipolar, small-swing output, assuming the application requires a bipolar signal with an output range of -2.0V to +2.0V.

[0094] By controlling the system, dynamically adjust the output of to +2.0V, and the output of to -2.0V.

[0095] Operation and results:

[0096] When the digital input D = 0, .

[0097] When the digital input D = 255, .

[0098] When the digital input D = 128, .

[0099] By simply adjusting the two reference voltages, the output range of the circuit is seamlessly switched to [-2.0V, +2.0V]. Most importantly, the entire switching process does not change the effective range of the digital input, so the resolution of the DAC remains a full 8-bit. At this time, the voltage step value represented by the least significant bit is . This demonstrates the advantage of the invention in achieving flexible amplitude adjustment without sacrificing resolution.

[0100] Example Two

[0101] This embodiment discloses another specific implementation of the weight circuit module, namely the binary-weighted resistance network structure, as shown in Figure 4 . This embodiment is the same as Example One except for the weight circuit module 47, the high-level adjustable reference source 43, the low-level adjustable reference source 44, and the switch module 45.

[0102] Referring to Figure 4 , the weight circuit module is composed of a set of resistors (R, 2R, 4R,..., 2^(n-1)R) with binary weight changes and a summing operational amplifier. One end of each weight resistor is connected to or through the corresponding switch. The other end of all these weight resistors is commonly connected to the inverting input terminal of a summing operational amplifier.

[0103] Working principle:

[0104] When this structure is adopted, the output voltage is the voltage generated by the current of each weight branch on the feedback resistor Rf. Its output can also be controlled by and . This structure can also achieve the same amplitude dynamic adjustment function as Example 1. For example, set and to +2V and -2V respectively, and the output range of [-2V, +2V] can be obtained.

[0105] Comparison with Example 1: intuitive structure, easy to understand.

[0106] Example 3

[0107] This embodiment discloses another implementation of the weight circuit module, i.e. a resistor string network structure, as shown in Figure 5 .

[0108] Referring to Figure 5 , the weight circuit module is composed of 2ⁿ identical series resistors to form a long resistor voltage divider chain. The top end of the resistor string is connected to a high-level adjustable constant voltage source , and the bottom end is connected to a low-level adjustable constant voltage source . In this way, a series of stable and evenly distributed voltage levels are generated on the 2ⁿ+1 nodes of the resistor string. The n-bit digital code provided by the digital output module is input into a 2ⁿ-to-1 multiplexer as an address, and the multiplexer selects a corresponding voltage from the numerous nodes of the resistor string as the output according to the address code.

[0109] By adjusting the values of and , the voltage range of the entire resistor voltage divider chain can be directly changed. For example, if =1.5V, =0.5V, the voltage on the resistor string will be evenly distributed between 0.5V and 1.5V. The digital input code selects one of the voltage divider points for output, thereby realizing digital-to-analog conversion within the range of [0.5V, 1.5V].

[0110] Comparison with the foregoing examples: simple structure, and since all resistors have the same value, it is easy to match, thus ensuring good monotonicity, i.e. the output voltage changes in one direction with the increase of the digital code.

[0111] Example 4

[0112] This embodiment discloses a weight circuit module based on a current source adder structure.

[0113] Referring to Figure 6 , the embodiment discloses a weight circuit module based on current source adder structure, which works similarly to binary weighted resistor network. The core of this structure is a set of binary weighted constant current source array. Digital input code Di controls, through switches, whether each weight current Ii flows to a common output summing branch or to ground. All selected currents flow through a load resistor after being collected in the output branch, thereby generating a voltage output proportional to the digital input code on the resistor.

[0114] In the framework of the present invention, the size of these constant current sources is no longer fixed, but is controlled by a high-level adjustable reference source VrefHigh or a low-level adjustable reference source VrefLow (or a combination thereof). For example, a reference voltage can be used to drive a reference current source, while all other current sources in the array are exact multiples or fractions of this reference current. By adjusting this reference voltage (i.e. VrefHigh or VrefLow), all weight currents can be scaled proportionally, thereby directly controlling the amplitude of the final output voltage.

[0115] Embodiment five

[0116] This embodiment will focus on the various specific hardware implementation schemes of the high-level adjustable reference source 43 and the low-level adjustable reference source 44, which are components of the present invention. It is important to emphasize that any of the schemes described below can be used independently or in combination to implement and . The choice of these schemes depends on the specific requirements of the application, such as cost, accuracy, power consumption, response speed, and control method. Moreover, the implementation schemes of these reference sources can be flexibly combined with any of the weight circuit modules described in the aforementioned embodiments one to four to form the complete technical solution of the present invention.

[0117] This embodiment aims to illustrate that the protection scope of the present invention does not depend on a specific reference voltage generation structure; any technology that can provide a stable, adjustable, and controllable voltage or current source as a reference level for the weight circuit falls within the scope of the present invention.

[0118] Scheme A: based on pulse width modulation (PWM) signal and low-pass filter.

[0119] As Figure 7 shown, this is a very low-cost implementation.

[0120] A PWM peripheral of the digital controller generates a square wave signal with a fixed frequency but adjustable duty cycle.

[0121] The PWM signal is passed through a simple passive low-pass filter, such as an RC filter.

[0122] The filter will filter out the high-frequency components of the PWM, outputting a stable DC voltage proportional to the duty cycle of the PWM. For example, if the high level of the PWM is 3.3V, the output voltage will be proportional to the duty cycle of the PWM.

[0123] In order to provide sufficient driving capability, a voltage follower composed of an operational amplifier is usually added as a buffer after the filter. Through two independent PWM channels, we can generate and respectively. If negative voltage is needed, it can be obtained by an inverting operational amplifier circuit after generating positive voltage.

[0124] Scheme B: Based on adjustable linear voltage regulator.

[0125] As shown in Figure 8 , this scheme uses an adjustable output linear voltage regulator chip to achieve dynamic voltage adjustment by digitally controlling its feedback network.

[0126] Circuit composition:

[0127] Adjustable LDO chip: For example, the classic LM317 or the modern low-dropout LDO chip. This type of chip has an output terminal (OUT), an input terminal (IN), and an adjustment terminal (ADJ).

[0128] Feedback resistor network: Usually composed of two resistors R1 and R2. R1 is connected between OUT and ADJ, and R2 is connected between ADJ and ground.

[0129] Digital control element: In order to achieve dynamic adjustment, resistor R2 or R1 can be replaced by a digital potentiometer. A digital potentiometer is an integrated circuit that can change its resistance value through a digital interface.

[0130] Working principle: The working principle of the adjustable LDO is that the internal circuit will adjust its output so that the voltage at the ADJ terminal is always maintained at a very stable internal reference voltage . The output voltage is determined by the feedback network:

[0131]

[0132] By sending instructions to the digital potentiometer through the MCU, we can change the equivalent resistance of R2, i.e. the equivalent resistance of R2, to accurately and programmatically change the output voltage .

[0133] The output voltage is very stable, with very low ripple and high power supply rejection ratio.

[0134] Scheme C: Based on the series / parallel structure of Zener diodes.

[0135] This scheme uses the reverse breakdown voltage regulation characteristics of Zener diodes to generate a series of discrete, fixed reference voltage levels through switch combinations.

[0136] Please refer to Figure 9 , the circuit composition is:

[0137] Multiple Zener diodes: Select Zener diodes with different stable voltages.

[0138] Analog switch array: A set of analog switches controlled by the MCU.

[0139] Current limiting resistor and buffer: Current limiting resistor to provide appropriate working current for Zener diodes, and voltage follower for output.

[0140] By controlling the analog switches to different paths through the MCU, you can select a single Zener diode, or connect multiple Zener diodes in series. For example, there are two Zener diodes with 3.3V and 5.1V, you can select 3.3V, 5.1V or 8.4V by connecting the two in series. By using the forward conduction voltage and reverse breakdown voltage of Zener diodes, more voltage values can be combined.

[0141] This scheme has a simple structure and the generated voltage is very stable.

[0142] Scheme D: Based on auxiliary DAC and buffer operational amplifier.

[0143] Please refer to Figure 10 , the circuit composition is:

[0144] Auxiliary digital-to-analog converter: A separate DAC chip, or an internal DAC module integrated in the MCU. Its resolution can be lower than the main DAC, for example, use an 8-bit DAC to control a 12-bit main DAC reference source.

[0145] Buffer operational amplifier: Configured as a voltage follower, connected to the output of the auxiliary DAC to provide driving capability.

[0146] Working principle: The MCU writes a digital code to the auxiliary DAC through a digital interface (such as SPI, I2C or parallel bus). The auxiliary DAC converts this code into an accurate analog voltage. After buffering by the operational amplifier, it becomes a stable and low output impedance reference source ( or ). Since the output of the auxiliary DAC is continuously adjustable, the generated reference source is also continuously adjustable.

[0147] This scheme has the advantage of high precision, resolution determined by the auxiliary DAC, easy digital control, and fast response speed.

[0148] Scheme E: Based on digital potentiometer and operational amplifier follower.

[0149] This scheme is similar to scheme B, but the structure is more direct, using a digital potentiometer as a programmable voltage divider.

[0150] Please refer to Figure 11 , circuit composition:

[0151] Digital potentiometer: its two ends are connected to a stable high voltage and ground.

[0152] Operational amplifier: its non-inverting input is connected to the wiper of the digital potentiometer, and is configured as a voltage follower.

[0153] Working principle: the digital potentiometer internally has a resistor string and a series of switches controlled by digital logic. By sending a value through the SPI or I2C interface, you can choose to connect the wiper W to different voltage division points on the resistor string. Therefore, the voltage at W can be linearly changed between and This voltage is buffered by the operational amplifier and output, which becomes the adjustable reference voltage. This scheme is simple to control and can achieve linear voltage regulation in a large range.

[0154] Scheme F: Based on analog adder / weighted operational amplifier structure.

[0155] This scheme uses the summing function of the operational amplifier to combine multiple input signals to synthesize the required reference voltage.

[0156] Please refer to

[0157] , circuit composition: an operational amplifier inverting or non-inverting adder circuit. The input end can be connected to multiple controllable voltage source signals. Figure 12 Working principle: for an inverting adder, the output voltage is:

[0158]

[0159]

[0160] By controlling which input voltages (V1, V2...) are connected through digital switches, or by adjusting the input resistors (R1, R2...) to change their weights, a very flexible output voltage can be synthesized. This can achieve more complex amplitude mapping or nonlinear response relationships.

[0161] This scheme is extremely flexible and can achieve complex voltage synthesis. ​

[0162] Scheme G: based on a dedicated programmable power supply chip.

[0163] A dedicated programmable power supply chip or power management integrated circuit.

[0164] Working principle: This kind of chip integrates a high-precision bandgap reference, DAC, error amplifier and output stage inside. The user can directly write a digital value to the chip through a standard digital communication interface, and the chip can generate a corresponding high-precision, large-drive-capability stable voltage at its output.

[0165] The advantage of this scheme is excellent performance, high precision, good stability, low noise, and usually integrated with overcurrent, overtemperature and other protection functions.

[0166] Scheme H: based on an adjustable constant current source.

[0167] This scheme is to generate an adjustable current first, and then convert it to an adjustable voltage through a precision resistor.

[0168] Please refer to Figure 13 , circuit composition:

[0169] Adjustable constant current source: for example, a voltage-controlled current source composed of an operational amplifier and a transistor, the control voltage of which can be generated by any of the above schemes.

[0170] Load resistor: a low-temperature-coefficient high-precision resistor.

[0171] Working principle: the adjustable constant current source outputs an accurately controllable current . This current flows through the load resistor , and according to Ohm's law, a voltage = × is generated across the load resistor . By adjusting , the voltage can be accurately controlled. . This scheme can realize a load-independent stable voltage, and is especially suitable for some specific circuit topologies. This embodiment demonstrates in detail a variety of ways to realize the core idea of the application. In actual product design, the above schemes can be flexibly selected or combined according to specific technical indicators and cost budget, to build an efficient and reliable high / low level adjustable reference source, so as to realize the amplitude dynamic adjustable function of the entire digital-to-analog conversion circuit.

[0172] This embodiment demonstrates in detail a variety of ways to realize the core idea of the application. In actual product design, the above schemes can be flexibly selected or combined according to specific technical indicators and cost budget, to build an efficient and reliable high / low level adjustable reference source, so as to realize the amplitude dynamic adjustable function of the entire digital-to-analog conversion circuit.

[0173] This embodiment demonstrates in detail a variety of ways to realize the core idea of the application. In actual product design, the above schemes can be flexibly selected or combined according to specific technical indicators and cost budget, to build an efficient and reliable high / low level adjustable reference source, so as to realize the amplitude dynamic adjustable function of the entire digital-to-analog conversion circuit.

[0174] The above merely describes preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application. Any person skilled in the art, without departing from the technical solution of the present application, can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solution of the present application, shall still fall within the scope of the technical solution of the present application.

Claims

1. A digital-to-analog conversion circuit comprising a digital output module, a switching module and a weight circuit module, characterized in that, The circuit further comprises: a high-level adjustable reference source for generating a dynamically adjustable high reference level; a low-level adjustable reference source for generating a dynamically adjustable low reference level; the switch module selectively connects the multiple input nodes of the weight circuit module to the high-level adjustable reference source or the low-level adjustable reference source according to the control signal of the digital output module; the weight circuit module is configured to perform weighting processing on the high reference level or the low reference level selectively accessed by the switch module to generate an analog output signal corresponding to the control signal of the digital output module.

2. The digital-to-analog conversion circuit according to claim 1, wherein: the weight circuit module is an R-2R ladder resistor network structure; the R-2R ladder resistor network structure comprises multiple resistors with resistance R and multiple resistors with resistance 2R, and has multiple input nodes connected to the switch module and an output terminal for generating the analog output signal; the switch module connects the corresponding input node to the high-level adjustable reference source or the low-level adjustable reference source according to each digital control signal of the digital output module.

3. The digital-to-analog conversion circuit of claim 1, wherein: the weight circuit module is a binary weighted resistor network structure, which comprises: a set of weight resistors with resistance changing according to binary weights R, 2R, 4R,..., 2^(n-1)R; and a summing operational amplifier; wherein one end of each weight resistor is connected to the corresponding output terminal of the switch module as an input node, and the other end is commonly connected to the summing input terminal of the summing operational amplifier, and the output terminal of the summing operational amplifier generates the analog output signal.

4. The digital-to-analog conversion circuit of claim 1, wherein: the weight circuit module is a resistor string network structure, which comprises: a resistor voltage divider chain formed by multiple resistors with the same resistance connected in series; the top end of the resistor voltage divider chain is connected to the high-level adjustable reference source, and the bottom end is connected to the low-level adjustable reference source; a multiplexer, multiple input terminals of which are connected to the connection nodes of the resistor voltage divider chain respectively; and the digital code output by the digital output module is used as an address signal to control the multiplexer to select one of the multiple voltage divider levels as the analog output signal.

5. The digital-to-analog conversion circuit of claim 1, wherein: the weight circuit module is a current source adder structure, which comprises: a constant current source array with binary weighted output currents; a common output summing branch; the switch module controls the output currents of each weight current source to selectively flow to the common output summing branch according to the digital code output by the digital output module; all the selected currents are collected in the common output summing branch, and then pass through a load element to generate an analog output signal proportional to the digital code; wherein the output current values of the constant current sources in the constant current source array change proportionally under the control of the high-level adjustable reference source and / or the low-level adjustable reference source.

6. The digital-to-analog conversion circuit of claim 1, wherein: the high-level adjustable reference source and the low-level adjustable reference source are adjustable constant voltage sources or adjustable constant current sources.

7. The digital-to-analog conversion circuit of claim 6, wherein: the adjustable constant voltage source is implemented in at least one of the following ways: A pulse width modulated signal is combined with a low pass filter; Adjustable linear voltage regulator; A digital potentiometer is combined with an operational amplifier voltage follower; Another digital to analog converter is combined with a buffer operational amplifier; A dedicated programmable power supply chip.

8. The digital-to-analog conversion circuit of claim 1, wherein: The amplitude of the output analog signal is controlled by adjusting the voltage difference between the high and low reference levels.

9. The digital-to-analog conversion circuit of claim 1, wherein: The low reference level can be adjusted to be a positive voltage, zero voltage, or negative voltage.

10. A method of digital-to-analog conversion using the digital-to-analog conversion circuit according to any one of claims 1 to 9, characterized by, The method comprises the following steps: According to the amplitude requirement of the target output signal, the output voltage of the high level adjustable reference source and the output voltage of the low level adjustable reference source are set; A digital code is provided by the digital output module; The switch module controls each weight bit of the weight circuit module to access the output voltage of the high level adjustable reference source or the output voltage of the low level adjustable reference source according to the digital code; The weight circuit module outputs an analog signal, and the dynamic range of the analog signal is defined by the output voltage of the high level adjustable reference source and the output voltage of the low level adjustable reference source.

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