A neural network deployment method of a reRAM computing and storage integrated array

Abstract

The application discloses a neural network deployment method of a ReRAM memory-computing integrated array, comprising the following steps: (1) adopting a Reset-Set double sequence verification combined with a non-disturbance conductance reading, subdividing device states of the ReRAM array into three categories of easy-to-use states, low-impact states and high-impact states; configuring differentiated scores, and generating a state matrix and a score matrix consistent with the dimension of the ReRAM array; (2) based on the state matrix and the score matrix, taking the maximum normalized score rate of a subarray as the target, and through the combination of a greedy algorithm, a hill climbing algorithm and a genetic algorithm, a target subarray matched with a target weight matrix is screened out; (3) the target weight matrix is mapped to the target subarray according to rows and columns, the weight is converted into a device conductance through an adaptive programming pulse, and solidification deployment is completed. By using the application, the hardware utilization rate of the ReRAM memory-computing integrated array and the neural network weight deployment efficiency can be significantly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor storage and neural network hardware acceleration technology, and in particular to a method for deploying neural networks using a ReRAM in-memory computing array. Background Technology

[0002] The core advantage of Resistive Random Access Memory (ReRAM) cross-arrays lies in their inherent support for parallel inference through in-memory computing. Their cross-row physical structure can directly construct the computational path for parallel inference in neural networks: by inputting feature vectors in parallel through row electrodes and collecting the output current after weight calculations synchronously through column electrodes, the core operation of matrix-vector multiplication in neural networks can be completed in a single clock cycle. This fundamentally breaks through the data transport bottleneck of the traditional "storage-computation separation" architecture, thus becoming the preferred hardware solution for carrying neural network weights and achieving efficient parallel inference in scenarios such as edge computing and AI acceleration chips.

[0003] When deploying neural networks on a ReRAM cross-array, the core interconnectivity directly addresses the structural requirements of parallel inference: a complete K-row L-column cross-array structure (rather than isolated K×L devices) matching the target weight size needs to be selected from the original M×N array. The "K rows" of this subarray must correspond to the K row vectors of the weight matrix, and the "L columns" must correspond to the L column vectors of the weight matrix. Parallel computation pathways are built through the physical connection of "row-column cross-arrays." Only this complete row-column cross-array structure can ensure that the input signal is accurately distributed to each weight unit and the output current is synchronously aggregated, ultimately achieving stable parallel inference.

[0004] Therefore, the selection accuracy of the subarray not only determines the accuracy of the weight mapping but also directly affects the computational efficiency and reliability of parallel inference results. This process is constrained by both algorithm complexity and the non-ideal characteristics of hardware, facing two major challenges:

[0005] (1) Subarray selection faces an NP-hard row and column cross-selection dilemma. Subarray selection is essentially a two-dimensional combinatorial optimization problem of "selecting K rows from M rows and L complete columns from N columns, and ensuring that the selected K rows and L columns form an effective cross-operation path", which has been proven to be an NP-hard problem. As the array size increases (e.g., 256×256 and above), the number of feasible row and column cross-combinations grows exponentially, and is completely different from the selection logic of traditional storage - traditional storage only needs to ensure that the total capacity meets the standard, without needing to select complete row and column cross-structures, and even less needing to deal with such a two-dimensional selection problem that is strongly tied to parallel inference paths.

[0006] (2) Device heterogeneity exacerbates the complexity of row and column crossover decisions. ReRAM is affected by manufacturing process deviations, resulting in significant multi-state differentiation in device performance (rather than the binary characteristic of "good / bad cells" in traditional memory): if there are many resistive-locked deviation devices in a complete row / column, it may cause the entire parallel path of that row / column to fail (rather than the failure of a single device). Excessive removal of such "problem rows and columns" will significantly reduce the range of available row and column crossover combinations, reducing the hardware utilization of parallel inference; if too much is tolerated, it will cause multiple row and column paths to be distorted simultaneously during parallel operation, and the superposition of deviations will seriously degrade the accuracy of neural network inference. Traditional memory only needs to remove isolated bad devices to ensure data storage function, without considering the impact of "the state of the entire row / column on the parallel inference path", and there is no such decision trade-off.

[0007] The combination of these problems means that existing solutions cannot support high-precision and high-efficiency weight mapping and solidification through effective screening logic. They also struggle to balance the accuracy, efficiency, and hardware utilization of ReRAM neural network deployment, becoming a key bottleneck restricting its large-scale application. Summary of the Invention

[0008] To address the bottlenecks in neural network deployment of ReRAM in-memory computing arrays, namely the difficulty in overcoming NP-hard subarray selection and the imbalance between accuracy and utilization caused by coarse device state classification, this invention provides a neural network deployment method for ReRAM in-memory computing arrays, which can significantly improve the hardware utilization and neural network weight deployment efficiency of ReRAM in-memory computing arrays.

[0009] A method for deploying neural networks using a ReRAM in-memory computing array includes the following steps:

[0010] (1) Using Reset-Set dual-sequence verification combined with perturbation-free conductance reading, The device states of a large-scale ReRAM array are subdivided into usable states. Low impact state High-impact state Three categories; according to Configure differentiated scores to generate a state matrix with dimensions consistent with the ReRAM array. Score matrix ;in, , , Corresponding to states respectively , , ;

[0011] (2) Based on the state matrix Score matrix The subarray normalized score rate With the objective of maximizing the target, a combination of greedy, hill-climbing, and genetic algorithms is used to select a target subarray that matches the target weight matrix, with a size of [missing value]. ;

[0012] (3) Map the target weight matrix to the target subarray by row and column, and convert the weights into device conductivity through the appropriate programming pulse to complete the solidification deployment.

[0013] Step (1) Differentiate devices using specific electrical test sequences Status, prioritize retention Limited tolerance Prioritize avoiding The scores are configured based on the accuracy requirements of the neural network, providing a quantitative basis for subarray selection.

[0014] Easy-to-use status Its resistive switching characteristics are stable, and its adjustable conductance range completely covers the weight quantization range of the neural network. The weight solidification error is controllable and has no negative impact on inference accuracy, making it an ideal weight mapping carrier.

[0015] Low impact state The device is locked in a high-resistivity state (corresponding to low conductance), and cannot switch to the target low-resistivity state even when a Set (low-resistance) pulse is applied. Since low conductance corresponds to small weights (or weights close to 0) in the neural network, its fixed bias has a limited impact on the overall feature extraction and inference results, which is a tolerable low-impact state.

[0016] High-impact status The device is locked in a low-resistance state (corresponding to high conductance), and even if a Reset pulse is applied, it cannot switch to the target high-resistance state. High conductance corresponds to large weights in the neural network, and large weights contribute significantly to the output results in feature transfer—their fixed bias will be amplified and dominate the inference error, which is the main cause of a significant decrease in the accuracy of the neural network. It is a high-impact state that needs to be strictly controlled.

[0017] In step (1), the Reset-Set dual-sequence verification combined with perturbation-free conductance reading is used, specifically including:

[0018] The parameters of the Reset voltage pulse sequence and Set voltage pulse sequence are preset according to the characteristics of the ReRAM device (resistive switching window, threshold voltage, etc.); among which, the voltage start value, end value, step size, and pulse width can be adjusted as needed (example configuration: start value 1V, end value 3V, step size 0.1V and pulse width 100ns).

[0019] First, apply a Reset voltage pulse sequence to the device, gradually increasing the voltage step by step. Pause after each voltage step is completed, and then apply a non-disturbance reading voltage (configured according to device characteristics, such as 0.1V, the core function of which is to avoid disturbing the current resistive switching state of the device). Read and record the device's conductance value in real time until the conductance reaches the threshold or the voltage reaches the termination value.

[0020] After the Reset voltage pulse sequence verification is completed, the same method is used to apply the Set voltage pulse sequence to the ReRAM device and record the conductance value until the conductance reaches the threshold or the voltage reaches the termination value.

[0021] In step (1), based on the device state step-by-step judgment rule, the following steps are performed: The device states of a large-scale ReRAM array are subdivided into usable states. Low impact state High-impact state Three categories, as detailed below:

[0022] First, determine the high-impact status. For all devices, if the conductance remains greater than the preset high-resistance threshold (e.g., 200 μS) after the Reset voltage pulse sequence operation, and can only maintain a low-resistance state (corresponding to high conductance), it is determined to be a high-impact state. ;

[0023] In exclusion If, after the Set voltage pulse sequence operation, the conductance remains below the preset low-resistance threshold (e.g., 550 μS), it can only maintain a high-resistance state (corresponding to low conductance), and is thus determined to be a low-impact state. ;

[0024] After the above two elimination steps, the remaining devices are determined to be in an easy-to-use state. This indicates that the device's resistive switching characteristics are stable and its conductivity covers the weighted quantization range, meeting the requirements for ease of use.

[0025] In step (1), the state matrix middle Mapping ReRAM array OK List device status; scoring matrix middle Follow Pick , or ,and , , Adjust according to accuracy requirements.

[0026] Matrix dimension: State matrix The number of rows and the number of rows in the ReRAM array Same, number of columns and number of columns in ReRAM array Same, that is for Line × Column matrix;

[0027] Element definition: The element in the matrix. line, number Column (of which) , ) elements Directly maps the corresponding position in the ReRAM array (the first position) line, number The detection status of the (column) device, with a value range of [value range missing]. ;

[0028] If ReRAM is the line, number If the device is determined to be in an easy-to-use state, then If it is determined to be a low-impact state, then If it is determined to be a high-impact state, then .

[0029] Based on the logic that "the greater the impact of device state on inference accuracy, the lower the score," the core constraint is set as follows: --in, (No impact) Highest score configuration , (Low impact) Configuration with medium score , (High Impact) Configuration Minimum Score The specific score can be dynamically adjusted according to the actual reasoning accuracy requirements. (Example configuration:) It does not need to be limited to a fixed value, so as to adapt to the needs of balancing accuracy and hardware utilization in different scenarios.

[0030] The score matrix W is an M-row × N-column matrix (with the same dimensions as the state matrix S and the ReRAM array), and its th... line, number Column elements The value is determined by the state matrix elements at the corresponding positions. The decision is:

[0031] ;

[0032] In step (2), the subarray normalized score rate The formula is:

[0033] ;

[0034] In the formula, For the target subarray size, For the selected row set, To select the column set, for The score of the state device, Representing the score matrix The Middle OK The score of the column.

[0035] In step (2), a target subarray matching the target weight size is selected by combining greedy algorithm, hill-climbing algorithm, and genetic algorithm, specifically as follows:

[0036] Greedy Algorithm: Select the top results in descending order of row and column scores. OK, Columns, to obtain the initial row set Initial column set ;

[0037] Hill Climbing Algorithm: Recursively Replace Initial Row Set Lowest row and unselected highest row, initial column set The lowest selected column and the highest unselected column are selected and replaced until no replacement is needed, resulting in the optimized row set. , column set ;

[0038] Genetic Algorithm: Position row encoding ( (binary 1) and Position code ( The binary 1) represents the selection scheme, which, after population initialization, selection, crossover, mutation, and elite retention operations, iterates to obtain the final optimized row set. , column set That is, the target subarray.

[0039] The details of the three algorithms are explained below.

[0040] (2-1) Greedy Algorithm for Fast Initialization

[0041] (2-1-1) row filtering: the first row The score for the line is Calculate the score for each row, according to Before selecting descending order , thus obtaining the initial row set. ;

[0042] (2-1-2) Column Filtering: The The column's score is Calculate the score for each column, by Before selecting descending order Columns, to obtain the initial column set

[0043] (2-2) Hill Climbing Algorithm Optimization

[0044] (2-2-1) Initialization: Set the current row set = Current Column Set = ;

[0045] (2-2-2) Row optimization: Calculate all rows in Scoring under constraints ;position The row with the lowest score ;Calculate the row with the highest score among the unselected rows ;like Then use row replace line Otherwise, stop line optimization.

[0046] (2-2-3) Column optimization: All columns in Scoring under constraints ;position The column with the lowest score ;Calculate the column with the highest score among the unselected columns. ;like Then use columns replace Columns in Otherwise, stop column optimization.

[0047] (2-2-4) Iteration: Iterate by row optimization → column optimization until no replacement is needed in row optimization and no replacement is needed in column optimization in a single iteration, and output the set of rows after local optimization. Column set .

[0048] (2-3) Genetic Algorithm Optimization

[0049] (2-3-1) Encoding scheme: A dual encoding (row encoding + column encoding) structure is used to represent the individual selection scheme. The row encoding is M bits (binary 1 indicates that the row is selected, with a total of K binary 1s); the column encoding is N bits (binary 1 indicates that the column is selected, with a total of L binary 1s).

[0050] (2-3-2) Population Initialization: Set the preset population size (typical values ​​are adapted to ReRAM array size: 100 for 128×128 array, 200 for 256×256 array, and 400 for 512×512 array, balancing optimization accuracy and efficiency); the population includes high-quality individuals (based on...). Random mutation (keeping the number of binary 1s constant, accounting for 60%) and random individuals (randomly selected) OK / (40% of the population is included in the initial population) to ensure that the initial population has both a high-quality foundation and diversity;

[0051] (2-3-3) Genetic operations: Iterate a preset number of times (e.g., 500 times), and execute "selection → crossover → mutation → elite retention" each time:

[0052] a) Selection: A tournament strategy is adopted, and 3 to 5 individuals are randomly selected each time to form a group (3 for a 128×128 array, 4 for a 256×256 array, and 5 for a 512×512 array). The normalized score rate of the corresponding subarray within the group is selected. The tallest individual serves as the parent generation;

[0053] b) Crossover: Pair the parent individuals and perform double-point crossover on the row / column codes respectively. If the number of binary 1s deviates from K / L after crossover, it is corrected by "if there are too many, the binary 1s corresponding to the lowest score row / column are converted to 0, and if there are too few, the binary 0s corresponding to the highest score row / column are converted to binary 1".

[0054] c) Mutation: Perform swap mutation on the offspring after crossover (swap one 1 and one 0 state in each row / column encoding) to ensure that the number of binary 1s remains unchanged;

[0055] d) Elite Preservation: Normalizing the score of the parent neutron array The top 10% of the best individuals are directly included in the offspring to avoid losing high-quality solutions;

[0056] (2-3-4) Output: After the iteration is complete, select the individual with the highest fitness in the population and parse it to obtain the final row set. Column set Corresponding subarray .

[0057] In this invention, the population size of the genetic algorithm is adapted to the ReRAM array size, and high-quality mutant individuals are based on... , Generate and maintain the same number of binary 1s in the encoding.

[0058] In the genetic algorithm, row and column codes are crossed at two points. If the number of binary 1s in the row code deviates from K or the number of binary 1s in the column code deviates from L, then the binary 1s corresponding to the lowest-scoring row / column are changed to 0, or the binary 0s corresponding to the highest-scoring row / column are changed to 1.

[0059] The specific process of step (3) is as follows:

[0060] (3-1) Weight mapping: mapping the weights of the neural network The weight matrix line, number Each weight ( , ), mapped to subarray OK, ReRAM devices in series;

[0061] (3-2) Weight solidification: By using the preset programming pulse of the adjustable conductivity characteristic of the adapter device (the parameters are calibrated according to the resistivity curve of the device), the weight value is converted into the target conductivity of the corresponding ReRAM device, thus completing the weight solidification and finally realizing the deployment of the neural network on the ReRAM array.

[0062] Compared with the prior art, the present invention has the following beneficial effects:

[0063] 1. Overcoming the NP-hard screening dilemma and abandoning the limitations of traditional single algorithms, the algorithm effectively solves the NP-hard problem of subarray screening through a three-level collaborative algorithm of "greedy initialization - hill climbing optimization - genetic optimization", selecting K-row L-column subarrays that fit the weight mapping and ensuring the screening effect.

[0064] 2. Balancing inference accuracy and hardware utilization to adapt to diverse needs: Breaking away from the traditional "good / bad binary judgment" logic of storage, ReRAM devices are subdivided into... (Easy to use) (Low impact) (High impact) Three categories, combined Dynamic score configuration, limited tolerance To avoid hardware waste, strict control To ensure accuracy; scores can be adjusted as needed, flexibly adapting to scenarios prioritizing accuracy or hardware utilization, without the need to redesign the filtering logic.

[0065] 3. Supports multi-size subarray screening, improving adaptability and deployment efficiency. Through dimension-independent screening logic, it can support the deployment of neural network weights of any size from 1×1 to M×N, without the need to design dedicated screening modules for different neural network layers (such as convolutional layers and fully connected layers); it integrates the end-to-end process and automatically completes the deployment from device detection to weight solidification, improving deployment efficiency.

[0066] 4. Adapt to in-memory computing and parallel inference to ensure reliable computational pathways. The selection target is "complete". OK The "column cross structure subarray" instead of isolated devices can directly build a stable parallel computing path; at the same time, the algorithm ensures the stability of the device state within the subarray, reduces the deviation of parallel computing, and fully releases the parallel efficiency of ReRAM in-memory computing. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0068] Figure 1 This is a flowchart of a neural network deployment method for a ReRAM in-memory computing array according to an embodiment of the present invention.

[0069] Figure 2 This is a flowchart of the ReRAM device state detection process used in the embodiments of the present invention. Detailed Implementation

[0070] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0071] It should be noted that, unless otherwise specified, the features in the following embodiments and implementation methods can be combined with each other.

[0072] The prerequisites for implementing this invention are as follows:

[0073] ReRAM array: A 256×256 ReRAM cross-connect array is used. , The device's resistive switching window covers the conductance range corresponding to the neural network weights, supporting Reset / Set resistive state switching and perturbation-free conductance reading.

[0074] Neural Network Requirement: The target weight size of a certain layer in the neural network to be deployed is 100×100 ( , , , ).

[0075] Preset parameters and calibration logic:

[0076] (1) Electrical detection parameters: The disturbance-free reading voltage is set to 0.1V (this voltage does not change the resistance state of the device); Reset voltage pulse sequence (start 1V, end 3V, step size 0.1V, pulse width 100ns, to ensure coverage of the high resistance state switching range); Set voltage pulse sequence (start 1V, end 3V, step size 0.1V, pulse width 100ns, to avoid overvoltage damage).

[0077] (2) State determination threshold: High resistance threshold 200μS (corresponding to the low conductivity range with a weight close to 0, When locking high resistance, the conductance is less than 200μS, which is tolerable for weighting; the low resistance threshold is 550μS (corresponding to a medium weighting range). It needs to be able to switch to a state longer than 550μs to cover the weight mapping requirements.

[0078] (3) Algorithm parameters: Genetic algorithm population size 200; number of iterations 500.

[0079] The implementation process of this invention is as follows: Figure 1 As shown, a method for deploying a neural network using a ReRAM in-memory computing array includes the following steps:

[0080] Step 1: ReRAM device state detection and dynamic score matrix construction.

[0081] 1.1 Device status detection, such as Figure 2 As shown:

[0082] (1) Single device verification: the first stage of the gating array line, number Series of devices ( , First, a Reset voltage pulse sequence is applied. After each step of voltage boosting, a 0.1V uninterrupted read voltage is applied to read the conductance. Then, a Set voltage sequence is applied to read the conductance synchronously. The above voltage application and reading process continues until the device conductance reaches a preset threshold or the voltage rises to the end value of the sequence.

[0083] Status determination:

[0084] a) First determine If the conductivity remains greater than 200 μS after a reset, it is determined to be... (High-impact status corresponds to high weight; deviations must be avoided.)

[0085] b) In exclusion Among the remaining devices, determine If the conductivity remains less than 550 μS after setting, it is determined to be... (Low impact state, corresponding to low weight, deviation is tolerable).

[0086] c) After the above two elimination steps, the remaining devices are determined to be... Its conductance after reset is less than or equal to 200 μS and its conductance after set is greater than or equal to 550 μS, and it is judged as (Easy to use);

[0087] d) Traversal detection: Repeat steps 1.1(1) to 1.1(2) to complete the detection of all devices in the 256×256 array, and obtain the statistics. Approximately 95.5% Approximately 4% It accounts for approximately 0.5%.

[0088] 1.2 Construction of the State Matrix and Score Matrix:

[0089] (1) State matrix S: Construct a 256×256 matrix, Assign values ​​according to the test results ( →0, →1, →2), directly map the state of the array devices.

[0090] (2) Score matrix W: Core constraint configuration with lower score for greater influence ( ),set up =1 ( (No impact) =0.2 ( (Low impact) =-0.2 ( (High impact, enhanced avoidance); generate a 256×256 matrix W, Follow Values:

[0091] ;

[0092] Step 2: 100×100 subarray screening using a three-level algorithm.

[0093] Normalized score by subarray The maximum value is the target (R is the selected row set, C is the selected column set, K=100, L=100). Perform three-level screening:

[0094] 2.1 Greedy Algorithm for Fast Initialization:

[0095] (1) Row filtering: Calculate the score for each row. ,according to Select the first K rows in descending order to obtain the initial row set. ;

[0096] (2) Column filtering: Calculate the score for each column. ,according to Select the first L columns in descending order to obtain the initial column set. ;

[0097] (3) Initial subarray: Subarray normalized score .

[0098] 2.2 Hill Climbing Algorithm Optimization:

[0099] (1) Initialization: Set the current row set = Current Column Set = ;

[0100] (2) Row optimization: Calculate all rows in Scoring under constraints ,turn up The row with the lowest score , ;Calculate the row with the highest score among the unselected rows ;like Then use row replace line ,renew Otherwise, stop line optimization.

[0101] (3) Column optimization: All columns in Scoring under constraints ;position The column with the lowest score ;Calculate the column with the highest score among the unselected columns. ;like Then use columns replace Columns in ,renew Otherwise, stop column optimization.

[0102] (4) Iteration Termination: Iterate in a loop from row optimization to column optimization until there are no replacements in row optimization and no replacements in column optimization in a single iteration, and output the set of rows after local optimization. Column set Subarray normalized score .

[0103] 2.3 Genetic Algorithm Optimization:

[0104] (1) Encoding: The row encoding is 256 bits (100 bits of binary 1 represent the selected row), the column encoding is 256 bits (100 bits of binary 1 represent the selected column), and each individual is "row encoding + column encoding";

[0105] (2) Population initialization: 200 individuals (60% of which are high-quality individuals: based on) Random mutation, keeping the number of binary 1s constant at 60%, randomly swapping the positions of one binary 1 and one binary 0, keeping the total number of 100 binary 1s constant; 40% are random individuals: randomly selected from 100 rows and 100 columns).

[0106] (3) Genetic operations (500 iterations):

[0107] a) Selection: Group 3 individuals into 1 group (tournament strategy), and select the individual with the highest F in the group as the parent;

[0108] b) Crossing: After the parent generation is paired, the row / column codes are crossed at two points (e.g., the row code is crossed at the 50th and 150th positions). If the number of binary 1s deviates from 100, if it is greater than 100, the binary 1 corresponding to the lowest score row / column is converted to 0; if it is less than 100, the binary 0 corresponding to the highest score row / column is converted to 1.

[0109] c) Mutation: The child generation row / column encodings each swap one binary 1 and one binary 0 (swap mutation), retaining 100 binary 1s;

[0110] d) Elite retention: The top 20 from the parent generation (highest F) directly enter the offspring generation to avoid losing high-quality solutions;

[0111] (4) Output: After the iteration is completed, select the individual with the highest fitness in the population and parse it to obtain the final row set. Column set Corresponding to a 100×100 subarray ( ).

[0112] Step 3: 100×100 weight mapping and deployment.

[0113] 3.1 Weight Mapping: Based on Adjustable conductance range of state-controlled devices, calibration mapping relationship, and the first weight of the 100×100 weight matrix of the neural network. Line number List( , The weight values ​​of ) are mapped to the subarray. OK, ReRAM devices in series;

[0114] 3.2 Weight Fixing: Apply appropriate programming pulses to the devices, traverse all 100×100 subarray devices, and complete the weight fixing.

[0115] The embodiments described above provide a detailed explanation of the technical solution of the present invention. The present invention can stably implement the entire process of "device detection - subarray screening - weight deployment" in actual ReRAM arrays, adapting to the requirements of in-memory computing parallel inference in neural networks. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, supplements, and equivalent substitutions made within the scope of the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A neural network deployment method of a ReRAM in-memory computing array, characterized in that, Includes the following steps: (1) Using Reset-Set dual-sequence verification combined with perturbation-free conductance reading, The device states of a large-scale ReRAM array are subdivided into usable states. Low impact state High-impact state Three categories; according to Configure differentiated scores to generate a state matrix with dimensions consistent with the ReRAM array. Score matrix ;in, , , Corresponding to states respectively , , ; (2) Based on the state matrix Score matrix The subarray normalized score rate With the objective of maximizing the target, a combination of greedy, hill-climbing, and genetic algorithms is used to select a target subarray that matches the target weight matrix, with a size of [missing value]. Specifically: Greedy algorithm: select the front according to the descending order of row and column scores Row, Column, get initial row set , initial column set ; Hill Climbing Algorithm: Recursively Replace Initial Row Set Lowest row and unselected highest row, initial column set The lowest selected column and the highest unselected column are selected and replaced until no replacement is needed, resulting in the optimized row set. , column set ; Genetic Algorithm: The row-level encoding and N-column encoding represent the selection scheme. After population initialization, selection, crossover, mutation, and elite retention operations, the final optimized row set is obtained through iteration. , column set That is, the target subarray; (3) Map the target weight matrix to the target subarray by row and column, and convert the weights into device conductivity through the appropriate programming pulse to complete the solidification deployment.

2. The neural network deployment method of the ReRAM in-memory array according to claim 1, characterized in that, In step (1), the Reset-Set dual-sequence verification combined with perturbation-free conductance reading is used, specifically including: The parameters of the Reset voltage pulse sequence and the Set voltage pulse sequence are preset according to the characteristics of the ReRAM device; First, apply a Reset voltage pulse sequence to the device, gradually increase the voltage according to a preset step size, pause after each voltage step is completed, then apply a non-disturbance reading voltage, read and record the device's conductance value in real time, until the conductance reaches the threshold or the voltage reaches the termination value; After the Reset voltage pulse sequence verification is completed, the same method is used to apply the Set voltage pulse sequence to the ReRAM device and record the conductance value until the conductance reaches the threshold or the voltage reaches the termination value.

3. The neural network deployment method of the ReRAM in-memory array according to claim 1, characterized in that, In step (1), based on the device state step-by-step judgment rule, the device states of the large-scale ReRAM array are subdivided into three categories, as follows: • easy-to-use state • low-impact state • high-impact state First determine high impact state For all devices, if the conductance is always greater than the preset high resistance threshold value after the reset voltage pulse sequence operation is completed, only the low resistance state can be maintained, and the high impact state is determined ; In exclusion If, after the Set voltage pulse sequence operation, the conductance remains below the preset low-resistance threshold and can only maintain a high-resistance state, it is determined to be a low-impedance state. ; After the above two steps, the remaining device is determined as easy-to-use state , indicating that the device has stable resistance characteristics, and the conductance cover weight interval is quantized, meeting the requirements of easy-to-use state.

4. The neural network deployment method for the ReRAM in-memory computing array according to claim 1, characterized in that, In step (1), the state matrix middle Mapping ReRAM array OK List device status; scoring matrix middle Follow Pick , or ,and , , Adjust according to accuracy requirements.

5. The neural network deployment method of the ReRAM in-memory array according to claim 1, characterized in that, In step (2), the sub-array normalized score rate The formula is: ； In the formula, For the target subarray size, For the selected row set, To select the column set, for The score of the state device, Representing the score matrix The Middle OK The score of the column.

6. The neural network deployment method of the ReRAM in-memory array according to claim 1, characterized in that, The population size of the genetic algorithm is adapted to the ReRAM array size, and the high-quality mutated individuals are generated and maintained based on , the number of binary Is in the encoding is unchanged.

7. The neural network deployment method of the ReRAM in-memory array according to claim 1, characterized in that, In the genetic algorithm, row and column codes are crossed at two points. If the number of binary 1s in the row code deviates from K or the number of binary 1s in the column code deviates from L, then the binary 1s corresponding to the lowest-scoring row / column are changed to 0, or the binary 0s corresponding to the highest-scoring row / column are changed to 1.

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