Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device, the display panel comprises a plurality of pixel units, each pixel unit comprises a driving module, a pre-charging control module, a frequency control module, a storage module and a light emitting module, and the driving module is electrically connected to the pre-charging control module, the storage module, the frequency control module and the light emitting module. The driving module receives the data signal and transmits the data signal to the storage module for storage through the pre-charging control module; the driving module drives the light-emitting module to emit light according to the data signal so as to execute image display; the frequency control module is electrically connected to the pre-charging control module and used for controlling the pre-charging control module to receive or stop receiving the data signals transmitted to the storage module, and when the pre-charging control module receives the data signals, the pixel units are used for executing image display of a first refresh rate; when the pre-charging control module stops receiving the data signal, the pre-charging control module is used for executing image display of a second refresh rate, so that the display area is controlled to realize partitioned multi-frequency display, and longitudinal partitioned multi-frequency display can be realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, the application scenarios of display panels are more and more, and the display requirements of users for display panels are more and more diversified. Many application scenarios in the use of terminal products by users will use split-screen display, for example, watching video while playing mobile games or reading novels, etc. And in most cases, the frequencies required by different scenes of split-screen display are not the same. Therefore, researchers have begun to study the technology of multi-frequency display in different areas. However, in the current multi-frequency display in different areas, the display area is usually partitioned horizontally. However, in different scenes, vertical partitioning is also very necessary in order to save power consumption. Therefore, how to realize vertical partitioning and make each partition perform multi-frequency display is a problem to be solved. SUMMARY

[0003] In order to solve the foregoing technical problems, the embodiments of the present application provide a display panel and a display device which can effectively realize vertical partitioning multi-frequency display.

[0004] In a first aspect, the embodiments of the present application provide a display panel, comprising a display area, the display area comprising a plurality of pixel units arranged in an array, the pixel units being used to perform image display according to received data signals, the pixel units comprising a driving module, a pre-charge control module, a frequency control module, a storage module and a light-emitting module, the driving module being electrically connected to the pre-charge control module, the storage module, the frequency control module and the light-emitting module, in a signal pre-charge phase of a frame image display period, the driving module receives the data signals and transmits them to the storage module for storage through the pre-charge control module, in an image display phase of a frame image display period, the driving module drives the light-emitting module to emit light to perform image display according to the data signals; the frequency control module is electrically connected to the pre-charge control module and is used to control the pre-charge control module to receive or stop receiving data signals transmitted to the storage module, wherein the pixel units are used to perform image display at a first refresh rate when the pre-charge control module receives the data signals, and are used to perform image display at a second refresh rate when the pre-charge control module stops receiving the data signals, the signal pre-charge phase and the display phase being two continuous phases for the pixel units to perform image display.

[0005] The pixel unit receives the data signal when the pixel unit is controlled by the frequency control module to perform image display at the first refresh rate, and stops receiving the data signal when the pixel unit is controlled by the frequency control module to perform image display at the second refresh rate, so that the display area can be divided into multiple display areas performing different refresh rates, thereby realizing partitioned multi-frequency display. Since the pixel unit connected to the same data line can be controlled to receive the data signal at the first refresh rate and stop receiving the data signal at the second refresh rate, vertical partitioned multi-frequency display can be realized.

[0006] Optionally, the display area includes at least one preset area, when the preset area performs the first refresh rate, the pre-charge control module in the pixel unit receives the data signal in each frame of image display, and when the preset area performs the second refresh rate, the pre-charge control module in the pixel unit stops receiving the data signal in a plurality of continuous frames of image display.

[0007] The pixel unit in the preset area receives the data signal in each frame of image display when the pixel unit is controlled to perform image display at the first refresh rate, and stops receiving the data signal when the area other than the preset area performs image display at the second refresh rate, thereby realizing partitioned multi-frequency display.

[0008] Optionally, the pixel unit further includes a first reset module, a second reset module, a first light-emitting control module and a second light-emitting control module, the first reset module is electrically connected to the driving module and is used to reset the driving module before the driving module receives the data signal, the second reset module is electrically connected to the light-emitting module and is used to reset the light-emitting module before the driving module drives the light-emitting module, the first light-emitting control module is electrically connected to the driving module and a power voltage terminal, the second light-emitting control module is electrically connected between the driving module and the light-emitting module, and the first light-emitting control module and the second light-emitting control module are used to drive the light-emitting module to emit light in cooperation with the driving module in the light-emitting stage.

[0009] Optionally, the driving module includes a first switch tube and a driving switch tube, a control end of the first switch tube is electrically connected to the scan line, a first end of the first switch tube is electrically connected to the data line, a second end of the first switch tube is electrically connected to a first end of the driving switch tube, a control end of the driving switch tube is electrically connected to a first node, and a second end of the driving switch tube is electrically connected to a second node; the first switch tube is used to conduct under the control of the scan signal, so as to receive the data signal and transmit the data signal to the driving switch tube, and when the first node receives a first level signal, the driving switch tube is turned on to transmit the data signal to the second node.

[0010] Optionally, the pre-charge control module comprises a second switch tube, a third switch tube, a first capacitor and a second capacitor, and the storage module comprises a storage capacitor, wherein the control end of the second switch tube is electrically connected to the frequency control module, the first end of the second switch tube is electrically connected to a reference voltage end, the second end of the second switch tube is electrically connected to the first node, the control end of the third switch tube is electrically connected to the frequency control module, the first end of the third switch tube is electrically connected to the second node, the second end of the third switch tube is electrically connected to the first node, the second end of the third switch tube is electrically connected to the first node and the first end of the storage capacitor through the first node, the second end of the storage capacitor is electrically connected to a power voltage end, the first end of the first capacitor is electrically connected to the control end of the second switch tube, the second end of the first capacitor is electrically connected to the power voltage end, the first end of the second capacitor is electrically connected to the control end of the third switch tube, and the second end of the second capacitor is electrically connected to the power voltage end. When the pixel unit is in the area performing image display at the first refresh rate, the frequency control module controls the second switch tube and the third switch tube to be turned on, when the second switch tube is turned on, the reference voltage end outputs a first level signal to the first node to control the driving switch tube to be turned on, and the data signal is transmitted to the storage capacitor through the driving switch tube, the second node and the third switch tube to be stored; when the pixel unit is in the area performing image display at the second refresh rate, the frequency control module controls the second switch tube and the third switch tube to be turned off to control the storage capacitor to stop receiving the data signal of the current frame image display.

[0011] By controlling the turn-on and turn-off of the second switch tube and the third switch tube, the pixel unit can effectively receive or not receive the data signal for image display, so that the pixel unit can effectively receive the data signal for image display when performing the first refresh rate and stop receiving the data signal when performing the second refresh rate, thereby maintaining the previous frame image.

[0012] Optionally, the frequency control module comprises a fourth switch tube, a fifth switch tube and a third capacitor, a control end of the fourth switch tube is electrically connected to the frequency control end, a first end of the fourth switch tube is electrically connected to the first signal end, a second end of the fourth switch tube is electrically connected to a control end of the second switch tube, a control end of the fifth switch tube is electrically connected to the frequency control end, a first end of the fifth switch tube is electrically connected to the second signal end, a second end of the fifth switch tube is electrically connected to a control end of the third switch tube, a first end of the third capacitor is electrically connected to the frequency control end, and a second end of the third capacitor is electrically connected to the power voltage end; when the region where the pixel unit is located displays an image at the first refresh rate, the frequency control end controls the fourth switch tube and the fifth switch tube to be turned on, so as to control the first signal end and the second signal end to output a second level signal to the control end of the second switch tube and the control end of the third switch tube, so as to control the second switch tube and the third switch tube to be turned on; when the region where the pixel unit is located displays an image at the second refresh rate, the frequency control module controls the fourth switch tube and the fifth switch tube to be turned off, so as to control the second switch tube and the third switch tube to be turned off.

[0013] Optionally, the first reset module comprises a sixth switch tube, the second reset module comprises a seventh switch tube, a control end of the sixth switch tube is electrically connected to a third signal end, a first end of the sixth switch tube is electrically connected to a first reset end, a second end of the sixth switch tube is electrically connected to a first end of the driving switch tube, a control end of the seventh switch tube is electrically connected to a fourth signal end, a first end of the seventh switch tube is electrically connected to a second reset end, and a second end of the seventh switch tube is electrically connected to the light emitting module; the sixth switch tube is used for being turned on under the control of the third signal end, so as to control the first reset end to output a reset signal to reset the driving switch tube, and the seventh switch tube is used for being turned on under the control of the fourth signal end, so as to control the second reset end to reset the light emitting module.

[0014] Optionally, the first light emitting control module comprises an eighth switch tube, and the second light emitting control module comprises a ninth switch tube, a control end of the eighth switch tube is electrically connected to the fifth signal end, a first end of the eighth switch tube is electrically connected to the first end of the driving switch tube, and a second end of the eighth switch tube is electrically connected to the power voltage end, a control end of the ninth switch tube is electrically connected to the sixth signal end, a first end of the ninth switch tube is electrically connected to the second node, and a second end of the ninth switch tube is electrically connected to the light emitting module; in the image display stage, the eighth switch tube is used for being turned on under the control of the fifth signal end, the ninth switch tube is used for being turned on under the control of the sixth signal end, the driving switch tube is turned on under the control of the data signal, and the power voltage end outputs the power voltage to output the power voltage through the eighth switch tube, the driving switch tube and the ninth switch tube to drive the light emitting module to emit light.

[0015] Optionally, when the region where the pixel unit is located performs image display at the first refresh rate, the pixel unit performs image display comprising a continuous first period, a second period, a third period, a fourth period, a fifth period and a sixth period, in the first period, the fifth signal end outputs a second level signal to control the eighth switch tube to be turned off, to control the power voltage end to stop outputting the power voltage to the driving switch tube; in the second period, the frequency control end controls the fourth switch tube and the fifth switch tube to be turned on, the second signal end controls the third switch tube to be turned on, and at the same time, the third signal end controls the sixth switch tube to be turned on, to control the first reset end to reset the driving switch tube; in the third period, the first signal end controls the second switch tube to be turned on, to control the reference voltage end to output a first level signal to the first node to control the driving switch tube to be turned on. In the fourth period, the scanning signal controls the first switch tube to be turned on, and the data signal is transmitted to the storage capacitor through the driving switch tube and the third switch tube; in the fifth period, the second signal end controls the fourth switch tube to be turned off, the third signal end controls the sixth switch tube to be turned on, to control the first reset end to reset the driving switch tube; in the sixth period, the fifth signal end controls the seventh switch tube and the eighth switch tube to be turned on, the data signal controls the driving switch tube to be turned on, and the power voltage end outputs the power voltage to the light emitting module through the eighth switch tube, the driving switch tube and the ninth switch tube, to control the light emitting module to emit light; when the region where the pixel unit is located performs image display at the second refresh rate, in the second period and the third period, the frequency control end outputs a second frequency control signal to control the fourth switch tube and the fifth switch tube to be turned off, to control the second switch tube and the third switch tube to be turned off, and to control the storage capacitor to stop receiving the data signal.

[0016] Optionally, the display panel further comprises a data driving circuit, a selection circuit and a conversion circuit, the selection circuit is electrically connected to the data driving circuit, the conversion circuit and the pixel unit, the conversion circuit is electrically connected to the frequency control end, the data driving circuit is configured to output the data signal and an initial signal to the selection circuit at different times, the selection circuit is configured to transmit the data signal to the pixel unit and transmit the initial signal to the conversion circuit, and the conversion circuit is configured to identify rising and falling edges of the initial signal, when the conversion circuit outputs the first frequency control signal to the frequency control end according to the rising edge of the initial signal, the region where the pixel unit is located displays images at the first refresh rate, and when the conversion circuit outputs the second frequency control signal to the frequency control end according to the falling edge of the initial signal, the region where the pixel unit is located displays images at the second refresh rate.

[0017] By setting the selection circuit to control the data driving circuit to output the data signal to the pixel unit and output the initial signal to the conversion circuit, the timeliness and accuracy of signal output can be effectively ensured, and display failure caused by incorrect signals can be avoided.

[0018] Optionally, the selection circuit comprises a first control tube and a second control tube, a control end of the first control tube is electrically connected to a selection signal end, a first end of the first control tube is electrically connected to the data driving circuit, a second end of the first control tube is electrically connected to the pixel unit, a control end of the second control tube is electrically connected to the selection signal end, a first end of the second control tube is electrically connected to the data driving circuit, and a second end of the second control tube is electrically connected to the conversion circuit, when the selection signal end outputs a first level signal, the first control tube is turned on, the data driving circuit outputs the data signal to the pixel unit through the first control tube, when the selection signal end outputs a second level signal, the second control tube is turned on, and the data driving circuit outputs the initial signal to the conversion circuit through the second control tube.

[0019] Optionally, the conversion circuit comprises an adjusting module, an output module and a maintaining module, the adjusting module is electrically connected to the data driving circuit and the output module, the adjusting module is used for identifying the rising edge and the falling edge of the initial signal, when the adjusting module identifies the rising edge of the initial signal, the adjusting module outputs a first control signal to the output module, when the adjusting module identifies the falling edge of the initial signal, the adjusting module outputs a second control signal, the output module outputs the first frequency control signal to the frequency control end according to the first control signal, the output module outputs the second frequency control signal to the frequency control end according to the second control signal, and the maintaining module is electrically connected to the adjusting module and is used for maintaining the voltage stability in the adjusting module when the adjusting module performs voltage adjustment.

[0020] By outputting the high level signal and the low level signal according to the rising edge and the falling edge of the initial signal respectively through the conversion circuit, the voltage limitation of the output voltage of the data driving circuit is avoided, so that the conversion circuit can output effective level control signals.

[0021] Optionally, the adjusting module comprises a third control tube, a fourth control tube, a fourth capacitor and a fifth capacitor, the first end of the fourth capacitor is electrically connected to the input end, the second end of the fourth capacitor is electrically connected to the control end of the third control tube, the first end of the third control tube is electrically connected to the closing voltage end, the second end of the third control tube is electrically connected to the control node, the control end of the fourth control tube is electrically connected to the input end, the first end of the fourth control tube is electrically connected to the opening voltage end, the second end of the fourth control tube is electrically connected to the control node, the first end of the fifth capacitor is electrically connected to the input end, and the second end of the fifth capacitor is electrically connected to the second end of the fourth control tube, the third control tube is used for turning on according to the rising edge of the initial signal to control the closing voltage end to output the first level signal to the control node, and the fourth control tube is used for turning on according to the falling edge of the initial signal to control the opening voltage end to output the second level signal to the control node.

[0022] Optionally, the output module comprises a fifth control tube and a sixth control tube, the maintaining module comprises a seventh control tube, a control end of the fifth control tube is electrically connected to the control node, a first end of the fifth control tube is electrically connected to the opening voltage end, a second end of the fifth control tube is electrically connected to the output end, a control end of the sixth control tube is electrically connected to the control node, a first end of the sixth control tube is electrically connected to the closing voltage end, a second end of the sixth control tube is electrically connected to the output end, a control end of the seventh control tube is electrically connected to an input end, a first end of the seventh control tube is electrically connected to the closing voltage end, and a second end of the seventh control tube is electrically connected to the control end of the third control tube; the fifth control tube is turned on according to the first level signal to control the opening voltage end to output the first frequency control signal to the frequency control end through the output end, the sixth control tube is turned on according to the second level signal to control the closing voltage end to output the second frequency control signal to the frequency control end through the output end, and the seventh control tube is used to be turned on when the initial signal is at the first level to control the closing voltage end to output the first level signal to the control end of the third control tube to control the third control tube to maintain in the off state.

[0023] In a second aspect, the embodiments of the present application further provide a display device, comprising a power supply module and a display panel as described above, wherein the power supply module is configured to provide a driving current for the display panel to drive the display panel to perform image display.

[0024] Compared with the prior art, the embodiments of the present application set a frequency control module in the pixel unit to control the pixel unit to receive a data signal when displaying an image at a first refresh rate and to stop receiving the data signal when displaying an image at a second refresh rate, so that the display area can be divided into multiple display areas performing different refresh rates, thereby realizing multi-frequency display of display partitioning, and due to the accurate control of the pixel unit to receive or not to receive the data signal, the refresh rate of the display area in any range can be controlled, both horizontal partitioning display and vertical partitioning display can be realized.

[0025] It should be understood that the beneficial effects achieved by the second aspect of the embodiments of the present application can be referred to the technical effects of the first aspect and the corresponding possible implementation manners thereof described above, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0027] Figure 1 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1.

[0028] Figure 2 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1. Figure 1 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1.

[0029] Figure 3 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1. Figure 2 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1.

[0030] Figure 4 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1. Figure 2 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1.

[0031] Figure 5 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1. Figure 4 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1.

[0032] Figure 6 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1.

[0033] Figure 7 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1. Figure 6 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1.

[0034] Figure 8 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1. Figure 7 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1.

[0035] Figure 9 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1. DETAILED DESCRIPTION

[0036] In order to better understand the technical solutions provided by the embodiments of the present application, the related embodiments of the present application will be described below.

[0037] Please refer to Figure 1 , A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1. Figure 1 A structural schematic diagram of a display device 100 provided by the first embodiment of the present application is shown in FIG. 1.

[0038] As Figure 1As shown, the display device 100 comprises a display panel 10 and a power module 20, the power module 20 is arranged on the back of the display panel 10, that is, the non-display surface of the display panel 10. The power module 20 is used to provide driving current for the display panel 10 to display images.

[0039] Please refer to Figure 2 , Figure 2 For Figure 1 the schematic diagram of the planar layout of the display panel in FIG. 1.

[0040] As Figure 2 shown, the display area of the display panel 10 comprises a plurality of pixel units P arranged in a matrix, m data lines S1-Sm and n scan lines G1-Gn, m and n are natural numbers greater than 1.

[0041] Among them, the n scan lines G1-Gn extend along the first direction F1 and are insulated and arranged in parallel along the second direction F2, the m data lines S1-Sm extend along the second direction F2 and are insulated and arranged in parallel along the first direction F1, and the first direction F1 and the second direction F2 are perpendicular to each other.

[0042] The non-display area of the display panel 10 comprises a timing control circuit 11 for driving the pixel units to display images, a data driving circuit 12, and a scan driving circuit 13 arranged on the array substrate 10c.

[0043] Among them, the timing control circuit 11 is electrically connected to the data driving circuit 12 and the scan driving circuit 13, used to control the working time sequence of the data driving circuit 12 and the scan driving circuit 13, that is, output corresponding timing light-emitting signals to the data driving circuit 12 to the scan driving circuit 13, to control when to output corresponding scan signals and data signals.

[0044] The data driving circuit 12 is electrically connected to the m data lines S1-Sm, used to transmit the data signal (Data) to be displayed to the plurality of pixel units P in the form of data voltage through the m data lines S1-Sm.

[0045] The scan driving circuit 13 is electrically connected to the n scan lines G1-Gn, used to output scan signals through the n scan lines G1-Gn to control when the pixel units P receive data signals. Among them, the scan driving circuit 13 outputs scan signals from the scan lines G1, G2, …, Gn in turn according to the scan period according to the position arrangement order.

[0046] Please refer to Figure 3 , Figure 3 For Figure 2 the schematic diagram of the refresh rate control of the display area 10a in FIG. 2.

[0047] As shown in Figure 3 The display area 10a includes a first display area A and a second display area B, wherein the first display area A can be a preset area, the size range of which can be set according to specific settings, the first display area A is an area between the a-th scanning line Ga and the b-th scanning line Gb and between the a-th data line Sa and the b-th data line Sb, and the second display area B is a display area other than the first display area A.

[0048] The display panel 10 includes a first display mode, a second display mode and a third display mode. When the display panel 10 executes the first display mode, the first display area A and the second display area B have the same refresh rate when performing image display. When the display panel 10 executes the second display mode, the refresh rate of the first display area A is greater than that of the second display area B. When the display panel executes the third display mode, the refresh rate of the first display area A is less than that of the second display area B. The refresh rate refers to the number of frames of displayed images per unit time.

[0049] When the first display mode is executed, the n scanning lines Ga-Gn output scanning signals at the same frequency to control the first display area A and the second display area B to perform image display at the same refresh rate.

[0050] When the second display mode is executed, the a-th scanning line Ga to the b-th scanning line Gb output scanning signals at a first frequency (high refresh rate) in sequence, and the pixel units in the first display area A receive data signals at the first frequency to perform image display, so that the first display area A performs image display at the first refresh rate. The 1st scanning line G1 to the a-1st scanning line and the b+1st scanning line to the n-th scanning line Gn output scanning signals at the first frequency or a second frequency (low refresh rate), and the pixel units P in the second display area B receive data signals at the second frequency to perform image display, so that the second display area B performs image display at the second refresh rate. The first frequency is greater than the second frequency.

[0051] When the third display mode is executed, the a-th scanning line Ga to the b-th scanning line Gb output scanning signals at the first frequency or the second frequency, and the pixel units in the first display area A receive data signals at the second frequency to perform image display. The 1st scanning line G1 to the a-1st scanning line and the b+1st scanning line to the n-th scanning line Gn output scanning signals at the first frequency, and the pixel units P in the second display area B receive data signals at the first frequency to perform image display.

[0052] It can be understood that, since the same column of pixel units P is connected to the same data line S, when the pixel units P in the first display area A are refreshed at a first frequency, or in other words, perform image display at a first refresh rate, and the pixel units P in the second display area B are refreshed at a second frequency, or in other words, perform image display at a second refresh rate, in a continuous a-frame image display process, the pixel units P in the first display area A can be controlled to receive data signals for image display in each frame of image display, while the pixel units P in the second display area B can be controlled to stop receiving data signals for a continuous c-frame image, that is, to maintain the current frame unchanged, so that the pixel units connected to the same data line S can be controlled to perform image display at different frequencies, where c is an integer greater than or equal to 1.

[0053] In exemplary embodiments, c can be set according to specific needs, for example, set to 10, 20, 30, etc., that is, the pixel units refreshed at the second frequency are stopped from receiving data signals for refreshing in a continuous 10-frame, 20-frame, 30-frame image display, and of course c can also be set to other quantities according to needs, which is not limited in the present application.

[0054] Please refer to Figure 4 , Figure 4 for Figure 2 the equivalent circuit diagram of the pixel unit in the display area.

[0055] As shown in Figure 4 , the pixel unit P includes a pixel circuit 15, which is used to receive data signals and control the pixel unit P to emit light, wherein the pixel circuit 15 includes a driving module 151, a pre-charge control module 152, a storage module 153, a frequency control module 154 and a light-emitting module 155, the driving module 151 is electrically connected to the pre-charge control module 152, the storage module 153 and the light-emitting module 155, in the signal pre-charge stage, the driving module 151 receives data signals and transmits them to the pre-charge control module 152, and transmits them to the storage module 153 through the pre-charge control module 152 for storage, in the display stage, the storage module 153 transmits the data signals to the driving module 151 to control the driving module 151 to drive the light-emitting module 155 to emit light. The frequency control module 154 is electrically connected to the pre-charge control module 152, and is used to control whether the pre-charge control module 152 transmits data signals to the storage module 153 for storage. When the display area where the pixel unit P is located performs image display at a first refresh rate, the frequency control module 154 controls the pre-charge control module 152 to transmit data signals to the storage module 153 in a continuous multi-frame image display, and when the display area where the pixel unit P is located performs image display at a second refresh rate, the frequency control module 154 controls the pre-charge control module 152 to stop transmitting data signals to the storage module 153 in a continuous c-frame image display.

[0056] For example, when the display panel 10 executes the second display mode, the frequency control module 154 in the pixel unit in the first display area A controls the pre-charge control module 152 to receive the data signal and transmit to the storage module 153, so as to control the driving module 151 to drive the light-emitting module 155 to emit light in each frame of image display, while the frequency control module 154 in the pixel unit in the second display area B controls the pre-charge control module 152 to stop receiving the data signal, so as to control the driving module 151 to stop driving the light-emitting module 155 to emit light, i.e. to control the pixel unit P to maintain the brightness of the previous frame, thereby controlling the first display area A to maintain the high refresh rate state and the second display area B to maintain the low refresh rate state.

[0057] Similarly, when the display panel 10 executes the third display mode, the frequency control module 154 in the pixel unit P in the first display area A controls the pre-charge control module 152 to stop transmitting the received data signal to the storage module 153, so as to control the driving module 151 to stop driving the light-emitting module 155 to emit light, i.e. to control the pixel unit P to maintain the brightness of the previous frame, while the frequency control module 154 in the pixel unit P in the second display area B controls the pre-charge control module 152 to receive the data signal and transmit to the storage module 153, so as to control the driving module 151 to drive the light-emitting module 155 to emit light in each frame of image display, thereby controlling the first display area A to maintain the low refresh rate state and the second display area B to maintain the high refresh rate state.

[0058] The pixel circuit 15 further comprises a first reset module 156, a second reset module 157, a first light-emitting control module 158 and a second light-emitting control module 159, wherein the first reset module 156 is electrically connected to the driving module 151 and is used to reset the driving module 151 before the driving module 151 receives the data signal, the second reset module 157 is electrically connected to the light-emitting module 155 and is used to reset the light-emitting module 155 before the driving module 151 drives the light-emitting module 155 to emit light, the first light-emitting control module 158 is electrically connected to the driving module 151 and the power voltage terminal VDD, and the second light-emitting control module 159 is electrically connected between the driving module 151 and the light-emitting module 155, the first light-emitting control module 158 and the second light-emitting control module 159 are used to cooperate with the driving module 151 to drive the light-emitting module 155 to emit light in the light-emitting stage.

[0059] Specifically, the driving module 151 includes a first switch tube T1 and a driving switch tube DT, a control end of the first switch tube T1 is electrically connected to the scan line G, a first end of the first switch tube T1 is electrically connected to the data line S, a second end of the first switch tube T1 is electrically connected to a first end of the driving switch tube DT, a control end of the driving switch tube DT is electrically connected to the first node N1, and a second end of the driving switch tube DT is electrically connected to the second node N2. When the control end of the first switch tube T1 receives a scan signal from the scan line G, the first switch tube T1 is turned on, and the data signal is transmitted to the first end of the driving switch tube DT through the first switch tube T1. When the first node N1 is at the first potential, the driving switch tube DT is turned on to transmit the data signal to the second node N2.

[0060] The pre-charge control module 152 includes a second switch tube T2, a third switch tube T3, a first capacitor C1 and a second capacitor C2, and the storage module 153 includes a storage capacitor Cst. A control end of the second switch tube T2 is electrically connected to the frequency control module 154, a first end of the second switch tube T2 is electrically connected to the reference voltage end Vref, a second end of the second switch tube T2 is electrically connected to the first node N1 and the storage capacitor Cst through the first node N1, and the second switch tube T2 is used to be turned on under the control of the frequency control module 154 in the signal pre-charge stage to charge the first node N1 to the first potential by the reference voltage end Vref.

[0061] A control end of the third switch tube T3 is electrically connected to the frequency control module 154, a first end of the third switch tube T3 is electrically connected to the second node N2, a second end of the third switch tube T3 is electrically connected to the first node N1 and the storage capacitor Cst through the first node N1, and a second end of the storage capacitor Cst is electrically connected to the power voltage end VDD. The third switch tube T3 is used to be turned on under the control of the frequency control module 154 in the signal pre-charge stage, receive the data signal from the second node N2 and transmit it to the storage capacitor Cst for storage. A first end of the first capacitor C1 is electrically connected to the control end of the second switch tube T2, a second end of the first capacitor C1 is electrically connected to the power voltage end VDD, a first end of the second capacitor C2 is electrically connected to the control end of the third switch tube T3, and a second end of the second capacitor C2 is electrically connected to the power voltage end VDD.

[0062] When the display area where the pixel unit P is located is refreshed at the first frequency, in the signal pre-charge stage, the frequency control module 154 controls the second switch tube T2 to be turned on to charge the first node N1 to the first potential, to control the driving switch tube TD to be turned on, so that the data signal is transmitted to the storage capacitor Cst through the driving switch tube DT, the second node N2, the third switch tube T3 and the first node N1 for storage. When the display area where the pixel unit P is located is refreshed at the second frequency, the frequency control module 154 controls the second switch tube T2 and the third switch tube T3 to be turned off, so that the storage capacitor Cst stops receiving the data signal for the next frame image display, that is, controls the pixel unit P not to refresh the image in the next frame image display. The first capacitor C1 is used to maintain the stability of the voltage at the control end of the second switch tube T2, and the second capacitor C2 is used to maintain the stability of the voltage at the control end of the third switch tube T3.

[0063] The frequency control module 154 includes a fourth switch tube T4, a fifth switch tube T5 and a third capacitor C3. The control end of the fourth switch tube T4 is electrically connected to the frequency control end Vc, the first end of the fourth switch tube T4 is electrically connected to the first signal end SC1, and the second end of the fourth switch tube T4 is electrically connected to the control end of the second switch tube T2. The fourth switch tube T4 is used to be turned on under the control of the frequency control end Vc, so that the first signal end SC1 outputs the second level signal (high level) to the control end of the second switch tube T2 to control the second switch tube T2 to be turned on.

[0064] The control end of the fifth switch tube T5 is electrically connected to the frequency control end Vc, the first end of the fifth switch tube T5 is electrically connected to the second signal end SC2, and the second end of the fifth switch tube T5 is electrically connected to the control end of the third switch tube T3. The fifth switch tube T5 is used to be turned on under the control of the frequency control end Vc, so that the second signal end SC2 outputs the second level signal to the control end of the second switch tube T2 to control the second switch tube T2 to be turned on.

[0065] The first end of the third capacitor C3 is electrically connected to the frequency control end Vc, that is, the control ends of the fourth switch tube T4 and the fifth switch tube T5, and the second end of the third capacitor C3 is electrically connected to the power voltage end VDD. The third capacitor C3 is used to maintain the stability of the voltage at the control ends of the fourth switch tube T4 and the fifth switch tube T5.

[0066] When the region where the pixel unit P is located is refreshed at the first frequency, the frequency control end Vc outputs a first frequency control signal to control the fourth switch tube T4 and the fifth switch tube T5 to be turned on, to control the first signal end SC1 and the second signal end SC2 to output a second level signal to the second switch tube T2 and the third switch tube T3, so as to control the second switch tube T2 and the third switch tube T3 to be turned on. When the region where the pixel unit P is located is refreshed at the second frequency, the frequency control end Vc outputs a second frequency control signal to control the second fourth switch tube T4 and the fifth switch tube T5 to be turned off, thereby controlling the second switch tube T2 and the third switch tube T3 to be turned off.

[0067] The light emitting module 155 includes a light emitting element D, an anode of the light emitting element D is electrically connected to the second reset module 157, and a cathode of the light emitting element D is electrically connected to the low voltage end VSS. Wherein, the light emitting element D can be an organic light emitting diode (OLED).

[0068] The first reset module 156 includes a sixth switch tube T6, and the second reset module 157 includes a seventh switch tube T7. The control end of the sixth switch tube T6 is electrically connected to the third signal end SC3, the first end of the sixth switch tube T6 is electrically connected to the first reset end VR1, and the second end of the sixth switch tube T6 is electrically connected to the first end of the driving switch tube TD. The sixth switch tube T6 is used to be turned on under the control of the first level signal (low level) output by the third signal end SC3, so that the first reset end VR1 outputs a reset signal to the driving switch tube DT to reset the driving switch tube DT.

[0069] The control end of the seventh switch tube T7 is electrically connected to the fourth signal end SC4, the first end of the seventh switch tube T7 is electrically connected to the second reset end VR2, and the second end of the seventh switch tube T7 is electrically connected to the anode of the light emitting element D. The seventh switch tube T7 is used to be turned on under the control of the first level signal output by the fourth signal end SC4, so that the second reset end VR2 resets the light emitting element D.

[0070] The first light-emitting control module 158 comprises an eighth switch tube T8, and the second light-emitting control module 159 comprises a ninth switch tube T9. The control end of the eighth switch tube T8 is electrically connected to the fifth signal end SC5, the first end of the eighth switch tube T8 is electrically connected to the power supply voltage end VDD, the second end of the eighth switch tube T8 is electrically connected to the first end of the driving switch tube DT, and the eighth switch tube T8 is used to be turned on under the control of the first level signal output by the fifth signal end SC5, so that the power supply voltage end VDD outputs the power supply voltage to the first end of the driving switch tube DT. The control end of the ninth switch tube T9 is electrically connected to the sixth signal end SC6, the first end of the ninth switch tube T9 is electrically connected to the second node N2, and the second end of the ninth switch tube T9 is electrically connected to the anode of the light-emitting element D. The ninth switch tube T9 is used to be turned on under the control of the first level signal output by the sixth signal end SC6, so that the power supply voltage transmitted to the second node N2 by the driving switch tube DT is transmitted to the anode of the light-emitting element D, so as to drive the light-emitting element D to emit light. That is, when the eighth switch tube T8, the ninth switch tube T9 and the driving switch tube DT are turned on at the same time, the power supply voltage end VDD outputs the power supply voltage to the anode of the light-emitting element D, so as to drive the light-emitting element D to emit light.

[0071] In the embodiment, the driving switch tube DT, the first switch tube T1, the sixth switch tube T6, the seventh switch tube T7, the eighth switch tube T8 and the ninth switch tube T9 are P-type thin film transistors (TFTs), the second switch tube T2, the third switch tube T3, the fourth switch tube T4 and the fifth switch tube T5 are N-type TFTs. Of course, the first switch tube T1 to the ninth switch tube T9 can also be set according to specific needs, and the present application does not limit this. The control end of the switch tube can be a gate, the first end of the switch tube can be a source, and the second end of the switch tube can be a drain.

[0072] Please refer to Figure 5 , Figure 5 for Figure 4 the signal output timing diagram.

[0073] As Figure 5 shown, when the area where the pixel unit P is located is refreshed at a first frequency, the pixel unit P performs image display, which includes a continuous first time period t1, a second time period t2, a third time period t3, a fourth time period t4, a fifth time period t5 and a sixth time period t6. In the first time period t1, the fifth signal end SC5 outputs a second level signal (high level) to control the eighth switch tube T8 to be turned off, so as to control the power supply voltage end VDD to stop outputting the power supply voltage to the driving switch tube DT.

[0074] In the second time period t2, the frequency control terminal Vc outputs a first frequency control signal to control the fifth switch tube T5 to be turned on, the second signal terminal SC2 outputs a second level signal to control the third switch tube T3 to be turned on, and the third signal terminal SC3 outputs a first level signal to control the sixth switch tube T6 to be turned on, so that the first reset terminal VR1 resets the driving switch tube DT.

[0075] In the third time period t3, the first signal terminal SC1 outputs a second level signal through the fourth switch tube T4 to control the second switch tube T2 to be turned on, so that the reference voltage terminal Vref outputs a first level signal to the driving switch tube DT through the second switch tube T2 and the first node N1 to control the driving switch tube DT to be turned on.

[0076] In the fourth time period t4, the scan line G outputs a scanning signal to control the first switch tube T1 to be turned on, so that the data signal is transmitted to the driving switch tube DT through the first switch tube T1, transmitted to the second node N2 through the driving switch tube DT, and transmitted to the storage capacitor Cst through the third switch tube T3 and the first node N1 to be stored.

[0077] In the fifth time period t5, the second signal terminal SC2 outputs a first level signal to control the third switch tube T3 to be turned off, and the third signal terminal SC3 outputs a first level signal to control the sixth switch tube T6 to be turned on to reset the driving switch tube DT.

[0078] In the sixth time period t6, the fifth signal terminal SC5 outputs a first level signal to control the seventh switch tube T7 and the eighth switch tube T8 to be turned on, the data signal in the storage capacitor Cst controls the driving switch tube DT to be turned on, and the power voltage terminal VDD outputs a power voltage to be transmitted to the anode of the light emitting element D through the eighth switch tube T8, the driving switch tube DT and the seventh switch tube T7 to drive the light emitting element D to emit light.

[0079] When the region where the pixel unit P is located is refreshed at a second frequency, the frequency control terminal Vc outputs a second frequency control signal to the control terminals of the fourth switch tube T4 and the fifth switch tube T5 to control the fourth switch tube T4 and the fifth switch tube T5 to be in the turned-off state, so as to control the second switch tube T2 and the third switch tube T3 to be in the turned-off state in the second time period t2 and the third time period t3, so as to control the storage capacitor Cst to stop receiving the data signal of the current frame, and control the pixel unit P to maintain the image of the previous frame, that is, not to refresh the image of the current frame.

[0080] Please refer to Figure 6 , Figure 6 The layout diagram of the conversion circuit is shown in FIG. 2.

[0081] As Figure 6As shown, the display panel 10 further comprises a selection circuit 16 and a conversion circuit 17, the selection circuit 16 is electrically connected to the data driving circuit 12, the conversion circuit 17 and the pixel circuit 15 in the display area 10a, the conversion circuit 17 is electrically connected to the frequency control end Vc in the pixel circuit 15, wherein the data driving circuit 12 is configured to output data signals and initial signals at different times to the selection circuit 16, the selection circuit 16 is configured to transmit the data signals to the pixel circuit 15 and transmit the initial signals to the conversion circuit 17.

[0082] The conversion circuit 17 is configured to output a first frequency control signal or a second frequency control signal according to the initial signal and transmit to the frequency control end Vc, when the area where the pixel unit P is located is refreshed at a first frequency, the conversion circuit 17 outputs the first frequency control signal to the frequency control end Vc, when the area where the pixel unit P is located is refreshed at a second frequency, the conversion circuit 17 outputs the second frequency control signal to the frequency control end Vc, wherein the first frequency control signal is a high-level signal, the second frequency control signal is a low-level signal, the first frequency control signal is used to transmit to the control end of the fourth switch tube T4 and the fifth switch tube T5 to control the fourth switch tube T4 and the fifth switch tube T5 to be turned on, thereby controlling the pixel unit P to display images according to the received data signals, the second frequency control signal is used to transmit to the control end of the fourth switch tube T4 and the fifth switch tube T5 to control the fourth switch tube T4 and the fifth switch tube T5 to be turned off, thereby controlling the pixel unit P not to receive the current frame data signal, so as to continue to display the previous frame image, that is, not to refresh the image.

[0083] Specifically, the selection circuit 16 comprises a first control tube M1 and a second control tube M2, the control end of the first control tube M1 is electrically connected to the selection signal end K, the first end of the first control tube M1 is electrically connected to the data driving circuit 12, and the second end of the first control tube M1 is electrically connected to the pixel circuit 15. The control end of the second control tube M2 is electrically connected to the selection signal end K, the first end of the second control tube M2 is electrically connected to the data driving circuit 12, and the second end of the second control tube M2 is electrically connected to the conversion circuit 17. When the selection signal end K outputs a first-level signal, the first control tube M1 is turned on, and the data driving circuit 12 transmits the output data signal to the pixel circuit 15 through the first switch tube M1, so that the pixel circuit 15 controls the pixel unit P to emit light according to the data signal, when the selection signal end K outputs a second-level signal, the second control tube M2 is turned on, and the data driving circuit 12 transmits the initial signal to the conversion circuit 17 through the second control tube M2. Wherein, the selection signal end K can be electrically connected to the timing control circuit 11, that is, the conduction and cut-off of the first control tube M1 and the second control tube M2 can be controlled by the timing control circuit 11.

[0084] In the embodiment, the first control tube M1 is an N-type transistor, used for conducting under the control of a high-level signal, and the second control tube M2 is a P-type transistor, used for conducting under the control of a low-level signal. The control end of the control tube can be a gate, the first end of the control tube can be a source, and the second end of the control tube can be a drain. Of course, the first control tube M1 and the second control tube M2 can also be set as other types of transistors according to the needs, which are not limited in the application.

[0085] Since the data driving circuit 12 can only output a voltage of 0V to 7V, and the fourth switch tube T4 and the fifth switch tube T5 need high-level signals and low-level signals, i.e. a voltage of (-7)V to 7V, to control the conduction and the cutoff, the conversion circuit 17 is used to identify the rising edge and the falling edge of the initial signal output by the data driving circuit 12, and output a first frequency control signal to the pixel circuit 15 according to the rising edge of the initial signal, and output a second frequency control signal to the pixel circuit 15 according to the falling edge of the initial signal.

[0086] Please refer to Figure 7 and Figure 8 , Figure 7 for Figure 6 the equivalent circuit diagram of the conversion circuit, Figure 8 for Figure 7 the voltage change diagram of the input end and the output end of the conversion circuit.

[0087] As shown in Figure 7 and Figure 8 , the conversion circuit 17 includes an adjusting module 171, an output module 172, and a maintaining module 173. The adjusting module 171 is electrically connected to the data driving circuit 12 and the output module 172, used for receiving the initial signal input by the data driving circuit 12 and identifying the rising edge or the falling edge of the initial signal. When the adjusting module 171 identifies the rising edge of the initial signal, the adjusting module 171 outputs a first control signal to the output module 172. When the adjusting module 171 identifies the falling edge of the initial signal, the adjusting module 171 outputs a second control signal to the output module 172.

[0088] The output module 172 is electrically connected to the frequency control end Vc in the pixel circuit 15. The output module 172 outputs a first frequency control signal to the frequency control end Vc according to the first control signal, so as to control the pixel circuit 15 to receive the data signal, thereby making the preset area execute the first display mode. The output module 172 outputs a second frequency control signal to the frequency control end Vc according to the second control signal, so as to control the pixel circuit 15 to stop receiving the data signal, thereby making the preset area execute the second display mode. The maintaining module 173 is electrically connected to the adjusting module 171, used for maintaining the stability of the voltage in the adjusting module 171 when the adjusting module 171 performs voltage adjustment.

[0089] Specifically, the adjusting module 171 comprises a third control tube M3, a fourth control tube M4, a fourth capacitor C4 and a fifth capacitor C5, wherein a first end of the fourth capacitor C4 is electrically connected to the input end input, a second end of the fourth capacitor C4 is electrically connected to a control end of the third control tube M3, a first end of the third control tube M3 is electrically connected to the closing voltage end VGL, a second end of the third control tube M3 is electrically connected to the control node Q. A control end of the fourth control tube M4 is electrically connected to the input end input, a first end of the fourth control tube M4 is electrically connected to the opening voltage end VGH, a second end of the fourth control tube M4 is electrically connected to the control node Q. A first end of the fifth capacitor C5 is electrically connected to the input end input, a second end of the fifth capacitor C5 is electrically connected to the second end of the fourth control tube M4. The third control tube M3 is used to be turned on when the initial signal is at a rising edge, so as to control the closing voltage end VGL to output the first level signal to the control node Q. The fourth control tube M4 is used to be turned on when the initial signal is at a falling edge, so as to control the opening voltage end to output the second level signal to the control node Q.

[0090] The output module 172 comprises a fifth control tube M5 and a sixth control tube M6, wherein a control end of the fifth control tube M5 is electrically connected to the control node Q, a first end of the fifth control tube M5 is electrically connected to the opening voltage end VGH, and a second end of the fifth control tube M5 is electrically connected to the output end output. A control end of the sixth control tube M6 is electrically connected to the control node Q, a first end of the sixth control tube M6 is electrically connected to the closing voltage end VGL, and a second end of the sixth control tube M6 is electrically connected to the output end output. When the display panel 10 executes the first display mode, the fifth control tube M5 is turned on according to the first level signal, so as to control the opening voltage end VGH to output the second level signal as the first frequency control signal to the frequency control end Vc through the output end output. When the display panel 10 executes the second display mode, the sixth control tube M6 is turned on according to the second level signal, so as to control the closing voltage end VGL to output the first level signal as the second frequency control signal to the frequency control end Vc through the output end output.

[0091] The maintaining module 173 comprises a seventh control tube M7, a control end of the seventh control tube M7 is electrically connected to the input end input, a first end of the seventh control tube M7 is electrically connected to the closing voltage end VGL, and a second end of the seventh control tube M7 is electrically connected to the control end of the third control tube M3. The seventh control tube M7 is used to be turned on when the initial signal is at a falling edge or the initial signal is at a first level (low level), so as to control the closing voltage end VGL to output the first level signal to the control end of the third control tube M3, so as to control the third control tube M3 to be maintained in the off state.

[0092] The conversion circuit 17 outputs a high level signal (7V) and a low level signal (-7V) as the first frequency control signal and the second frequency control signal according to the rising edge and the falling edge of the initial signal respectively to the frequency control end Vc of the pixel circuit 15 to control the display panel 10 to execute the first display mode or the second display mode.

[0093] In the embodiment, the third control tube M3 and the sixth control tube M6 are N-type transistors for conducting under the control of a high level signal, the fourth control tube M4, the fifth control tube M5 and the seventh control tube M7 are P-type transistors for conducting under the control of a low level signal, the control end of the control tube can be a gate, the first end of the control tube can be a source, and the second end of the control tube can be a drain. Of course, the third control tube M3 to the seventh control tube M7 can also be set as other types of transistors according to the needs, which is not limited in the application.

[0094] Please refer to Figure 9 , Figure 9 the timing diagram of the signal output of the pixel unit when displaying a plurality of continuous frames of images.

[0095] As Figure 9 shown, when the display panel 10 displays images, for example, in the process of displaying three continuous frames of images, in the first frame of image display, the preset area is written with the first data signal Data1 for image display, in the second frame of image display, the preset area is not written with data to maintain the previous frame of image, and in the third frame of image display, the preset area is refreshed and written with the second data signal Data2 for image display, wherein the preset area can be the first display area A or the second display area B.

[0096] In the first frame of image display, the second level signal (high level) is output from the selection signal end K to control the second control tube M2 to conduct, the conversion circuit 17 receives the initial signal from the data driving circuit 12 and outputs the first frequency control signal to the frequency control end Vc, at this time, the frequency control end Vc is at a high level to control the second switch tube T2 Figure 3 ) and the third switch tube T3 to conduct, so that the pixel unit P receives the first data signal Data1, and in the pixel circuit 15, the first data signal Data1 controls the driving switch tube DT to conduct, thereby driving the light emitting element D to emit light to execute the current frame of image display.

[0097] In the second frame image display, the selection signal terminal K outputs the second level signal (high level) to control the second control tube M2 to be turned on, the conversion circuit 17 receives the initial signal from the data driving circuit and outputs the second frequency control signal to the frequency control terminal Vc, at this time, the frequency control terminal Vc is at low level, to control the second switch tube T2 and the third switch tube T3 to be turned off, at this time, the pixel unit P does not receive the data signal, the driving switch tube DT maintains the on state, at this time, the pixel unit P maintains the previous frame image, that is, the image is not refreshed.

[0098] In the third frame image display, the selection signal terminal K outputs the initial signal, the selection signal terminal K outputs the second level signal (high level) to control the second control tube M2 to be turned on, the conversion circuit 17 receives the initial signal from the data driving circuit 12 and outputs the first frequency control signal to the frequency control terminal Vc, at this time, the frequency control terminal Vc is at high level, to control the second switch tube T2 ( Figure 3 ) and the third switch tube T3 to be turned on, so that the pixel unit P receives the second data signal Data2, the second data signal Data2 controls the driving switch tube DT to be turned on in the pixel circuit 15, so as to drive the light emitting element D to emit light to perform the current frame image display.

[0099] Through the pixel circuit 15 provided by the embodiment of the present application, the pixel unit of any column in the display panel can be controlled to receive or not receive the data signal, so that the refresh rate of the preset area can be reduced, thereby reducing the power consumption, and since whether the pixel unit of the preset area receives the data signal can be directly controlled, the refresh rate of any display area can be reduced, while ensuring the display effect, the power consumption is further reduced.

[0100] The above only discloses some embodiments of the present application, of course, cannot limit the scope of the present application, those skilled in the art can understand that the above-mentioned all or part of the process can be implemented, and the equivalent changes made according to the claims of the present application, still belong to the scope covered by the present application.

Claims

1. A display panel comprising a display area, the display area comprising a plurality of data lines, a plurality of scan lines and a plurality of pixel units arranged in an array, the data lines and the scan lines being electrically connected to the pixel units, the pixel units being configured to receive a data signal from the data lines under control of a scan signal output by the scan lines and perform image display according to the data signal; characterized in that the pixel unit comprising a driving module, a pre-charge control module, a frequency control module, a storage module and a light-emitting module, the driving module being electrically connected to the pre-charge control module, the storage module, the frequency control module and the light-emitting module, in a signal pre-charge phase of a frame image display period, the driving module receiving the data signal and transmitting the data signal to the storage module for storage through the pre-charge control module, in an image display phase of a frame image display period, the driving module driving the light-emitting module to emit light to perform image display according to the data signal; the frequency control module being electrically connected to the pre-charge control module and configured to control the pre-charge control module to receive or stop receiving the data signal transmitted to the storage module, wherein the pixel unit is configured to perform image display at a first refresh rate when the pre-charge control module receives the data signal, and the pixel unit is configured to perform image display at a second refresh rate when the pre-charge control module stops receiving the data signal.

2. The display panel of claim 1, wherein, the display area comprising at least one preset area, when the preset area performs the first refresh rate, the pre-charge control module in the pixel unit receives the data signal every frame of image display, when the preset area performs the second refresh rate, the pre-charge control module in the pixel unit stops receiving the data signal in a plurality of consecutive frames of image display.

3. The display panel of claim 2, wherein, the pixel unit further comprising a first reset module, a second reset module, a first light-emitting control module and a second light-emitting control module, the first reset module being electrically connected to the driving module and configured to reset the driving module before the driving module receives the data signal, the second reset module being electrically connected to the light-emitting module and configured to reset the light-emitting module before the driving module drives the light-emitting module, the first light-emitting control module being electrically connected to the driving module and a power voltage terminal, the second light-emitting control module being electrically connected between the driving module and the light-emitting module, the first light-emitting control module and the second light-emitting control module being configured to drive the light-emitting module to emit light in cooperation with the driving module in a light-emitting phase.

4. The display panel of claim 3, wherein, the driving module comprising a first switch tube and a driving switch tube, a control terminal of the first switch tube being electrically connected to the scan line, a first terminal of the first switch tube being electrically connected to the data line, a second terminal of the first switch tube being electrically connected to a first terminal of the driving switch tube, a control terminal of the driving switch tube being electrically connected to a first node, a second terminal of the driving switch tube being electrically connected to a second node. The first switch tube is used for being turned on under the control of the scanning signal to receive the data signal and transmit to the driving switch tube, and when the first node receives a first level signal, the driving switch tube is turned on to transmit the data signal to the second node.

5. The display panel of claim 4, wherein, The pre-charge control module comprises a second switch tube, a third switch tube, a first capacitor and a second capacitor, and the storage module comprises a storage capacitor, wherein the control end of the second switch tube is electrically connected to the frequency control module, the first end of the second switch tube is electrically connected to a reference voltage end, the second end of the second switch tube is electrically connected to the first node, the control end of the third switch tube is electrically connected to the frequency control module, the first end of the third switch tube is electrically connected to the second node, the second end of the third switch tube is electrically connected to the first node, the second end of the third switch tube is electrically connected to the first end of the storage capacitor through the first node, the second end of the storage capacitor is electrically connected to a power voltage end, the first end of the first capacitor is electrically connected to the control end of the second switch tube, the second end of the first capacitor is electrically connected to the power voltage end, the first end of the second capacitor is electrically connected to the control end of the third switch tube, and the second end of the second capacitor is electrically connected to the power voltage end; When the region where the pixel unit is located displays an image at the first refresh rate, the frequency control module controls the second switch tube and the third switch tube to be turned on, when the second switch tube is turned on, the reference voltage end outputs a first level signal to the first node to control the driving switch tube to be turned on, and the data signal is transmitted to the storage capacitor through the driving switch tube, the second node and the third switch tube to be stored; when the region where the pixel unit is located displays an image at the second refresh rate, the frequency control module controls the second switch tube and the third switch tube to be turned off to control the storage capacitor to stop receiving the data signal of the current frame image display.

6. The display panel of claim 5, wherein, The frequency control module comprises a fourth switch tube, a fifth switch tube and a third capacitor, the control end of the fourth switch tube is electrically connected to a frequency control end, the first end of the fourth switch tube is electrically connected to a first signal end, the second end of the fourth switch tube is electrically connected to the control end of the second switch tube, the control end of the fifth switch tube is electrically connected to the frequency control end, the first end of the fifth switch tube is electrically connected to a second signal end, the second end of the fifth switch tube is electrically connected to the control end of the third switch tube, the first end of the third capacitor is electrically connected to the frequency control end, and the second end of the third capacitor is electrically connected to a power voltage end. When the region where the pixel unit is located displays an image at the first refresh rate, the frequency control end controls the fourth switch tube and the fifth switch tube to be turned on, so as to control the first signal end and the second signal end to output a second level signal to the control end of the second switch tube and the control end of the third switch tube, so as to control the second switch tube and the third switch tube to be turned on; when the region where the pixel unit is located displays an image at the second refresh rate, the frequency control module controls the fourth switch tube and the fifth switch tube to be turned off, so as to control the second switch tube and the third switch tube to be turned off.

7. The display panel of claim 6, wherein, The first reset module comprises a sixth switch tube, and the second reset module comprises a seventh switch tube; a control end of the sixth switch tube is electrically connected to a third signal end; a first end of the sixth switch tube is electrically connected to a first reset end; a second end of the sixth switch tube is electrically connected to a first end of the driving switch tube; a control end of the seventh switch tube is electrically connected to a fourth signal end; a first end of the seventh switch tube is electrically connected to a second reset end; and a second end of the seventh switch tube is electrically connected to the light-emitting module. The sixth switch tube is used for being turned on under the control of the third signal end, so as to control the first reset end to output a reset signal to reset the driving switch tube; and the seventh switch tube is used for being turned on under the control of the fourth signal end, so as to control the second reset end to reset the light-emitting module.

8. The display panel of claim 7, wherein, The first light-emitting control module comprises an eighth switch tube, and the second light-emitting control module comprises a ninth switch tube; a control end of the eighth switch tube is electrically connected to a fifth signal end; a first end of the eighth switch tube is electrically connected to the first end of the driving switch tube; a second end of the eighth switch tube is electrically connected to a power supply voltage end; a control end of the ninth switch tube is electrically connected to a sixth signal end; a first end of the ninth switch tube is electrically connected to the second node; and a second end of the ninth switch tube is electrically connected to the light-emitting module. In the image display stage, the eighth switch tube is used for being turned on under the control of the fifth signal end; the ninth switch tube is used for being turned on under the control of the sixth signal end; the driving switch tube is turned on under the control of the data signal; and the power supply voltage end outputs a power supply voltage, which is output through the eighth switch tube, the driving switch tube and the ninth switch tube to drive the light-emitting module to emit light.

9. The display panel of claim 8, wherein, When the region where the pixel unit is located displays an image at the first refresh rate, the pixel unit performs image display, which comprises a first period, a second period, a third period, a fourth period, a fifth period and a sixth period in succession; in the first period, the fifth signal end outputs a second level signal to control the eighth switch tube to be turned off, so as to control the power supply voltage end to stop outputting a power supply voltage to the driving switch tube; In the second period, the frequency control end controls the fourth switch tube and the fifth switch tube to be turned on; the second signal end controls the third switch tube to be turned on; and the third signal end controls the sixth switch tube to be turned on, so as to control the first reset end to reset the driving switch tube; In the third period, the frequency control end controls the fourth switch tube and the fifth switch tube to be turned off; the second signal end controls the third switch tube to be turned off; and the third signal end controls the sixth switch tube to be turned off, so as to control the second reset end to reset the light-emitting module; In the fourth period, the frequency control end controls the fourth switch tube and the fifth switch tube to be turned on; the second signal end controls the third switch tube to be turned on; and the third signal end controls the sixth switch tube to be turned on, so as to control the first reset end to reset the driving switch tube; In the fifth period, the frequency control end controls the fourth switch tube and the fifth switch tube to be turned off; the second signal end controls the third switch tube to be turned off; and the third signal end controls the sixth switch tube to be turned off, so as to control the second reset end to reset the light-emitting module; and In the sixth period, the frequency control end controls the fourth switch tube and the fifth switch tube to be turned on; the second signal end controls the third switch tube to be turned on; and the third signal end controls the sixth switch tube to be turned on, so as to control the first reset end to reset the driving switch tube. In the third time period, the first signal end controls the second switch tube to be turned on, so as to control the reference voltage end to output a first level signal to the first node, thereby controlling the driving switch tube to be turned on; In the fourth time period, the scanning signal controls the first switch tube to be turned on, and the data signal is transmitted to the storage capacitor through the driving switch tube and the third switch tube; In the fifth time period, the second signal end controls the point switch tube to be turned off, and the third signal end controls the sixth switch tube to be turned on, so as to control the first reset end to reset the driving switch tube; In the sixth time period, the fifth signal end controls the seventh switch tube and the eighth switch tube to be turned on, the data signal controls the driving switch tube to be turned on, and the power voltage end outputs the power voltage to the light emitting module through the eighth switch tube, the driving switch tube and the ninth switch tube, so as to control the light emitting module to emit light. When the region where the pixel unit is located displays an image at the second refresh rate, in the second time period and the third time period, the frequency control end outputs a second frequency control signal for controlling the fourth switch tube and the fifth switch tube to be turned off, so as to control the second switch tube and the third switch tube to be turned off, thereby controlling the storage capacitor to stop receiving the data signal.

10. The display panel of claim 9, wherein, The display panel further comprises a data driving circuit, a selection circuit and a conversion circuit, the selection circuit is electrically connected to the data driving circuit, the conversion circuit and the pixel unit, the conversion circuit is electrically connected to the frequency control end, the data driving circuit is configured to output the data signal and an initial signal to the selection circuit at different times, the selection circuit is configured to transmit the data signal to the pixel unit and transmit the initial signal to the conversion circuit, and the conversion circuit is configured to identify rising and falling edges of the initial signal, when the conversion circuit outputs the first frequency control signal to the frequency control end according to the rising edge of the initial signal, the region where the pixel unit is located displays an image at the first refresh rate, and when the conversion circuit outputs the second frequency control signal to the frequency control end according to the falling edge of the initial signal, the region where the pixel unit is located displays an image at the second refresh rate.

11. The display panel of claim 10, wherein, The selection circuit comprises a first control tube and a second control tube, the control end of the first control tube is electrically connected to a selection signal end, the first end of the first control tube is electrically connected to the data driving circuit, the second end of the first control tube is electrically connected to the pixel unit, the control end of the second control tube is electrically connected to the selection signal end, the first end of the second control tube is electrically connected to the data driving circuit, and the second end of the second control tube is electrically connected to the conversion circuit. When the selection signal end outputs a first level signal, the first control tube is turned on, and the data driving circuit outputs the data signal to the pixel unit through the first control tube, and when the selection signal end outputs a second level signal, the second control tube is turned on, and the data driving circuit outputs the initial signal to the conversion circuit through the second control tube.

12. The display panel of claim 11, wherein, The conversion circuit comprises an adjusting module, an output module and a maintaining module, the adjusting module is electrically connected to the data driving circuit and the output module, the adjusting module is used for identifying rising and falling edges of the initial signal, when the adjusting module identifies the rising edge of the initial signal, the adjusting module outputs a first control signal to the output module, when the adjusting module identifies the falling edge of the initial signal, the adjusting module outputs a second control signal, the output module outputs the first frequency control signal to the frequency control end according to the first control signal, the output module outputs the second frequency control signal to the frequency control end according to the second control signal, and the maintaining module is electrically connected to the adjusting module and is used for maintaining voltage stability in the adjusting module when the adjusting module performs voltage adjustment.

13. The display panel of claim 12, wherein, The adjusting module comprises a third control tube, a fourth control tube, a fourth capacitor and a fifth capacitor, wherein the first end of the fourth capacitor is electrically connected to an input end, the second end of the fourth capacitor is electrically connected to the control end of the third control tube, the first end of the third control tube is electrically connected to a closing voltage end, the second end of the third control tube is electrically connected to a control node, the control end of the fourth control tube is electrically connected to the input end, the first end of the fourth control tube is electrically connected to an opening voltage end, the second end of the fourth control tube is electrically connected to the control node, the first end of the fifth capacitor is electrically connected to the input end, and the second end of the fifth capacitor is electrically connected to the second end of the fourth control tube. The third control tube is used for turning on according to the rising edge of the initial signal to control the closing voltage end to output a first level signal to the control node, and the fourth control tube is used for turning on according to the falling edge of the initial signal to control the opening voltage end to output a second level signal to the control node.

14. The display panel of claim 13, wherein, The output module comprises a fifth control tube and a sixth control tube, the maintaining module comprises a seventh control tube, the control end of the fifth control tube is electrically connected to the control node, the first end of the fifth control tube is electrically connected to the opening voltage end, the second end of the fifth control tube is electrically connected to an output end, the control end of the sixth control tube is electrically connected to the control node, the first end of the sixth control tube is electrically connected to the closing voltage end, the second end of the sixth control tube is electrically connected to the output end, the control end of the seventh control tube is electrically connected to an input end, the first end of the seventh control tube is electrically connected to the closing voltage end, and the second end of the seventh control tube is electrically connected to the control end of the third control tube. The fifth control tube is turned on according to the first level signal to control the open voltage end to output the first frequency control signal to the frequency control end through the output end, the sixth control tube is turned on according to the second level signal to control the close voltage end to output the second frequency control signal to the frequency control end through the output end, and the seventh control tube is used to be turned on when the initial signal is at a first level to control the close voltage end to output a first level signal to the control end of the third control tube to control the third control tube to maintain in an off state.

15. A display device comprising: The display panel comprises a power module and a display panel according to any one of claims 1-14, and the power module is used to provide driving current for the display panel to drive the display panel to perform image display.

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