Method for improving electric leakage of semiconductor device with dislocation structure
By forming a gate structure, sidewalls, and germanium-silicon layer in a semiconductor device, etching away twin defects, and epitaxially growing a silicon layer, the leakage problem caused by dislocation structures is solved, and the device performance is improved.
Patent Information
- Application Number
- CN202511140724.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-14
- Publication Date
- 2025-12-09
AI Technical Summary
In the prior art, semiconductor devices with dislocation structures exhibit severe leakage current after process node reduction, mainly because twin defects formed by dislocation structures easily create leakage current channels at LDD and S/D positions.
The process involves forming a gate structure and sidewalls on a substrate, creating an LDD region and a germanium-silicon layer, depositing a sacrificial layer and then annealing it to form a dislocation structure. Etching removes some of the dislocation structure and twin defects, epitaxially growing a silicon layer to re-form a complete dislocation structure, and finally performing a stress memory process and forming contact holes.
It effectively suppressed the formation of leakage channels, improved device performance, and enhanced the overall performance of the device by retaining some dislocation structures and eliminating twin defects.
Smart Images
Figure CN121099686A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a method for improving leakage current in semiconductor devices with dislocation structures. Background Technology
[0002] In high-k / metal gate back-gate processes, removing the dummy gate eliminates the high stress exerted by the gate on the channel, so it is necessary to enhance the source / drain stress memory effect (S / D SMT) to improve NMOS performance.
[0003] The current method involves injecting high-energy heavy ions into the S / D region to form an amorphous layer, then using conventional stress memory technology to cover the oxide layer and high-stress silicon nitride for S / D activation. During solid-state epitaxial growth, the crystal growth rate is (001)>(110)>(111), eventually forming a crystal defect on the (111) plane. This defect can enhance the tensile stress in the S / D region and the channel region, improve carrier mobility, and thus improve NMOS performance.
[0004] As process nodes shrink, semiconductor devices with dislocation structures formed using existing technologies exhibit severe leakage current. This is primarily because the formation of dislocation structures generates twin defects, such as… Figure 1 As shown, twin defects are often located shallower than dislocation structures, making it easy for leakage current channels to form at LDD and S / D locations. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method for improving leakage current in semiconductor devices with dislocation structures, in order to solve the problem that twin defect regions forming leakage current channels exist in semiconductor devices with dislocation structures formed in the prior art.
[0006] To achieve the above and other related objectives, this application provides a method for improving leakage current in a semiconductor device with a dislocation structure, comprising:
[0007] Step 1: Provide a substrate and form a gate structure on the substrate;
[0008] Step 2: After forming the first sidewall on the side of the gate structure, LDD regions are formed in the substrate on both sides of the first sidewall.
[0009] Step 3: Form a germanium-silicon layer in the PMOS region of the substrate;
[0010] Step four: Form an amorphous region in the NMOS region of the substrate;
[0011] Step 5: After depositing the sacrificial layer in the NMOS region, an annealing process is performed to recrystallize the amorphous region and form a dislocation structure.
[0012] Step 6: After removing the sacrificial layer, etch the NMOS region to remove some dislocation structures;
[0013] Step 7: Epitaxially grow a silicon layer in the trenches formed in the etched area to re-form a complete dislocation structure;
[0014] Step 8: After forming the second sidewall on the side of the first sidewall, source / drain regions are formed in the substrate on both sides of the second sidewall.
[0015] Step nine: After implementing the stress memory process, contact holes are formed.
[0016] Preferably, in step six, twin defects are completely removed while removing some dislocation structures.
[0017] Preferably, the etching performed in step six is dry etching or wet etching, and the etching depth is [insert depth here].
[0018] Preferably, in step four, an amorphous region is formed by ion implantation, with implanted ions including Ge, Si, or Xe, an implantation energy of 10 keV to 60 keV, and a dose of 1E13cm. -2 ~1E15cm -2 The injection angle is 0°-7°, and the injection temperature is -100℃ to room temperature.
[0019] Preferably, the sacrificial layer comprises a silicon oxide layer and a silicon nitride layer stacked from bottom to top.
[0020] Preferably, the annealing process implemented in step five includes rapid thermal annealing, millisecond thermal annealing, microsecond thermal annealing, peak annealing, or furnace tube annealing, with an annealing temperature of 900℃~1100℃.
[0021] Preferably, the thickness of the silicon layer epitaxially grown in step seven is the same as the etching depth performed in step six.
[0022] Preferably, the silicon layer is epitaxially grown while being doped with P or C.
[0023] Preferably, the step of forming the germanium-silicon layer in step three includes: forming a Σ-shaped groove in the PMOS region of the substrate by etching; and epitaxially growing a germanium-silicon layer inside and outside the Σ-shaped groove.
[0024] Preferably, the material of the first sidewall is an oxide, and the material of the second sidewall is silicon nitride.
[0025] As described above, the method for improving leakage current in semiconductor devices with dislocation structures provided in this application has the following beneficial effects: after forming the dislocation structure, the region with twin defects is etched and a portion of the dislocation structure is retained, and then silicon is epitaxially grown. The dislocation will continue to grow along the remaining portion, and the twin defects will be eliminated, thereby suppressing the formation of leakage channels and improving device performance. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0027] Figure 1 The diagram shows a cross-sectional structure of a semiconductor device with a dislocation structure formed according to the prior art, in which a twin defect region is formed.
[0028] Figure 2 The flowchart shown is a method for improving leakage current in semiconductor devices with dislocation structures according to an embodiment of this application.
[0029] Figures 3A-3I The diagram shown is a cross-sectional view of the device formed after each step in the method for improving leakage current of a semiconductor device with a dislocation structure provided in this application embodiment. Detailed Implementation
[0030] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.
[0031] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0032] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0033] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0034] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0035] Please see Figure 2 The diagram illustrates a flowchart of a method for improving leakage current in semiconductor devices with dislocation structures, provided in an embodiment of this application.
[0036] like Figure 2 As shown, the method for improving leakage current in semiconductor devices with dislocation structures includes:
[0037] Step 1: Provide a substrate and form a gate structure on the substrate;
[0038] Step 2: After forming the first sidewall on the side of the gate structure, LDD regions are formed in the substrate on both sides of the first sidewall.
[0039] Step 3: Form a germanium-silicon layer in the PMOS region of the substrate;
[0040] Step four: Form an amorphous region in the NMOS region of the substrate;
[0041] Step 5: After depositing the sacrificial layer in the NMOS region, an annealing process is performed to recrystallize the amorphous region and form a dislocation structure.
[0042] Step 6: After removing the sacrificial layer, etch the NMOS region to remove some dislocation structures;
[0043] Step 7: Epitaxially grow a silicon layer in the trenches formed in the etched area to re-form a complete dislocation structure;
[0044] Step 8: After forming the second sidewall on the side of the first sidewall, source / drain regions are formed in the substrate on both sides of the second sidewall.
[0045] Step nine: After implementing the stress memory process, contact holes are formed.
[0046] In step one, as Figure 3A As shown, the substrate 300 can be any suitable substrate material known to those skilled in the art, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium silicide, and other III-V compounds.
[0047] An isolation component 312 is formed on the substrate 300, which divides the substrate 300 into a PMOS region and an NMOS region.
[0048] The insulating component 312 may be composed of any insulating material such as silicon dioxide (SiO2) or a "high-k" dielectric with a high dielectric constant, for example, greater than 3.9. In some cases, the insulating component 312 may be composed of oxide materials. Suitable materials for constituting the insulating component 312 may include, for example, silicon dioxide (SiO2), hafnium oxide (HfO2), bauxite (Al2O3), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), titanium dioxide (TiO2), praseodymium oxide (Pr2O3), zirconium oxide (ZrO2), erbium oxide (ErOx), and other materials with similar properties, either currently known or developed later.
[0049] For example, the isolation component 312 is formed by a shallow trench isolation process (STI), which includes, but is not limited to, shallow trench etching, oxide filling, and oxide planarization.
[0050] Shallow trench etching includes, but is not limited to, isolating oxide layers, nitride deposition, shallow trench isolation using masks, and STI shallow trench etching. STI oxide filling includes, but is not limited to, trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide filling, or PVD (physical vapor deposition) oxide filling. Silicon wafer surface planarization can be achieved through various methods. Planarization can be achieved by using SOG (spin-on-glass) to fill the gaps. SOG can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked to evaporate the solvent, leaving the silicon dioxide in the gaps. Alternatively, the entire surface can be reverse-etched to reduce the overall wafer thickness. Planarization can also be effectively achieved through CMP (chemical mechanical polishing) processes, including but not limited to polishing the trench oxides (using chemical mechanical polishing) and nitride removal.
[0051] A gate structure 301 is formed on the PMOS and NMOS regions of the substrate 300. As an example, the gate structure 301 includes a gate insulating layer and a gate layer stacked from bottom to top. The gate structure 301 can be a pseudo-gate structure in a high-k / metal gate-after-gate process.
[0052] In step two, as Figure 3B As shown, after the first sidewall 302 is formed on the side of the gate structure 301, LDD regions are formed in the substrates 300 on both sides of the first sidewall 302.
[0053] As an example, the material of the first sidewall 302 is oxide, and an LDD region is formed by ion implantation. The process steps for forming the LDD region are familiar to those skilled in the art and will not be described in detail here.
[0054] In step three, as Figure 3C As shown, a germanium-silicon layer 303 is formed in the PMOS region of the substrate 300.
[0055] As an example, the steps for forming the germanium-silicon layer 303 include: forming a Σ-shaped groove in the PMOS region of the substrate 300 by an etching process; and epitaxially growing the germanium-silicon layer 303 inside and outside the Σ-shaped groove.
[0056] In step four, as Figure 3D As shown, an amorphous region 305 is formed in the NMOS region of the substrate 300.
[0057] As an example, an amorphous region 305 is formed by ion implantation, with implanted ions including Ge, Si, or Xe, an implantation energy of 10 keV to 60 keV, and a dose of 1E13cm. -2 ~1E15cm -2 The injection angle is 0°-7°, and the injection temperature is -100℃ to room temperature.
[0058] In step five, as Figure 3E As shown, after depositing the sacrificial layer 306 in the NMOS region, an annealing process is performed to recrystallize the amorphous region 305 and form a dislocation structure 307.
[0059] As an example, the sacrificial layer 306 comprises a silicon oxide layer and a silicon nitride layer stacked from bottom to top. The annealing process includes rapid thermal annealing (RTA), millisecond thermal annealing (MSA), microsecond thermal annealing (μSA), peak annealing (SPK), or furnace tube annealing, with an annealing temperature of 900°C to 1100°C.
[0060] After implementing step five, a twin defect 308 is formed in the upper part of the region where the dislocation structure 307 is located.
[0061] In step six, as Figure 3F As shown, after removing the sacrificial layer 306, the NMOS region is etched to remove some of the dislocation structures 307. At the same time, the twin defect 308 is completely removed.
[0062] As an example, the etching is either dry or wet etching, and the etching depth is...
[0063] In step seven, as Figure 3G As shown, a silicon layer 309 is epitaxially grown in the trench formed in the etched region of step six, thus reforming the complete dislocation structure 307. The thickness of the epitaxially grown silicon layer 309 is the same as the etching depth in step six (the depth of the trench formed in the etched region). As an example, P or C can be doped simultaneously with the epitaxial growth of the silicon layer 309.
[0064] In step eight, as Figure 3H As shown, after the second sidewall 310 is formed on the side of the first sidewall 302, source / drain regions are formed in the substrate 300 on both sides of the second sidewall 310.
[0065] As an example, the material of the second sidewall 310 is silicon nitride, and the source / drain regions are formed by ion implantation. The process steps for forming the source / drain regions are familiar to those skilled in the art and will not be described in detail here.
[0066] Step nine, as Figure 3I As shown, after implementing the stress memory process, contact hole 311 is formed. The stress memory process and the process steps for forming contact hole 311 are familiar to those skilled in the art and will not be described in detail here.
[0067] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0068] In summary, the method for improving leakage current in semiconductor devices with dislocation structures provided in this application involves forming a dislocation structure 307, etching the region where twin defects 308 are formed, retaining a portion of the dislocation structure 307, and then epitaxially growing a silicon layer 309. The dislocations continue to grow along the remaining portion, while the twin defects 308 are eliminated, thereby suppressing the formation of leakage channels and improving device performance. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.
[0069] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.
Claims
1. A method for improving leakage current in a semiconductor device with a dislocation structure, characterized in that, The method includes: Step 1: Provide a substrate and form a gate structure on the substrate; Step 2: After forming the first sidewall on the side of the gate structure, LDD regions are formed in the substrate on both sides of the first sidewall. Step 3: Form a germanium-silicon layer in the PMOS region of the substrate; Step four: Form an amorphous region in the NMOS region of the substrate; Step 5: After depositing a sacrificial layer in the NMOS region, an annealing process is performed to recrystallize the amorphous region and form a dislocation structure. Step six: After removing the sacrificial layer, the NMOS region is etched to remove part of the dislocation structure; Step 7: Epitaxially grow a silicon layer in the trenches formed in the etched area to reform a complete dislocation structure; Step 8: After forming the second sidewall on the side of the first sidewall, form source / drain regions in the substrate on both sides of the second sidewall; Step nine: After implementing the stress memory process, contact holes are formed.
2. The method according to claim 1, characterized in that, In step six, while removing part of the dislocation structure, twin defects are completely removed.
3. The method according to claim 1 or 2, characterized in that, The etching performed in step six is either dry etching or wet etching, and the etching depth is [insert depth here].
4. The method according to claim 1, characterized in that, In step four, the amorphous region is formed by ion implantation. The implanted ions include Ge, Si, or Xe, the implantation energy is 10 keV to 60 keV, and the dose is 1E13cm. -2 ~1E15cm -2 The injection angle is 0°-7°, and the injection temperature is -100℃ to room temperature.
5. The method according to claim 1, characterized in that, The sacrificial layer comprises silicon oxide and silicon nitride layers stacked from bottom to top.
6. The method according to claim 1, characterized in that, The annealing process implemented in step five includes rapid thermal annealing, millisecond thermal annealing, microsecond thermal annealing, peak annealing, or furnace tube annealing, with an annealing temperature of 900℃~1100℃.
7. The method according to claim 3, characterized in that, The thickness of the silicon layer epitaxially grown in step seven is the same as the etching depth.
8. The method according to claim 1, characterized in that, The epitaxial silicon layer is simultaneously doped with P or C.
9. The method according to claim 1, characterized in that, The step of forming the germanium-silicon layer in step three includes: forming a Σ-shaped groove in the PMOS region of the substrate by etching; and epitaxially growing the germanium-silicon layer inside and outside the Σ-shaped groove.
10. The method according to claim 1, characterized in that, The first sidewall is made of oxide, and the second sidewall is made of silicon nitride.