Back contact cells, cell assemblies and photovoltaic systems

Abstract

The application is suitable for the technical field of solar cells, and provides a back contact cell, a cell module and a photovoltaic system. In the back contact cell, a first pad, a third pad, a first connecting grid line, a third connecting grid line and a first busbar grid line are arranged on the back surface. The first connecting grid line is electrically connected with the first pad and connected with a first fine grid line between the first edge and the first pad. The third connecting grid line is electrically connected with the third pad and connected with a second fine grid line between the first edge and the third pad. The second fine grid line is disconnected at the first connecting grid line. The first fine grid line is disconnected at the third connecting grid line. The first busbar grid line is arranged close to the third edge. The first busbar grid line is connected with at least the second fine grid line between the first pad closest to the third edge and the third edge. The width of the first busbar grid line is smaller than the width of the first connecting grid line. In this way, the efficiency of the back contact cell can be improved.

Description

[0001] Priority information

[0002] This application claims priority and benefits to patent application No. 202511082713.1, filed with the China National Intellectual Property Administration on August 1, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of solar cell technology, and more particularly to a back-contact cell, a cell module, and a photovoltaic system. Background Technology

[0004] A back-contact battery is a type of battery in which both P-type and N-type doped layers are placed on the back of a silicon wafer, with no metal electrodes obstructing the front. It has higher short-circuit current and conversion efficiency.

[0005] In related technologies, the back of a back-contact battery has two types of fine grids and two types of pads with different polarities. The pads are used to weld and fix the battery to the solder ribbon. The fine grids of the same polarity are connected to the pads, and the grids are disconnected at the pads of opposite polarities. When setting the pads, to avoid microcracks in the battery cell during soldering due to the pads being too close to the edge, the pads are usually placed at a certain distance from the edge. However, this setting results in the current in the fine grids located at the edge not being fully collected, leading to lower efficiency. Therefore, how to improve the efficiency of back-contact batteries has become an urgent problem to be solved. Summary of the Invention

[0006] This application provides a back-contact battery, a battery module, and a photovoltaic system.

[0007] This application is implemented as follows: the back contact battery in the embodiments of this application includes:

[0008] A silicon substrate having opposing back and front sides;

[0009] A plurality of first fine gates and a plurality of second fine gates are disposed on the back side, the plurality of first fine gates and the plurality of second fine gates are arranged alternately and alternately along a first direction and all extend along a second direction, the first direction and the second direction intersect, the silicon substrate has a first edge and a second edge opposite to each other in the first direction, and the silicon substrate has a third edge and a fourth edge opposite to each other in the second direction;

[0010] A plurality of first pads and a plurality of third pads are disposed on the back side. The first pads and the third pads are both disposed close to the first edge and have a plurality of first fine gates and a plurality of second fine gates between them and the first edge. The first pads are connected to a portion of the first fine gates and are insulated from the second fine gates. The third pads are connected to a portion of the second fine gates. The second fine gates are disconnected at the first pads and the first fine gates are disconnected at the third pads. Among the plurality of first pads and the plurality of third pads, the pad closest to the third edge is the first pad.

[0011] A first connecting gate line and a third connecting gate line, the first connecting gate line being electrically connected to the first pad and to a first fine gate located between the first edge and the first pad, the third connecting gate line being electrically connected to the third pad and to a second fine gate located between the first edge and the third pad, the second fine gate being disconnected at the first connecting gate line, and the first fine gate being disconnected at the third connecting gate line; and

[0012] A first bus gate line is disposed near the third edge, the first bus gate line being connected at least to a second fine gate located between the first pad closest to the third edge and the third edge, the width of the first bus gate line being smaller than the width of the first connecting gate line.

[0013] In some embodiments, the first busbar is connected to all of the second fine gates.

[0014] In some embodiments, a first chamfer is formed at the intersection of the first edge and the third edge. Among the first fine gate and the second fine gate, the fine gate closest to the first edge is the first edge fine gate and the first edge fine gate is the second fine gate. The first edge fine gate corresponds to the first chamfer. The first bus gate line is connected to all the second fine gates except for the first edge fine gate.

[0015] In some embodiments, the width of the first bus gate line is 190μm-210μm, and the width of the first connecting gate line is 240μm-260μm.

[0016] In some embodiments, the ratio between the width of the first busbar and the width of the first connecting busbar is 0.6-0.9.

[0017] In some embodiments, among the first and second fine gates, the width of the fine gate closest to the first and second edges is greater than the width of the remaining fine gates.

[0018] In some embodiments, among the first fine gate and the second fine gate, the fine gate closest to the first edge is the first edge fine gate, the fine gate closest to the second edge is the second edge fine gate, and the fine gate located between the first edge fine gate and the second edge fine gate is the middle fine gate;

[0019] Wherein, the width of the first edge fine gate and the second edge fine gate is greater than the width of the middle fine gate, and the width of the first bus gate line is greater than the width of the middle fine gate and less than the width of the first edge fine gate and the second edge fine gate.

[0020] In some embodiments, among the plurality of first pads and the plurality of third pads, the pad closest to the fourth edge is the third pad, and the back contact battery further includes a second bus gate line disposed close to the fourth edge. The second bus gate line is connected at least to the first fine gate located between the third pad closest to the fourth edge and the fourth edge, and the width of the second bus gate line is smaller than the width of the third connecting gate line.

[0021] In some embodiments, the second busbar is connected to all of the first fine gates.

[0022] In some embodiments, the width of the second bus gate is 190μm-210μm, and the width of the third connecting gate is 240μm-260μm.

[0023] In some embodiments, the ratio between the width of the second busbar and the width of the third connecting busbar is 0.6-0.9.

[0024] In some embodiments, among the first fine gate and the second fine gate, the fine gate closest to the first edge is the first edge fine gate, the fine gate closest to the second edge is the second edge fine gate, and the fine gate located between the first edge fine gate and the second edge fine gate is the middle fine gate;

[0025] Wherein, the width of the first edge fine gate and the second edge fine gate is greater than the width of the middle fine gate, and the width of the second bus gate line is greater than the width of the middle fine gate and less than the width of the first edge fine gate and the second edge fine gate.

[0026] This application also provides a battery assembly, which may include a plurality of back contact batteries as described in any of the above claims.

[0027] This application also provides a photovoltaic system, which includes the above-described battery components.

[0028] In the back-contact battery, battery module, and photovoltaic system of this application embodiment, the presence of the first connecting grid line allows the current collected by the first fine grid at the edge position to be directly channeled to the first pad and the first solder strip. Due to the presence of the third connecting grid line, the current collected by the second fine grid at the edge position can be directly channeled to the third pad and the second solder strip, improving efficiency. Simultaneously, the arrangement of the first bus grid line ensures that the isolated grid line segments of the second fine grid located between the third edge and the first pad and the first connecting grid line can be completely collected, thereby improving the efficiency of the back-contact battery. Furthermore, the first connecting grid line needs to channel the current on the grid line segments on both sides of the first connecting grid line, while the third connecting grid line needs to channel the current on both sides of the third connecting grid line. The first bus grid line only needs to channel the current on one side of the grid line segment of the first connecting grid line, and the second bus grid line only needs to channel the current on one side of the grid line segment of the third connecting grid line. Therefore, by setting the width of the first and second busbars to be smaller, the cost of the slurry can be reduced while avoiding excessive busbar loss. Furthermore, setting the width of the first and second busbars to be narrower can also reduce the risk of microcracks caused by stress concentration at the edges.

[0029] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a photovoltaic system module provided in an embodiment of this application;

[0031] Figure 2 This is a schematic diagram of a battery assembly provided in an embodiment of this application;

[0032] Figure 3 This is a schematic diagram of the battery string module provided in an embodiment of this application;

[0033] Figure 4 This is a schematic diagram of the planar structure of the back contact battery provided in an embodiment of this application;

[0034] Figure 5 This is a schematic diagram of a planar structure of a back contact battery with a first solder strip and a second solder strip provided in an embodiment of this application;

[0035] Figure 6 This is another planar structural schematic diagram of the back contact battery provided in the embodiments of this application;

[0036] Figure 7 This is another planar structural schematic diagram of the back contact battery provided in the embodiments of this application;

[0037] Figure 8This is another planar structural schematic diagram of the back contact battery provided in the embodiments of this application;

[0038] Figure 9 yes Figure 8 A magnified schematic diagram of the back contact battery at point IX;

[0039] Figure 10 yes Figure 8 A magnified schematic diagram of the back contact battery at point X;

[0040] Figure 11 yes Figure 8 A magnified schematic diagram of the back contact battery at point XI;

[0041] Figure 12 yes Figure 11 A schematic diagram of the cross-sectional structure of the back contact battery along line XII-XII.

[0042] Explanation of key component symbols:

[0043] Photovoltaic system 1000, battery module 300, battery string 200, first solder ribbon 210, second solder ribbon 220, back contact cell 100, silicon substrate 10, back side 11, front side 12, first edge 101, second edge 102, third edge 103, fourth edge 104, first fine grid 20, first thickened segment 21, second thickened segment 22, first pad 30, first connecting grid line 40, first connecting segment 41, second pad 50, second connecting grid line 60, second connecting segment 61, second fine grid 70, third thickened segment 71, fourth thickened segment 72, third pad 80, third connecting grid line 90, third connecting segment 91, fourth pad 110, fourth connecting grid line 120, fourth connecting segment 121, first busbar 130, second busbar 140, first test section 150, second test section 160. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0045] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "top", "bottom", "lateral", "longitudinal", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "several," "multiple," and "more than" mean two (roots) or more, unless otherwise explicitly specified.

[0047] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0048] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0049] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0050] Please see Figures 1-3 The photovoltaic system 1000 in this application embodiment may include the battery module 300 in this application embodiment. The battery module 300 in this application embodiment may include a plurality of battery strings 200. The battery strings 200 may include a plurality of back contact batteries 100 in this application embodiment.

[0051] In this application, the individual battery strings 200 in the battery assembly 300 can be connected in series, in parallel, or in a series-parallel combination to achieve current bus output. For example, the connection between the individual battery strings 200 can be achieved through a bus bar. The battery string 200 may include a plurality of back contact batteries 100 and a plurality of solder strips (such as the first solder strip 210 and the second solder strip 220 described below). The plurality of back contact batteries 100 may be arranged along a first direction, and the solder strips may extend along the first direction to connect the back contact batteries 100 in the battery string 200 in series sequentially.

[0052] Please see Figures 4-12 The back contact battery 100 in this embodiment may include a silicon substrate 10, a plurality of first fine gates 20, first pads 30, and first connecting gate lines 40. The silicon substrate 10 has opposing back surfaces 11 and front surfaces 12. The first fine gates 20 are disposed on the back surface 11, and are spaced apart along a first direction and extend along a second direction, the first direction intersecting the second direction. The back contact battery 100 also includes a plurality of second fine gates 70, which are also disposed on the back surface 11. The plurality of first fine gates 20 and the plurality of second fine gates 70 are arranged alternately along the first direction and all extend along the second direction. The silicon substrate 10 has opposing first edges 101 and second edges 102 in the first direction.

[0053] Specifically, such as Figure 4 As shown, the first direction and the second direction can be the longitudinal direction and the transverse direction of the back contact battery 100, respectively, and they are perpendicular to each other. Of course, in other embodiments, the first direction and the second direction can also be other directions, and there is no specific limitation here.

[0054] Furthermore, please refer to the following: Figure 4 , Figure 8 as well as Figure 12 In the back contact cell 100, a plurality of first doped layers 14 and a plurality of second doped layers 15 are alternately arranged along a first direction on the back side 11 of the silicon substrate 10. Both the first doped layers 14 and the second doped layers 15 extend along a second direction, and both the first doped layers 14 and the second doped layers 15 are provided with a back passivation layer (not shown in the figure). The first doped layer 14 is disposed below the first fine gate 20 and corresponds one-to-one with the first fine gate 20. The first fine gate 20 at least partially penetrates the passivation layer and forms an ohmic contact with the first doped layer 14. The second doped layer 15 is disposed below the second fine gate 70 and corresponds one-to-one with the second fine gate 70. The second fine gate 70 at least partially penetrates the back passivation layer and forms an ohmic contact with the second doped layer 15.

[0055] In some embodiments, a tunneling layer (not shown) may be present between the first doped layer 14 and the silicon substrate 10, and a tunneling layer (not shown) may also be present between the second doped layer 15 and the silicon substrate 10; specific details are not limited here.

[0056] like Figures 4-8 As shown, in the back contact battery 100, a first pad 30 may be disposed on the back surface 11. The first pad 30 is disposed near the first edge 101. Between the first pad 30 and the first edge 101, there are a plurality of first fine gates 20 and a plurality of second fine gates 70. The first pad 30 is connected to a portion of the first fine gates 20 and is insulated from the second fine gates 70. The first pad 30 is used for soldering to the first solder ribbon 210. A first connecting gate line 40 is located between the first pad 30 and the first edge 101. The first connecting gate line 40 is electrically connected to the first pad 30 and is also electrically connected to all the first fine gates 20 located between the first edge 101 and the first pad 30.

[0057] Please see Figure 4 In some embodiments, the first connection gate line 40 may be located on one side of the center line S1 of the first pad 30 in the second direction (i.e., the first connection gate line 40 and the center line S1 of the first pad 30 are spaced apart in the second direction), that is, the first connection gate line 40 and the center line S1 of the first pad 30 in the second direction are spaced apart in the second direction.

[0058] Please see Figures 4-8In some embodiments, the back contact battery 100 may further include a third pad 80 and a third connecting gate line 90. The third pad 80 is disposed on the back surface 11, and is located near the first edge 101, having a plurality of first fine gates 20 and a plurality of second fine gates 70 between the third pad 80 and the first edge 101. The first pad 30 and the first connecting gate line 40 are both insulated from the second fine gates 70. The third pad 80 is connected to a portion of the second fine gates 70 and is insulated from the first fine gates 20. The third pad 80 is used for soldering to the second solder ribbon 220. The third connecting gate line 90 may be disposed on the back surface 11, and is electrically connected to the third pad 80. The third connecting gate line 90 is also connected to the second fine gates 70 located between the first edge 101 and the third pad 80 and is insulated from the first fine gates 20.

[0059] like Figure 4 As shown, in some embodiments, the third connection gate line 90 may be located on one side of the center line S3 in the second direction of the third pad 80.

[0060] like Figures 4-8 As shown, in an embodiment of this application, the second fine gate 70 may be disconnected at the first pad 30 and the first connecting gate line 40 to be insulated from the first pad 30 and the first connecting gate line 40, and the first fine gate 20 may be disconnected at the third pad 80 and the third connecting gate line 90 to be insulated from the third pad 80 and the third connecting gate line 90.

[0061] like Figure 4 As shown in the embodiments of this application, the number of first pads 30 is multiple (only two are shown in the figure as an example. In actual process, the number of first pads 30 can be selected according to the size of the battery and actual needs). Multiple first pads 30 can be arranged at intervals along the second direction and can all be set collinearly. Of course, in some embodiments, multiple first pads 30 may not be set collinearly, and no specific limitation is made here.

[0062] The number of third pads 80 is also multiple (only two are shown in the figure as an example. In actual process, the number of third pads 80 can be selected according to the size of the battery and actual needs). Multiple third pads 80 can be arranged at intervals along the second direction and can be set collinearly, non-collinearly, or only partially collinearly. The first pad 30 and the third pad 80 are arranged alternately at intervals along the second direction.

[0063] Each first pad 30 corresponds to one first connection gate line 40, and the number of first connection gate lines 40 corresponds to the number of first pads 30. Each third pad 80 corresponds to one third connection gate line 90, and the number of third connection gate lines 90 corresponds to the number of third pads 80. The number of first solder ribbons 210 on each back contact battery 100 corresponds to the number of first pads 30 and first connection gate lines 40. The number of second solder ribbons 220 on each back contact battery 100 corresponds to the number of third pads 80 and third connection gate lines 90.

[0064] In some embodiments, in the battery string 200, a plurality of back-contact batteries 100 may be arranged along a first direction, and the first solder strip 210 of the battery string 200 extends along the first direction and is soldered to the first solder pad 30. The first solder strip 210 and the first connecting grid line 40 do not have an overlapping portion (e.g., Figure 5 (As shown). Each first pad 30 corresponds to a first connection gate line 40.

[0065] Additionally, in some embodiments, in the battery string 200, the second solder strip 220 extends along the first direction and is soldered to the third solder pad 80, and the second solder strip 220 and the third connecting grid line 90 do not have overlapping portions (e.g., Figure 5 (As shown).

[0066] Understandably, to prevent leakage, in some embodiments, insulating adhesive may be provided at the intersection of the first fine grid 20 and the second solder strip 220 to achieve insulation isolation between the two, or the first fine grid 20 may be disconnected at the position of the second solder strip 220. Similarly, in some embodiments, insulating adhesive may be provided at the intersection of the first fine grid 20 and the second solder strip 220 to achieve insulation isolation between the two, and insulating adhesive may be provided at the intersection of the second fine grid 70 and the first solder strip 210 to achieve insulation isolation between the two, or the second fine grid 70 may be disconnected at the position of the first solder strip 210.

[0067] In some embodiments of this application, the first solder ribbon 210 can be soldered to the first pad 30 without soldering to the first fine gate 20 between the first pad 30 and the first edge 101. The first solder ribbon 210 does not have solder points on the first fine gate 20 between the first pad 30 and the first edge 101. The second solder ribbon 220 can be soldered to the third pad 80 without soldering to the second fine gate 70 between the third pad 80 and the first edge 101. The second solder ribbon 220 does not have solder points on the second fine gate 70 between the third pad 80 and the first edge 101. This can effectively avoid cold solder joints and microcracks at the first edge 101 and ensure the quality of the component.

[0068] Furthermore, due to the presence of the first connecting gate line 40, the current collected by the first fine gate 20 at the edge position can be directly channeled to the first pad 30 and the first solder strip 210. Due to the presence of the third connecting gate line 90, the current collected by the second fine gate 70 at the edge position can be directly channeled to the third pad 80 and the second solder strip 220, thereby improving efficiency.

[0069] Furthermore, in some embodiments, in the battery string 200 and battery module 300, the first solder ribbon 210 and the first connecting grid line 40 do not overlap, and the second solder ribbon 220 and the third connecting grid line 90 do not overlap. This can reduce stress concentration during the module manufacturing process, reduce the risk of microcracks in the back contact battery 100, and improve the reliability of the module.

[0070] Specifically, in the embodiments of this application, the back contact battery 100 may be a gridless back contact battery. The silicon substrate 10 may be an N-type silicon substrate or a P-type silicon substrate, and there is no specific limitation here. One of the first doped layer 14 and the second doped layer 15 is a P-type doped layer and the other is an N-type doped layer, with opposite polarities. One of the first fine gate 20 and the second fine gate 70 is a positive electrode fine gate and the other is a negative electrode fine gate. One of the first solder ribbons 210 is a positive electrode solder ribbon and the other is a negative electrode solder ribbon.

[0071] like Figures 4-8 As shown, in some embodiments, all pads (such as the first pad 30 and the third pad 80 mentioned above, and the second pad 50 and the fourth pad 110 mentioned below) can be regular shapes, such as circles, rectangles, triangles, isosceles trapezoids, and symmetrical polygons, etc., without any specific limitation. The center lines of all pads are parallel to the first direction, and in the second direction, the structure of the pads is symmetrical about the center lines, that is, the center lines of the pads are straight lines parallel to the first direction and passing through the geometric center of the pads. Of course, in other possible embodiments, the pads can also be other regular or irregular shapes, without any specific limitation.

[0072] Please see Figures 4-8In some embodiments, the back contact battery 100 may further include a second pad 50 and a second connecting grid line 60. The second pad 50 is disposed on the back surface 11, and is located near the second edge 102, having a plurality of first fine grids 20 and a plurality of second fine grids 70 between the second pad 50 and the second edge 102. The second pad 50 is connected to a portion of the first fine grids 20 and is insulated from the second fine grids 70. The first pad 30 and the second pad 50 correspond one-to-one in a first direction and are collinearly disposed. The second pad 50 is used for soldering to the same first solder strip 210 soldered to the first pad 30. The second connecting grid line 60 is electrically connected to the second pad 50, and is also connected to all the first fine grids 20 located between the first edge 101 and the second pad 50 and is insulated from the second fine grids 70.

[0073] like Figure 4 As shown, in some embodiments, the second connecting gate line 60 may be located on one side of the center line S2 of the second pad 50 in the second direction. In such a case, the first solder strip 210 and the second connecting gate line 60 do not overlap in the battery string 200.

[0074] In addition, please see Figures 4-8 In some embodiments, the back contact battery 100 may further include a fourth pad 110 and a fourth connecting gate line 120. The fourth pad 110 is disposed on the back surface 11, and is located near the second edge 102, having a plurality of first fine gates 20 and a plurality of second fine gates 70 between the fourth pad 110 and the second edge 102. The fourth pad 110 is connected to a portion of the second fine gates 70 and is insulated from the first fine gates 20. The fourth pad 110 is used for welding to the same second solder strip 220 that is welded to the third pad 80. The third pad 80 and the fourth pad 110 correspond one-to-one in a first direction and are collinearly arranged. The fourth connecting gate line 120 is electrically connected to the fourth pad 110, and is connected to the second fine gates 70 located between the second edge 102 and the fourth pad 110 and is insulated from the first fine gates 20.

[0075] like Figure 4 As shown, in some embodiments, the fourth connection gate line 120 may be located on one side of the center line S4 of the fourth pad 110 in the second direction. In such a case, the second solder strip 220 and the fourth connection gate line 120 do not overlap in the battery string 200.

[0076] Specifically, the first solder ribbon 210 is soldered to the first pad 30 and the second pad 50, and is also soldered to or electrically connected to the first fine gate 20 between the first pad 30 and the second pad 50, thereby achieving conduction between all the first fine gates 20 and the first solder ribbon 210 to realize the current collection and transmission on all the first fine gates 20. The second solder ribbon 220 is soldered to the third pad 80 and the fourth pad 110, and is also soldered to or electrically connected to the second fine gate 70 between the third pad 80 and the fourth pad 110, thereby achieving conduction between all the second fine gates 70 and the second solder ribbon 220 to realize the current collection and transmission on all the second fine gates 70.

[0077] Furthermore, in such an embodiment, the second fine gate 70 may be disconnected at the second pad 50 and the second connecting gate line 60 to achieve mutual insulation isolation, and the first fine gate 20 may be disconnected at the fourth pad 110 and the fourth connecting gate line 120 to achieve mutual insulation isolation.

[0078] Thus, on the one hand, the first solder ribbon 210 can be soldered to the second pad 50 without soldering to the first fine gate 20 between the second pad 50 and the second edge 102. The first solder ribbon 210 does not have soldering points on the first fine gate 20 between the second pad 50 and the second edge 102. On the other hand, the second solder ribbon 220 can be soldered to the third pad 80 without soldering to the second fine gate 70 between the third pad 80 and the first edge 101. The second solder ribbon 220 does not have soldering points on the second fine gate 70 between the third pad 80 and the first edge 101, effectively preventing cold solder joints and microcracks at the second edge 102 and ensuring component quality. Simultaneously, due to the presence of the second connecting gate line 60, the current collected by the first fine gate 20 at the edge position can be directly channeled to the second pad 50 and the first solder ribbon 210. Similarly, due to the presence of the third connecting gate line 90, the current collected by the second fine gate 70 at the edge position can be directly channeled to the third pad 80 and the second solder ribbon 220, improving efficiency. On the other hand, in the battery string 200 and the battery module 300, the first solder strip 210 and the second connecting grid line 60 do not overlap, and the second solder strip 220 and the third connecting grid line 90 do not overlap. This can reduce stress concentration during the module manufacturing process, reduce the risk of microcracks in the back contact battery 100, and improve the reliability of the module.

[0079] Please see Figure 4 In some embodiments, the first connection gate line 40 may be in direct contact with the first pad 30. This direct contact between the first connection gate line 40 and the first pad 30 effectively reduces transmission bus losses.

[0080] Specifically, such as Figure 4As shown, in such an embodiment, the first connecting gate line 40 is cross-connected with the first pad 30 and located above the first pad 30. During the manufacturing process, the first connecting gate line 40 and the first pad 30 can be integrally printed.

[0081] In this embodiment, the first connecting gate line 40 can be directly connected to the first pad 30. The first connecting gate line 40 and the center line S1 of the first pad 30 are spaced apart in the second direction, and the distance between them is 0.5mm-1.5mm. In this way, it can effectively avoid the stress concentration caused by the overlap between the solder strip and the first connecting gate line 40 due to misalignment during the lamination and soldering of the solder strip.

[0082] Please see Figure 6 In some embodiments, the first connection gate line 40 may also be spaced apart from the first pad 30 in the second direction, and the first connection gate line 40 and at least one first fine gate 20 connected to the first pad 30 are electrically connected.

[0083] Thus, the first connecting gate line 40 is spaced apart from the first pad 30 and is electrically connected through the first fine gate 20 connected to the first pad 30. This allows the first connecting gate line 40 and the first pad 30 to have sufficient distance, thereby further reducing stress concentration.

[0084] Specifically, in such an embodiment, the first connecting gate line 40 does not directly contact the first pad 30, but is suspended on one side of the first pad 30 and is electrically connected to the first pad 30 through the first fine gate 20.

[0085] like Figure 6 As shown, in such an embodiment, the first connecting gate line 40 may be connected only to the first fine gate 20 on the first pad 30 that is closest to the first edge 101, thereby avoiding the second fine gate 70 from having isolated gate line segments between the first pad 30 and the first connecting gate line 40, which would result in efficiency loss.

[0086] In some embodiments, the distance between the first connecting gate line 40 and the first pad 30 in the second direction is less than or equal to 6 mm.

[0087] In this way, excessive transmission loss can be avoided due to the distance between the first connecting gate line 40 and the first pad 30 being too far.

[0088] Specifically, the spacing between the first connecting gate line 40 and the first pad 30 in the second direction can be, for example, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.5mm, 6mm or other values ​​between 0 and 6mm, without any specific limitation here.

[0089] Please see Figure 6In some embodiments, in the first fine gate 20 connected to the first pad 30, the first fine gate 20 connected to the first connecting gate line 40 includes a first thickened segment 21 located between the first pad 30 and the first connecting gate line 40, the width of the first thickened segment 21 being greater than the width of the rest of the first fine gate 20.

[0090] Thus, the first thickened segment 21 is used to transmit the current of the first connecting gate line 40 to the first pad 30 and the first solder strip 210. Setting the width of the first thickened segment 21 to be wider can reduce the transmission resistance of this part, thereby reducing transmission loss.

[0091] In some embodiments, the ratio of the first thickened segment 21 to the remainder of the first fine gate 20 may be 1.5:1 to 3:1.

[0092] Thus, by optimizing the ratio of the first thickened section 21 to the rest of the first fine grid 20, the width of the first thickened section 21 is avoided from being too small and thus failing to effectively reduce transmission loss, and the first thickened section 21 is also avoided from being too wide and thus causing the required slurry cost to be too high.

[0093] Specifically, the ratio of the first bold segment 21 to the rest of the first fine gate 20 can be, for example, 1.5:1, 1.6:1, 1.7:1, 1.8:1, 1.9:1, 2:1, 2.1:1, 2.2:1, 2.3:1, 2.4:1, 2.5:1, 2.6:1, 2.7:1, 2.8:1, 2.9:1, 3:1, or other values ​​between 1.5:1 and 3:1, without any specific limitation here.

[0094] In some embodiments, the distance between the first pad 30 and the first edge 101 may be 1mm-8mm; and / or the number of first fine gates 20 between the first pad 30 and the first edge 101 may be 5-12.

[0095] This ensures a sufficient safety distance between the first pad 30 and the first edge 101, effectively reducing the risk of microcracks and spalling at the edge of the first pad 30 when it is soldered to the first solder strip 210.

[0096] The distance between the first pad 30 and the first edge 101 can be, for example, 1mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, or other values ​​between 1mm and 8mm. In this application, the distance is preferably 4mm-6mm. The number of first fine gates 20 between the first pad 30 and the first edge 101 can be, for example, 5, 6, 7, 8, 9, 10, 11, and 12, preferably 5-10.

[0097] In some embodiments, the ratio between the length of the first connection gate line 40 in the first direction and the length of the silicon substrate 10 in the first direction is 1:10-1:6.

[0098] Thus, by optimizing the ratio range of the length of the first connection gate line 40 to the length of the silicon substrate 10, the amount of paste used for the first connection gate line 40 can be reduced, thereby lowering the cost.

[0099] Specifically, the ratio can be, for example, 1:10, 1:9.5, 1:9, 1:8.5, 1:8, 1:7.5, 1:7, 1:6.5, 1:6, or other values ​​between 1.10 and 1:6.

[0100] Please see Figure 4 and Figure 8 In some embodiments, the second connection gate line 60 may be in direct contact with the second pad 50. This direct contact between the second connection gate line 60 and the second pad 50 effectively reduces transmission bus losses.

[0101] Specifically, such as Figure 4 As shown, in such an embodiment, the second connecting gate line 60 is cross-connected with the second pad 50 and located above the second pad 50. During the manufacturing process, the second connecting gate line 60 and the second pad 50 can be integrally printed.

[0102] In this embodiment, the second connecting gate line 60 can be directly connected to the second pad 50. The second connecting gate line 60 and the center line S2 of the second pad 50 are spaced apart in the second direction, and the distance between them is 0.5mm-1.5mm. In this way, it can effectively avoid the stress concentration caused by the overlap between the solder strip and the second connecting gate line 60 due to misalignment during the lamination and soldering of the solder strip.

[0103] Of course, please see Figure 6 In some embodiments, the second connection gate line 60 may also be spaced apart from the second pad 50 in the second direction, and the second connection gate line 60 and at least one first fine gate 20 connected to the second pad 50 are electrically connected.

[0104] Thus, the second connecting gate line 60 is spaced apart from the second pad 50 and is electrically connected through the first fine gate 20 connected to the second pad 50. This allows the second connecting gate line 60 and the second pad 50 to have sufficient distance, thereby further reducing stress concentration.

[0105] Specifically, in such an embodiment, the second connecting gate line 60 does not directly contact the second pad 50, but is suspended on one side of the second pad 50 and is electrically connected to the second pad 50 through the first fine gate 20.

[0106] like Figure 6 As shown, in such an embodiment, the second connecting gate line 60 may be connected only to the first fine gate 20 on the second pad 50 that is closest to the second edge 102, thereby avoiding the formation of isolated gate line segments of the second fine gate 70 between the second pad 50 and the second connecting gate line 60, which would result in efficiency loss.

[0107] In some embodiments, the spacing between the second connecting gate line 60 and the second pad 50 in the second direction is less than or equal to 6 mm.

[0108] This avoids excessive transmission loss caused by the distance between the second connecting gate line 60 and the second pad 50 being too far.

[0109] Specifically, the spacing between the second connecting gate line 60 and the second pad 50 in the second direction can be, for example, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.5mm, 6mm or other values ​​between 0 and 6mm, without any specific limitation here.

[0110] Please see Figure 6 In some embodiments, in the first fine gate 20 connected to the second pad 50, the first fine gate 20 connected to the second connecting gate line 60 includes a second thickened segment 22 located between the second pad 50 and the second connecting gate line 60, the width of the second thickened segment 22 being greater than the width of the rest of the first fine gate 20.

[0111] Thus, the second thickened section 22 is used to transmit the current from the second connecting gate line 60 to the second pad 50 and the first solder strip 210. Setting the width of the second thickened section 22 to be wider can reduce the transmission resistance of this part, thereby reducing transmission loss.

[0112] In some embodiments, the ratio of the second thickened segment 22 to the remainder of the first fine gate 20 may be 1.5:1 to 3:1.

[0113] Thus, by optimizing the ratio of the second thickened section 22 to the rest of the first fine grid 20, the width of the second thickened section 22 is avoided from being too small to effectively reduce transmission loss, and the second thickened section 22 is also avoided from being too wide to result in excessively high slurry costs.

[0114] Specifically, the ratio of the second thickened segment 22 to the rest of the first fine grid 20 can be, for example, 1.5:1, 1.6:1, 1.7:1, 1.8:1, 1.9:1, 2:1, 2.1:1, 2.2:1, 2.3:1, 2.4:1, 2.5:1, 2.6:1, 2.7:1, 2.8:1, 2.9:1, 3:1, or other values ​​between 1.5:1 and 3:1, without any specific limitation here.

[0115] In some embodiments, the distance between the second pad 50 and the second edge 102 may be 1mm-8mm; and / or the number of first fine gates 20 between the second pad 50 and the second edge 102 may be 5-12.

[0116] This ensures a sufficient safety distance between the second pad 50 and the second edge 102, effectively reducing the risk of microcracks and spalling at the edge when the second pad 50 is soldered to the first solder strip 210.

[0117] The distance between the second pad 50 and the second edge 102 can be, for example, 1mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, or other values ​​between 1mm and 8mm. In this application, the distance is preferably 4mm-6mm. The number of first fine gates 20 between the second pad 50 and the second edge 102 can be, for example, 5, 6, 7, 8, 9, 10, 11, and 12, preferably 5-10.

[0118] In some embodiments, the ratio between the length of the second connection gate line 60 in the first direction and the length of the silicon substrate 10 in the first direction is 1:10-1:6.

[0119] Thus, by optimizing the ratio range of the length of the second connection gate line 60 to the length of the silicon substrate 10, the amount of paste used for the second connection gate line 60 can be reduced, thereby lowering the cost.

[0120] Specifically, the ratio can be, for example, 1:10, 1:9.5, 1:9, 1:8.5, 1:8, 1:7.5, 1:7, 1:6.5, 1:6, or other values ​​between 1.10 and 1:6.

[0121] Please see Figure 7 In some embodiments, the first connecting grid line 40 may include a plurality of first connecting segments 41, which are arranged at intervals along the second direction. Each first connecting segment 41 is connected to at least two first fine grids 20, and two adjacent first connecting segments 41 are connected through the first fine grids 20.

[0122] Thus, by designing the first connecting grid line 40 in a segmented and spaced manner, stress concentration can be further reduced.

[0123] Specifically, such as Figure 7 As shown, in Figure 7In the illustrated embodiment, multiple first connection segments 41 are all located on the same side of the first pad 30. The extension lines of all first connection segments 41 do not intersect with the first pad 30, and adjacent first connection segments 41 are directly connected through the first fine gate 20. That is, all first connection segments 41 are suspended outside the first pad 30. It is understood that in some possible embodiments, among the multiple first connection segments 41, some first connection segments 41 may be located on one side of the first pad 30, and other first connection segments 41 may be located on the other side of the first pad 30. This is not limited here. Of course, it is also understood that in some possible embodiments, the first connection segment 41 closest to the first pad 30 may also be in direct contact with the first pad 30 to form a cross connection between the two. This is not limited here.

[0124] In addition, such as Figure 7 As shown, in this embodiment, multiple first connection segments 41 are arranged along a first direction. In this first direction, the multiple first connection segments 41 are connected end-to-end by a first fine gate 20. Adjacent first connection segments 41 do not overlap in the second direction; they are connected only by a single first fine gate 20. Specifically, in two adjacent first connection segments 41, the tail end of the preceding first connection segment 41 and the head end of the following first connection segment 41 are connected by the same first fine gate 20. It should be noted that the head end of the first connection segment 41 referred to herein is the end of the first connection segment 41 facing the first pad 30, and the tail end of the first connection segment 41 is the end of the first connection segment 41 facing away from the first pad 30. This avoids the formation of isolated gate segments in the second fine gate 70 between adjacent first connection segments 41, which could lead to efficiency losses.

[0125] Furthermore, in such an embodiment, the width of the portion of the first fine gate 20 connecting two adjacent first connection segments 41 is greater than the width of the remaining portion of the first fine gate 20. That is, the portion of the first fine gate 20 located between adjacent first connection segments 41 is wider. In this way, transmission loss can be effectively reduced.

[0126] In some embodiments, among the plurality of first connection segments 41, the spacing between two adjacent first connection segments 41 in the second direction may be 0.5mm-6mm. Optionally, the spacing between the first connection segment 41 farthest from the first pad 30 in the second direction and the first pad 30 in the second direction may be 1mm-12mm.

[0127] This can shorten the convergence transmission path and avoid excessive transmission loss due to an excessively long transmission path.

[0128] Specifically, in such an embodiment, the spacing between two adjacent first connection segments 41 in the second direction can be, for example, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.5mm, 6mm, or other values ​​between 0.5mm and 6mm. The spacing between the first connection segment 41 furthest from the first pad 30 in the second direction and the first pad 30 in the second direction can be, for example, 1mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, 9mm, 10mm, 11mm, 12mm, or other values ​​between 1mm and 12mm.

[0129] like Figure 7 As shown, the number of first connecting segments 41 can be 3. Of course, the number of first connecting segments 41 can also be 2 or 4 or even more, preferably no more than 4.

[0130] In some embodiments, the second connecting grid line 60 may include a plurality of second connecting segments 61, which are arranged at intervals along a second direction. Each second connecting segment 61 is connected to at least two first fine grids 20, and two adjacent second connecting segments 61 are connected through the first fine grids 20.

[0131] Thus, by designing the second connecting grid line 60 in a segmented and spaced manner, stress concentration can be further reduced.

[0132] Specifically, such as Figure 7 As shown, in Figure 7 In the illustrated embodiment, multiple second connection segments 61 are all located on the same side of the second pad 50. The extension lines of all second connection segments 61 do not intersect with the second pad 50, and adjacent second connection segments 61 are directly connected through the first fine gate 20. That is, all second connection segments 61 are suspended outside the second pad 50. It is understood that in some possible embodiments, some of the multiple second connection segments 61 may be located on one side of the second pad 50, while others may be located on the other side; this is not a limitation. Of course, it is also understood that in some possible embodiments, the second connection segment 61 closest to the second pad 50 may also be in direct contact with the second pad 50 to form a cross connection; this is not a limitation either.

[0133] In addition, such as Figure 7In this embodiment, multiple second connection segments 61 are arranged along a first direction. In this first direction, the multiple second connection segments 61 are connected end-to-end by a first fine gate 20. Adjacent second connection segments 61 do not overlap in the second direction; they are connected only by a single first fine gate 20. Specifically, in two adjacent second connection segments 61, the tail end of the preceding second connection segment 61 and the head end of the following second connection segment 61 are connected by the same first fine gate 20. It should be noted that the head end of the second connection segment 61 referred to herein is the end of the second connection segment 61 facing the second pad 50, and the tail end of the second connection segment 61 is the end of the second connection segment 61 facing away from the second pad 50. This avoids the formation of isolated gate line segments between adjacent second connection segments 61, which would lead to efficiency losses.

[0134] Furthermore, in such an embodiment, the width of the portion of the first fine gate 20 connecting two adjacent second connecting segments 61 is greater than the width of the remaining portion of the first fine gate 20. That is, the portion of the first fine gate 20 located between adjacent second connecting segments 61 is wider. In this way, transmission loss can be effectively reduced.

[0135] In some embodiments, among the plurality of second connection segments 61, the spacing between two adjacent second connection segments 61 in the second direction can be 0.5mm-6mm. The spacing between the second connection segment 61 farthest from the second pad 50 in the second direction and the second pad 50 in the second direction can be 1mm-12mm.

[0136] This can shorten the convergence transmission path and avoid excessive transmission loss due to an excessively long transmission path.

[0137] Specifically, in such an embodiment, the spacing between two adjacent second connection segments 61 in the second direction can be, for example, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.5mm, 6mm, or other values ​​between 0.5mm and 6mm. The spacing between the second connection segment 61 furthest from the second pad 50 in the second direction and the second pad 50 in the second direction can be, for example, 1mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, 9mm, 10mm, 11mm, 12mm, or other values ​​between 1mm and 12mm.

[0138] like Figure 7 As shown, the number of second connecting segments 61 can be 3. Of course, the number of second connecting segments 61 can also be 2, 4 or even more, preferably no more than 4.

[0139] like Figures 4-8As shown, in some embodiments, the first connection gate line 40 and the third connection gate line 90 are both located on the same side of the first pad 30 and the third pad 80.

[0140] Of course, in some embodiments, the first connecting gate line 40 and the third connecting gate line 90 may also be located on different sides of the first pad 30 and the third pad 80. For example, the first connecting gate line 40 may be located on the right side of the first pad 30, and the third connecting gate line 90 may be located on the left side of the third pad 80. In this way, the positions of solder ribbons of different polarities can be distinguished by identifying the positions of the first connecting gate line 40 and the third connecting gate line 90, which facilitates the precise placement of the solder ribbons.

[0141] At the same time, Figures 4-8 As shown, in some embodiments, the first connection gate line 40 and the second connection gate line 60 are also located on the same side of the first pad 30 and the second pad 50. It is understood that in other embodiments, the first connection gate line 40 and the second connection gate line 60 may also be located on different sides of the first pad 30 and the second pad 50, for example, the first connection gate line 40 may be located on the right side of the first pad 30, and the second connection gate line 60 may be located on the left side of the second pad 50. Similarly, in some embodiments, the second connection gate line 60 and the fourth connection gate line 120 are also located on the same side of the second pad 50 and the fourth pad 110. It is understood that in other embodiments, the second connection gate line 60 and the fourth connection gate line 120 may also be located on different sides of the second pad 50 and the fourth pad 110, for example, the second connection gate line 60 may be located on the right side of the second pad 50, and the fourth connection gate line 120 may be located on the left side of the fourth pad 110.

[0142] Please see Figure 4 In some embodiments, the third connection gate line 90 may be in direct contact with the third pad 80. This direct contact between the third connection gate line 90 and the third pad 80 effectively reduces transmission bus losses.

[0143] Specifically, such as Figure 4 As shown, in such an embodiment, the third connecting gate line 90 is cross-connected with the third pad 80 and is located above the third pad 80. During the manufacturing process, the third connecting gate line 90 and the third pad 80 can be integrally printed.

[0144] In this embodiment, the third connecting gate line 90 can be directly connected to the third pad 80. The center line S3 of the third connecting gate line 90 and the third pad 80 are spaced apart in the second direction, and the distance between them is 0.5mm-1.5mm. In this way, it can effectively avoid the stress concentration caused by the overlap between the solder strip and the first connecting gate line 40 due to misalignment during the lamination and soldering of the solder strip.

[0145] In some embodiments, the third connection gate line 90 may also be spaced apart from the third pad 80 in the second direction, and the third connection gate line 90, the first connection gate line 40, and at least one second fine gate 70 connected to the third pad 80 are electrically connected.

[0146] Thus, the third connecting gate line 90 is spaced apart from the third pad 80 and is electrically connected through the second fine gate 70 connected to the third pad 80. This allows the third connecting gate line 90 and the third pad 80 to have sufficient distance, thereby further reducing stress concentration.

[0147] Specifically, in such an embodiment, the third connecting gate line 90 does not directly contact the third pad 80, but is suspended on one side of the third pad 80 and is electrically connected to the third pad 80 through the second fine gate 70.

[0148] like Figure 6 As shown, in such an embodiment, the third connecting gate line 90 may be connected only to the second fine gate 70 on the third pad 80 that is closest to the first edge 101, thereby avoiding the first fine gate 20 from having isolated gate line segments between the third pad 80 and the third connecting gate line 90, which would lead to efficiency loss.

[0149] In some embodiments, the spacing between the third connecting gate line 90 and the third pad 80 in the second direction is less than or equal to 6 mm.

[0150] This avoids excessive transmission loss caused by the distance between the third connecting gate line 90 and the third pad 80 being too far.

[0151] Specifically, the spacing between the third connecting gate line 90 and the third pad 80 in the second direction can be, for example, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.5mm, 6mm or other values ​​between 0 and 6mm, without any specific limitation here.

[0152] Please see Figure 6 In some embodiments, in the second fine gate 70 connected to the third pad 80, the second fine gate 70 connected to the third connecting gate line 90 includes a third thickened segment 71 located between the third pad 80 and the third connecting gate line 90, the width of the third thickened segment 71 being greater than the width of the rest of the second fine gate 70.

[0153] Thus, the third thickened section 71 is used to transmit the current of the third connecting gate line 90 to the third pad 80 and the second solder strip 220. Setting the width of the third thickened section 71 to be wider can reduce the transmission resistance of this part, thereby reducing transmission loss.

[0154] In some embodiments, the ratio of the third thickened segment 71 to the remainder of the second fine gate 70 may be 1.5:1 to 3:1.

[0155] Thus, by optimizing the ratio of the third thickened section 71 to the rest of the second fine grid 70, the width of the third thickened section 71 is avoided from being too small to effectively reduce transmission loss, and the required slurry cost is also avoided from being too high due to the third thickened section 71 being too wide.

[0156] Specifically, the ratio of the third thickened segment 71 to the rest of the second fine grid 70 can be, for example, 1.5:1, 1.6:1, 1.7:1, 1.8:1, 1.9:1, 2:1, 2.1:1, 2.2:1, 2.3:1, 2.4:1, 2.5:1, 2.6:1, 2.7:1, 2.8:1, 2.9:1, 3:1, or other values ​​between 1.5:1 and 3:1, without any specific limitation here.

[0157] In some embodiments, the distance between the third pad 80 and the second edge 102 may be 1mm-8mm; and / or the number of second fine gates 70 between the third pad 80 and the second edge 102 may be 5-12.

[0158] This ensures a sufficient safety distance between the third pad 80 and the second edge 102, effectively reducing the risk of microcracks and spalling at the edge when the third pad 80 is soldered to the second solder strip 220.

[0159] The distance between the third pad 80 and the second edge 102 can be, for example, 1mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, or other values ​​between 1mm and 8mm. In this application, the distance is preferably 4mm-6mm. The number of second fine gates 70 between the third pad 80 and the second edge 102 can be, for example, 5, 6, 7, 8, 9, 10, 11, and 12, preferably 5-10.

[0160] In some embodiments, the ratio between the length of the third connection gate line 90 in the first direction and the length of the silicon substrate 10 in the first direction is 1:10-1:6.

[0161] Thus, by optimizing the ratio range of the length of the third connection gate line 90 to the length of the silicon substrate 10, the amount of paste used for the third connection gate line 90 can be reduced, thereby lowering the cost.

[0162] Specifically, the ratio can be, for example, 1:10, 1:9.5, 1:9, 1:8.5, 1:8, 1:7.5, 1:7, 1:6.5, 1:6, or other values ​​between 1.10 and 1:6.

[0163] Please see Figure 4 In some embodiments, the fourth connection gate line 120 may be in direct contact with the fourth pad 110. This direct contact between the fourth connection gate line 120 and the fourth pad 110 can effectively reduce transmission bus losses.

[0164] Specifically, such as Figure 4 As shown, in such an embodiment, the fourth connecting gate line 120 is cross-connected to the second pad 50 and located above the fourth pad 110. During the manufacturing process, the fourth connecting gate line 120 and the fourth pad 110 can be integrally printed.

[0165] In this embodiment, the fourth connecting gate line 120 can be directly connected to the fourth pad 110. The center line S4 of the fourth connecting gate line 120 and the fourth pad 110 are spaced apart in the second direction, and the distance between them is 0.5mm-1.5mm. In this way, it can effectively avoid the stress concentration caused by the overlap between the solder strip and the second connecting gate line 60 due to misalignment during the lamination and soldering of the solder strip.

[0166] Of course, please see Figure 6 In some embodiments, the fourth connection gate line 120 is spaced apart from the fourth pad 110 in a second direction and is electrically connected to at least one second fine gate 70 connected to the fourth pad 110.

[0167] Thus, the fourth connecting gate line 120 is spaced apart from the fourth pad 110 and is electrically connected through the second fine gate 70 connected to the fourth pad 110. This allows the fourth connecting gate line 120 and the fourth pad 110 to have sufficient distance, thereby further reducing stress concentration.

[0168] Specifically, in such an embodiment, the fourth connecting gate line 120 does not directly contact the fourth pad 110, but is suspended on one side of the fourth pad 110 and is electrically connected to the fourth pad 110 through the second fine gate 70.

[0169] like Figure 6 As shown, in such an embodiment, the fourth connecting gate line 120 may be connected only to the second fine gate 70 on the fourth pad 110 that is closest to the second edge 102, thereby avoiding the first fine gate 20 from having isolated gate line segments between the fourth pad 110 and the fourth connecting gate line 120, which would result in efficiency loss.

[0170] In some embodiments, the spacing between the fourth connecting gate line 120 and the fourth pad 110 in the second direction is less than or equal to 6 mm.

[0171] In this way, excessive transmission loss can be avoided due to the distance between the fourth connecting gate line 120 and the fourth pad 110 being too far.

[0172] Specifically, the spacing between the fourth connecting gate line 120 and the fourth pad 110 in the second direction can be, for example, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.5mm, 6mm or other values ​​between 0 and 6mm, without any specific limitation.

[0173] In some embodiments, in the second fine gate 70 connected to the fourth pad 110, the second fine gate 70 connected to the fourth connecting gate line 120 includes a fourth thickened segment 72 located between the fourth pad 110 and the fourth connecting gate line 120, the width of the fourth thickened segment 72 being greater than the width of the rest of the second fine gate 70.

[0174] Thus, the fourth thickened segment 72 is used to transmit the current from the fourth connecting gate line 120 to the fourth pad 110 and the second solder strip 220. Setting the width of the fourth thickened segment 72 to be wider can reduce the transmission resistance of this part, thereby reducing transmission loss.

[0175] In some embodiments, the ratio of the fourth thickened segment 72 to the remainder of the second fine gate 70 can be 1.5:1 to 3:1.

[0176] Thus, by optimizing the ratio of the fourth thickened section 72 to the rest of the second fine grid 70, the width of the fourth thickened section 72 is avoided from being too small to effectively reduce transmission loss, and the fourth thickened section 72 is also avoided from being too wide, which would result in excessively high slurry costs.

[0177] Specifically, the ratio of the fourth thickened segment 72 to the rest of the second fine grid 70 can be, for example, 1.5:1, 1.6:1, 1.7:1, 1.8:1, 1.9:1, 2:1, 2.1:1, 2.2:1, 2.3:1, 2.4:1, 2.5:1, 2.6:1, 2.7:1, 2.8:1, 2.9:1, 3:1, or other values ​​between 1.5:1 and 3:1, without any specific limitation here.

[0178] In some embodiments, the distance between the fourth pad 110 and the second edge 102 may be 1mm-8mm; and / or the number of second fine gates 70 between the fourth pad 110 and the second edge 102 may be 5-12.

[0179] This ensures a sufficient safety distance between the fourth pad 110 and the second edge 102, effectively reducing the risk of microcracks and spalling at the edge when the fourth pad 110 is soldered to the second solder strip 220.

[0180] The distance between the fourth pad 110 and the second edge 102 can be, for example, 1mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, or other values ​​between 1mm and 8mm. In this application, the distance is preferably 4mm-6mm. The number of second fine gates 70 between the fourth pad 110 and the second edge 102 can be, for example, 5, 6, 7, 8, 9, 10, 11, and 12, preferably 5-10.

[0181] In some embodiments, the ratio between the length of the fourth connection gate line 120 in the first direction and the length of the silicon substrate 10 in the first direction is 1:10-1:6.

[0182] Thus, by optimizing the ratio range of the length of the fourth connection gate line 120 to the length of the silicon substrate 10, the amount of paste used for the fourth connection gate line 120 can be reduced, thereby lowering the cost.

[0183] Specifically, the ratio can be, for example, 1:10, 1:9.5, 1:9, 1:8.5, 1:8, 1:7.5, 1:7, 1:6.5, 1:6, or other values ​​between 1.10 and 1:6.

[0184] Please see Figure 7 In some embodiments, the third connecting grid line 90 may include a plurality of third connecting segments 91, which are arranged at intervals along the second direction. Each third connecting segment 91 is connected to at least two second fine grids 70, and two adjacent third connecting segments 91 are connected through the second fine grids 70.

[0185] Thus, by designing the third connecting grid line 90 in segments, stress concentration can be further reduced.

[0186] Specifically, such as Figure 7 As shown, in Figure 7 In the illustrated embodiment, multiple third connection segments 91 are all located on the same side of the third pad 80. The extension lines of all third connection segments 91 do not intersect with the third pad 80, and adjacent third connection segments 91 are directly connected through the second fine gate 70. That is, all third connection segments 91 are suspended outside the third pad 80. It is understood that in some possible embodiments, some of the multiple third connection segments 91 may be located on one side of the third pad 80, while others may be located on the other side; this is not a limitation. Of course, it is also understood that in some possible embodiments, the third connection segment 91 closest to the third pad 80 may also be in direct contact with the third pad 80 to form a cross connection; this is not a limitation either.

[0187] In addition, such as Figure 7In this embodiment, multiple third connection segments 91 are arranged along a first direction. In this first direction, the multiple third connection segments 91 are connected end-to-end by a second fine grid 70. Adjacent third connection segments 91 do not overlap in the second direction; they are connected only by a single second fine grid 70. Specifically, in two adjacent third connection segments 91, the tail end of the preceding third connection segment 91 and the head end of the following third connection segment 91 are connected by the same second fine grid 70. It should be noted that the head end of the third connection segment 91 referred to herein is the end of the third connection segment 91 facing the third pad 80, and the tail end of the third connection segment 91 is the end of the third connection segment 91 facing away from the third pad 80. Thus, when the back contact battery 100 is a back contact battery, the isolated grid line segments of the first fine grid 20 between two adjacent third connection segments 91, which would lead to efficiency loss, can be avoided.

[0188] Furthermore, in such an embodiment, the width of the portion of the second fine gate 70 connecting two adjacent third connecting segments 91 is greater than the width of the remaining portion of the second fine gate 70. That is, the portion of the second fine gate 70 located between adjacent third connecting segments 91 is wider. In this way, transmission loss can be effectively reduced.

[0189] In some embodiments, among the plurality of third connection segments 91, the spacing between two adjacent third connection segments 91 in the second direction can be 0.5mm-6mm. Optionally, the spacing between the third connection segment 91 farthest from the third pad 80 in the second direction and the third pad 80 in the second direction can be 1mm-12mm.

[0190] This can shorten the convergence transmission path and avoid excessive transmission loss due to an excessively long transmission path.

[0191] Specifically, in such an embodiment, the spacing between two adjacent third connection segments 91 in the second direction can be, for example, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.5mm, 6mm, or other values ​​between 0.5mm and 6mm. The spacing between the third connection segment 91 furthest from the third pad 80 in the second direction and the third pad 80 can be, for example, 1mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, 9mm, 10mm, 11mm, 12mm, or other values ​​between 1mm and 12mm.

[0192] like Figure 7 As shown, the number of third connecting segments 91 can be 3. Of course, the number of third connecting segments 91 can also be 2, 4 or even more, preferably no more than 4.

[0193] Please see Figure 7In some embodiments, the fourth connecting grid line 120 may include a plurality of fourth connecting segments 121, which are arranged at intervals along the second direction. Each fourth connecting segment 121 is connected to at least two second fine grids 70, and two adjacent fourth connecting segments 121 are connected through the second fine grids 70.

[0194] Thus, by designing the fourth connecting grid line 120 in a segmented and spaced manner, stress concentration can be further reduced.

[0195] Specifically, such as Figure 7 As shown, in Figure 7 In the illustrated embodiment, multiple fourth connection segments 121 are all located on the same side of the fourth pad 110. The extension lines of all fourth connection segments 121 do not intersect with the fourth pad 110, and adjacent fourth connection segments 121 are directly connected through the second fine gate 70. That is, all fourth connection segments 121 are suspended outside the fourth pad 110. It is understood that in some possible embodiments, among the multiple fourth connection segments 121, some may be located on one side of the fourth pad 110, while others may be located on the other side; this is not a limitation. Of course, it is also understood that in some possible embodiments, the fourth connection segment 121 closest to the fourth pad 110 may also be in direct contact with the fourth pad 110 to form a cross connection; this is not a limitation.

[0196] In addition, such as Figure 7 In this embodiment, multiple fourth connection segments 121 are arranged along a first direction. In this first direction, the multiple fourth connection segments 121 are connected end-to-end by a second fine gate 70. Adjacent fourth connection segments 121 do not overlap in the second direction; they are connected only by a single second fine gate 70. Specifically, in two adjacent fourth connection segments 121, the tail end of the preceding fourth connection segment 121 and the head end of the following fourth connection segment 121 are connected by the same second fine gate 70. It should be noted that, as discussed herein, the head end of the fourth connection segment 121 is the end facing the fourth pad 110, and the tail end is the end facing away from the fourth pad 110. This avoids the first fine gate 20 from having isolated gate segments between adjacent fourth connection segments 121, which would lead to efficiency loss.

[0197] Furthermore, in such an embodiment, the width of the portion of the second fine gate 70 connecting two adjacent fourth connection segments 121 is greater than the width of the remaining portion of the second fine gate 70. That is, the portion of the second fine gate 70 located between adjacent fourth connection segments 121 is wider. In this way, transmission loss can be effectively reduced.

[0198] In some embodiments, among the plurality of fourth connection segments 121, the spacing between two adjacent fourth connection segments 121 in the second direction can be 0.5mm-6mm. The spacing between the fourth connection segment 121 farthest from the fourth pad 110 in the second direction and the fourth pad 110 in the second direction can be 1mm-12mm.

[0199] This can shorten the convergence transmission path and avoid excessive transmission loss due to an excessively long transmission path.

[0200] Specifically, in such an embodiment, the spacing between two adjacent fourth connection segments 121 in the second direction can be, for example, 0.5mm, 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, 5.5mm, 6mm, or other values ​​between 0.5mm and 6mm. The spacing between the fourth connection segment 121 furthest from the fourth pad 110 in the second direction and the fourth pad 110 can be, for example, 1mm, 2mm, 3mm, 4mm, 5mm, 6mm, 7mm, 8mm, 9mm, 10mm, 11mm, 12mm, or other values ​​between 1mm and 12mm.

[0201] like Figure 7 As shown, the number of fourth connecting segments 121 can be 3. Of course, the number of fourth connecting segments 121 can also be 2, 4 or even more, preferably no more than 4.

[0202] Please see Figure 8 In some embodiments, among all the first fine gates 20 and all the second fine gates 70, the fine gate closest to the first edge 101 is the first edge fine gate 107, the fine gate closest to the second edge 102 is the second edge fine gate 108, and the fine gate located between the first edge fine gate 107 and the second edge fine gate 108 is the middle fine gate 109. The width of the first edge fine gate 107 is greater than the width of the middle fine gate 109, and the width of the second edge fine gate 108 is also greater than the width of the middle fine gate 109. That is to say, among the first fine gates 20 and the second fine gates 70, the widths of the fine gates closest to the first edge 101 and the fine gates closest to the second edge 102 are both greater than the widths of the remaining fine gates.

[0203] Specifically, during the cleaning process, the outermost fine grid is prone to over-washing, resulting in its width becoming too narrow. Therefore, setting the width of the two outermost fine grids to be wider can prevent over-washing during the cleaning process, thus ensuring the collection capacity and efficiency of the outermost fine grid.

[0204] like Figure 4 and Figure 8As shown, in some embodiments, both the first edge fine grid 107 and the second edge fine grid 108 can be second fine grids 70. That is, in some embodiments, in the first direction, the second fine grids 70 and the first fine grids 20 are arranged alternately from the beginning to the end, and the fine grids at the beginning and end are both second fine grids 70. In this case, the width of the second fine grids 70 located at the beginning and end is greater than the width of the remaining second fine grids 70 and the first fine grids 20.

[0205] Of course, in some possible embodiments, both the first edge fine gate 107 and the second edge fine gate 108 can be the first fine gate 20, and no specific limitation is made here. In addition, in some embodiments, the first edge fine gate 107 can be of the type of the second fine gate 70, and the second edge fine gate 108 can be of the type of the first fine gate 20, or the first edge fine gate 107 can be of the type of the first fine gate 20, and the second edge fine gate 108 can be of the type of the second fine gate 70, and no specific limitation is made here.

[0206] Specifically, in such embodiments, the width of both the first edge fine gate 107 and the second edge fine gate 108 can be 200μm-220μm, such as any value between 200μm, 202μm, 204μm, 206μm, 208μm, 210μm, 212μm, 214μm, 216μm, 218μm, 220μm or 200μm-220μm, and no specific limitation is made here.

[0207] The width of the intermediate fine gate 109 (i.e., the first fine gate 20 and the second fine gate 70 outside the first edge fine gate 107 and the second edge fine gate 108) can be 150μm-170μm, for example, any value between 150μm, 152μm, 154μm, 156μm, 158μm, 160μm, 162μm, 164μm, 166μm, 168μm, 170μm or 150μm-170μm, and is not limited here.

[0208] In some embodiments, the width of the first connecting gate line 40 may be greater than the width of the first fine gate 20 and the second fine gate 70, and the width of the third connecting gate line 90 may be greater than the width of the first fine gate 20 and the second fine gate 70.

[0209] Therefore, by setting the widths of the first connecting gate line 40 and the third connecting gate line 90 to be relatively large, the bus transmission loss can be reduced.

[0210] Specifically, the first connecting gate line 40 is used to collect the current gathered by all the first fine gates 20 located between the first pad 30 and the first edge 101. Therefore, making the first connecting gate line 40 wider can reduce the transmission resistance, thereby reducing the bus transmission loss. Similarly, the third connecting gate line 90 is used to collect the current gathered by all the second fine gates 70 located between the third pad 80 and the first edge 101. Therefore, making the third connecting gate line 90 wider can reduce the transmission resistance, thereby reducing the bus transmission loss.

[0211] In some embodiments, the width of the second connecting gate line 60 may be greater than the width of the first fine gate 20 and the second fine gate 70, and the width of the fourth connecting gate line 120 may be greater than the width of the first fine gate 20 and the second fine gate 70.

[0212] Therefore, by setting the widths of the second connecting gate line 60 and the fourth connecting gate line 120 to be larger, the bus transmission loss can be reduced.

[0213] Specifically, the second connecting gate line 60 is used to collect the current gathered by all the first fine gates 20 located between the second pad 50 and the second edge 102. Therefore, making the second connecting gate line 60 wider can reduce the transmission resistance, thereby reducing the bus transmission loss. Similarly, the fourth connecting gate line 120 is used to collect the current gathered by all the second fine gates 70 located between the fourth pad 110 and the first edge 102. Therefore, making the fourth connecting gate line 120 wider can reduce the transmission resistance, thereby reducing the bus transmission loss.

[0214] In this embodiment, the widths of the first fine gate 20 and the second fine gate 70 are as described above and will not be repeated here. The widths of the first connecting gate line 40, the second connecting gate line 60, the third connecting gate line 90, and the fourth connecting gate line 120 can be 240μm-260μm, for example, any value between 240μm, 242μm, 244μm, 246μm, 248μm, 250μm, 252μm, 254μm, 256μm, 258μm, 260μm, or 240μm-260μm, and are not specifically limited here.

[0215] Please see Figure 4 and Figure 8 As shown, in some embodiments, the silicon substrate 10 has opposing third edges 103 and fourth edges 104 in a second direction. Among the first pad 30 and the third pad 80, the pad closest to the third edge 103 is the first pad 30, and the pad closest to the fourth edge 104 is the second pad 80.

[0216] The back contact battery 100 may further include a first busbar 130 and a second busbar 140, wherein the first busbar 130 is disposed near the third edge 103 and located between the first pad 30 closest to the third edge 103 and the third edge 103. Figure 4 and Figure 8 As shown, the first bus gate line 130 is connected to at least the second fine gate 70 located between the first pad 30 closest to the third edge 103 and the third edge 103.

[0217] like Figure 4 As shown, in some embodiments, the first busbar 130 may be connected to all the second fine gates 70. Of course, as... Figure 8 As shown, in some embodiments, the first edge gate 107 is of the type of second gate 70. In such cases, the first bus gate 130 may also be electrically connected at least to the ends of all the second gates 70 in the intermediate gate 109 toward the third edge 103, without being connected to the first edge gate 107.

[0218] like Figure 4 and Figure 8 As shown, the second bus gate line 140 is disposed near the fourth edge 104 and located between the third pad 80 closest to the fourth edge 104 and the fourth edge 104. The second bus gate line 140 is electrically connected to at least the ends of all the first fine gates 20 of the intermediate fine gate 109 facing the fourth edge 104.

[0219] Specifically, such as Figure 8 As shown, in some embodiments, in the back contact battery 100, when the fine grid closest to the first edge 101 (i.e., the first edge fine grid 107) and the fine grid closest to the second edge 102 (i.e., the second edge fine grid 108) are both second fine grids 70, the first busbar 130 can connect all the second fine grids 70 except the first edge fine grid 107 (including the middle fine grid 109 and the second edge fine grid 108) to electrical connection, and the second busbar 140 can connect all the first fine grids 20.

[0220] Of course, such as Figure 4 As shown, in some possible embodiments, the first bus gate line 130 may also be electrically connected to the ends of all the second fine gates 70 toward the third edge 103, and the second bus gate line 140 may be electrically connected to the ends of all the first fine gates 20 toward the fourth edge 104, without limitation here.

[0221] Thus, by setting the first busbar 130, all the second fine gates 70 in all the intermediate fine gates 109 can be electrically connected to form a whole, which optimizes the overall current transmission path and effectively reduces transmission loss. Furthermore, during manufacturing, even if some second fine gates 70 do not form a stable connection with the second solder strip 220, current can still be transmitted through the first busbar 130. Similarly, by setting the second busbar 140, all the first fine gates 20 in all the intermediate fine gates 109 can be electrically connected to form a whole, which optimizes the overall current transmission path and effectively reduces transmission loss. Furthermore, during manufacturing, even if some first fine gates 20 do not form a stable connection with the first solder strip 210, current can still be transmitted through the second busbar 140.

[0222] Furthermore, by setting the first bus gate line 130, the isolated gate line segment of the second fine gate 70 located between the third edge 103 and the first pad 30 and the first connecting gate line 40 can be completely collected. At the same time, the isolated gate line segment of the second fine gate 70 located between the third edge 103 and the second pad 50 and the second connecting gate line 60 can be completely collected, thus avoiding efficiency loss.

[0223] That is, in some embodiments, the first bus gate line 130 may at least connect to a second fine gate 70 located between the first pad 30 and the first connecting gate line 40 and the third edge 103, and disconnected at the first connecting gate line 40 and the first pad 30; it may also at least connect to a second fine gate 70 located between the second pad 50 and the second connecting gate line 60 and the third edge 103, and disconnected at the second connecting gate line 60 and the second pad 50; and it may also connect to at least one second fine gate 70 located between the first pad 30 and the second pad 50. Figure 4 and Figure 8 What is shown is the second fine gate 70 connecting all the first pads 30 and the second pads 50.

[0224] By configuring the second bus gate 140, the isolated gate segments of the first fine gate 20 located between the fourth edge 104, the third pad 80, and the third connecting gate 90 can be completely collected. Simultaneously, the isolated gate segments of the first fine gate 20 located between the fourth edge 104, the fourth pad 110, and the fourth connecting gate 120 can also be completely collected, avoiding efficiency loss. That is, in the embodiments of this application, the second bus gate 140 at least connects the first fine gate 20 located between the third pad 80 and the third connecting gate 90 and the fourth edge 104, and also at least connects the first fine gate 20 located between the fourth pad 110 and the fourth connecting gate 120 and the fourth edge 104, which is disconnected at the fourth connecting gate 120 and the fourth pad 110, and also connects at least one first fine gate 20 located between the third pad 80 and the fourth pad 120. Figure 4 and Figure 8 What is shown is all the first fine gates 20 located between the third pad 80 and the fourth pad 120.

[0225] In some embodiments, the width of the first busbar 130 may be greater than the width of the second fine gate 70, and the width of the second busbar 140 may be greater than the width of the first fine gate 20.

[0226] In this way, by setting the width of the first bus gate 130 and the second bus gate 140 used for busing to be wider, the busing transmission loss can be effectively reduced.

[0227] In some possible embodiments, the width of the first busbar 130 may be greater than the width of the intermediate fine gate 109 and less than the width of the first edge fine gate 107 and the second edge fine gate 108; and / or, the width of the second busbar 140 may be greater than the width of the intermediate fine gate 109 and less than the width of the first edge fine gate 107 and the second edge fine gate 108.

[0228] In this way, the problem of edge overwashing can be solved while effectively reducing the loss of bus transmission.

[0229] Specifically, in some embodiments, the width of the intermediate fine gate 109 is as described above and will not be repeated here. The width of the first bus gate line 130 and the second bus gate line 140 can be 190μm-210μm, for example, any value between 190μm, 192μm, 194μm, 196μm, 198μm, 200μm, 202μm, 204μm, 206μm, 208μm, 210μm or 190μm-210μm, and is not limited here.

[0230] In some embodiments, the width of the first bus gate 130 is smaller than the width of the first connecting gate 40, and the width of the second bus gate 140 is smaller.

[0231] Thus, by setting the widths of the first busbar 130 and the second busbar 140 to be smaller, the cost of the slurry can be reduced while minimizing busbar transmission losses.

[0232] Specifically, the first connecting gate line 40 needs to collect the current on the gate line segments on both sides of the first connecting gate line 40, and the third connecting gate line 90 needs to collect the current on the gate line segments on both sides of the third connecting gate line 90. The main function of the first bus gate line 130 is to collect the current on the isolated gate line segments of the second gate line 70 located at the first pad 30 closest to the third edge 103 and between the first connecting gate line 40 and the third edge 103. That is, the first bus gate line 130 only needs to collect the current on one side of the gate line segment of the first connecting gate line 40. Similarly, the main function of the second bus gate line 140 is to collect the current on the isolated gate line segments of the first gate line 20 located at the third pad 80 closest to the fourth edge 104 and between the third connecting gate line 90 and the fourth edge 104. That is, the second bus gate line 140 only needs to collect the current on one side of the gate line segment of the third connecting gate line 90. Therefore, the current carrying capacity of the first busbar 130 and the second busbar 140 can be less than that of the first connecting busbar 40 and the third connecting busbar 90. Based on this, by setting the width of the first busbar 130 and the second busbar 140 to be smaller, the cost of the slurry can be reduced. At the same time, setting the width of the first busbar 130 and the second busbar 140 to be narrower can reduce the risk of microcracks caused by stress concentration at the edge.

[0233] In such an embodiment, the widths of the first connecting gate line 40 and the third connecting gate line 90 are substantially the same, the width of the second connecting gate line 60 is substantially the same as the width of the first connecting gate line 40, and the width of the fourth connecting gate line 120 is substantially the same as the width of the third connecting gate line 90.

[0234] Specifically, the widths of the first bus gate 130 and the second bus gate 140 are as described above, and the widths of the first connecting gate 40 and the third connecting gate 90 are also as described above, and will not be repeated here.

[0235] It should be noted that in some embodiments, the widths of the first connecting gate line 40, the second connecting gate line 60, the third connecting gate line 90, and the fourth connecting gate line 120 can all be substantially the same.

[0236] In some embodiments, the ratio between the width of the first bus gate 130 and the width of the first connecting gate 40 is 0.6-0.9, such as 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9 or other values ​​between 0.6 and 0.9.

[0237] Thus, by optimizing the design of setting the width of the first busbar 130 to 0.6 to 0.9 times the width of the first connecting busbar 40, the slurry cost can be reduced as much as possible while ensuring that the current transmission loss of the first busbar 130 is not too large.

[0238] In some embodiments, the ratio between the width of the second bus gate 140 and the width of the third connecting gate 90 is 0.6-0.9, such as 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9 or other values ​​between 0.6 and 0.9.

[0239] Thus, by optimizing the design of setting the width of the second busbar 140 to 0.6 to 0.9 times the width of the third connecting busbar 90, the slurry cost can be reduced as much as possible while ensuring that the current transmission loss of the second busbar 140 is not too large.

[0240] Please see Figures 4-8 In some embodiments, the back surface 11 may also be provided with a plurality of first test sections 150 and a plurality of second test sections 160. The plurality of first test sections 150 are disposed near the third edge 103 and arranged at intervals along the first direction. The first test sections 150 are connected to a portion of the second fine gate 70 and are all electrically connected to the first bus gate line 130. The first test sections 150 are insulated from the second fine gate 70. The plurality of second test sections 160 are disposed near the fourth edge 104 and arranged at intervals along the first direction. The second test sections 160 are connected to a portion of the first fine gate 20 and are all electrically connected to the second bus gate line 140. The second test sections 160 are insulated from the first fine gate 20.

[0241] Thus, due to the presence of the first busbar 130, the second busbar 140, the first test section 150, and the second test section 160, when the back contact battery 100 is tested for electrical performance (e.g., IV test), PL test, and hot spot tests, the positive and negative electrode probes of the test device can form stable contact with the first test section 150 and the second test section 160 respectively, reducing the difficulty of testing and improving the reliability and stability of testing.

[0242] Taking IV testing as an example, when performing IV testing on the back contact battery 100 of this application, the positive electrode probe and the negative electrode probe of the testing device can form stable contact with the first testing section 150 and the second testing section 160 respectively, thereby obtaining the IV test data of the back contact battery 100.

[0243] Taking hot spot testing as an example, when conducting hot spot testing on the back contact battery 100 of this application, the positive electrode probe and negative electrode probe of the testing device can form stable contact with the first testing section 150 and the second testing section 160 respectively, and then simulate the scenario where the back contact battery 100 is blocked to observe the temperature at various points of the back contact battery 100.

[0244] Specifically, such as Figure 8 As shown, the first test section 150 is in direct contact with the first busbar 130, and the second test section 160 is in direct contact with the second busbar 140.

[0245] Please see Figure 8 In some embodiments, the area of ​​at least one first test section 150 is smaller than the area of ​​the first pad 30, and the area of ​​at least one second test section 160 is also smaller than the area of ​​the first pad 30.

[0246] Thus, setting the area of ​​the pads to be larger can ensure the welding area between the solder strips, thereby ensuring the stability and reliability of the welding. Setting the area of ​​the first test section 150 and the second test section 160 to be smaller can reduce the light-shielding area on the back side and improve the double-sided ratio while enabling the test section to form a stable contact with the probe of the test device. At the same time, when the test section contacts the doped layer below, metallization recombination can also be reduced.

[0247] It should be noted that the "area" here refers to the projected area of ​​each component in the thickness direction of the back contact battery 100.

[0248] In some embodiments, the area of ​​the first test section 150 may be smaller than the area of ​​the second pad 50 and the fourth pad 110, and the area of ​​the second test section 160 may also be smaller than the area of ​​the second pad 50 and the fourth pad 110.

[0249] In some embodiments, the area of ​​all first test sections 150 may be smaller than the area of ​​the first pad 30, and the area of ​​the second test sections 160 may also be smaller than the area of ​​the first pad 30.

[0250] In some embodiments, the first pad 30 and the third pad 80 have the same area, the second pad 50 has the same area as the first pad 30, and the fourth pad 110 has the same area as the third pad 80.

[0251] In some embodiments, the ratio between the area of ​​the first test section 150 and the area of ​​the first pad 30 may be 0.7-0.9, such as 0.7, 0.72, 0.74, 0.76, 0.78, 0.8, 0.82, 0.84, 0.86, 0.88, 0.9 or other values ​​between 0.7 and 0.9, and no specific limitation is made here.

[0252] Thus, by setting the area of ​​the first test section 150 to 0.7 to 0.9 times the area of ​​the first pad 30, the light-shielding area can be reduced as much as possible while ensuring the contact stability of the probe.

[0253] In some embodiments, the ratio between the area of ​​the second test section 160 and the area of ​​the first pad 30 may also be 0.7-0.9, such as 0.7, 0.72, 0.74, 0.76, 0.78, 0.8, 0.82, 0.84, 0.86, 0.88, 0.9 or other values ​​between 0.7 and 0.9, and no specific limitation is made here.

[0254] Thus, by setting the area of ​​the second test section 160 to 0.7 to 0.9 times the area of ​​the first pad 30, the light-shielding area can be reduced as much as possible while ensuring the contact stability of the probe.

[0255] Specifically, in such an embodiment, the area of ​​the first test section 150 may be substantially the same as the area of ​​the second test section 160.

[0256] In some embodiments, the first pad 30, the second pad 50, the third pad 80 and the fourth pad 110 are all rectangular, and the first test section 150 and the second test section 160 are also rectangular.

[0257] In some embodiments, the length of the first test section 150 in the first direction is greater than the length of the first pad 30 in the first direction, and the length of the first test section 150 in the second direction is less than the length of the first pad 30 in the second direction.

[0258] Thus, the first pad 30 is shorter in length and wider in width, which increases the length of the welding surface between the first pad 30 and the first solder strip 210 in the second direction, thereby improving the welding stability. The first test section 150 is longer in length and narrower in width, which allows the first test section 150 to connect multiple second fine gates 70 to form a stable test circuit, thereby improving the stability of electrical performance and other tests.

[0259] Similarly, in some embodiments, the length of the second test section 160 in the first direction is greater than the length of the first pad 30 in the first direction, and the length of the second test section 160 in the second direction is less than the length of the first pad 30 in the second direction.

[0260] Specifically, in such an embodiment, the first pad 30, the second pad 50, the third pad 80 and the fourth pad 110 can be substantially identical in shape and size, and the first test section 150 and the second test section 160 can also be substantially identical in shape and size.

[0261] In some embodiments, the lengths of the first pad 30, the second pad 50, the third pad 80, and the fourth pad 110 in the first direction can be 1.5mm-1.7mm, such as 1.5mm, 1.55mm, 1.6mm, 1.65mm, 1.7mm, or any value between 1.5mm and 1.7mm, preferably 1.6mm. The length of the first pad 30 in the second direction can be 1.7mm-2.1mm, such as 1.7mm, 1.75mm, 1.8mm, 1.85mm, 1.9mm, 1.95mm, 2mm, 2.05mm, 2.1mm, or any value between 1.8mm and 2.1mm, preferably 2.05mm.

[0262] The lengths of the first testing section 150 and the second testing section 160 in the first direction can be 1.6mm-1.8mm, such as 1.6mm, 1.65mm, 1.7mm, 1.75mm, 1.8mm, or any value between 1.6mm and 1.8mm, preferably 1.75mm. The lengths of the first testing section 150 and the second testing section 160 in the second direction can be 1.3mm-1.5mm, such as 1.3mm, 1.35mm, 1.4mm, 1.45mm, 1.5mm, or any value between 1.3mm and 1.5mm, preferably 1.4mm.

[0263] In this way, by optimizing the dimensions of the pads and test sections, the stability of electrical performance and other tests can be improved while ensuring the welding stability of the pads and solder strips.

[0264] Please see Figures 4-8 In some embodiments, the first fine gate 20 is an N-type fine gate and the second fine gate 70 is a P-type fine gate. Among the plurality of first fine gates 20 and the plurality of second fine gates 70, the fine gates closest to the first edge 101 and the second edge 102 are all second fine gates 70. That is to say, the first edge fine gate 107 and the second edge fine gate 108 are both P-type fine gates, and each has a corresponding P-type doped layer below it.

[0265] Thus, the doped layer closest to the first edge 101 and the second edge 102 can be a P-type doped layer, which can improve the collection efficiency of hole carriers.

[0266] In some embodiments, in the first direction, the spacing between adjacent first fine gates 20 and second fine gates 70 may be 0.3mm-0.5mm.

[0267] Please see Figure 12In some embodiments, among the plurality of first doped layers 14 and the plurality of second doped layers 15, at least one first doped layer 14 has an extension 142 extending onto an adjacent second doped layer 15. In such a case, the first doped layer 14 includes a body portion 141 and an extension portion 142, the body portion 141 having a trench between it and the adjacent second doped layer 15, that is, the body portion 141 is insulated from the second doped layer 15 by the trench. Figure 12 As shown, the extension 142 extends along the trench to the adjacent second doped layer 15 to cover a portion of the second doped layer 15. The second fine gate 70 on the second doped layer 15 on which the extension 142 is stacked is disposed outside the extension 142, that is, the second fine gate 70 and the extension 142 are spaced apart in the first direction.

[0268] In the first fine gate 20 and the second fine gate 70, the spacing L1 between the second fine gate 70 on the second doped layer 15 where the extension 142 is stacked and the adjacent first fine gate 20 is greater than the spacing L2 between the second fine gate 70 on the remaining second doped layers 15 and the adjacent first fine gate 20.

[0269] Thus, the extension 142 on the first doped layer 14 extends to the adjacent second doped layer 15 and overlaps with the second doped layer 15 in the thickness direction, forming an anti-hot spot structure. This reduces the reverse bias voltage and the heat generation power when the back contact battery 100 becomes a load after being shielded in the assembly, thereby reducing the risk of hot spots. Simultaneously, by placing the second fine gate 70 on the second doped layer 15 with the extension 142 outside the extension 142, and setting the spacing L1 between the second fine gate 70 on the second doped layer 15 with the extension 142 and the adjacent first fine gate 20 to be larger than the spacing L2 between the second fine gate 70 on the other second doped layers 15 and the adjacent first fine gate 20, sufficient space is provided for setting the anti-hot spot structure. This also reduces the risk of short circuits caused by contact between fine gates and doped regions with different polarities.

[0270] In some embodiments, the difference between the spacing L1 between the second fine gate 70 on the second doped layer 15 where the extension 142 is stacked and the adjacent first fine gate 20 and the spacing L2 between the second fine gate 70 and the adjacent first fine gate 20 on the remaining second doped layers 15 is 0.05mm-0.1mm, for example, 0.05mm, 0.06mm, 0.07mm, 0.08mm, 0.09mm, and 0.1mm.

[0271] This ensures that the difference between the two is within a suitable range, avoiding insufficient space for setting up the anti-hot spot structure due to an excessively small difference, and also avoiding poor carrier collection performance due to a large difference.

[0272] In some embodiments, the spacing L1 between the second fine gate 70 on the second doped layer 15, on which the extension 142 is stacked, and the adjacent first fine gate 20 can be 0.35mm-0.55mm, for example, 0.35mm, 0.4mm, 0.45mm, 0.475mm, 0.5mm, or 0.55mm. The spacing L2 between the remaining second fine gates 70 and the adjacent first fine gates 20 can be 0.3mm-0.45mm, for example, 0.3mm, 0.35mm, 0.4mm, or 0.45mm.

[0273] Thus, on the one hand, by setting the spacing L1 between the second fine gate 70 on the second doped layer 15 with the extension 142 and the adjacent first fine gate 20 within a reasonable range of 0.35mm-0.55mm, insufficient space for setting the anti-hot spot structure due to too small a spacing can be avoided, and poor carrier collection effect due to too large a spacing can also be avoided. On the other hand, setting the spacing between the remaining second fine gates 70 and the adjacent first fine gates 20 within a reasonable range of 0.3mm-0.45mm can avoid dense gate lines and high cost due to too small a spacing, and poor carrier collection effect due to too large a spacing can also be avoided.

[0274] Further, please refer to Figure 12 In some embodiments, among a plurality of second doped layers 15, the width L4 of the second doped layer 15 having the extension 142 is greater than the width L3 of the other second doped layers 15.

[0275] Thus, by setting the width of the second doped layer 15 with the hot spot resistance structure to be relatively large, sufficient space can be provided for the second fine gate 70 while forming the hot spot resistance structure, so as to avoid the second fine gate 70 from contacting the extension 142 and causing a short circuit.

[0276] Please see Figure 11 In some embodiments, the second fine gate 70 on the second doped layer 15 with the extension 142 is cross-connected to the first test section 150, and the structure of the first test section 150 is symmetrical about the second fine gate 70 in a first direction. That is, the center line of the second fine gate 70 on the second doped layer 15 with the extension 142 coincides with the center line of the first test section 150 in the first direction. This makes the current transmission distribution more uniform.

[0277] Please see Figure 8 and Figure 9In some embodiments, the back contact battery 100 has a first chamfer 105 formed at the intersection of the first edge 101 and the third edge 103. Among the first fine grid 20 and the second fine grid 70, the fine grid closest to the first edge 101 is the second fine grid 70 (that is, the type of the first edge fine grid 107 is the second fine grid 70). Among the several second fine grids 70, two second fine grids 70 are provided at the first chamfer 105. That is to say, the two second fine grids 70 closest to the first edge 101 correspond to the first chamfer 105, and their extension lines intersect the first chamfer 105, while the extension lines of the remaining second fine grids 70 do not intersect the first chamfer 105. The second fine gate 70 closest to the first edge 101 is connected to the third connecting gate line 90. The first bus gate line 130 is only electrically connected to the second fine gate 70 of the two second fine gates 70 located at the first chamfer 105 that is far from the first edge 101 (i.e., the fine gate closest to the first edge 101 among the middle fine gates 109) and not connected to the second fine gate 70 closest to the first edge 101 (i.e., the first edge fine gate 107). That is to say, the first bus gate line 130 only extends to the position of the second fine gate 70 of the two second fine gates 70 located at the first chamfer 105 that is far from the first edge 101.

[0278] Thus, the first chamfer 105 corresponds to only two second fine grids 70. The second fine grid 70 closest to the first edge 101 is connected to the third connecting grid line 90. The first bus grid line 130 is only electrically connected to the second fine grid 70 that is far from the first edge 101 among the two second fine grids 70. Therefore, it is not necessary to set the first bus grid line 130 at the entire first chamfer 105. That is, the first bus grid line 130 does not need to extend to the position of the first chamfer 105 near the first edge 101. This can effectively reduce the risk of microcracks caused by stress concentration at the first chamfer 105, and at the same time reduce the use of slurry and reduce costs.

[0279] Please see Figure 8 and Figure 9 Furthermore, in some embodiments, the first busbar 130 may include a first vertical segment 131 extending along the first direction and a first bent segment 132 bending relative to the first vertical segment 131 toward the fourth edge 104. The first vertical segment 131 is connected to all the second fine grids 70 located outside the first chamfer 105. The first bent segment 132 is at least partially located at the first chamfer 105. The end of the first bent segment 132 is connected to the second fine grid 70 of the two second fine grids 70 located at the first chamfer 105 that is farther away from the first edge 101.

[0280] Thus, the first bend 132 allows the first busbar 130 to be smoothly connected to the first second fine grid 70 located at the first chamfer 105.

[0281] Furthermore, in some embodiments, the first bend 132 is parallel to the first chamfer 105. This arrangement can further reduce the risk of microcracks at the first chamfer 105 due to stress concentration.

[0282] In some embodiments, the angle of the first chamfer 105 may be 40°-50°, such as 40°, 41°, 42°, 43°, 44°, 45°, 46°, 47°, 48°, 49°, 50° or other values ​​between 40°-50°, preferably 42°-46°, but no specific limitation is made here.

[0283] Please see Figure 10 In some embodiments, the back contact battery 100 has a second chamfer 106 formed at the intersection of the first edge 101 and the fourth edge 104. Of the first fine grid 20 and the second fine grid 70, the fine grid closest to the first edge 101 is the second fine grid 70. The second chamfer 106 corresponds to one first fine grid 20 and two second fine grids 70. That is, the extension line of the first fine grid 20 closest to the first edge 101 intersects the second chamfer 106, while the extension lines of the remaining first fine grids 20 do not intersect the second chamfer 106. The second busbar line 140 connects to all the first fine grids 20.

[0284] Thus, the second chamfer 106 corresponds to only one first fine grid 20. The connection can be achieved by setting the second busbar 140 at a certain position of the second chamfer 106. This can effectively reduce the risk of microcracks caused by stress concentration at the second chamfer 106, and at the same time reduce the use of slurry and reduce costs.

[0285] Further, please refer to Figure 10 In such an embodiment, the second busbar 140 may include a second vertical segment 1401 extending along the second direction and a second bent segment 1402 bent relative to the second vertical segment 1401 toward the third edge 103. The second vertical segment 1401 is connected to all the first fine grids 20 located outside the second chamfer 106. The second bent segment 1402 is at least partially located at the second chamfer 106 and the end of the second bent segment 1402 is connected to the first fine grids 20 located at the second chamfer 106.

[0286] Thus, the second bend 1402 allows the second busbar 140 to be smoothly connected to the second fine grid 70 located at the second chamfer 106.

[0287] like Figure 10 As shown, in some embodiments, the second bend 1402 is parallel to the second chamfer 106. This further reduces the risk of microcracks at the second chamfer 106 due to stress concentration.

[0288] In some embodiments, the angle of the second chamfer 106 may be the same as the angle of the first chamfer 105, and the two are symmetrical in the second direction. The angle of the second chamfer 105 may also be 40°-50°, such as 40°, 41°, 42°, 43°, 44°, 45°, 46°, 47°, 48°, 49°, 50° or other values ​​between 40°-50°, preferably 42°-46°, but no specific limitation is made here.

[0289] In some embodiments, the second fine gate 70, which is electrically connected to the first bus gate 130, may protrude from the first bus gate 130 in a second direction toward the end of the third edge 103.

[0290] This configuration ensures that all second fine gates 70 can be effectively electrically connected to the first bus gate 130, effectively preventing positional deviations during the printing process of the first bus gate 130 that could prevent the first bus gate 130 from contacting some of the second fine gates 70.

[0291] Furthermore, in some embodiments, the end of the first fine gate 20, which is electrically connected to the second bus gate 140, protrudes out of the second bus gate 140 in a second direction toward the fourth edge 104.

[0292] This configuration ensures that all first fine gates 20 can be effectively electrically connected to the second bus gate 140, effectively preventing positional deviations during the printing and fabrication of the second bus gate 140 that could prevent the second bus gate 140 from contacting some of the first fine gates 20.

[0293] In some embodiments, when the first edge fine gate 107 is the second fine gate 70, the end of the third connecting gate line 90 may protrude from the first edge fine gate 107 along the first direction. Similarly, in some embodiments, when the second edge fine gate 108 is the second fine gate 70, the end of the fourth connecting gate line 120 may also protrude from the second edge fine gate 108 along the first direction, and there are no specific limitations here.

[0294] In summary, a back contact battery 100 in this embodiment may include:

[0295] Silicon substrate 10, having opposing back side 11 and front side 12;

[0296] A plurality of first fine gates 20 and a plurality of second fine gates 70 are disposed on the back surface 11. The plurality of first fine gates 20 and the plurality of second fine gates 70 are arranged alternately along the first direction and all extend along the second direction. The first direction and the second direction intersect. The silicon substrate 10 has a first edge 101 and a second edge 102 opposite to each other in the first direction. The silicon substrate 10 has a third edge 103 and a fourth edge 104 opposite to each other in the second direction.

[0297] A plurality of first pads 30 and a plurality of third pads 80 are disposed on the back side 11. The first pads 30 and the third pads 80 are both disposed close to the first edge 101 and have a plurality of first fine gates 20 and a plurality of second fine gates 70 between them and the first edge 101. The first pads 30 are connected to a portion of the first fine gates 20 and are insulated from the second fine gates 70. The third pads 80 are connected to a portion of the second fine gates 70. The second fine gates 70 are disconnected at the first pads 30 and the first fine gates 20 are disconnected at the third pads 80. Among the plurality of first pads 30 and the plurality of third pads 80, the pad closest to the third edge 103 is the first pad 30.

[0298] A first connecting gate line 40 and a third connecting gate line 90 are connected. The first connecting gate line 40 is electrically connected to a first pad 30 and to a first fine gate 20 located between a first edge 101 and the first pad 30. The third connecting gate line 90 is electrically connected to a third pad 80 and to a second fine gate 70 located between the first edge 101 and the third pad 80. The second fine gate 70 is disconnected at the first connecting gate line 40, and the first fine gate 20 is disconnected at the third connecting gate line 90.

[0299] A first bus gate 130 is disposed near the third edge 103. The first bus gate 130 is connected to at least the second fine gate 70 located between the first pad 30 closest to the third edge 103 and the third edge 103. The width of the first bus gate 130 is smaller than the width of the first connecting gate 40.

[0300] In the back contact battery 100 of this application embodiment, the presence of the first connecting grid line 40 allows the current collected by the first fine grid 20 at the edge position to be directly channeled to the first pad 30 and the first solder ribbon 210. Due to the presence of the third connecting grid line 90, the current collected by the second fine grid 70 at the edge position can be directly channeled to the third pad 80 and the second solder ribbon 220, improving efficiency. Simultaneously, the arrangement of the first bus grid line 130 allows the isolated grid segment of the second fine grid 70 located between the third edge 103 and the first pad 30 and the first connecting grid line 40 to be completely collected, thereby improving the efficiency of the back contact battery 100. Furthermore, by setting the width of the first bus grid line 130 to be smaller than the width of the first connecting grid line 40, current transmission losses can be reduced while paste costs are lowered.

[0301] Furthermore, in some embodiments, the first busbar 130 is connected to all the second fine gates 70.

[0302] In some embodiments, a first chamfer 105 is formed at the intersection of the first edge 101 and the third edge 103. Among the first fine gate 20 and the second fine gate 70, the fine gate closest to the first edge 101 is the first edge fine gate 107 and the first edge fine gate 107 is the second fine gate 70. The first edge fine gate 107 corresponds to the first chamfer 105. The first bus gate line 130 is connected to all the second fine gates 70 except for the first edge fine gate 107.

[0303] In some embodiments, the width of the first bus gate 130 is 190μm-210μm, and the width of the first connecting gate 40 is 240μm-260μm.

[0304] In some embodiments, the ratio between the width of the first bus gate 130 and the width of the first connecting gate 40 is 0.6-0.9.

[0305] In some embodiments, in the first fine gate 20 and the second fine gate 70, the width of the fine gate closest to the first edge 101 and the second edge 102 is greater than the width of the remaining fine gates.

[0306] In some embodiments, in the first fine gate 20 and the second fine gate 70, the fine gate closest to the first edge 101 is the first edge fine gate 107, the fine gate closest to the second edge 102 is the second edge fine gate 108, and the fine gate located between the first edge fine gate 107 and the second edge fine gate 108 is the middle fine gate 109.

[0307] The widths of the first edge fine gate 107 and the second edge fine gate 108 are greater than the width of the middle fine gate 109, and the width of the first bus gate line 130 is greater than the width of the middle fine gate 109 and less than the widths of the first edge fine gate 107 and the second edge fine gate 108.

[0308] In some embodiments, among the plurality of first pads 30 and the plurality of third pads 80, the pad closest to the fourth edge 104 is the third pad 80. The back contact battery 100 also includes a second busbar 140, which is disposed close to the fourth edge 104. The second busbar 140 is connected at least to a first fine gate 20 located between the third pad 80 closest to the fourth edge 104 and the fourth edge 104. The width of the second busbar 140 is smaller than the width of the third connecting gate 90.

[0309] In some embodiments, the second busbar 140 is connected to all the first fine gates 20.

[0310] In some embodiments, the width of the second bus gate 140 is 190μm-210μm, and the width of the third connecting gate 90 is 240μm-260μm.

[0311] In some embodiments, the ratio between the width of the second bus gate 140 and the width of the third connecting gate 90 is 0.6-0.9.

[0312] In some embodiments, in the first fine gate 20 and the second fine gate 70, the fine gate closest to the first edge 101 is the first edge fine gate 107, the fine gate closest to the second edge 102 is the second edge fine gate 108, and the fine gate located between the first edge fine gate 107 and the second edge fine gate 108 is the middle fine gate 109.

[0313] The widths of the first edge fine gate 107 and the second edge fine gate 108 are greater than the width of the middle fine gate 109, and the width of the second bus gate line 140 is greater than the width of the middle fine gate 109 and less than the widths of the first edge fine gate 107 and the second edge fine gate 108.

[0314] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the described embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0315] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A back-contact battery, characterized in that, include: A silicon substrate having opposing back and front sides; A plurality of first fine gates and a plurality of second fine gates are disposed on the back side, the plurality of first fine gates and the plurality of second fine gates are arranged alternately and alternately along a first direction and all extend along a second direction, the first direction and the second direction intersect, the silicon substrate has a first edge and a second edge opposite to each other in the first direction, and the silicon substrate has a third edge and a fourth edge opposite to each other in the second direction; A plurality of first pads and a plurality of third pads are disposed on the back side. The first pads and the third pads are both disposed close to the first edge and have a plurality of first fine gates and a plurality of second fine gates between them and the first edge. The first pads are connected to a portion of the first fine gates and are insulated from the second fine gates. The third pads are connected to a portion of the second fine gates. The second fine gates are disconnected at the first pads and the first fine gates are disconnected at the third pads. Among the plurality of first pads and the plurality of third pads, the pad closest to the third edge is the first pad. A first connecting gate line and a third connecting gate line, the first connecting gate line being electrically connected to the first pad and to a first fine gate located between the first edge and the first pad, the third connecting gate line being electrically connected to the third pad and to a second fine gate located between the first edge and the third pad, the second fine gate being disconnected at the first connecting gate line, and the first fine gate being disconnected at the third connecting gate line; and A first bus gate line is disposed near the third edge, the first bus gate line being connected at least to a second fine gate located between the first pad closest to the third edge and the third edge, the width of the first bus gate line being smaller than the width of the first connecting gate line.

2. The back contact battery according to claim 1, characterized in that, The first busbar is connected to all the second fine gates.

3. The back contact battery according to claim 1, characterized in that, A first chamfer is formed at the intersection of the first edge and the third edge. Among the first fine gate and the second fine gate, the fine gate closest to the first edge is the first edge fine gate and the first edge fine gate is the second fine gate. The first edge fine gate corresponds to the first chamfer. The first bus gate line is connected to all the second fine gates except the first edge fine gate.

4. The back contact battery according to claim 1, characterized in that, The width of the first bus gate is 190μm-210μm, and the width of the first connecting gate is 240μm-260μm.

5. The back contact battery according to claim 1, characterized in that, The ratio between the width of the first busbar and the width of the first connecting busbar is 0.6-0.

9.

6. The back contact battery according to claim 1, characterized in that, In the first and second fine gates, the width of the fine gate closest to the first and second edges is greater than the width of the remaining fine gates.

7. The back contact battery according to claim 6, characterized in that, In the first fine gate and the second fine gate, the fine gate closest to the first edge is the first edge fine gate, the fine gate closest to the second edge is the second edge fine gate, and the fine gate located between the first edge fine gate and the second edge fine gate is the middle fine gate; Wherein, the width of the first edge fine gate and the second edge fine gate is greater than the width of the middle fine gate, and the width of the first bus gate line is greater than the width of the middle fine gate and less than the width of the first edge fine gate and the second edge fine gate.

8. The back contact battery according to claim 1, characterized in that, Among the plurality of first pads and the plurality of third pads, the pad closest to the fourth edge is the third pad. The back contact battery further includes a second busbar, which is disposed close to the fourth edge. The second busbar is connected to at least the first fine gate located between the third pad closest to the fourth edge and the fourth edge. The width of the second busbar is smaller than the width of the third connecting gate.

9. The back contact battery according to claim 8, characterized in that, The second busbar is connected to all of the first fine gates.

10. The back contact battery according to claim 8, characterized in that, The width of the second busbar is 190μm-210μm, and the width of the third connecting busbar is 240μm-260μm.

11. The back contact battery according to claim 8, characterized in that, The ratio between the width of the second busbar and the width of the third connecting busbar is 0.6-0.

9.

12. The back contact battery according to claim 8, characterized in that, In the first fine gate and the second fine gate, the fine gate closest to the first edge is the first edge fine gate, the fine gate closest to the second edge is the second edge fine gate, and the fine gate located between the first edge fine gate and the second edge fine gate is the middle fine gate; Wherein, the width of the first edge fine gate and the second edge fine gate is greater than the width of the middle fine gate, and the width of the second bus gate line is greater than the width of the middle fine gate and less than the width of the first edge fine gate and the second edge fine gate.

13. A battery assembly, characterized in that, Includes the back contact battery as described in any one of claims 1-12.

14. A photovoltaic system, characterized in that, Includes the battery assembly as described in claim 13.

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