Computing memory

Abstract

The invention relates to a computing memory. The disclosed memory architecture eliminates the need for conventional queue-based work request models by allowing calculations to be made directly within the memory module in response to data writes. The system is designed to automatically update compute values, such as hashes, within a specified compute memory region in response to a write to a corresponding dataset region without explicit instructions from a host. The computation is performed according to a defined policy that may include computing a new result immediately after a write to a dataset segment, computing the result if a write to a dataset segment is not detected within a specified period of time, computing the result after the host reads invalid compute validity bits, and the like.

Description

Technical Field

[0001] The embodiments relate to memory devices with computing capabilities. Some embodiments relate to methods for providing computing capabilities in a memory device. Background Technology

[0002] Memory devices used in computers or other electronic devices can be classified as volatile and non-volatile memory. Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory retains stored data when no power is supplied and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), static RAM (SRAM), erasable programmable ROM (EPROM), resistive variable memory, phase-change memory, memory-class memory, resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), etc. Persistent memory is an architectural property of a system, in which data stored in a medium is available after a system reset or power cycle. In some instances, non-volatile memory media can be used to build systems with persistent memory models.

[0003] Memory devices can interface with a host, such as a host processor or another computing device, to store basic data, commands, and instructions for the operation of the host system. The connection between the host and the memory device can be established via a local bus or interconnect, allowing the memory device to function within the host system, such as within a conventional computing device. Alternatively, the memory device can be configured within a distributed memory system, which involves a network of interconnected host and memory devices spanning multiple locations. This configuration enables the creation of scalable systems that utilize the collective resources of numerous host and memory devices.

[0004] Distributed memory systems facilitate communication and data sharing across multiple hosts and memory devices by employing a distributed communication architecture that interconnects multiple hosts and memory devices. This system differs from local memory configurations where memory devices are directly and physically connected to a single host.

[0005] Communication within a distributed memory system follows various protocols or standards designed to ensure efficient and reliable data exchange. For example, the Compute High-Speed ​​Link (CXL) protocol is a standard that provides high bandwidth and low latency connectivity, thereby optimizing the performance of distributed memory systems.

[0006] CXL.mem is part of the CXL protocol, which facilitates high-speed, efficient communication between host processors and one or more memory devices. The architecture is characterized by its ability to provide coherent memory space between the CPU and memory extensions (such as RAM modules or non-volatile memory) via the CXL interface. CXL.mem employs advanced features such as memory pooling, where memory resources can be dynamically allocated and deallocated across various processors and devices, and memory sharing, which allows multiple CPUs or accelerators to access the same physical memory simultaneously. This architecture is designed to significantly reduce latency and increase bandwidth, thereby improving overall system performance. The CXL.mem architecture is also scalable, supporting a wide range of applications from data centers to high-performance computing environments. Its compatibility with existing and future CXL specifications ensures that it can be integrated into next-generation computing systems with minimal modifications. Summary of the Invention

[0007] One embodiment of this disclosure provides a memory device. The memory device includes a memory storage device comprising a first region and a second region; and a memory controller. The memory controller is configured to perform operations including: recognizing a write command to write first data from a host to the first region; calculating a result value in response to recognizing the write command to write the first data from the host to the first region, the result value being calculated using the first data; and storing the result value in the second region in response to calculating the result value.

[0008] Another embodiment of this disclosure provides a method for operating a memory device, the memory device including a memory storage device having a first region and a second region. The method includes: identifying a write command to write first data from a host to the first region; calculating a result value in response to identifying the write command to write the first data from the host to the first region, the result value being calculated using the first data; and storing the result value in the second region in response to calculating the result value.

[0009] Another embodiment of this disclosure provides a non-transitory machine-readable medium for storing instructions, which, when executed by a memory controller of a memory device including a memory storage device having a first region and a second region, cause the memory controller to perform operations including: recognizing a write command to write first data from a host to the first region; calculating a result value in response to recognizing the write command to write the first data from the host to the first region, the result value being calculated using the first data; and storing the result value in the second region in response to calculating the result value. Attached Figure Description

[0010] In the accompanying drawings, which are not necessarily drawn to scale, similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar components. The accompanying drawings are intended to illustrate, by way of example and not limitation, the various embodiments discussed in this document.

[0011] Figure 1 Distributed memory systems according to some examples of this disclosure are shown.

[0012] Figure 2 A logic diagram of a near-memory computing system according to this disclosure is shown.

[0013] Figure 3 A logical diagram of a memory address space according to some examples of this disclosure is shown.

[0014] Figure 4 A timeline of host access computation results is shown according to some examples of this disclosure.

[0015] Figure 5 A state machine for managing computation validity bits associated with computation segments in a memory device, according to some examples of this disclosure, is shown.

[0016] Figure 6 A block diagram of a unique hardware architecture for a computational memory controller within a CXL memory device, according to some examples of this disclosure, is shown.

[0017] Figure 7 A flowchart illustrating a method for computational memory processing according to some examples of this disclosure is shown.

[0018] Figure 8 It is a block diagram illustrating an example of a machine on which one or more embodiments may be implemented. Detailed Implementation

[0019] In distributed memory systems, compute memory devices, also known as near-memory compute devices, are innovative memory systems with processing elements physically close to the memory cell. Unlike the traditional von Neumann architecture, this design paradigm embeds computational functionality within the memory subsystem, allowing data processing to occur at or near the location where the data is stored. This architectural innovation offers several benefits, primarily by alleviating the data transfer bottleneck typically associated with the traditional von Neumann architecture. By performing computations physically close to the location where the data is stored, compute memory devices reduce latency and energy consumption that would otherwise occur during data movement between the processor and memory. This proximity between memory and computation allows for higher bandwidth and more efficient data throughput, enabling faster processing speeds for data-intensive applications such as machine learning, big data analytics, and real-time processing. In addition to higher bandwidth and more efficient data throughput, compute memory devices reduce the overall complexity of system design and improve parallel processing capabilities by allowing multiple computations to occur simultaneously within the memory array. This design also promotes better scalability, as adding more compute memory devices directly increases computing power without requiring significant modifications to the central processing unit (CPU) or system bus. Overall, computing memory devices provide a revolutionary computing approach that can bring new levels of performance and efficiency to a wide range of computing tasks.

[0020] Computational memory systems that include computational memory devices typically rely on a traditional queuing model, where the host processor sends job requests to memory modules (e.g., memory devices) to perform computational tasks. While conceptually simple, this model introduces several inefficiencies that can significantly hinder system performance. One problem with this model is the latency associated with the round-trip communication between the host and memory modules. Each job request and subsequent response adds to the total time required to complete a computational task. Furthermore, this model requires managing queues of job requests, which can become a bottleneck for data-intensive applications, leading to underutilization of computational resources and increased energy consumption.

[0021] Another limitation of current systems is the complexity they impose on software developers, who must explicitly manage the tracking of memory storage and the corresponding computational tasks. This requirement not only complicates the development process but also increases the likelihood of programming errors. Developers must ensure that every time data is written to memory, any associated computations are triggered, which can be particularly challenging in high-concurrency systems or when processing large datasets. The burden of tracking storage also extends to handling dirty data flags, further complicating the programming model and increasing the overhead of ensuring data consistency and integrity.

[0022] Existing queue-based approaches for computational memory systems also present challenges in terms of scalability and flexibility. As data volume and computational task complexity increase, queue models may struggle to keep up, leading to increased latency and reduced throughput. Furthermore, the rigid nature of queue systems makes them difficult to adapt to different types of computational tasks or to efficiently allocate resources based on dynamic workloads. This inflexibility can result in suboptimal performance, especially in heterogeneous computing environments where different types of computation may be needed to operate on the same dataset.

[0023] Some examples disclose methods, systems, memory devices, and machine-readable media for providing more efficient computational memory systems. The disclosed memory architecture eliminates the need for conventional queue-based job request models by allowing direct computation within a memory module in response to writing computational arguments to a defined memory location. The computation result is then stored in another defined location, which may correspond to the defined memory location where the arguments were written.

[0024] The system is therefore designed to automatically update the computed values ​​in a specified dataset region in response to a write to that region, without explicit instructions from the host. Computations can be performed according to a defined strategy, which may include computed a new result immediately after a write to a segment of the dataset region, computed the result if no write to the dataset segment is detected within a specified time period, computed the result after the host reads an invalid compute validity bit, etc. Instance computations may include hashing (e.g., SHA-256), compressibility of computed data, pattern matching algorithms for finding the frequency and location of patterns within the dataset, tokenization of the dataset, thumbnail computation, content analysis, etc. Computations can be pre-specified and selected by the host. In other instances, computations can be customized by the host, and the address of the computation instructions can be specified by the host. General-purpose hardware processors can perform computations using predefined or custom instructions from the host. In other instances, custom hardware processors can be used to perform computations.

[0025] In some instances, to ensure the validity and integrity of results in computation memory, the architecture utilizes validity bits and minimum recalculation cycles, allowing the host system to be confident that the results are valid for a set of inputs.

[0026] Figure 1A distributed memory system 100 according to some embodiments of the present disclosure is illustrated. The distributed memory system 100 facilitates high-speed, efficient communication between hosts 110-A, 110-B…110-P and one or more memory devices 114-A, 114-B…114-N. The memory system 100 can provide coherent memory space between processing elements (e.g., CPUs or other hardware processors) on hosts 110-A, 110-B…110-P and memory devices 114-A to 114-N. As an example, the distributed memory system 100 can be a CXL memory architecture according to the CXL.mem standard. The distributed memory system 100 may have memory pooling, where memory resources can be dynamically allocated and deallocated across various processors and devices, and may have memory sharing, which allows multiple CPUs or accelerators to access the same physical memory simultaneously.

[0027] Hosts 110-A, 110-B...110-P are connected to one or more memory devices 114-A, 114-B...114-N using an interconnect structure such as structure 112. The interconnect structure, for example, structure 112, is a network framework that enables data transfer between various components of a computing system (e.g., processors, memory modules, storage devices, and input / output peripherals). This structure typically includes interconnect nodes, switches, and communication links that facilitate coherent and coordinated operation of multi-component systems, thereby allowing for integrated performance and resource optimization.

[0028] In a distributed near-memory computing system, such as a Computing High-Speed ​​Link (CXL) system, memory devices 114-A, 114-B...114-N are equipped with a memory controller that not only manages the data flow to and from the memory medium but also facilitates computational tasks located near the stored data. Figure 1 For example, the memory controller 1214-A includes components such as host interface component 130, CXL structure interface component 132, structure-attached memory (FAM) control component 136, and media control component 138. These components can be implemented in hardware or a combination of hardware and software configuration.

[0029] The host interface component 130 is responsible for implementing protocols or interfaces that allow the memory controller to receive memory commands from the host, including data mover calls for efficiently moving data within the system. The CXL architecture interface component 132 facilitates communication across the CXL architecture 112, thereby enabling high-speed data transfer and coordination across the distributed memory system.

[0030] Media control component 138 manages memory operations such as read and write scheduling, refresh control for maintaining data integrity in volatile memory types, and error correction codes (ECC) for detecting and correcting data corruption. An example of this component is a DRAM controller, which specifically manages dynamic random access memory operations.

[0031] FAM control component 136 maintains address translation tables and access control tables. These tables are used to translate addresses between various forms and route memory requests to the appropriate memory devices, thereby ensuring efficient data access and security within the distributed memory architecture.

[0032] Furthermore, the memory controller may also include a compute interface 140. This interface implements an efficient compute-memory system, enabling computational tasks, such as data analysis, machine learning, and other processing, to be performed directly within the memory module according to the disclosed methods. For example, the compute interface 140 configures compute areas and dataset areas, monitors writes to the dataset area, executes strategies in response to writes, and executes computational logic to produce results stored in the corresponding compute areas. Additionally, the compute interface 140 can manage validity bits. By doing so, the compute interface 140 reduces the latency and bandwidth limitations associated with transferring data to the central processing unit, thereby improving the overall system performance and efficiency of near-memory computational operations.

[0033] Figure 2 A logic diagram 200 of a near-memory computing system according to the present disclosure is shown. The memory device 216 may be... Figure 1 An example of one of the memory devices 114-A to 114-N. Host A 212 and host B 210 may be from Figure 1 An instance of a host (e.g., host 1 110-A, host 2 110-B... host p 110-P). The memory device 216 may be in the form of a memory module having memory media and a memory controller. The memory device 216 may contain volatile and / or non-volatile memory media. The memory device may allocate a portion of the memory cells in the memory media to the dataset area 220 and a portion to the computation area 218. The dataset area 220 is a portion of memory designated for storing data intended as independent variables for computational tasks. This area may be divided into fixed-length segments, where one or more segments (e.g., a single segment) correspond to a segment in the computation area 218 storing the results of computations performed on the independent variables in the dataset area.

[0034] In some instances, dataset area 220 may be configured as a labeled capacity area accessible to the distributed host after authorization by the structure manager. When a host writes data to a segment within dataset area 220, the associated memory device (e.g., the compute interface 140 of the memory controller) is responsible for automatically performing the specified computation and updating the corresponding segment in compute area 218. For example, memory module local compute 222 may perform the computation. In some instances, memory module local compute 222 may be a general-purpose hardware processor configured to perform computations according to one or more software programs. In other instances, memory module local compute 222 may perform the computation in hardware.

[0035] When a host processor, such as host A 212 or host B 210, intends to access the computation results in computation area 218, it references the computation area based on known structure and segment pairings. The host knows the starting addresses and segment sizes of both dataset area 220 and computation area 218 because these parameters are defined during the setup process managed by the structure manager. Using this information, the host can calculate the address of a specific segment in computation area 218 corresponding to a specific segment in dataset area 220 (for example, by using a fixed offset).

[0036] As previously described, writing to a segment in dataset area 220 acts as a request to perform a computation defined by a computation algorithm. This eliminates the need for a formal request sent via a structure. The computation is then performed automatically when instructed by a defined policy, and the result is placed in computation area 218. The computation algorithm performed can be a standard pre-defined algorithm, such as SHA-256 for hashing, or a custom algorithm for tasks such as pattern matching or data tokenization. In some instances, the host can choose from a plurality of pre-defined algorithms, for example, by writing values ​​to a dataset area that acts as a selection field or flag.

[0037] In other instances, the structure manager 214 can be used, for example, to select a computation algorithm from multiple predetermined algorithms using management mailbox commands. In some instances, a custom algorithm can be loaded into a predetermined memory location. The code for the algorithm can be stored in the algorithm segment 224 of the memory device, or, in the case of a predetermined algorithm, the algorithm segment 224 can be custom hardware that implements the predetermined algorithm in hardware.

[0038] In some instances, mailbox commands 250 can be used to create pairs of regions, namely dataset region 220 and computation region 218. These mailbox commands 250 can also specify the computation algorithm to be used, along with other parameters such as the segment size and starting address of each region. Once the memory device 216 is configured, it actively monitors for writes to dataset region 220. Upon detecting a write, the memory device 216 can trigger the selected computation algorithm to process the new data and update computation region 218 with the results.

[0039] As mentioned, computation can begin according to a computation initiation strategy. In some instances, the strategy may specify that computation begins after data is written, after a certain delay, or immediately after a specific request from the host. In some instances, computation may begin when the host attempts to write to the corresponding segment in computation area 218. Memory device 216 may intercept the write (and effectively disallow writing to memory) and then begin computation.

[0040] In some instances, the memory device includes a validity area 255, which stores validity bits for segments of the computation area 218. The validity area 255 may be SRAM, a flip-flop, or other memory device. In other instances, the validity area may be stored together with the computation area 218.

[0041] Figure 3 A logical diagram of a memory address space 300 according to some embodiments of this disclosure is shown. Within the entire available memory of the media, some memory is designated for use by the controller as controller local memory and code segment 310. This available memory stores firmware and other operational code, as well as the code used by the controller. The remaining memory 312 is a distributed memory controlled by the memory controller. This memory may include host-visible memory 314. Within the host-visible memory, two memory segments may be created for computation memory. The first memory segment 316 is a computation area for storing results. This computation area may be subdivided into computation segments, such as computation segment 324. The computation segment may contain a computation validity bit 325 and a computation result 323. In some embodiments, the computation validity bit 325 may be stored in different locations, such as controller local memory and code segment 310, cache memory, other memory of the controller, on-chip structures such as SRAM or flip-flops, etc. The computation memory dataset area 318 may also be divided into segments 322. Segments 322 and 324 may be the same size or different sizes. For example, segment 322 can be greater than segment 324 because the result of the calculation can be less than the operand.

[0042] The host reading the compute area can utilize one or more processing algorithms to ensure the result is valid. In some instances, when the result size is equal to one cache line, a simple result processing algorithm can be used to read the compute result from the compute area. In short, this algorithm reads the result from the compute area until the validity bit is true. Specifically, the host first identifies the memory address of the compute area and prepares local memory space to store a copy of the compute area. The host initiates a loop to poll the compute validity bit. Within the loop, the host refreshes the cache line corresponding to the compute area address to ensure that the latest data is fetched directly from the memory module. The host then copies the cache line from the compute area to the local memory space and reads the compute validity bit. If the compute validity bit is false, indicating that the result is not yet valid, the loop continues and the host retryes the process. Once the compute validity bit is true, indicating that the result is valid, the host exits the loop and continues to use the data from the local copy of the compute area.

[0043] In other instances, where the computation result spans more than one cache line or when atomic cache line copy operations are not supported, a more general result reading algorithm may be more complex. For example, the host may first initialize variables for the start and end times of the operation, the addresses of the computation area and local memory space, and a flag for tracking the validity of the result. The host enters a loop for reading the computation result, which includes an inner loop for polling the computation validity bit. Within the inner loop, the host refreshes the cache line corresponding to the computation area address to ensure it fetches the latest data directly from the memory module. The host then reads the computation validity bit from the computation area into the local memory space. If the computation validity bit is false, the inner loop continues and the host retryes the process. Once the computation validity bit is true, the host records the start time, refreshes the entire computation area from the cache, and copies the computation result to the local memory space. The host then reads the computation validity bit a second time to ensure it has not changed during the read operation. The host records the end time of the operation and checks whether the time spent reading the result is less than the minimum recalculation cycle and whether both validity bit readings are true. If these conditions are met, the result is considered valid. If the conditions are not met, indicating that the result may have expired during the read operation, the host sets a flag to false, and the outer loop continues, prompting for a retry. Once the host successfully captures a valid result, it exits the loop and continues using data from its local memory space. This algorithm ensures that the host reads coherent and reliable computation results by verifying validity before and after the read operation and by adhering to a minimum recalculation cycle.

[0044] Figure 4A timeline 400 of host access calculation results according to some examples of this disclosure is shown. Figure 4 A more complex algorithm for reading the result is shown. Timeline 400 illustrates the use of a minimum recalculation cycle and a validity bit to ensure that the result read by the host is valid. As previously described, the validity bit is a flag stored in the memory controller or memory indicating whether the associated computation result is current and valid. Timeline 400 involves a single computation memory pair of the dataset area and the computation area. At 410, the computation result is initially set to the value "A", and the validity bit is true 416. During this time, host 1 reads the computation validity bit 422 and finds it to be true. Shortly thereafter, host 2 writes to the dataset area, making the computation result undefined 412 and clearing the validity bit to false 418. Host 1 continues reading the computation result at 424, 426, and 428. At 430, host 1 reads the validity bit and finds it to be false. This means that the result read by host 1 is invalid.

[0045] The calculation result is refreshed to result B at 414 based on the data written by host 2. Shortly thereafter, after the minimum recalculation period expires, the validity bit is set to true at 420. Host 1 then rereads the validity bit 432 and finds it to be true at 420. The result is then read at 434, 436, and 438. Host 1 then reads the validity bit 440 again and finds it to be true at 420. Because the host reads true for the validity bit before and after reading the result, and the reading duration is less than the minimum recalculation period, the read result is valid data.

[0046] Figure 5A state machine 500 for managing computation validity bits associated with computation segments in a memory device, according to some embodiments of this disclosure, is shown. The state machine ensures that the validity bits are correct to ensure that the host can determine the validity of the result. The state machine of the memory device includes the following states: Computation Invalid State 510, which is an initial state where the computation validity bit is set to indicate that the computation result is invalid or outdated due to a recent write to the corresponding dataset segment. When a write to the corresponding dataset segment occurs, the computation validity bit is cleared. Automatic Recomputation State 512: In this state, the memory module waits for a trigger to begin recomputing the computation result. This trigger can be based on a strategy specifying conditions under which recomputation should be performed, such as a write to the dataset segment or a host attempt to read an invalid computation validity bit or a write attempt to the computation area. Computation State 514: Once the trigger condition is met, the state transitions to the computation state, where the memory device performs computation using data from the dataset segment. During this state, the computation validity bit remains unset. Computation Valid State 516: After the computation is completed, the state transitions to the computation valid state 516, and the computation validity bit is set. This indicates that the computation result is now valid and readable by the host. A host write to the dataset segment clears the computation validity bit and moves the state to computation invalid state 510.

[0047] Figure 6 A block diagram 600 illustrates a hardware architecture for a computational memory controller within a CXL memory device according to some embodiments of this disclosure. The diagram illustrates the flow and processing of interactions between various components that request memory and manage computational tasks and memory access. The CXL.mem endpoint 610 is an interface of the CXL memory device for receiving and sending memory access messages. The CXL.MEM REQ message class 630 shows the path for initiating a read request from the host to the memory device. The CXL.mem RwD message class 646 shows the flow of a request message with data, typically a write request containing data to be written to memory. The CXL.mem DRS message class 648 shows the flow of a Data Response Packet (DRS) (e.g., a read return) sent from the memory device to the host in response to a read request. The CXL.mem Non-Data Response (NDR) message class 650 shows the flow of non-data response messages, which are responses from the memory device that do not contain data, such as acknowledgments of write requests.

[0048] The CXL media access controller 612 manages access to the physical media of the CXL memory device, such as reading from or writing to memory cells. A read request processing 618 intercepts read requests targeting computation segments and, for example, directs the requests to the appropriate component for processing, such as a computation queue 622, based on a policy setting 620. For instance, if a policy setting instructs a read request for a specific computation segment to trigger computation of the result, the read request processing can trigger computation, for example, by reordering requests in the computation queue 622. The RD / WR / ARB 614 is a read / write arbiter that manages the priority ordering and sorting of read and write operations to the memory.

[0049] The computation result validity group 616 is an on-die structure that stores computation validity bits for computation segments, indicating whether the computation result is valid. The computation result validity group 616 may place computations in the computation queue 622 due to a received request for data (e.g., a write to a dataset area). Policy settings 620 are policy settings that determine the behavior of the computation memory (e.g., when to start a new computation or how to prioritize tasks). The computation processor 624 manages computation tasks, including initiating and tracking the progress of computations. The results of the computation may be sent to RD / WR / ARB 614 for writing to the computation area 218.

[0050] The computation queue 622 may be a first-in, first-out (FIFO) queue that holds pending computation tasks and organizes them according to a policy setting before the computation processor 624 processes them. The read response handler 626 processes the generated read response and sends it back to the host, including merging the computation validity bits with the computation result after processing the read request.

[0051] Figure 7 A flowchart of a computational memory processing method 700 according to some embodiments of the present disclosure is shown. At operation 710, a memory device of, for example, a controller may receive a write request from the host to write first data from the host to a first designated area (for example, writing data to dataset area 220). At operation 712, it is determined whether a policy condition is met. If not, then at operation 714, the method is paused until the policy condition is met. Once the policy condition is met, then at operation 716, a result value is calculated. In some embodiments, operation 712 is satisfied by writing to the first designated area. At operation 718, once the result value is calculated, it is stored in a second designated area, for example, a segment of the computation area corresponding to the segment of the first designated area where the write command was initiated at operation 710.

[0052] In some instances, the zone is configured to use management messages (such as the CXL Management Mailbox protocol). Settings may include:

[0053]

[0054] In some instances, certain operations on the dataset and computation area may be restricted. For example:

[0055]

[0056] Figure 8 A block diagram of an instance machine 800 is shown above, capable of performing any one or more of the techniques (e.g., methods) discussed herein. In alternative embodiments, machine 800 may be used as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 800 may operate as a server machine, a client machine, or both in a server-client network environment. In one instance, machine 800 may act as a peer-to-peer (P2P) environment or other distributed network environment. Machine 800 may take the form of a distributed computing system, a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a smartphone, a network appliance, a network router, a switch, or a bridge, or any machine capable of (sequentially or otherwise) executing instructions specifying actions to be taken by said machine. Furthermore, although only a single machine is illustrated, the term "machine" should also be considered as encompassing any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein (e.g., cloud computing, Software as a Service (SaaS), or other computer cluster configurations). In some instances, machine 800 may include one or more of the memory devices described herein. In some instances, the memory devices described herein may include one or more of the components of machine 800. For example, machine 800 may be, may be configured to, or one or more components of machine 800 may constitute Figure 1 One or more hosts, such as hosts 110-A, 110-B to 110-P; structure nodes of structure 112; memory devices 114-A, 114-B...114-N. Machine 800 may be, may be configured to, or may be constituted by one or more components of machine 800. Figure 2 The host B 210, host A 212, memory device 216, and structure manager 214. Machine 800 may include, for example: Figure 3 The memory configuration shown in the diagram. Machine 800 can be configured as follows: Figure 4 The memory computation shown in the figure is performed and implemented. Figure 5 A state machine. Machine 800 can be, can be configured as, or one or more components of machine 800 can constitute... Figure 6 The component, and can be configured to execute Figure 7 The method.

[0057] As described herein, an instance may comprise one or more logical units, components, or mechanisms (hereinafter referred to as "components") or operable thereon. A component is a tangible entity (e.g., hardware) capable of performing a specified operation and may be configured or arranged in a certain manner. In an instance, circuitry may be arranged in a specified manner (e.g., internally or externally relative to other circuitry) as a component. In an instance, all or part of one or more computer systems (e.g., stand-alone client or server computer systems) or one or more hardware processors may be configured by firmware or software (e.g., instructions, application portions, or applications) to perform the specified operation as a component. In an instance, the software may reside on a machine-readable medium. In an instance, the software causes the hardware to perform the specified operation of the component when executed by the underlying hardware of the component.

[0058] Therefore, the term "component" is understood to encompass tangible entities, namely, entities that are physically constructed, specifically configured (e.g., hardwired) or temporarily (e.g., provisionally) configured (e.g., programmed) to operate or perform any of the operations described herein in a specified manner. Given that components are instances of provisional configuration, each of the components need not be materialized at any given time. For example, in the case where a component includes a general-purpose hardware processor configured using software, the general-purpose hardware processor can be configured as different components at different times. The software can accordingly configure the hardware processor, for example, to constitute a specific module at one time and different components at different times.

[0059] Machine (e.g., computer system) 800 may include one or more hardware processors, such as processor 802. Processor 802 may be a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof. Machine 800 may include main memory 804 and static memory 806, some or all of which may communicate with each other via interconnect (e.g., bus) 808. Instances of main memory 804 may include synchronous dynamic random access memory (SDRAM), such as dual data rate memory, such as DDR4 or DDR5. Interconnect 808 may be one or more different types of interconnects, allowing one or more components to be connected using a first type of interconnect and one or more components to be connected using a second type of interconnect. Instance interconnects may include memory buses, peripheral component interconnects (PCI), peripheral component interconnect high speed (PCIe) buses, universal serial buses (USB), etc.

[0060] Machine 800 may further include a display unit 810, an alphanumeric input device 812 (e.g., a keyboard), and a user interface (UI) navigation device 814 (e.g., a mouse). In one example, the display unit 810, input device 812, and UI navigation device 814 may be a touchscreen display. Machine 800 may additionally include a storage device (e.g., a drive unit) 816, a signal generation device 818 (e.g., a speaker), a network interface device 820, and one or more sensors 821, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or other sensors. Machine 800 may include an output controller 828, for example, serially (e.g., Universal Serial Bus (USB), parallelly, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connected to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0061] Storage device 816 may include machine-readable medium 822 on which one or more data structures or instruction sets 824 (e.g., software) embodying or utilizing any one or more of the techniques or functions described herein. Instructions 824 may also reside wholly or at least partially within main memory 804, static memory 806, or hardware processor 802 during execution by machine 800. In an example, one or any combination of hardware processor 802, main memory 804, static memory 806, or storage device 816 may constitute the machine-readable medium.

[0062] Although machine-readable media 822 is described as a single medium, the term "machine-readable media" may include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated cache and server) configured to store one or more instructions 824.

[0063] The term "machine-readable medium" can include any medium capable of storing, encoding, or transmitting instructions for execution by machine 800 and causing machine 800 to perform any or more of the technologies disclosed herein, or capable of storing, encoding, or transmitting data structures used by or associated with such instructions. Non-limiting examples of machine-readable media can include solid-state memory as well as optical and magnetic media. Specific examples of machine-readable media can include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable hard disks; magneto-optical disks; random access memory (RAM); solid-state drives (SSDs); and CD-ROM and DVD-ROM disks. In some instances, machine-readable media can include non-transitory machine-readable media. In some instances, machine-readable media can include machine-readable media that are not transient propagating signals.

[0064] Commands 824 can be further transmitted or received on the communication network 826 via a transmission medium through the network interface device 820. Machine 800 can communicate with one or more other machines, wired or wirelessly, using any of several transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include: Local Area Networks (LANs), Wide Area Networks (WANs), packet data networks (e.g., the Internet), mobile phone networks (e.g., cellular networks), conventional telephone networks (POTS), and wireless data networks, such as those known as… The standards include the IEEE 802.11 family, the IEEE 802.15.4 family, the 5G New Radio (NR) family, the LTE family, the UMTS family, peer-to-peer (P2P) networks, and so on. In one example, network interface device 820 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to communication network 826. In one example, network interface device 820 may include multiple antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. In some examples, network interface device 820 may wirelessly communicate using multiple user MIMO technologies.

[0065] Additional notes and examples.

[0066] Example 1 is a memory device comprising: a memory storage device including a first region and a second region; a memory controller configured to perform operations including: recognizing a write command to write first data from a host to the first region; calculating a result value in response to recognizing the write command to write the first data from the host to the first region, the result value being calculated using the first data; and storing the result value in the second region in response to calculating the result value.

[0067] In Example 2, the subject of Example 1 includes the fact that the operations of calculating the result value and storing the result value are performed according to a specified strategy.

[0068] In Example 3, the subject of Example 2 includes, wherein the specified strategy includes one of the following: an indication that the memory device will calculate the result value immediately after the write command; an indication that the memory device will calculate the result value if no other write is received within a specified time period; an indication that the memory device will calculate the result value immediately after the host attempts to read the valid bit; or an indication that the memory device will calculate the result value after a write to the second area.

[0069] In Example 4, the subject matter of Examples 1 to 3 includes the memory controller being further configured to perform operations of clearing the valid bit after recognizing the write command and setting the valid bit after storing the result value.

[0070] In Example 5, the subject of Example 4 includes an operation in which the memory controller is further configured to perform an operation of waiting for the valid bit to be set until the result value is stored and a predetermined amount of time has elapsed since the valid bit was previously set.

[0071] In Example 6, the topics of Examples 1 to 5 are included, wherein the specified algorithm is selected by the host from one of a plurality of predetermined algorithms.

[0072] In Example 7, the topics of Examples 1 through 6 are included, wherein the specified algorithm is provided by the host.

[0073] Example 8 is a method for operating a memory device including a memory storage device having a first region and a second region, the method comprising: identifying a write command to write first data from a host to the first region; calculating a result value in response to identifying the write command to write the first data from the host to the first region, the result value being calculated using the first data; and storing the result value in the second region in response to calculating the result value.

[0074] In Example 9, the subject of Example 8 includes the fact that the calculation of the result value and the storage of the result value are performed according to a specified strategy.

[0075] In Example 10, the subject of Example 9 includes the following: the specified strategy includes one of the following: an indication that the memory device will calculate the result value immediately after the write command; an indication that the memory device will calculate the result value if no other write is received within a specified time period; an indication that the memory device will calculate the result value immediately after the host attempts to read the valid bit; or an indication that the memory device will calculate the result value after a write to the second area.

[0076] In Example 11, the subject matter of Examples 8 to 10 includes clearing the valid bit after recognizing the write command and setting the valid bit after storing the result value.

[0077] In Example 12, the subject of Example 11 includes setting the valid bit until the result value is stored and a predetermined amount of time has elapsed since the valid bit was previously set.

[0078] In Example 13, the topics of Examples 8 to 12 include the specified algorithm being selected by the host from one of a plurality of predetermined algorithms.

[0079] In Example 14, the topics of Examples 8 through 13 are included, wherein the specified algorithm is provided by the host.

[0080] Example 15 is a non-transitory machine-readable medium that stores instructions, which, when executed by a memory controller of a memory device including a memory storage device having a first area and a second area, cause the memory controller to perform operations including: recognizing a write command to write first data from a host to the first area; calculating a result value in response to recognizing the write command to write the first data from the host to the first area, the result value being calculated using the first data; and storing the result value in the second area in response to calculating the result value.

[0081] In Example 16, the subject of Example 15 includes the fact that the calculation of the result value and the storage of the result value are performed according to a specified strategy.

[0082] In Example 17, the subject of Example 16 includes, wherein the specified strategy includes one of the following: an indication that the memory device will calculate the result value immediately after the write command; an indication that the memory device will calculate the result value if no other write is received within a specified time period; an indication that the memory device will calculate the result value immediately after the host attempts to read the valid bit; or an indication that the memory device will calculate the result value after a write to the second area.

[0083] In Example 18, the subject matter of Examples 15 to 17 includes clearing the valid bit after recognizing the write command and setting the valid bit after storing the result value.

[0084] In Example 19, the subject of Example 18 includes setting the valid bit until the result value is stored and a predetermined amount of time has elapsed since the valid bit was previously set.

[0085] In Example 20, the topics of Examples 15 to 19 are included, wherein the specified algorithm is selected by the host from one of a plurality of predetermined algorithms.

[0086] In Example 21, the topics of Examples 15 to 20 are included, wherein the specified algorithm is provided by the host.

[0087] Example 22 is at least one machine-readable medium containing instructions that, when executed by a processing circuitry system, cause the processing circuitry system to perform operations to implement any one of Examples 1 to 21.

[0088] Example 23 is a device that includes components for implementing any one of Examples 1 to 21.

[0089] Example 24 is a system for implementing any one of Examples 1 through 21.

[0090] Example 25 is a method for implementing any of Examples 1 through 21.

Claims

1. A memory device comprising: A memory storage device, comprising a first region and a second region; A memory controller configured to perform operations including the following: Identify the write command that writes the first data from the host to the first area; In response to recognizing a write command that writes first data from the host to the first area, a result value is calculated, the result value being calculated using the first data; and In response to calculating the result value, the result value is stored in the second area.

2. The memory device of claim 1, wherein the operations of calculating the result value and storing the result value are performed according to a specified strategy.

3. The memory device of claim 2, wherein the specified strategy comprises one of the following: an indication that the memory device will calculate the result value immediately after the write command; an indication that the memory device will calculate the result value if no other write is received within a specified time period; an indication that the memory device will calculate the result value immediately after the host attempts to read a valid bit; or an indication that the memory device will calculate the result value after a write to the second region.

4. The memory device of claim 1, wherein the memory controller is further configured to perform operations of clearing the valid bit after recognizing the write command and setting the valid bit after storing the result value.

5. The memory device of claim 4, wherein the memory controller is further configured to perform an operation of waiting to set the valid bit until the result value is stored and a predetermined amount of time has elapsed since the valid bit was previously set.

6. The memory device of claim 1, wherein the specified algorithm is selected by the host from one of a plurality of predetermined algorithms.

7. The memory device of claim 1, wherein the specified algorithm is provided by the host.

8. A method for operating a memory device including a memory storage means, the memory storage means having a first region and a second region, the method comprising: Identify the write command that writes the first data from the host to the first area; In response to recognizing a write command that writes first data from the host to the first area, a result value is calculated, the result value being calculated using the first data; and In response to calculating the result value, the result value is stored in the second area.

9. The method of claim 8, wherein calculating the result value and storing the result value are performed according to a specified strategy.

10. The method of claim 9, wherein the specified strategy comprises one of the following: an indication that the memory device will calculate the result value immediately after the write command; an indication that the memory device will calculate the result value if no other write is received within a specified time period; an indication that the memory device will calculate the result value immediately after the host attempts to read a valid bit; or an indication that the memory device will calculate the result value after a write to the second region.

11. The method of claim 8, further comprising clearing the valid bit after recognizing the write command and setting the valid bit after storing the result value.

12. The method of claim 11, further comprising setting the valid bit until the result value is stored and a predetermined amount of time has elapsed since the valid bit was previously set.

13. The method of claim 8, wherein the specified algorithm is selected by the host from one of a plurality of predetermined algorithms.

14. The method of claim 8, wherein the specified algorithm is provided by the host.

15. A non-transitory machine-readable medium storing instructions, said instructions, when executed by a memory controller of a memory device including a memory storage device having a first region and a second region, causing the memory controller to perform operations including: Identify the write command that writes the first data from the host to the first area; In response to recognizing a write command that writes first data from the host to the first area, a result value is calculated, the result value being calculated using the first data; and In response to calculating the result value, the result value is stored in the second area.

16. The non-transitory machine-readable medium of claim 15, wherein the calculation of the resulting value and the storage of the resulting value are performed according to a specified strategy.

17. The non-transitory machine-readable medium of claim 16, wherein the specified strategy comprises one of the following: an indication that the memory device will calculate the result value immediately after the write command; an indication that the memory device will calculate the result value if no other write is received within a specified time period; an indication that the memory device will calculate the result value immediately after the host attempts to read a valid bit; or an indication that the memory device will calculate the result value after a write to the second area.

18. The non-transitory machine-readable medium of claim 15, further comprising clearing the valid bit after recognizing the write command and setting the valid bit after storing the result value.

19. The non-transitory machine-readable medium of claim 18, further comprising setting the valid bit until the result value is stored and a predetermined amount of time has elapsed since the valid bit was previously set.

20. The non-transitory machine-readable medium of claim 15, wherein the specified algorithm is selected by the host from one of a plurality of predetermined algorithms.

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