Synchronization circuit for clock domain signals and system on chip

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By using a fast clock to perform high-frequency sampling and timing reference generation of a slow clock in the on-chip system, efficient synchronization of fast clock domain signals to the slow clock domain is achieved, solving the problem of high synchronization time overhead. This method is suitable for asynchronous clock domain communication in highly integrated SoCs.

CN121116892BActive Publication Date: 2026-06-12SILEAD +4

Patent Information

Authority / Receiving Office: CN · China
Patent Type: Patents(China)
Current Assignee / Owner: SILEAD
Filing Date: 2025-11-13
Publication Date: 2026-06-12

AI Technical Summary

Technical Problem

In on-chip systems, the synchronization time overhead is large when a fast clock domain signal is synchronized to a slow clock domain, especially when the frequency difference is large. Existing technologies require at least two slow clock cycles to complete the synchronization, resulting in large time and area overhead.

Method used

The first clock domain edge sampling module uses a fast clock to sample the slow clock at high frequency, capturing the edge of the slow clock within one fast clock cycle to generate a first indication signal. The synchronization clock generation module then determines the timing reference for cross-domain synchronization based on the first indication signal and the fast clock, generating a synchronization clock signal adapted to the slow clock domain in real time, thus shortening the synchronization time.

Benefits of technology

When the fast clock frequency is much higher than the slow clock frequency, the synchronization time does not exceed one slow clock cycle, which reduces time and area overhead and is suitable for scenarios with frequent asynchronous clock domain communication in highly integrated SoCs.

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Abstract

The present disclosure provides a clock domain signal synchronization circuit and a system on chip, and relates to the technical field of semiconductors. The clock domain signal synchronization circuit comprises: a first clock domain edge sampling module, comprising a first input end, a second input end and a first output end, the first input end being configured to access a first clock signal of a first clock domain, the second input end being configured to access a second clock signal of a second clock domain, and the first output end being configured to output a first indication signal; a synchronization clock generation module, comprising a third input end, a fourth input end and a second output end, the third input end being configured to access the first indication signal, the fourth input end being configured to access the second clock signal, and the first indication signal being configured to output, based on the second clock signal, a synchronization clock signal for synchronizing a second clock domain signal to the first clock domain from the second output end. Through the technical scheme of the present disclosure, the time cost of synchronizing a fast clock domain signal to a slow clock domain is shortened.

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