Multi-die integrated circuit with data processing engine array

Abstract

This provides a communication interface between data processing engine (DPE) arrays in a multi-die integrated circuit (IC). [Solution] The multi-die integrated circuit (IC) 100 includes an interposer and a first die 104 coupled to the interposer. The first die includes a data processing engine (DPE) array, the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also includes a second die 106 coupled to the interposer on which wire 116 is mounted. The second die includes a die interface. The DPE interface and the die interface communicate through the interposer.

Description

Technical Field

[0001] Technical Field The present disclosure relates to integrated circuits (ICs), and more particularly, to multi-die ICs including data processing engine arrays.

Background Art

[0002] Background Integrated circuits (ICs) can be implemented using a variety of different types of architectures. A single-die architecture is an architecture in which a single die is included within a package. The die can be homogeneous in that the die includes multiple similar or identical circuits. In other cases, the die can be heterogeneous in that the die includes a variety of different types of circuits and / or systems. A multi-die architecture is an architecture in which multiple dies are included within a single package. Within the package, the dies are communicatively coupled.

Summary of the Invention

Means for Solving the Problems

[0003] Summary In one aspect, a multi-die integrated circuit (IC) includes an interposer and a first die coupled to the interposer. The first die includes a data processing engine (DPE) array, and the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC can also include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.

[0004] In another embodiment, the multi-die IC includes a package substrate, a first die coupled to the package substrate, the first die configured as an interconnection bridge, and a second die coupled to the package substrate and the first die. The second die includes a DPE array, the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC may also include a third die coupled to the package substrate and the first die, the third die including a die interface. The DPE interface and the die interface are configured to communicate through the first die.

[0005] This summary section is provided solely to introduce a specific concept and is not intended to identify any important or essential features of the claimed subject matter. Other features of the present invention will become apparent from the accompanying drawings and the following detailed description.

[0006] Brief explanation of the drawing The configuration of the present invention is shown in the accompanying drawings as an example. However, the drawings should not be construed as limiting the configuration of the present invention to only the specific embodiments shown. Various aspects and advantages will become apparent when we consider the following detailed description and refer to the drawings. [Brief explanation of the drawing]

[0007] [Figure 1A] This figure shows an exemplary embodiment of a device having multiple dies. [Figure 1B] This figure shows an exemplary embodiment of a device having multiple dies. [Figure 2A] This figure shows another exemplary embodiment of a device having multiple dies. [Figure 2B] This figure shows another exemplary embodiment of a device having multiple dies. [Figure 3]This figure shows another exemplary embodiment of a device having multiple dies. [Figure 4] This figure shows an exemplary embodiment of a data processing engine (DPE) array. [Figure 5A] This figure shows an exemplary architecture of a DPE array. [Figure 5B] This figure shows an exemplary architecture of a DPE array. [Figure 6A] This figure shows an exemplary architecture of the logical interface tiles of the DPE interface. [Figure 6B] This figure shows an exemplary architecture of the logical interface tiles of the DPE interface. [Figure 6C] This figure shows an exemplary architecture of the logical interface tiles of the DPE interface. [Figure 7] This figure shows an exemplary embodiment of the interface of a logical interface tile. [Figure 8] This figure shows another exemplary embodiment of the interface of a logical interface tile. [Figure 9] This figure shows an exemplary embodiment of a direct memory access engine for logical interface tiles. [Figure 10] This figure shows an exemplary embodiment of a physical interface for a device having multiple dies. [Figure 11] This figure shows another exemplary embodiment of the physical interface of a device having multiple dies. [Figure 12] This figure shows another exemplary embodiment of the physical interface of a device having multiple dies. [Figure 13] This figure shows an exemplary embodiment including multiple DPE interfaces. [Figure 14] This figure shows another exemplary embodiment including multiple DPE interfaces. [Figure 15]This figure shows another exemplary embodiment including multiple DPE interfaces. [Figure 16] This figure shows another exemplary embodiment including multiple DPE interfaces. [Figure 17] This figure shows another exemplary embodiment including multiple DPE interfaces. [Modes for carrying out the invention]

[0008] Detailed explanation This disclosure is accompanied by claims defining novel features, but the various features described herein are to be better understood in conjunction with the drawings. The processes, machines, products, and any variations thereof described herein are provided for illustrative purposes only. The specific structural and functional details described herein should not be construed as limiting, but merely as the basis for the claims and as the basis for teaching those skilled in the art to employ various substantially any appropriately detailed structures. Furthermore, the terms and phrases used herein are not intended to be limiting, but are intended to provide an understandable description of the features described.

[0009] This disclosure relates to an integrated circuit (IC), and more particularly to a multi-die IC including a data processing engine (DPE) array. The DPE array, in combination with a DPE interface, comprises multiple hardwired and configurable components called data processing engines (DPEs). Refers to a circuit block. Each DPE can include a core that can perform data processing operations in combination with a memory module. The DPEs within the DPE array can communicate with each other through various different mechanisms. In one aspect, the DPEs can communicate with each other through a shared memory architecture in which the core can access a memory module within the same DPE and one or more other memory modules located in other different DPEs. In another aspect, the DPEs can communicate with each other through a stream switch that can carry a data stream between the DPEs. In yet another aspect, the cores of the DPE array may be directly connected by a cascade connection that allows one core to directly send data from the internal register of the core to one or more other cores of other DPEs within the DPE array.

[0010] The DPE interface implements circuit elements for one or more other circuits to communicate with the DPE array. These different circuits may be implemented within the same die as the DPE array, within other dies within the same package as the DPE array, or outside the package containing the DPE array. For example, in the context of a device implemented using one (or more) of the dies that includes the DPE array, the DPE interface facilitates communication with other circuits on the same die, one or more circuits implemented on different dies of the device, circuits outside the package containing the DPE array, or any combination of the above.

[0011] The DPE interface of the DPE array can include a logical interface and a physical interface. The logical interface can be implemented using a tile architecture in which each tile can communicate with a subset of the DPEs of the DPE array. The physical interface may be implemented using one or more different architectures as described herein with reference to the drawings. In some cases, the physical interface may be implemented using a standardized interface that allows different types of dies to be included in a package and communicate with the DPE array using the standardized interface.

[0012] Implementing the DPE array within a particular die or its own dedicated die and including various other types of dies within the same package provides significant flexibility to the IC designer. In this regard, the configurations of the present invention described within the present disclosure provide various advantages over other types of monolithic, single-die structures. For example, the die implementing the DPE array may be implemented using a particular type of process technology (e.g., feature size, technology node, or process node), while other dies communicatively coupled to the DPE array may be implemented using different process technologies. The term "process technology" refers to a particular semiconductor manufacturing process and its design rules for that particular semiconductor manufacturing process. Different process technologies often mean different circuit generations and architectures, and generally, with respect to process technology, the smaller the technology node, the smaller the feature size of the electronic components.

[0013] In one or more exemplary embodiments, different dies of the package may be included in different power domains. A power domain refers to circuit elements that are powered by the same power supply or power rail. Different power domains may have different potentials and may be turned on and / or off independently of other power domains. In the exemplary embodiments described herein, each die can turn on or off the power supply independently of one or more other dies.

[0014] In one or more exemplary embodiments, different dies in a package may be contained within different clock domains. A clock domain refers to a circuit element supplied by the same clock source. Different clock domains may have different clock sources and therefore can use clock signals independent of each other. For example, different clock domains The clock signals in the locked domain may have different clock frequencies and / or phases. In the exemplary embodiments described herein, each die is clocked by a different clock source and therefore can operate based on clock signals of different frequencies and / or phases.

[0015] Further aspects of the configuration of the present invention are described in more detail below with reference to the drawings. For simplicity and clarity, the elements shown in the drawings are not necessarily drawn to actual size. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, where appropriate, reference numerals are repeated between drawings to indicate corresponding, similar, or identical features.

[0016] Figures 1A and 1B together illustrate an exemplary embodiment of IC100. For illustrative purposes, Figures 1A and 1B may be collectively referred to as “Figure 1”. In the example of Figure 1, IC100 is implemented as a multi-die IC. Furthermore, one or more of the dies include a DPE array 110. In this disclosure, the term “multi-die IC” means an integrated circuit that is implemented to include two or more dies that are communicably coupled and contained within a single package.

[0017] Figure 1A shows a topographic diagram of IC100. In the example in Figure 1A, IC100 is implemented as a “stacked die” type device formed by stacking multiple dies. IC100 includes an interposer 102, die 104, die 106, and package substrate 108. Each of dies 104 and 106 is mounted on the surface of the interposer 102, for example, the top surface. In one embodiment, dies 104 and 106 are mounted on the interposer 102 using flip-chip technology. The interposer 102 is mounted on the top surface of the package substrate 108.

[0018] Generally, the interposer 102 is an intermediate die positioned between the dies 104, 106 and the package substrate 108. The interposer 102 is mounted to provide interconnection, routing, and / or ground / power surfaces. The package substrate 108 provides mechanical base support to the package and an electrical interface for connecting to nodes outside the package. The IC 100 may include cap portions not shown in Figure 1 or 2 for ease of illustration.

[0019] In the example shown in Figure 1A, the interposer 102 is a die having a flat surface on which dies 104 and 106 are stacked horizontally. As shown, dies 104 and 106 are located adjacent to each other on the flat surface of the interposer 102. The number of dies shown in the interposer 102 in Figure 1A is illustrative and not limiting. In other exemplary embodiments, three or more dies may be mounted on the interposer 102.

[0020] The interposer 102 provides a common mounting surface and electrical coupling to each of the dies 104 and 106. The manufacture of the interposer 102 may include one or more process steps that allow for the deposition of one or more conductive layers, which are patterned to form wires. These conductive layers may be formed from aluminum, gold, copper, nickel, various silicides, and / or other suitable materials. The interposer 102 may also be manufactured using one or more additional process steps that allow for the deposition of one or more dielectric or insulating layers, such as silicon dioxide. The interposer 102 may also include vias and through-beams (TVs). The TVs may be through-silicon vias (TSVs), through-glass vias (TGVs), or other via structures, depending on the specific materials used to mount the interposer 102 and its substrate. When the interposer 102 is mounted as a passive die, the interposer 102 may have various types of solder bumps, vias, wires, and T It may have only V and a subbump metallurgical layer (UBM). When the interposer 102 is implemented as an active die, the interposer 102 may include additional process layers that form one or more active elements, with reference to electrical elements such as transistors and diodes, which include PN junctions.

[0021] Die 104 is implemented as an active die and may include one or more DPE arrays 110. An active die is a die that includes one or more active elements. In one embodiment, die 104 may include only DPE arrays 110 (for example, only DPE arrays 110 that include any circuit elements necessary to communicate with other circuits located outside die 104). In another embodiment, die 104 may include DPE arrays 110 and additional circuit blocks that can perform other functions. Die 106 may be implemented as a passive die or an active die. For illustrative purposes, die 104 may include one or more DPE arrays 110, while die 106 implements one or more different subsystems. Exemplary subsystems are described herein. In one embodiment, die 106 may also include one or more DPE arrays 110. The examples provided herein are for illustrative purposes only and are not intended to limit the scope of the examples provided herein. IC100 may include, for example, three or more dies of different types and / or providing functions different from those described herein.

[0022] Figure 1B is a side cross-sectional view of IC100 in Figure 1A. Figure 1B shows IC100 in Figure 1A viewed along the cutting line 1B-1B. Each of the dies 104 and 106 is electrically and mechanically coupled to the first flat surface of the interposer 102 via solder bumps 112. In one example, the solder bumps 112 are implemented as microbumps. Furthermore, the dies 104 and 106 can be mounted to the interposer 102 using any of various other techniques. For example, the dies 104 and 106 can be mechanically and electrically mounted to the interposer 102 using bond wire or edge wire. In another example, the dies 104 and 106 can be mechanically mounted to the interposer 102 using adhesive material. The mounting of the dies 104 and 106 to the interposer 102 using solder bumps 112 is provided for illustrative purposes only and is not intended as an limitation, as shown in Figure 1B.

[0023] The interposer 102 includes one or more conductive layers 114, indicated as dashed or dotted lines within the interposer 102. The conductive layers 114 are mounted using one of the various metal layers described above. The conductive layers 114 are processed to form a patterned metal layer on which the wires 116 of the interposer 102 are mounted. Wires connecting at least two different dies, for example, dies 104 and 106, are called inter-die wires. In the example of Figure 1B, the wires 116 formed from the patterned metal layer 114 within the interposer 102 are inter-die wires. The wires 116 allow inter-die signals to pass between die 104 and die 106. For example, each of the wires 116 connects a solder bump 112 under die 104 to a solder bump 112 under die 106, thereby enabling the exchange of inter-die signals between die 104 and die 106. The wires 116 may also be data wires. In another embodiment, the wire 116 may include one or more power wires. The power wires may be wires that carry potential, or wires that have ground potential or reference potential.

[0024] Multiple different conductive layers 114 and wires 116 may be connected to each other using vias 118. Generally, via structures are used to implement vertical conductive paths. A vertical conductive path refers to a conductive path perpendicular to the process layer of the device. In this regard, the vertical portion of wire 116 that contacts the solder bump 112 is implemented as a via 118. By using multiple conductive layers to implement interconnections within the interposer 102, a greater number of signals can be routed, and more complex signal routing can be implemented within the interposer 102. It is possible to achieve this.

[0025] TV122 is a via that forms an extended electrical connection, for example, by perpendicularly traversing a substantial portion, if not the entire, of the interposer 102. TV122, like wires and vias, may be formed from any of a variety of different conductive materials, including but not limited to copper, aluminum, gold, nickel, various silicides, and / or other suitable materials. As shown in the figure, each TV122 extends from the bottom surface of the interposer 102 to the conductive layer 114 of the interposer 102. TV122 may further be combined with one or more vias 118 to bond to solder bumps 112 through one or more of the conductive layer 114.

[0026] Solder bumps 120 can be used to mechanically and electrically couple the second flat surface of the interposer 102 to the package substrate 108. In certain exemplary embodiments, the solder bumps 120 are implemented as fracture-suppression chip connection (C4) balls. The package substrate 108 includes conductive paths 124 that couple multiple different solder bumps 120 to one or more nodes and other circuit structures such as circuit boards beneath the package substrate 108. Thus, one or more of the solder bumps 120 couple the circuit in the interposer 102 to an external node of the IC 100 through circuit elements or wiring within the package substrate 108.

[0027] Figures 2A and 2B together show another exemplary embodiment of IC100. For illustrative purposes, Figures 2A and 2B may be collectively referred to as “Figure 2”. In the example of Figure 2, IC100 is implemented as a multi-die IC. Dies 104 and 106 may be implemented as described in relation to Figure 1. For example, die 104 may be an active die containing one or more DPE arrays 110. The circuit elements of die 104 may include only the DPE arrays 110 that contain any circuit elements necessary to communicate with nodes located outside die 104. In another example, die 104 may include the DPE arrays 110 and additional circuit elements. Die 106 may be active or passive. Die 106 may also contain one or more DPE arrays.

[0028] Figure 2A shows a topographic diagram of IC100. In the example in Figure 2A, dies 104 and 106 are communicatively connected by a bridge die 202. The bridge die 202 may be embedded within the package substrate 108. An example of the bridge die 202 is the Embedded Multi-Die Interconnect Bridge (EMIB), available from Intel Corporation in Santa Clara, California. It should be understood that the exemplary bridge dies provided herein are for illustrative purposes only and are not limiting.

[0029] The package substrate 108, including the bridge die 202, provides a common mounting surface and electrical coupling for each of the dies 104 and 106. The bridge die 202 mounts interconnection circuit elements, such as one or more patterned metal layers, which enable the die 104 to communicately connect to the die 106. In one embodiment, the bridge die 202 is a passive die. In another embodiment, the bridge die 202 is an active die. The dies 104 and 106 are located adjacent to each other on a flat surface formed by the package substrate 108 and the bridge die 202. The number of dies shown in Figure 2A is illustrative and not limiting. In other exemplary embodiments, three or more dies may be mounted on the package substrate 108 and communicately connected by additional bridge dies 202.

[0030] In the example in Figure 2A, die 104 may be implemented as an active die including one or more DPE arrays 110. Die 106 may be implemented as a passive die or an active die. Die 106 includes one or more additional DPE arrays as described herein. It may be configured to implement any of several different subsystems. The examples provided herein are illustrative and not intended to limit you. For example, IC100 in Figure 2 may include three or more dies of different types and / or functions.

[0031] Figure 2B is a side cross-sectional view of IC 100 in Figure 2A. Figure 2B shows IC 100 in Figure 2A as seen along the cutting line 2B-2B. Dies 104 and 106 are electrically and mechanically coupled to the first flat surface of the package substrate 108 and the first surface of the bridge circuit 202 via solder bumps 204 and 206. In one example, solder bumps 204 and / or 206 are mounted as microbumps. In one embodiment, the solder bumps used to connect dies 104 and 106 to the package substrate 108 may be larger in size and / or have a greater spacing than the solder bumps used to connect dies 104 and 106 to the bridge die 202. For example, solder bumps 206 may be closer together and further apart than solder bumps 204.

[0032] The bridge die 202 implements a circuit element that connects die 104 to die 106 in a communicative manner. Therefore, signals exchanged between die 104 and die 106 are carried through the bridge die 202. In this regard, the inter-die wire 116 in the example of Figure 2B is implemented within the bridge die 202. In one exemplary embodiment, the bridge die 202 includes a short interconnect wire for communicatively connecting die 104 to die 106. The bridge die 202 does not include any TVs that enable communication between die 104 and solder bump 208 or between die 106 and solder bump 208. That is, the bridge die 202 is reserved and used solely for communication between die 104 and die 106 and does not provide any access by die 104 or die 106 to any nodes outside of IC 100.

[0033] In the example in Figure 2B, dies 104 and 106 communicate with circuit elements outside the package via package traces 210, for example, via solder bumps 208. In an example where the bridge die 202 is implemented as an active die, the bridge die may be coupled to one or more of the solder bumps 208 by one or more additional package traces 210, which are not shown in Figure 2B.

[0034] In one exemplary embodiment, as described in relation to Figures 1 and / or 2, IC 100 may be implemented such that dies 104 and 106 are on the same power domain. In another exemplary embodiment, dies 104 and 106 in Figures 1 and / or 2 may be implemented in different power domains and may be powered on and off independently of each other. Furthermore, as described, when dies 104 and 106 are implemented in different power domains, they can operate at different voltage levels. When operating at different voltage levels, dies 104 and 106, the interposer 102, and / or the bridge die 202 may include appropriate interface circuit elements that allow signals to pass between different power domains.

[0035] In another exemplary embodiment, as described in relation to Figures 1 and / or 2, IC 100 may be implemented such that dies 104 and 106 operate as part of the same clock domain. Thus, dies 104 and 106 in Figures 1 and / or 2 may be implemented in different clock domains and therefore may be clocked at different frequencies.

[0036] In one exemplary embodiment, as described in relation to Figures 1 and / or 2, the IC 100 is implemented such that dies 104, 106, interposer 102, and / or bridge die 202 are implemented using different process technologies (e.g., having different feature sizes). For example, die 104, which includes the DPE array 110, may be implemented using 3nm process technology, while die 106 is implemented using 16nm technology.

[0037] Figure 3 shows another example of IC100. In the example in Figure 3, only dies 104 and 106 are shown. In one embodiment, dies 104 and 106 may be coupled by an inter-die wire 116 using an interposer as described in relation to Figure 1. In another embodiment, dies 104 and 106 may be coupled by an inter-die wire 116 using a bridge die embedded in the package substrate, as described in relation to Figure 2.

[0038] Die 104 includes a DPE array 110. The DPE array 110 includes a DPE interface 302 having a logical interface 304 and a physical interface 306. Die 106 includes a die interface 308 having a logical interface 310 and a physical interface 312. An inter-die wire 116 can connect physical interface 306 to physical interface 312. The inter-die wire 116 may be implemented within an interposer or bridge die as described above.

[0039] In the example shown in Figure 3, the physical interface 306 may be implemented using one or more different techniques, as described in more detail herein. In exemplary embodiments, the physical interface 306 is implemented as a parallel interface having one or more channels. In some cases, the channels may operate independently of each other and use separate clocking. Examples of parallel interfaces may include, but are not limited to, embodiments using one or more Laguna sites (available from Xilinx, Inc., San Jose, California) and embodiments using one or more high-bandwidth memory (HBM) interfaces. In another exemplary embodiment, the physical interface 306 may be implemented using one or more high-speed serial transceivers. Such transceivers may be capable of sending and receiving serialized data at gigabit-range speeds.

[0040] Figure 4 shows an exemplary embodiment of a DPE array 110. In the example of Figure 4, the DPE array 110 is implemented as a plurality of interconnected programmable DPEs 402. The DPEs 402 can be arranged in an array and wired together. Each DPE 402 may include one or more cores 404 and memory modules (abbreviated as "MM" in Figure 4) 406. In one embodiment, each core 404 can execute program code (e.g., computer-readable or executable instructions) stored in core-specific program memory (not shown) contained within each of its respective cores. Each core 404 can directly access memory modules 406 within the same DPE 402, and memory modules 406 of any other DPE 402 adjacent to the core 404 of the DPE 402 in the up, down, left, or right directions. For example, core 404-5 can directly read and / or write memory modules 406-5, 406-8, 406-6, and 406-2 (e.g., via their respective memory interfaces, not shown). Core 404-5 considers each of the memory modules 406-5, 406-8, 406-6, and 406-2 as a unified area of ​​addressable memory (e.g., a portion of local memory accessible to core 404-5). This facilitates data sharing between different DPEs 402 within the DPE array 110. In other examples, core 404-5 may be directly connected to a memory module 406 in another DPE.

[0041] The DPE402 is interconnected by programmable DPE interconnects. These programmable DPE interconnects can be used together to form one or more different, independent networks. For example, programmable DPE interconnects can be used together to form a streaming network (shaded arrow) formed from streaming connections, and a memory-mapped network (shaded arrow) formed from memory-mapped connections.

[0042] Each DPE402 and its components can be controlled independently by loading configuration data into the control registers of the DPE402 via a memory-mapped connection. Each DPE402 can be enabled / disabled individually. Each core 404 can be configured to access only the memory module 406 or a subset thereof, as described, to achieve isolation of a core 404 or multiple cores 404 operating as a cluster. Each streaming connection can be configured to establish a logical connection between selected DPE402s only, to achieve isolation of a DPE402 or multiple DPE402 operating as a cluster. Each core 404 can load program code specific to that core 404, so each DPE402 can implement one or more different kernels within it.

[0043] In other embodiments, programmable DPE interconnects within the DPE array 110 may include additional independent networks, such as a debug network and an event broadcast network, which are independent of each other and of the streaming and memory-mapped connections (e.g., clearly distinct and separate from these). In some embodiments, the debug network is formed from and / or is part of the memory-mapped connections.

[0044] A core 404 can be directly connected to one or more adjacent cores 404 via a cascading connection. In one embodiment, a cascading connection is a one-way direct connection between cores 404. Generally, a cascading connection is a direct inter-core connection that allows one core 404 to directly share data with another core 404. For example, through a cascading connection, content stored in the internal registers of core 404-2 can be directly provided to core 404-3 or core 404-5. Similarly, through a cascading connection, core 404-5 can directly receive content from the internal registers of core 404-6 or core 404-2.

[0045] In one exemplary embodiment, a core 404 transmitting content (e.g., a source core) can transmit the content directly from its internal registers via a cascaded connection. Similarly, the content may be received directly in the internal registers of a receiving core (e.g., a target core). In the exemplary embodiment, the internal registers may be the core's accumulation registers, or other internal registers that can be connected to (e.g., directly) and / or supplied to the accumulation registers. Each of the cascaded connections may be enabled or disabled independently, for example, separately, by loading configuration data into the control registers of their respective DPE 402s.

[0046] In exemplary embodiments, DPE 402 does not include cache memory. By omitting cache memory, the DPE array 110 can achieve predictable, for example, deterministic performance. Furthermore, significant processing overhead is avoided because there is no need to maintain consistency between cache memories located in different DPE 402s. In further examples, core 404 does not have input interrupts. Therefore, core 404 can operate without interruption. Omitting input interrupts to core 404 also enables the DPE array 110 to achieve predictable, for example, deterministic performance.

[0047] The DPE interface block 302 acts as an interface connecting the DPE 402 to other circuit elements. In the example in Figure 4, the other circuit elements include circuit blocks located within dies other than the die containing the DPE array 110. In the example in Figure 4, the logical interface 304 of the DPE interface block 302 includes multiple interconnected tiles 408 arranged in a row. In a particular example, within the DPE interface block 302... Different architectures can be used to implement tile 408, where each different tile architecture supports communication with different resources of IC100. Tiles 408 are connected so that data can propagate bidirectionally from one tile to another. Each tile 408 can act as an interface to the column of DPE402 directly above it.

[0048] Tile 408 is connected to adjacent tiles, the DPE 402 directly above it, and circuit elements below it, such as the physical interface 306, using streaming and memory-mapped connections as shown in the figure. Tile 408 may also include a debug network that connects to a debug network implemented within the DPE array 110. Tile 408 can transmit data from the DPE 402 to other circuit blocks of IC 100 via the physical interface 306. The physical interface 306 can communicate with such other circuit blocks of IC 100 via the die-to-die wire 116 as described above. Examples of other circuit blocks of IC 100 that may be included in die 106 are, but are not limited to, one or more processors or processor systems, programmable logic, one or more hardwired circuit blocks, and / or programmable network-on-chip (NoC).

[0049] Tile 408 can transmit data from other circuit blocks to DPE 402. Tile 408-1 can, for example, transmit data addressed to DPE 402 in other columns to other tiles 408, such as 408-2 or 408-3, while providing those portions of data addressed to DPE 402 in the column above to such DPE 402, regardless of the application or configuration. As a result, such tiles 408 can therefore route the data addressed to DPE 402 in each column.

[0050] It should be understood that in one or more other exemplary embodiments, one or more tiles or all of the tiles 408 may also include connections to circuit elements and / or circuit blocks located on die 104. For example, one or more of the tiles 408 may utilize memory-mapped connections and / or streaming connections to connect to circuit blocks located within die 104. In another example, the DPE array 110 may include several columns of DPE 402 that communicate with tiles 408 that connect to circuit elements located within the same die as the DPE array 110 (e.g., die 104), and other columns of DPE 402 that communicate with tiles that connect to circuit elements located on a different die than the die containing the DPE array 110 (e.g., to circuit elements in die 106).

[0051] As described, examples of other types of circuit elements include, but are not limited to, hardwired circuit blocks such as programmable logic, processor systems, NoCs, platform management controllers, and / or application-specific integrated circuits (ASICs). Programmable logic is a circuit element that can be programmed to perform a specified function. As an example, programmable logic may be implemented as a field-programmable gate array type circuit element. Programmable logic can include an array of programmable circuit blocks. Where defined herein, the term “programmable logic” means a circuit element used to construct a reconfigurable digital circuit. Programmable logic is formed from many programmable circuit blocks that provide basic functionality. The topology of programmable logic is highly configurable, unlike that of hardwired circuit elements. Each programmable circuit block of programmable logic typically includes a programmable functional element and a programmable interconnect. The programmable interconnect provides the highly configurable topology of the programmable logic. The programmable interconnect provides the programmable functionality of the programmable circuit blocks of the programmable logic. Unlike connections between DPE402s, which can be configured on a per-wire basis to provide connections between functional elements and can communicate via packetized data through a stream switch, for example, they can be configured on a per-bit basis (e.g., each wire carries 1 bit of information).

[0052] Before use, programmable logic must be programmed or “configured” by loading data called a configuration bitstream into an internal configuration memory cell. Once the configuration bitstream is loaded into the configuration memory cell, it defines how the programmable logic is configured and how it operates (e.g., specific functions to be performed), such as its topology. In this disclosure, “configuration bitstream” is not equivalent to program code executable by a processor or computer.

[0053] A processor system refers to a hardwired circuit element fabricated as part of a die. A processor system may be implemented as, or include, one or more processors capable of executing program code. A processor may include multiple different types of processors (e.g., application processors, real-time processors, etc.). In one example, a processor system is implemented as individual processors, such as a single core capable of executing program code. In another example, a processor system is implemented as a multi-core processor. In yet another example, a processor system includes one or more processors, whether or not they include one or more cores, modules, coprocessors, I / O interfaces, and / or other resources. A processor system may be implemented using any of several different types of architectures. Exemplary architectures that may be used to implement a processor system include, but are not limited to, ARM processor architectures, x86 processor architectures, graphics processing unit (GPU) architectures, mobile processor architectures, DSP architectures, combinations of the aforementioned architectures, or other suitable architectures capable of executing computer-readable instructions or program code (e.g., user applications).

[0054] NoC refers to a programmable interconnect network for sharing data between endpoint circuits within IC100. The endpoint circuits can be located within the DPE array 110 or within any of the various types of circuit blocks and / or resources of IC100 described herein (e.g., programmable logic, processor systems, and / or hardwired circuit blocks). NoC may include high-speed data paths with dedicated switching. For example, NoC may include one or more horizontal paths, one or more vertical paths, or both horizontal and vertical paths.

[0055] Within the NoC, the nets to be routed through the NoC are unknown until a user circuit design for implementation within IC100 is created. The NoC can be programmed by loading configuration data into internal configuration registers that defines how elements within the NoC, such as switches and interfaces, are configured and operate to pass data between switches and between NoC interfaces to connect endpoint circuits. Although the NoC is fabricated as part of IC100 (e.g., wired) and therefore not physically modifiable, it can be programmed to establish connections between multiple different master circuits and multiple different slave circuits of a user circuit design. In some cases, the NoC may not implement any data paths or routes within itself at power-up. However, once configured, the NoC will implement data paths or routes between endpoint circuits.

[0056] Another example of a circuit block is a Platform Management Controller (PMC). C is a circuit block that can manage IC100. For example, PMC may be implemented as a subsystem within IC100 that can manage other circuit resources throughout IC100. PMC can maintain a safe and secure environment, boot IC100, and manage IC100 during normal operation. For example, PMC can provide integrated programmable control over powering, booting / configuring, security, power management, safety monitoring, debugging, and / or error handling of multiple different circuit resources of IC100 (e.g., DPE array 110, programmable logic, NoC, and / or hardwired circuit blocks). PMC can act as a dedicated platform manager that separates the processor system from the programmable logic. Thus, the processor system and programmable logic can be managed, configured, and / or powered off and / or turned off independently of each other.

[0057] The PMC may be implemented as a processor with dedicated resources. The PMC may include multiple redundant processors. The processors of the PMC can run firmware. The use of firmware supports the configurability and segmentation of global functions of IC100, such as reset, clocking, and protection, to provide flexibility in creating separate processing domains (distinguished from “power domains” which may be die and / or subsystem-specific). A processing domain may include a mixture or combination of one or more different programmable circuit resources of IC100 (for example, a processing domain or partition may include different combinations or devices from the DPE array 110, processor system, programmable logic, NoC, and / or hardwired circuit blocks).

[0058] Hardwired circuit blocks include dedicated circuit blocks fabricated as part of IC100. While wired, hardwired circuit blocks can be configured by loading configuration data into control registers to implement one or more different operating modes. Examples of hardwired circuit blocks include input / output (I / O) blocks, transceivers for sending and receiving signals to and from circuits and / or systems outside IC100, and memory controllers. Examples of multiple different I / O blocks include single-ended and pseudo-differential I / O. Examples of transceivers include high-speed differential clock transceivers. Other examples of hardwired circuit blocks include, but are not limited to, cryptographic engines, digital-to-analog converters (DACs), and analog-to-digital converters (ADCs). Generally, hardwired circuit blocks are application-specific circuit blocks.

[0059] When the DPE array 110 is mounted on die 104, it may be coupled to any of the various other types of circuits not described. For example, die 104 may contain or be coupled to a die that includes RAM, other special circuit elements (e.g., ASICs), modems, transceivers, etc.

[0060] Figures 5A and 5B show an exemplary architecture of DPE402 in DPE array 110. For illustrative purposes, Figures 5A and 5B may be collectively referred to as "Figure 5".

[0061] Referring to Figure 5A, the DPE 402 includes a core 404 and a memory module 406. The DPE 402 further includes a DPE interconnect, which includes a stream switch 502 and a memory-mapped switch 504.

[0062] Core 404 provides the data processing capability for DPE402. Core 404 may be implemented as one of several different processing circuits. In the example in Figure 5, Core 404 is optional. The core includes program memory 506. In one or more exemplary embodiments, the core 404 is implemented as a processor capable of executing program code, such as computer-readable instructions. The program memory 506 can store instructions executed by the core 404. The core 404 may be implemented as, for example, a CPU, GPU, DSP, vector processor, or other type of processor capable of executing instructions. The core may be implemented using any of the various CPU and / or processor architectures described herein. In another example, the core 404 is implemented as a very long instruction word (VLIW) vector processor or DSP.

[0063] In certain exemplary embodiments, program memory 506 is implemented as dedicated program memory for core 404. Program memory 506 may be used only by cores of the same DPE 402. Thus, program memory 506 can only be accessed by core 404 and is not shared with any other DPE 402 or components of another DPE 402 within the DPE array 110. Program memory 506 may include a single port for read and write operations and is addressable using the memory-mapped network portion of the DPE array 110 via memory-mapped switch 504. Program code may be loaded into program memory 506, for example, by a master circuit outside the DPE array 110 via memory-mapped switch 504. The program code loaded into program memory 506 may be executed by core 404.

[0064] In one or more exemplary embodiments, the core 404 may have an architecture customized to support application-specific instruction sets. For example, the core 404 may be customized for wireless applications and configured to execute wireless-specific instructions. In another example, the core 404 may be customized for machine learning and configured to execute machine learning-specific instructions.

[0065] In one or more other exemplary embodiments, core 404 is implemented as a hardwired circuit element, such as a hard intellectual property (IP) core dedicated to performing a specific operation. In that case, core 404 does not need to execute program code. In embodiments where core 404 does not execute program code, program memory 506 may be omitted. As an exemplary and non-limiting example, core 404 may be implemented as a hard forward error correction (FEC) engine or other circuit block.

[0066] In some exemplary embodiments, different DPEs 402 of the DPE array 110 may include different types of cores 404. For example, one or more cores 404 may be implemented to execute program code, while the cores 404 of other DPEs 402 may not be able to execute program code. In any case, each core 404 is configured to perform computations, whether by execution of program code / instructions or not, and may include internal registers or registers 526 that can be used with the cascading connections described herein.

[0067] The core 404 may include a control register 508. The control register 508 can be loaded with configuration data for controlling the operation of the DPE 402. For example, the configuration data loaded into the control register 508 can configure and / or control the operation of the core 404, memory module 406, stream switch 502, and cascade interfaces 522, 524 of the DPE 402, which are described in more detail herein. In one or more exemplary embodiments, the DPE 402 may be activated and / or deactivated, for example, as a whole, based on the configuration data loaded into the control register 508. Similarly, the core 404 may be activated based on the configuration data loaded into the control register 508. Core 404 may be activated and / or deactivated independently of memory module 406 so that memory module 406 can be accessed by one or more other cores. In the example in Figure 5A, control register 508 is addressable (e.g., can be read and / or written) via a memory-mapped network through memory-mapped switch 504. Deactivation refers to putting a circuit block into a low-power mode, or cutting off power (e.g., supply voltage) from the circuit block.

[0068] In one or more exemplary embodiments, the memory module 406 may store data used and / or generated by the core 404 (or another core of another DPE 402), which is referred to herein as application data. The memory module 406 may include read / write memory, such as random access memory. Thus, the memory module 406 may store data that can be read and consumed by the core 404. The memory module 406 may also store data (e.g., results) that is written by the core 404.

[0069] In one or more other exemplary embodiments, the memory module 406 can store data, such as application data, that may be used and / or generated by one or more other cores 404 of other DPEs 402 in the DPE array 110. One or more other cores 404 of DPEs 402 can also read from and / or write to the memory module 406. In certain exemplary embodiments, the other cores 404 that can read from and / or write to the memory module 406 may be cores 404 of one or more neighboring DPEs 402. Another DPE (e.g., an adjacent DPE) that shares a boundary or border with the memory module 406 of DPE 402 in Figure 5A is said to be a “neighboring” DPE with respect to DPE 402 in Figure 5A. By enabling one or more other cores 404 from core 404 in Figure 5A and adjacent DPEs (for example, the DPEs above, below, left, and right of the target DPE 402 in Figure 5A) to read from and write to memory module 406, memory module 406 implements shared memory that supports communication between different DPEs 402 and / or cores 404 that can access memory module 406.

[0070] In one or more exemplary embodiments, the DPE interconnection circuit elements of the DPE array 110 include two distinct networks. The first network can exchange data with other DPEs 402 and / or other systems of IC 100 of the DPE array 110. For example, the first network can exchange application data. The second network can exchange data such as configuration, control, and / or debug data for the DPE(s) 402.

[0071] In the example in Figure 5, the first network of DPE interconnection circuit elements is formed from stream switch 502 and one or more stream switches of other DPEs 402. As shown, stream switch 502 is coupled to the stream switches of DPEs 402 located above, below, to the left, and to the right of DPE 402 in Figure 5A. When DPE 402 in Figure 5A is in the bottom row, stream switch 502 is coupled to tile 408 of DPE interface 302.

[0072] The stream switch 502 is coupled to the core 404 and can communicate with the core 404. The core 404 includes a stream interface that connects to the stream switch 502, thereby enabling the core 404 to communicate directly with other DPEs 402 via DPE interconnect circuit elements. For example, the core 404 enables the core 404 to send and / or receive application data directly through the stream switch 502. It may include instructions or hardwired circuit elements.

[0073] The stream switch 502 is coupled to the memory module 406 and can communicate with the memory module 406. The memory module 406 includes a stream interface that connects, for example, to the stream switch 502, thereby enabling other DPEs 402 to communicate with the memory module 406 in Figure 5 via the DPE interconnect circuit element. The stream switch 502 can enable DPEs that are not adjacent and / or not coupled to the memory interface of the memory module 406 in Figure 5A to communicate with the core 404 and / or the memory module 406 via the DPE interconnect circuit element, which includes the stream switch of each DPE 402 in the DPE array 110. Thus, the core 404 and / or the memory module 406 in Figure 5 can also communicate with any of the DPEs 402 in the DPE array 110 via the DPE interconnect circuit element in the DPE 402.

[0074] The stream switch 502 may also be used to communicate with other subsystems such as programmable logic, NoC, or other circuit blocks. Generally, the stream switch 502 may be programmed to operate as a circuit-switched stream interconnect or a packet-switched stream interconnect. A circuit-switched stream interconnect can implement a point-to-point dedicated stream suitable for high-bandwidth communication between DPEs 402. A packet-switched stream interconnect allows for the sharing of streams and time-multiplexing of multiple logical streams into a single physical stream for medium-bandwidth communication.

[0075] The stream switch 502 may be configured via a control register 508. The configuration data loaded into the control register 508 indicates, for example, which other DPE402 and / or IC100 systems the DPE402 in Figure 5A will communicate with, and whether such communication will be established as a circuit-switched point-to-point connection or a packet-switched connection.

[0076] A second network of DPE interconnect circuit elements is formed from the memory-mapped switch 504, which is connected to other memory-mapped switches of the DPE array 110. Each component of the DPE 402 in Figure 5 that can be read and / or written, such as the control register 508, program memory 506, and memory module 406, may be read or written using the mapped switch 504. The memory-mapped switch 504 may also be used to exchange configuration, control, and debug data for the DPE 402. In the example in Figure 5, the memory-mapped switch 504 can receive configuration data used to configure the DPE 402. The memory-mapped switch 504 may receive configuration data from the memory-mapped switch of the DPE 402 located below the DPE 402 in Figure 5, and / or from the DPE interface 302 (for example, if the DPE 402 in Figure 5 is located in the bottom row of the DPE array 110). The memory-mapped switch 504 can transfer the received configuration data to one or more other DPEs 402 above the DPE 402 in Figure 5, to the core 404 in Figure 5 (e.g., to the program memory 506 and / or control register 508), and / or to the memory module 406 in Figure 5 (e.g., to the memory within the memory module 406). Thus, the memory-mapped switch 504 in Figure 5 communicates with the memory-mapped switches of the DPE 402 or tile 408 of the lower DPE interface 302 and / or the memory-mapped switches of the upper DPE 402.

[0077] Considering them together, the DPE interconnections of the various DPEs 402 in the DPE array 110 form a DPE interconnection network (which may include a stream network and / or a memory-mapped network). Each DPE 402 has a control register 508 This may be programmed by loading configuration data through each memory-mapped switch 504. Through the configuration, the stream switch 502 and / or stream interface are programmed to establish connections with other endpoints, whether packet-switched or circuit-switched, whether they are located within one or more other DPE 402 and / or DPE interface 302.

[0078] For example, the DPE array 110 may be mapped to the address space of a processor (e.g., a processor system or a processor in a PMC). Therefore, any control registers and / or memories within the DPE 402 of the DPE array 110 may be accessed via a memory-mapped interface. For example, the memory in memory module 406, program memory 506, and / or control register 508 may be read and / or written via memory-mapped switches 504 within their respective DPE 402s.

[0079] The memory-mapped switch 504 in Figure 5, in combination with other memory-mapped switches 504 of the DPE402, implements a shared transaction exchange network where transactions propagate from memory-mapped switch to memory-mapped switch. Each of the memory-mapped switches 504 can dynamically route transactions based, for example, on an address. The memory-mapped switches 504 enable other subsystems of the IC100 to access resources (e.g., components) of the DPE402.

[0080] In the example in Figure 5, the memory module 406 comprises several memory interfaces 510-1, 510-2, 510-3, and 510-4. In Figure 5, memory interfaces 510-1 and 510-2 are abbreviated as "MI". The memory module 406 further comprises several memory banks 512-1 to 512-N. In a particular exemplary embodiment, the memory module 406 comprises eight memory banks. In other exemplary embodiments, the memory module 406 may comprise fewer or more memory banks 512. In the example in Figure 5, each of the memory banks 512-1 to 512-N has its own arbiter 514-1 to 514-N. Each arbiter 514 may include arbitration logic. Furthermore, each arbiter 514 may include a crossbar. Thus, any master can write to any particular one or more of the memory banks 512.

[0081] The memory module 406 may include a memory-mapped interface (not shown) that communicates with the memory-mapped switch 504. The memory-mapped interface within the memory module 406 may be connected to communication lines within the memory module 406 that are coupled to the direct memory access (DMA) engine 516, the memory interface 510, and the arbiter 514 for reading and / or writing to the memory bank 512.

[0082] The DMA engine 516 may include two or more interfaces. For example, one or more interfaces may receive input data streams from stream switches 502 in other DPEs 402 that write received data to memory bank 512. One or more other interfaces may read data from memory bank 512 and send the data to other DPEs 402 via the stream interfaces of the DMA engine 516.

[0083] The memory module 406 can operate as shared memory that can be accessed by multiple different DPEs 402. In the example in Figure 5A, the memory interface 510-1 is coupled to the core 404 via the core interface 518-1 included in the core 404. The memory interface 510-1 is connected to the memory via the arbiter 514. The memory interface 510-2 provides the core 404 with access to memory bank 512 (e.g., read and write capabilities). The memory interface 510-2 is coupled to the core interface of DPE402 in the DPE array 110 above DPE402 in Figure 5. The memory interface 510-2 provides the core 404 of DPE402 above DPE402 in Figure 5 with access to memory bank 512. The memory interface 510-3 is coupled to the core interface of DPE402 in the DPE array 110 to the right of DPE402 in Figure 5. The memory interface 510-3 provides the core 404 of DPE402 to the right of DPE402 in Figure 5 with access to memory bank 512. The memory interface 510-4 is coupled to the core interface of DPE402 in the DPE array 110 below DPE402 in Figure 5. The memory interface 510-4 provides the core 404 of the DPE402, located below the DPE402 in Figure 5, with access to the memory bank 512.

[0084] Core 404 can access the memory modules of other neighboring DPEs via core interfaces 518-2, 518-3, and 518-4. In the example in Figure 5, core interface 518-2 is coupled to the memory interface of the lower DPE402 in Figure 5. Therefore, core 404 can access the memory module 406 of the lower DPE402 in Figure 5. Core interface 518-3 is coupled to the memory interface of the left DPE402 in Figure 5. Therefore, core 404 can access the memory module 406 of the left DPE402 in Figure 5. Core interface 518-4 is coupled to the memory interface of the upper DPE402 in Figure 5. Therefore, core 404 can access the memory module 406 of the upper DPE402 in Figure 5.

[0085] As described above, core 404 can map read and / or write operations in the correct direction through core interfaces 518-1, 518-2, 518-3, and / or 518-4 based on the address of such operations. Once core 404 generates an address for a memory access, core 404 can decode the address to determine the direction (e.g., the specific DPE 402 to be accessed) and transfer the memory operation to the correct core interface in the determined direction.

[0086] The memory module 406 may include a hardware synchronization circuit element (HSC) 520. Generally, the HSC 520 can synchronize the operation of different cores 404 (e.g., a core 404 in a neighboring DPE 402), the core 404 in Figure 5, the DMA engine 516, and other external masters (e.g., processors) that can communicate with DPEs such as the DPE 402 in Figure 5A via DPE interconnect circuit elements. As an exemplary and non-limiting example, the HSC 520 can synchronize two different cores 404 in different DPEs 402 that access the same, for example, a shared buffer, in the memory module 406 in Figure 5A. The HSC 520 may be accessed by the core 404 and / or the core of a neighboring DPE (e.g., a core 404 in another DPE 402 connected to the memory interface 510), and / or by the memory-mapped switch 504 of the other DPE 402.

[0087] In addition to communicating with neighboring DPE 402s through the shared memory module 406 via DPE interconnect circuit elements and through adjacent and / or non-adjacent DPE 402s, core 404 may include one or more cascading interfaces 522, 524, such as cascading inputs (indicated as "CI" 522) and cascading outputs (indicated as "CI" 524). Cascading interfaces 522 and 524 can provide direct communication with other cores 404s of adjacent DPE 402s. As illustrated, the cascading interface 522 of core 405 receives an input data stream directly from a core 404 of an adjacent DPE 402 (e.g., a DPE 402 to the left, above, or below). The data stream received via the cascade interface 522 can be provided to the data processing circuitry in the core 404. The cascade interface 524 of the core 404 can directly transmit the output data stream to the core 404 of an adjacent DPE 402 (e.g., a DPE 402 to the right, above, or below).

[0088] In the example in Figure 5, each of the cascade interfaces 522 and 524 may include a first-in, first-out (FIFO) interface for buffering (not shown). In the exemplary embodiment, the cascade interfaces 522 and 524 can carry data streams that may be several hundred bits wide. The specific bit widths of the cascade interfaces 522 and 524 are not intended to be limiting. In the example in Figure 5, the cascade interface 522 is coupled to an internal register 526 in the core 404. The internal register 526 can store data generated and / or calculated by data processing circuit elements in the core 404.

[0089] In one embodiment, internal register 526 may be a accumulating register. The accumulating register of core 404 is an internal register in which intermediate results of calculations performed by core 404 can be stored. The accumulating register allows core 404 to store such intermediate calculation results without having to write such content / data to another memory located outside core 404. In another embodiment, internal register 526 is another register that may be connected to the accumulating register. For example, internal register 526 may be a register that is connected to the accumulating register and is specifically accessible to receive data via cascading interface 522, write data to the accumulating register via cascading interface 524, and / or output data from the accumulating register. Cascading interface 524 can output the contents of internal register 526, and can output them per clock cycle.

[0090] In the example shown in Figure 5, cascade interfaces 522 and 524 can be programmed based on configuration data loaded into the control register 508. For example, cascade interface 522 can be activated or deactivated based on the control register 508. Similarly, cascade interface 524 can be activated or deactivated based on the control register 508. Cascade interface 522 may be activated and / or deactivated independently of cascade interface 524.

[0091] In exemplary embodiments, cascade interfaces 522 and 524 are controlled by core 404. For example, core 404 may include instructions for reading from and writing to cascade interfaces 522 and / or 524. In another example, core 404 may include hardwired circuitry that can read from and / or write to cascade interfaces 522 and / or 524. In certain exemplary embodiments, cascade interfaces 522 and 524 may be controlled by entities outside of core 404.

[0092] In one or more exemplary embodiments, the DPE array 110 may be functionally separated into multiple groups, e.g., clusters, of one or more DPE 402s. For example, a particular core interface 518 and / or memory interface 510 can be enabled and / or disabled via configuration data to create one or more clusters of DPE 402s, each cluster comprising one or more DPE 402s of the DPE array 110 (e.g., a subset), a memory module 406 of a selected DPE 402, a core 404 of a selected DPE 402, or a different combination thereof. In addition, or in an alternative form, the stream interface may comprise other cores 404 and / or other DPE 402s within the same cluster. Alternatively, each cluster can be independently configured to communicate with the memory module 406 and / or with specified input sources and / or output destinations (for example, only with them). In addition, or in an alternative configuration, the cascade interfaces 522, 524 may be configured so that only cores 404 within the same cluster can communicate through the cascade interfaces 522, 524. This effectively isolates the clusters of the DPE 402 so that different clusters can independently and separately run different applications.

[0093] It should be understood that DPE402 can be organized into clusters, thereby allowing a specific DPE402(or all DPE402(or all)) in a cluster to connect to other DPE402 within the same cluster through one or more or any combination of the stream switches 502, shared memory (e.g., core interface 518 and / or memory interface 510), and / or cascade interfaces 522, 524. In addition, a specific DPE(or all) 402 in a cluster can be isolated from a DPE(or all) 402 in another cluster in that it cannot communicate between clusters using one or more of the stream switches 502, shared memory, and / or cascade interfaces 522, 524, but can communicate between clusters using a subset of the stream switches 502, shared memory, and / or cascade interfaces 522, 524.

[0094] As described, in one or more exemplary embodiments, the DPE array 110 may be formed from homogeneous DPE 402. In one or more other exemplary embodiments, the DPE array 110 may be formed from different types of DPE 402. For example, the DPE 402 may include different types of cores 404, such as cores 404 that execute program code, hardwired cores that do not execute program code, special purpose cores, or any combination thereof. In yet another exemplary embodiment, the DPE array 110 may include one or more DPEs that are dummy DPEs, for example, not functional DPEs. Each different DPE array may include a different number of DPEs and / or different types of DPEs, whether they are mounted on the same die or different dies.

[0095] Figure 5B shows an example of event processing circuit elements within DPE 402. A DPE may include event processing circuit elements interconnected with event processing circuit elements of other DPEs. In the example in Figure 5B, event processing circuit elements are implemented within the core 404 and the memory module 406. The core 404 may include an event broadcast circuit element 552 and an event logic 554. The memory module 406 may include a separate event processing circuit element containing an event broadcast circuit element 562 and an event logic 564.

[0096] The event broadcast circuit element 552 can be connected to the event broadcast circuit elements in the cores of the adjacent DPEs above and below DPE402 in Figure 5. The event broadcast circuit element 552 can also be connected to the event broadcast circuit element in the memory module of the DPE to the left of DPE402 in Figure 5. As shown, the event broadcast circuit element 552 is connected to the event broadcast circuit element 562. The event broadcast circuit element 562 can also be connected to the event broadcast circuit elements in the memory modules of the adjacent DPEs above and below DPE402 shown in Figure 5. The event broadcast circuit element 562 can also be connected to the event broadcast circuit element in the core of the DPE to the right of DPE402 in Figure 5.

[0097] In this way, the event processing circuit elements of the DPE can form an independent event broadcast network within the DPE array 110. The event broadcast network may exist independently of the other networks described herein. Furthermore, the event broadcast network may be individually configurable by loading appropriate configuration data into the control register 508.

[0098] In the example shown in Figure 5, the control register 508 programs event logics 554 and 564 to detect specific types of events occurring within the core 404 and memory module 406, respectively. The data loaded into the control register 508 determines, for example, which of several different types of predetermined events will be detected by event logics 552 and 562. Examples of events that can be detected by the event broadcast circuit element 552 are events occurring within the core 404. These events may include, but are not limited to, the start and / or end of read operations by the core 404, the start and / or end of write operations by the core 404, stalls, and the occurrence of other operations performed by the core 404. Examples of events that can be detected by the event broadcast circuit element 562 are events occurring within the memory module 406. These events may include, but are not limited to, the start and / or end of read operations by the DMA engine 516, the start and / or end of write operations by the DMA engine 516, stalls, and the occurrence of other operations performed by the memory module 406. The data loaded into the control register 508 determines, for example, which of several different types of predetermined events will be detected by the event logic 554 and / or 564. It should be understood that the event logic 554 and / or event logic 564 can detect events originating from and / or related to the DMA engine 516, memory-mapped switch 504, stream switch 502, memory interface 510, core interface 518, cascade interfaces 522, 524, and / or other components located within the DPE.

[0099] For example, configuration data loaded into control register 508 can determine which events received by event broadcast circuit elements 552 and / or 562 from other event broadcast circuit elements are propagated to other event broadcast circuit elements or other circuit elements. The configuration data can also specify which events internally generated by event logic 554 and / or 564 are propagated to other event broadcast circuit elements and / or other circuit elements.

[0100] Therefore, events generated by event logics 554 and 564 are provided to event broadcast circuit elements 552 and 562, respectively, and may be broadcast to other DPEs. In the example of Figure 5B, event broadcast circuit elements 552 and / or 562 can broadcast events to the upper DPE, the left DPE, and the lower DPE or logic interface 304, whether they were generated internally or received from other DPEs. Event broadcast circuit element 552 can also broadcast events to event broadcast circuit element 562 in the memory module 406.

[0101] In the example in Figure 5A, an event broadcast circuit element located within the core communicates vertically with an event broadcast circuit element located within the core of an adjacent DPE above and / or below. If a DPE is directly above (or adjacent to) the logic interface 304, the event broadcast circuit element within the core of that DPE can communicate with the logic interface 304. Similarly, an event broadcast circuit element located within a memory module communicates vertically with an event broadcast circuit element located within the memory module of an adjacent DPE above and / or below. If a DPE is directly above (e.g., adjacent to) the logic interface 304, the event broadcast circuit element within the memory module of that DPE can communicate with the logic interface 304. An event broadcast circuit element can communicate with the logic interface 304. An event broadcast circuit element can further communicate with an event broadcast circuit element immediately to its left and / or right, regardless of whether such an event broadcast circuit element is located within another DPE and / or core or memory module.

[0102] Once control register 508 is written, event logic 554 and event logic 564 can operate in the background. In one or more exemplary embodiments, event logic 554 generates events only in response to the detection of a specific state in core 404, and event logic 562 generates events only in response to the detection of a specific state in memory module 406.

[0103] Figures 6A, 6B, and 6C show exemplary architectures for implementing tiles of the logical interface 304. Figure 6A shows an exemplary embodiment of tile 408. The architecture shown in Figure 6A may also be used to implement any of the other tiles included in the logical interface 304.

[0104] Tile 408 includes a memory-mapped switch 602. The memory-mapped switch 602 may include multiple memory-mapped interfaces for communication in each of several different directions. As an exemplary and non-limiting example, the memory-mapped switch 602 may include one or more memory-mapped interfaces, each having a master that connects perpendicularly to the memory-mapped interface of the DPE 402 directly above it. Thus, the memory-mapped switch 602 can act as a master to one or more memory-mapped interfaces of the DPE 402. In a particular example, the memory-mapped switch 602 may act as a master to a subset of the DPE 402. For example, the memory-mapped switch 602 may act as a master to a column of DPE 402s on tile 408. It should be understood that the memory-mapped switch 602 may include additional memory-mapped interfaces for connecting to several different circuits (e.g., DPEs) within the DPE array 110. The memory-mapped interface of the memory-mapped switch 602 may also include one or more slaves that can communicate with circuit elements located above tile 408 (e.g., one or more DPEs).

[0105] In the example in Figure 6A, the memory-mapped switch 602 may include one or more memory-mapped interfaces to facilitate horizontal communication to memory-mapped switches in adjacent tiles of the logical interface 304. For illustrative purposes, the memory-mapped switch 602 may connect to adjacent tiles horizontally via memory-mapped interfaces, each of which may include one or more masters and / or one or more slaves. Thus, the memory-mapped switch 602 can direct data (e.g., configuration, control, and / or debug data) from one tile to another, regardless of whether such DPEs are in the upper column of tile 408 or in another subset of the logical interface 304 acting as interfaces, so that the data reaches the correct DPE 402 and / or subset of the multiple DPEs 402, and direct the data to the target DPE. For example, if a memory-mapped transaction is received from the physical interface 306, the memory-mapped switch 602 can distribute the transaction(s) horizontally, for example, to other tiles in the logical interface 304.

[0106] The memory-mapped switch 602 also has a memory-mapped interface having one or more masters and / or slaves coupled to the control register 636 in tile 408. This may include: Configuration data can be loaded into the control register 636 via the memory-mapped switch 602 to control various functions and operations performed by the components within the tile 408. Figures 6A, 6B, and 6C show the connections between the control register 636 and one or more elements of the tile 408. However, it should be understood that the control register 636 may control other elements of the tile 408 and therefore may have connections to such other elements, but such connections are not shown in Figures 6A, 6B, and / or 6C.

[0107] The memory-mapped switch 602 may include a memory-mapped interface coupled to the physical interface 306 via a bridge 618. The memory-mapped interface may include one or more masters and / or slaves. The bridge 618 can convert memory-mapped data transfers from the physical interface 306 (e.g., configuration, control, and / or debug data) into memory-mapped data that can be received by the memory-mapped switch 602.

[0108] Tile 408 may also include event processing circuit elements. For example, tile 408 includes event logic 632. Event logic 632 may be configured by a control register 636. In the example in Figure 6A, event logic 632 is coupled to a control, debug, and trace (CDT) circuit 620. Configuration data loaded into the control register 636 defines specific events that can be detected locally within tile 408. Each control register 636 can detect a variety of different events originating from and / or related to the DMA engine 612, memory-mapped switch 602, stream switch 606, first-in, first-out (FIFO) memory located in the bitwise interface 610, and / or stream interface 614. Examples of events may include, but are not limited to, DMA transfer completion, lock release, lock acquisition, end of bitwise transfer, or other events related to the start or end of data flow through tile 408. Event logic 632 can provide such events to event broadcast circuit elements 604 and / or CDT circuit 620. In another exemplary embodiment, the event logic 632 does not have to have a direct connection to the CDT circuit 620, but rather may be connected to the CDT circuit 620 via the event broadcast circuit element 604.

[0109] Tile 408 includes event broadcast circuit elements 604 and 630. Each of event broadcast circuit elements 604 and 630 provides an interface between the event broadcast network of the DPE array 110 and other tiles of the logical interface 304. Event broadcast circuit element 604 is coupled to event broadcast circuit elements and event broadcast circuit elements 630 in adjacent or neighboring tiles of the logical interface 304. Event broadcast circuit element 630 is coupled to event broadcast circuit elements in adjacent or neighboring tiles of the logical interface 304. In one or more other exemplary embodiments in which the tiles of the logical interface 304 are arranged in a grid or array, event broadcast circuit elements 604 and / or event broadcast circuit elements 630 may be connected to event broadcast circuit elements located in other tiles above and / or below tile 408.

[0110] In the example in Figure 6A, event broadcast circuit element 604 is coupled to an event broadcast circuit element in the core of DPE 402 which is directly adjacent to tile 408 (for example, above). Event broadcast circuit element 604 is also coupled to bitwise interface 610. Event broadcast circuit element 630 is (for example) It is coupled to an event broadcast circuit element in the memory module of DPE402, which is directly adjacent to the upper tile 408. In another exemplary embodiment, though not shown, the event broadcast circuit element 630 may also be coupled to a bitwise interface 610.

[0111] Event broadcast circuit elements 604 and 630 can transmit events internally generated by event logic 632, events received from other tiles 408 of logic interface 304, and / or events received from DPE 402 to other tiles. Event broadcast circuit element 604 can further transmit such events to other dies via bitwise interface 610. In another example, events may be transmitted from event broadcast circuit element 604 to other blocks and / or systems within IC 100, such as ASICs and / or PL circuit blocks located outside the DPE array 110, using bitwise interface 610 (not shown). Furthermore, bitwise interface 610 can receive events from other dies and provide such events to event broadcast switch 604 and / or stream switch 606. In one embodiment, event broadcast circuit element 604 can transmit any events received from other dies of IC 100 via bitwise interface 610 to other tiles 408 of logic interface 304 and / or DPE 402 of DPE array 110. Since events can be broadcast between tiles 408 within the logical interface 304, events can reach any DPE 402 in the DPE array 110 by traversing through the tiles 408 and event broadcast circuit elements within the logical interface 304 to the target (e.g., intended) DPE 402. For example, an event broadcast circuit element in a tile 408 of the logical interface 304 below a column (or subset) of DPE 402 managed by a tile 408 containing one or more target DPEs can propagate the event to the target DPE.

[0112] In the example shown in Figure 6A, the event broadcast circuit element 604 and event logic 632 are coupled to the CDT circuit 620. The event broadcast circuit element 604 and event logic 632 can transmit events to the CDT circuit 620. The CDT circuit 620 can packetize the received events and transmit them from the event broadcast circuit element 604 and / or event logic 632 to the stream switch 606. In certain exemplary embodiments, the event broadcast circuit element 630 may also be connected to the stream switch 606 and / or the CDT circuit 620.

[0113] In one or more exemplary embodiments, the event broadcast circuit elements 604 and 630 can collect broadcast events from one or more or all directions, as shown in Figure 6A (for example, via any of the connections shown in Figure 6A). In some cases, the event broadcast circuit elements 604 and / or 630 can perform a logical "OR" of signals and forward the result in one or more or all directions (including to the CDT circuit 620). Each output from the event broadcast circuit elements 604 and 630 may include a bitmask configurable by configuration data loaded into the control register 636. The bitmask determines which events are broadcast individually in each direction. Such a bitmask can, for example, eliminate unwanted or duplicate propagation of events.

[0114] The interrupt handler 634 is coupled to the event broadcast circuit element 604 and receives events broadcast from the event broadcast circuit element 604. It can be trusted. In one or more exemplary embodiments, the interrupt handler 634 may be configured by configuration data loaded into the control register 636 to generate interrupts to the physical interface 306 in response to selected events and / or combinations of events from the event broadcast circuit element 604 (e.g., DPE generation events and / or events generated within tile 408). Based on the configuration data, the interrupt handler 634 can generate interrupts to circuits located on other dies of the IC 100. For example, based on the interrupt(s) generated by the interrupt handler 634, the interrupt handler 634 can notify other device-level management blocks, such as a processor or processor system, of events occurring within the DPE array 110 and / or within tile 408 of the logical interface 304.

[0115] The bitwise interface 610 is coupled to the physical interface 306. In one or more exemplary embodiments, the bitwise interface 610 provides an asynchronous clock domain crossover between the DPE array 110 and another clock domain. The bitwise interface 610 can also provide level shifters and / or isolation cells for integration with power rails. In certain exemplary embodiments, the bitwise interface 610 may be configured to provide 32-bit, 64-bit, and / or 128-bit interfaces with FIFO support for handling back pressure. The specific width of the bitwise interface 610 may be controlled by configuration data loaded into the control register 636.

[0116] In one or more other exemplary embodiments, the bitwise interface 610 is coupled to other types of circuit blocks and / or systems in other dies via the physical interface 306. For example, the bitwise interface 610 may be coupled to an ASIC, an analog / mixed-signal circuit element, and / or other systems. Thus, the bitwise interface 610 can transfer data between tile 408 and such other systems and / or circuit blocks.

[0117] In the example in Figure 6A, tile 408 includes a stream switch 606. The stream switch 606 is coupled to stream switches in adjacent or neighboring tiles 408 and stream switches in adjacent or neighboring tiles 408 through one or more stream interfaces. Each stream interface may include one or more masters and / or one or more slaves. In certain exemplary embodiments, each pair of adjacent stream switches can exchange data through one or more streams in each direction. The stream switch 606 is also coupled to stream switches in the DPE directly above tile 408 by one or more stream interfaces. The stream switch 606 is also coupled to a bitwise interface 610, a DMA engine 612, and / or a stream interface 614 via a stream multiplexer / demultiplexer 608 (abbreviated as stream mux / demux in Figure 6A). The steam switch 606 may include, for example, one or more stream interfaces used to communicate with each of the bitwise interface 610, the DMA engine 612, and / or stream interface 614 via a stream multiplexer / demultiplexer 608.

[0118] The stream switch 606 may be configurable by configuration data loaded into the control register 636. The stream switch 606 may be configured, for example, to support packet-switched and / or circuit-switched operation based on the configuration data. Furthermore, the configuration data defines a specific DPE(s) 402 with which the stream switch 606 communicates. In one or more exemplary embodiments, the configuration data defines the stream switch 606 Defines a specific DPE402 and / or a subset of DPE402 in the column of DPE402 directly above tile 408 with which 6 communicates.

[0119] The stream multiplexer / demultiplexer 608 can route data received from the bitwise interface 610, the DMA engine 612, and / or the stream interface 614 to the stream switch 606. Similarly, the stream multiplexer / demultiplexer 608 can route data received from the stream switch 606 to the bitwise interface 610, the DMA engine 612, and / or the stream interface 614. For example, the stream multiplexer / demultiplexer 608 can be programmed by configuration data stored in the control register 636 to route selected data to the bitwise interface 610, to route selected data to the DMA engine 612 (such data is sent to the physical interface 306 as a memory-mapped transaction), and / or to route selected data to the stream interface 614 (the data is sent via the physical interface 306 as one or more data streams).

[0120] The DMA engine 612 can act as a master for directing data to the physical interface 306 through the selector block 616. The DMA engine 612 can receive data from the DPE 402 and provide such data to the physical interface 306 as memory-mapped data transactions. In one or more exemplary embodiments, the DMA engine 612 includes hardware synchronization circuit elements that can be used to synchronize multiple channels included in the DMA engine 612 and / or one channel within the DMA engine 612 with a master that polls and drives lock requests. For example, the master may be a processor and / or a processor system in another die of IC 100. The master may also receive interrupts generated by the hardware synchronization circuit elements within the DMA engine 612.

[0121] In one or more exemplary embodiments, the DMA engine 612 can access external memory (e.g., memory outside IC 100) and / or memory implemented on another die of IC 100 (e.g., a die containing only RAM). For example, the DMA engine 612 can receive a data stream from DPE 402 and transmit the data stream to memory through the physical interface 306. Similarly, the DMA engine 612 can receive data from external memory, and the data can be distributed to other tiles 408 of the logical interface 304 and / or to the target DPE 402.

[0122] In one or more exemplary embodiments, the DMA engine 612 includes security bits that can be set using the DPE Global Control Setting Register (DPE GCS register) 638. The memory may be divided into different regions or partitions, and the DPE array 110 is permitted to access only specific regions of memory. The security bits in the DMA engine 612 may be set so that the DPE array 110 can access only the specific region(s) of memory permitted by the DMA engine 612 for each security bit. For example, an application implemented by the DPE array 110 may be restricted to accessing only specific regions of memory, restricted to reading only from specific regions of memory, and / or may be completely restricted to writing to memory using this mechanism.

[0123] The security bits in the DMA engine 612 that control access to memory may be implemented to control the DPE array 110 as a whole, or access to memory The system may be implemented in a more granular manner, where a set can be specified and / or controlled for each DPE, for example, for each core, or for a group of cores configured to work together to implement, for example, the kernel and / or other applications.

[0124] The stream interface 614 can receive data from the physical interface 306 and transfer that data as a stream to the multiplexer / demultiplexer 608. The stream interface 614 can also receive data from the stream multiplexer / demultiplexer 608 and transfer that data to the physical interface 306. The selector block 616 can be configured to pass data from the DMA engine 612 or the stream interface 614 to the physical interface 306.

[0125] The CDT circuit 620 can perform control, debug, and trace operations within tile 408. For debugging purposes, each register located within tile 408 is mapped onto a memory map accessible via memory-mapped switch 602. The CDT circuit 620 may include circuits such as trace hardware, trace buffers, performance counters, and / or stall logic. The trace hardware of the CDT circuit 620 can collect trace data. The trace buffer of the CDT circuit 620 can buffer trace data. Furthermore, the CDT circuit 620 can output trace data to stream switch 606.

[0126] In one or more exemplary embodiments, the CDT circuit 620 can collect data, such as trace and / or debug data, packetize such data, and then output the packetized data via the stream switch 606. For example, the CDT circuit 620 can output the packetized data and supply such data to the stream switch 606. Furthermore, control registers 636 or others can be read or written during debugging via memory-mapped transactions through the memory-mapped switches 602 of each tile. Similarly, performance counters within the CDT circuit 620 can be read or written during profiling via memory-mapped transactions through the memory-mapped switches 602 of each tile.

[0127] In one or more exemplary embodiments, the CDT circuit 620 can receive any event propagated by the event broadcast circuit element 604 (or event broadcast circuit element 630), or selected events per bitmask utilized by the interface of the event broadcast circuit element 604 coupled to the CDT circuit 620. The CDT circuit 620 can further receive events generated by the event logic 632. For example, the CDT circuit 620 can receive broadcast events from the DPE 402, tile 408 (e.g., event logic 632 and / or event broadcast switch 604), and / or other tiles of the logic interface 304. The CDT circuit 620 can pack multiple such events together into a packet, e.g., packetize them, and associate the packetized events with a timestamp(s). The CDT circuit 620 can further transmit the packetized events to an external destination outside of tile 408 via the stream switch 606. The events may be transmitted by the stream switch 606 and the stream multiplexer / demultiplexer 608 to the physical interface 306 via the bitwise interface 610, the DMA engine 612, and / or the stream interface 614.

[0128] The DPE GCS register 638 is used to enable or disable secure access to and / or from the DPE array 110. The DPE GCS register 638 can store settings / bits (also referred to herein as "security bits"). The DPE GCS register 638 can be programmed via the SoC secure / initialization interface, which is described in more detail below in relation to Figure 6C. Security bits(s) received from the SoC secure / initialization interface can be propagated via the bus from one tile to the next on the logical interface 304, as shown in Figure 6A.

[0129] In one or more exemplary embodiments, external memory-mapped data transfers to the DPE array 110 may be insecure or unreliable. Any entity within IC 100 that can communicate via memory-mapped data transfer without setting a security bit in the DPE GCS register 638 can communicate with the DPE array 110. By setting a security bit in the DPE GCS register 638, the specific entities permitted to communicate with the DPE array 110 can be defined such that only designated entities capable of generating secure traffic can communicate with the DPE array 110.

[0130] In one or more exemplary embodiments, a memory-mapped data transfer may include additional sideband signals, such as bits, that indicate whether a transaction is secure or not. If the security bit in the DPE GCS register 638 is set, a memory-mapped transaction entering a logical interface 304, for example, tile 408, must set a sideband signal to indicate that the memory-mapped transaction reaching the logical interface 304 is secure. If the sideband bit is not set for a memory-mapped transaction reaching the logical interface 304, and the security bit is set in the DPE GCS register 638, the logical interface 304 will not allow the transaction to enter or pass through DPE 402.

[0131] In one or more exemplary embodiments, IC100 includes a secure agent (e.g., a circuit) acting as the root of trust. The PMC may be, for example, a secure agent. The secure agent can configure different entities (e.g., a circuit) within IC100 with the necessary permissions to set sideband bits in memory-mapped transactions to access the DPE array 110 when the security bit of the DPE GCS register 638 is set. Once IC100 is configured, the secure agent grants permissions to different masters that may be implemented within it, thereby giving such masters the ability to issue secure transactions to the DPE array 110.

[0132] Figure 6B shows another exemplary embodiment of tile 408. The exemplary architecture shown in Figure 6B may also be used to implement any of the other tiles included in the logic interface 304. The example in Figure 6B shows a simplified version of the architecture shown in Figure 6A. The tile architecture in Figure 6B provides connectivity between the DPE 402 and other systems and / or dies within IC 100. For example, tile 408 in Figure 6B can provide an interface between the DPE 402 and an analog / mixed-signal circuit block, an ASIC, or other systems described herein. In the example in Figure 6B, the DMA engine 612, stream interface 614, selector block 616, bridge 618, and stream multiplexer / demultiplexer 608 are omitted. Thus, tile 408 in Figure 6B can be implemented using IC 100 with a smaller area. Furthermore, as illustrated, the stream switch 606 is directly coupled to the bitwise interface 610.

[0133] The exemplary architecture in Figure 6B cannot receive memory-mapped data, such as configuration data, for the purpose of configuring DPE 402. Such configuration data may be received from an adjacent tile via a memory-mapped switch 602 and directed to a subset of DPEs managed by tile 408 (for example, up to the row of DPE 402 above tile 408 in Figure 6B).

[0134] Figure 6C shows another exemplary embodiment of tile 408. In certain exemplary embodiments, only one tile can be implemented within the logical interface 304 using the architecture shown in Figure 6C. The architecture shown in Figure 6C is similar to the architecture shown in Figure 6B. Figure 6C includes additional components such as a secure / initialization interface 640, a clock signal generator 642, and a global timer 644.

[0135] In the example shown in Figure 6C, the secure / initialization interface 640 can provide access to the global reset register (not shown) and the DPE GCS register 638 of the DPE array 110. The DPE GCS register 638 may include a control register for the clock signal generator 642. As illustrated, the secure / initialization interface 640 can provide a security bit to the DPE GCS register 638 and propagate the security bit to other DPE GCS registers 638 in other tiles of the logical interface 304. The secure / initialization interface 640 can implement a single slave endpoint for the logical interface 304.

[0136] In the example shown in Figure 6C, the clock signal generator 642 can generate one or more clock signals 646 and / or one or more reset signals 650. The clock signals 646 and / or reset signals 650 can be distributed to each of the DPE 402 and / or other tiles of the logic interface 304 of the DPE array 110. For example, the clock signal generator 642 may include one or more phase-locked loop circuits (PLLs). As shown, the clock signal generator 642 can receive a reference clock signal generated by another circuit outside the DPE array 110, which may be located on the same die as the DPE array 110. In another example, the reference clock may be received from the physical interface 306. The clock signal generator 642 can generate clock signals 646 based on the received reference clock signal.

[0137] In the example in Figure 6C, the clock signal generator 642 is configured through the secure / initialization interface 640. For example, the clock signal generator 642 may be configured by loading data into the DPE GCS register 638. Thus, one or more clock frequencies of the DPE array 110, and the generation of the reset signal 650, can be set by writing appropriate configuration data to the DPE GCS register 638 through the secure / initialization interface 640. For test purposes, the clock signal(s) 646 and / or reset signal 650 may also be routed directly to the physical interface 306.

[0138] The secure / initialization interface 640 can be coupled to a control / debug (circuit) block (e.g., a control and / or debug system for IC 100, not shown). In one or more exemplary embodiments, the secure / initialization interface 640 can provide status signals to the control / debug block. As an exemplary and non-limiting example, the secure / initialization interface 640 can provide the control / debug block with a "PLL lock" signal generated from within the clock signal generator 642. The PLL lock signal can indicate when the PLL acquires a lock on a reference clock signal.

[0139] The secure / initialization interface 640 can receive instructions and / or data via the physical interface 306. The data may include security bits as described herein, clock signal generator configuration data, and / or other data that can be written to the DPE GCS register 638.

[0140] The global timer 644 can interface with the CDT circuit 620. For example, the global timer 644 may be coupled to the CDT circuit 620. The global timer 644 can provide signals used by the CDT circuit 620 for time stamping events used for tracking. In one or more exemplary embodiments, the global timer 644 may be coupled to the CDT circuit 620 in other tiles of the logic interface 304 tile. For example, the global timer 644 may be coupled to the CDT circuit 620 in the exemplary tile of Figures 6A, 6B, and / or 6C. The global timer 644 may also be coupled to a control / debug block.

[0141] Referring together to the architectures in Figures 6A, 6B, and 6C, tile 408 can communicate with DPE 402 using various different data paths. In one example, tile 408 can communicate with DPE 402 using DMA engine 612. For example, tile 408 can communicate with the DMA engine of one or more DPE 402 in the DPE array 110 using DMA engine 612. Communication can flow from DPE 402 to tile 408 on logical interface 304, or from tile 408 on logical interface 304 to DPE 402. In another example, DMA engine 612 can communicate with one or more cores 404 of one or more DPE 402 in the DPE array 110 via stream switches within each DPE. Communication can flow from one or more cores 404 to tile 408 of logical interface 304, and / or from tile 408 of logical interface 304 to one or more cores 404 of one or more DPEs 402 of DPE array 110.

[0142] In one or more exemplary embodiments, each of the bitwise interface 610, the DMA engine 612, and the stream interface 614 may be selectively turned on and connected to the physical interface 306, or turned off and disconnected from the physical interface 306. Thus, any one or more or any combination of the bitwise interface 610, the DMA engine 612, and the stream interface 614 may be connected to or disconnected from the physical interface 306 based on the configuration data of tile 408. In one embodiment, such configuration data may be loaded into the control register 636. In another embodiment, such configuration data may be provided by the configuration pins of IC 100.

[0143] The specific interface(s) connected to or disconnected from physical interface 306 may differ for each tile 408. For example, in a first tile 408, one or more specific combinations of interfaces may be connected to physical interface 306, while in a second different tile 408, one or more different combinations of interfaces may be connected to physical interface 306. Furthermore, the specific interfaces and / or interfaces connected to and / or disconnected from physical interface 306 may vary based on the specific types of interfaces included in each of the respective tiles 408.

[0144] In one exemplary embodiment, the configuration data of tile 408 enables the stream interface 614 while the bitwise interface 610 and / or DMA engine 612 are disconnected from the physical interface 306. For illustrative purposes, the stream interface 614 may be connected to the physical interface 306 to facilitate or access hardware functions on other dies of IC100 with low latency.

[0145] In another exemplary embodiment, the configuration data of tile 408 enables a DMA engine 612 (e.g., a memory-mapped interface) and connects to the physical interface 306 while the bitwise interface 610 and / or stream interface 614 are disconnected from the physical interface 306. For illustrative purposes, the DMA engine 612 may be connected to the physical interface 306 to access external memory by referencing memory located outside the chip or outside IC 100, or to access memory implemented within IC 100 on a different die. Examples of memory include, but are not limited to, RAM (e.g., DDR) and / or high-bandwidth memory (HBM), whether implemented on other dies of IC 100 and / or implemented outside IC 100.

[0146] In another exemplary embodiment, the configuration data of tile 408 enables the bitwise interface 610 and connects it to the physical interface 306 while the DMA engine 612 and / or stream interface 614 are disconnected from the physical interface 306. For illustrative purposes, the bitwise interface 610 may also be connected to the physical interface 306 to provide error notifications and / or interrupts to other dies of IC 100.

[0147] Figure 7 shows an exemplary embodiment of the bitwise interface 610. In the example of Figure 7, the bitwise interface 610 includes multiple channels that couple the physical interface 306 to the stream switch 606 and / or stream multiplexer / demultiplexer 608, depending on the specific tile architecture used. The particular number of channels shown in Figure 7 within the bitwise interface 610 is illustrative and not limiting. In other embodiments, the bitwise interface 610 may include fewer or more channels than those shown in Figure 7. Furthermore, while the bitwise interface 610 connects to the physical interface 306, in one or more other exemplary embodiments, the bitwise interface 610 may couple to one or more other systems and / or circuit blocks of IC 100.

[0148] In one or more exemplary embodiments, the physical interface 306 and / or other dies coupled thereto operate at different reference voltages and different clock speeds than the DPE 402. Thus, in the example of Figure 7, the bitwise interface 610 includes a plurality of shift isolation circuits 702 and a plurality of asynchronous FIFO memories 704. Each channel includes a shift isolation circuit 702 and an asynchronous FIFO memory 704. A first subset of channels carries data from the physical interface 306 (and / or other circuit elements) to the stream switch 606 and / or stream multiplexer / demultiplexer 608. A second subset of channels carries data from the stream switch 606 and / or stream multiplexer / demultiplexer 608 to the physical interface 306 and / or other circuit elements.

[0149] The shift isolation circuit 702 can interface between domains of different voltages. In this case, the shift isolation circuit 702 can provide an interface for transitions between the operating voltage of the physical interface 306 and / or other circuit elements and the operating voltage of the DPE 402. The asynchronous FIFO memory 704 can interface between two different clock domains. In this case, the asynchronous FIFO memory 704 can interface between the physical interface 306 and / or other circuit elements and / or It can provide an interface for transitioning between the clock rate of other circuit elements coupled to it and the clock rate of the DPE402.

[0150] In one or more exemplary embodiments, the asynchronous FIFO memory 704 has a 32-bit interface to the DPE array 110. The connections between the asynchronous FIFO memory 704 and the shift isolation circuit 702, and between the shift isolation circuit 702 and the physical interface 306, may have a programmable (e.g., configurable) width. For example, the connections between the asynchronous FIFO memory 704 and the shift isolation circuit 702, and between the shift isolation circuit 702 and the physical interface 306, may be configured to have a width of 32 bits, 64 bits, or 128 bits. As described, the bit-wide interface 610 is configurable by having the memory-mapped switch 602 write configuration data to the control register 636 in order to achieve the described bit widths. Using the memory-mapped switch 602, the side of the asynchronous FIFO memory 704 on the physical interface 306 side may be configured to use 32 bits, 64 bits, or 128 bits. The bit widths provided herein are for illustrative purposes only. In other embodiments, other bit widths may be used. In any case, the widths described for the various components can be changed based on the configuration data loaded into the control register 636.

[0151] Figure 8 shows an exemplary embodiment of the stream interface 614. In one embodiment, the DPE 402 can access the DMA engine 612 using the stream switch 606. The DMA engine 612 can convert memory-mapped transactions from the physical interface 306 into data streams for transmission to the DPE, and convert data streams from the DPE into memory-mapped transactions for transmission via the physical interface 306. In another embodiment, the data stream may be directed to the stream interface 614.

[0152] In the example shown in Figure 8, the stream interface 614 includes multiple channels that connect the physical interface 306 to the stream switch 606 and / or the stream multiplexer / demultiplexer 608. Each channel may include a FIFO memory and either an upsizing or downsizing circuit. A first subset of channels carries data from the physical interface 306 to the stream switch 606 and / or the stream multiplexer / demultiplexer 608. A second subset of channels carries data from the stream switch 606 and / or the stream multiplexer / demultiplexer 608 back to the physical interface 306. The specific number of channels shown in Figure 8 within the NoC stream interface 614 is illustrative and not limiting. In other exemplary embodiments, the stream interface 614 may include fewer or more channels than those shown in Figure 8.

[0153] In one or more exemplary embodiments, each upsizing circuit 808 (abbreviated as “US circuit” in Figure 8) can receive a data stream and increase the width of the received data stream. For example, each upsizing circuit 808 may receive a 32-bit data stream and output a 128-bit data stream to the corresponding FIFO memory 810. Each FIFO memory 810 is coupled to an arbitration multiplexer circuit 812. The arbitration multiplexer circuit 812 can arbitrate between received data streams using a specific arbitration scheme or priority (e.g., round-robin or other style) to provide the resulting output data stream to the physical interface 306. The arbitration multiplexer circuit 812 can process and accept new requests each clock cycle. Intersections can be processed within tile 408 using, for example, FIFO memory 804.

[0154] The demultiplexer 802 can receive a data stream from the physical interface 306. For illustrative purposes, the data stream may be 128 bits wide. Clock domain crossovers between the DPE 402 and the physical interface 306 may be handled within the bitwise interface 610 as described above. The demultiplexer 802 can transfer the received data stream to one of the FIFO memories 804. The specific FIFO memory 804 to which the demultiplexer 802 provides the data stream may be encoded within the data stream itself. The FIFO memory 804 is coupled to a downsizing circuit 806 (abbreviated as "DS circuit" in Figure 8). The downsizing circuit 806 can downsize the received stream to a smaller width after buffering using time-division multiplexing. For example, the downsizing circuit 806 may downsize the stream from 128 bits wide to 32 bits wide.

[0155] As shown in the figure, the downsizing circuit 806 and the upsizing circuit 808 are coupled to either the stream switch 606 or the stream multiplexer / demultiplexer 608, depending on the specific architecture of the tile of the logic interface 304 used. Figure 8 is provided for illustrative purposes only and is not intended as an limitation. The order and / or connectivity of the components within the channel (e.g., the upsizing / downsizing circuit and the FIFO memory) may vary.

[0156] In one or more other exemplary embodiments, the bitwise interface 610 may include upsizing and / or downsizing circuits, as described in relation to Figure 7, as described in relation to Figure 8. For example, downsizing circuits may be included in each channel that carries data from the physical interface 308 (or other circuit elements) to the stream switch 606 and / or stream multiplexer / demultiplexer 608. Upsizing circuits may be included in each channel that carries data from the stream switch 606 and / or stream multiplexer / demultiplexer 608 to the physical interface 306 (or other circuit elements).

[0157] In one or more other exemplary embodiments, each downsizing circuit 806 may be combined with the corresponding FIFO memory 804, for example, as a single block or circuit, although shown as an independent element. Similarly, each upsizing circuit 808 may be combined with the corresponding FIFO memory 810, for example, as a single block or circuit.

[0158] Figure 9 shows an exemplary embodiment of the DMA engine 612. In the example of Figure 9, the DMA engine 612 includes a DMA controller 902. The DMA controller 902 may be divided into two separate modules or interfaces. Each module can operate independently of the others. The DMA controller 902 may include memory mapped to a memory-mapped-stream interface (interface) 904 and a stream-memory-mapped interface (interface) 906. Each of interfaces 904 and 906 may include two or more separate channels. Thus, the DMA engine 612 can receive two or more incoming streams from the stream switch 606 via interface 906 and send two or more outgoing streams to the stream switch 606 via interface 904. The DMA controller 902 may further include a master memory-mapped interface 914. The master memory-mapped interface 914 connects the physical interface 306 to interfaces 904 and 906.

[0159] The DMA engine 612 may also include hardware synchronization circuit elements 910 and a buffer descriptor register file 908. Both the hardware synchronization circuit elements 910 and the buffer descriptor register file 908 can be accessed via the multiplexer 912. Therefore, both the hardware synchronization circuit elements 910 and the buffer descriptor register file 908 can be accessed externally via a control interface. Examples of such control interfaces include, but are not limited to, a memory-mapped interface or a control stream interface from the DPE 402. An example of a control stream interface for the DPE is the streaming interface output from the DPE core.

[0160] The hardware synchronization circuit element 910 can be used to synchronize multiple channels included in the DMA engine 612 and / or one channel within the DMA engine 612 with a master that polls and drives lock requests. For example, the master may be another system coupled to the DMA engine 612 via the physical interface 306. In another example, the master may also receive interrupts generated by the hardware synchronization circuit element 910 within the DMA engine 612 when a lock is available.

[0161] DMA transfers can be defined by buffer descriptors stored in the buffer descriptor register file 908. Interface 906 can request read transfers to the physical interface 306 based on the information in the buffer descriptors. Outgoing streams from interface 904 to stream switch 606 can be configured as packet-switched or circuit-switched based on the configuration registers of the stream switch.

[0162] Figure 10 shows exemplary embodiments of physical interfaces 306 and 312. Physical interface 306 may include a plurality of circuit blocks 1002 (for example, shown as 1002-1 to 1002-N in Figure 10). In the example in Figure 10, physical interface 306 is implemented as a multi-channel interface where each of the circuit blocks 1002 corresponds to a channel. Physical interface 312 of die 106 also includes a plurality of circuit blocks 1006 (for example, shown as 1006-1 to 1006-N). Physical interface 312 is implemented as a multi-channel interface where each of the blocks 1006 corresponds to a channel. In the example in Figure 10, a channel consists of a pair of circuit blocks, for example, circuit block 1002-1 and circuit block 1006-1, also called the "corresponding circuit block," forming a single channel. In the exemplary embodiments, each of blocks 1002 and 1004 may be implemented as a Laguna site (available from Xilinx, Inc., San Jose, California).

[0163] Circuit block 1002-1 contains multiple flip-flops 1004 (labeled "FF" in Figure 10). In the example in Figure 10, six flip-flops 1004 (e.g., FF1004-1 to FF1004-6) form a channel. Each flip-flop 1004 is supplied with a clock signal (TX-CLK), a clock enable signal (CE), and a set reset (SR) signal. Similarly, circuit block 1006-1 contains multiple flip-flops 1008 (labeled "FF" in Figure 10). In the example in Figure 10, six flip-flops 1008 (e.g., FF1008-1 to FF1008-6) form a channel. Each flip-flop 1008 is supplied with a clock signal (RX-CLK), a clock enable signal (CE), and a set reset (SR) signal. Each pair of transmit and receive flip-flops (e.g., FF1004-6 and FF1008-6) forms a cell. Therefore, the exemplary channel shown in Figure 10 contains six cells.

[0164] In the example in Figure 10, the inter-die wire 116 connects the flip-flop 1004 of circuit block 1002-1 to the flip-flop 1008 of circuit block 1006-1. In one or more exemplary embodiments, the inter-die wire 116 may be implemented within an interposer as described in relation to Figure 1. In one or more other exemplary embodiments, the inter-die wire 116 may be implemented within a bridge die as described in relation to Figure 2.

[0165] In one exemplary embodiment, each circuit block 1002 may use the same or a common clock signal. In another exemplary embodiment, each circuit block 1002 may use a clock signal independent of the other circuit blocks 1002. The independent clock signals may not be each other's derivatives, or they may differ in one or more characteristics, such as phase, frequency, or duty cycle. In yet another exemplary embodiment, different groups of one or more circuit blocks 1002 may use the same or a common clock signal, and the clock signals from one group to another are independent of each other. The clock signal provided to circuit block 1006 may correspond to or match the clock signal of the corresponding circuit block 1002. In this regard, the different channels do not need to be synchronized with each other.

[0166] In another exemplary embodiment, the flip-flops in each circuit block 1002 may be configured to be either transmit or receive flip-flops. The corresponding flip-flops in the corresponding circuit block 1006 are configured in reverse. In the example in Figure 10, each flip-flop 1004 in circuit block 1002-1 is configured as a transmit flip-flop, and each flip-flop 1008 in the corresponding circuit block 1006-1 is configured as a receive flip-flop. In another example, each flip-flop 1004 in circuit block 1002-1 may be configured as a receive flip-flop, and each flip-flop 1008 in the corresponding circuit block 1006-1 may be configured as a transmit flip-flop. Each circuit block 1002 may be configured independently of the corresponding circuit block 1006 configured in reverse.

[0167] In another example, one or more of the flip-flops 1004 in circuit block 1002-1 may be configured as transmit flip-flops (e.g., FF1004-1 and FF1004-2), while one or more other flip-flops in flip-flop 1004 (e.g., FF1004-3, 1004-4, 1004-5, and 1004-6) are configured as receive flip-flops. The corresponding circuit block 1006-1 is configured in reverse, where one or more of the flip-flops 1008 may be configured as receive flip-flops (e.g., FF1008-1 and FF1008-2), while one or more other flip-flops in flip-flop 1008 (e.g., FF1008-3, 1008-4, 1008-5, and 1008-6) are configured as transmit flip-flops. In this way, each circuit block 1002 can be configured using a desired number of transmit and receive flip-flops, while each corresponding circuit block 1006 can be configured in reverse.

[0168] In one exemplary embodiment, any data stream received from the interface of tile 408 (e.g., bitwise interface 610, DMA engine 612, and / or stream interface 614) may be provided to different circuit blocks 1002 in a bit-to-bit (e.g., wire-to-wire) correspondence. For example, a 32-bit data stream from the interface of tile 408 may be provided to the physical interface 306, utilizing six circuit blocks 1002. A 128-bit stream provided from the interface of tile 408 can be mapped to 22 circuit blocks 1002. However, each circuit block 1002 and It should be understood that the number of signal lines (e.g., flip-flops) included in 1006 is for illustrative purposes only. In other exemplary embodiments, the number of signal lines may be less than six, while in other cases it may be more than six.

[0169] Figure 11 shows another exemplary embodiment of physical interfaces 306 and 312. Physical interfaces 306 and 312 are implemented as multi-channel interfaces. In the example in Figure 11, circuit blocks 1002 and 1006 are implemented as high-bandwidth memory (HBM) physical interfaces (PHYs). In the exemplary embodiment, physical interfaces 306 and 312 may be implemented to comply with the 2013 High-Bandwidth Memory (HBM) DRAM Memory Standard (JESD235) or the 2020 HBM DRAM Memory Standard (JESD235A).

[0170] Circuit block 1002-1 includes a data channel circuit 1102, a command address circuit 1104, and a clock / power manager 1106. The corresponding circuit block 1006-1 includes a data channel circuit 1108, a command address circuit 1110, and a clock / power manager circuit 1112. Data channel blocks 1102 and 1108 each provide eight channels, each having four 32-bit words. The example in Figure 11 shows that each pair of circuit blocks (e.g., 1002-1 and 1006-1) includes eight channels and is therefore capable of exchanging 1028 bits of parallel data.

[0171] In exemplary embodiments, each of the eight channels may have independent clocking and power management, supported by clock and power managers 1106 and 1112. In this regard, the different channels do not need to be synchronized with one another. Furthermore, each of the eight channels supports bidirectional communication. In the example of Figure 11, the die-to-die wire 116 connects circuit block 1002-1 to circuit block 1006-1. In one or more exemplary embodiments, the die-to-die wire 116 may be implemented within an interposer as described in relation to Figure 1. In one or more other exemplary embodiments, the die-to-die wire 116 may be implemented within a bridge die as described in relation to Figure 2.

[0172] In one exemplary embodiment, any data stream received from the interface of tile 408 (e.g., bitwise interface 610, DMA engine 612, and / or stream interface 614) may be provided to different circuit blocks 1002 in a bit-to-bit (e.g., wire-to-wire) correspondence. For example, a 32-bit data stream output from the interface of tile 408 may be provided to physical interface 306, utilizing one 32-bit word of a channel in circuit block 1002-1. A 128-bit data stream may be mapped to an entire channel in circuit block 1002-1.

[0173] Figure 12 shows another exemplary embodiment of physical interfaces 306 and 312. Physical interface 306 includes one or more circuit blocks 1002, while physical interface 312 includes one or more circuit blocks 1006. In the example of Figure 12, each circuit block 1002, 1006 implements a transceiver. The transceiver may be implemented as a high-speed transceiver capable of sending and receiving data at high data rates, for example, in the range of gigabits per second, and each pair of circuit blocks 1002, 1006 (e.g., 1002-1 and 1006-1) implements a channel. Each channel includes a serial transmission path and a serial reception path.

[0174] Referring to the physical interface 306, circuit block 1002 can include a serializer / deserializer (SERDES) 1202 and a transceiver 1204. SERDES1202 can receive data streams (e.g., parallel data) from the interfaces of tile 408 (e.g., bitwise interface 610, DMA engine 612, and / or stream interface 614) and convert the data streams into serialized data output to transceiver 1204. The data streams received from the interfaces of tile 408 may be of any of several different bit widths. Exemplary bit widths include, but are not limited to, 32, 64, 128, and 256 bits.

[0175] SERDES1202 can also receive serialized data from transceiver 1204 and convert the received serialized data into a data stream containing parallel data. The resulting data stream generated by SERDES1202 may have any of the various bit widths described above. SERDES1202 can output the resulting data stream to the interface of tile 408.

[0176] The transceiver 1204 may include a transmit physical coding sublayer (PCS) circuit 1206, a receive PCS circuit 1208, a transmit physical media connection (PMA) circuit 1210, and a receive PMA 1212. The transmit PCS circuit 1206 can receive serialized data from SERDES 1202. The transmit PCS circuit 1206 can perform operations such as data coding, scrambling, alignment marker insertion, block and symbol redistribution, and lane block synchronization and deskew. The transmit PMA 1210 receives data from the transmit PCS 1206 and can perform operations such as PMA framing, octet synchronization / detection, and further scrambling. The transmit PMA 1210 can transmit serialized data to the physical interface 312 via the inter-die wire 116.

[0177] The receiving PMA1212 can receive data from the physical interface 312 via the die-to-die wire 116. The receiving PMA1212 can perform operations such as PMA framing, octet synchronization / detection, and descrambling. The receiving PMA1212 outputs the data to the receiving PCS1208. The receiving PCS1208 can perform operations on the received data such as data decoding, descrambling, alignment marker removal, block and symbol redistribution, and lane-block synchronization and deskue. The receiving PCS1208 sends the processed data to the SERDES1202 to be converted into a data stream provided to the interface of tile 408.

[0178] The circuit block 1006 may include a transceiver 1214. The transceiver 1214 may include a receiving PCS 1216, a receiving PMA 1220, a transmitting PMA 1222, and a transmitting PCS 1218. Depending on the specific type of circuit block implemented on die 106 that transmits data to and / or receives data from the DPE array 110, the circuit block 1006 may or may not include SERDES.

[0179] In exemplary embodiments, transceivers 1204 and 1214 may each be implemented as Gigabit transceivers (GTs) available from Xilinx, Inc. in San Jose, California. In the example of Figure 12, the inter-die wire 116 connects transceiver 1204 to transceiver 1214 as shown. In one or more exemplary embodiments, the inter-die wire 116 may be implemented within an interposer as described in relation to Figure 1. In one or more other exemplary embodiments, the inter-die wire 116 may be implemented within a bridge die as described in relation to Figure 2.

[0180] The exemplary embodiments described in relation to Figures 10, 11, and 12 illustrate several different types of physical interfaces that can be used to connect die 104 to die 106 in a communicative manner. In other exemplary embodiments, the physical interface 306 may include several different types of circuit blocks 1002. For example, the physical interface 306 may include one or more of the circuit blocks 1002 in Figure 10, one or more of the circuit blocks 1002 in Figure 11, one or more of the circuit blocks 1002 in Figure 12, or any combination thereof.

[0181] In one embodiment, in such heterogeneous embodiments of the physical interface 306, a similar type of circuit block may be used to connect to one die (e.g., die 106), while another type of circuit block (e.g., “type” in this context refers to a specific embodiment such as Figure 10, Figure 11, or Figure 12) is used to communicate with a different die (e.g., an additional die other than the bridge die).

[0182] In another embodiment, heterogeneous embodiments of the physical interface 306 may include different types of circuit blocks connected to the die 106. For example, the physical interface may include one or more of the circuit blocks 1002 in Figure 10, one or more of the circuit blocks 1002 in Figure 11, one or more of the circuit blocks 1002 in Figure 12, or any combination thereof, which communicate with the corresponding embodiment of the physical interface 312 on the die 106.

[0183] Figure 13 shows an exemplary embodiment including multiple DPE interfaces. In the example of Figure 13, dies 104 and 106 of IC 100 are shown. Inter-die wires may be implemented as described in relation to Figure 1 or Figure 2. As shown, die 104 includes two DPE arrays 110-1 and 110-2. DPE array 110-1 is connected to DPE interface 302-1. DPE interface 302-1 includes a logical interface 304-1 and a physical interface 306-1. DPE array 110-2 is connected to DPE interface 302-2. DPE interface 302-2 includes a logical interface 304-2 and a physical interface 306-2.

[0184] Die 106 includes physical interface 312-1 and physical interface 312-2. Physical interface 312-1 connects to physical interface 306-1. Physical interface 312-2 connects to physical interface 306-2. In one or more exemplary embodiments, physical interfaces 306-1, 312-1, 306-2, and 312-2 are implemented as the same interface (e.g., matching, as shown in one of Figures 10, 11, or 12). In one or more other exemplary embodiments, physical interfaces 306-1 and 312-1 are of the same type (e.g., matching, as shown in one of Figures 10, 11, or 12), while physical interfaces 306-2 and 312-2 are of the same type (e.g., matching), but different in type from physical interfaces 306-1 and 312-1.

[0185] In the example in Figure 13, the inclusion of an additional DPE interface increases the bandwidth to and from die 104. In this example, DPE arrays 110-1 and 110-2, implemented as separate DPE arrays, are not connected to each other in a communicative manner, thereby preventing DPE array 110-1 from communicating with DPE array 110-2. That is, DPE 402 of DPE array 110-1 must communicate via the inter-die wire 116 (e.g., via die 106) to communicate with DPE array 1 Unable to communicate with DPE402 on unit 10-2.

[0186] Figure 14 shows another exemplary embodiment including multiple DPE interfaces. In the example of Figure 14, dies 104 and 106 of IC 100 are shown. The inter-die wires may be implemented as described in relation to Figure 1 or Figure 2. As shown, die 104 includes one DPE array 110. DPE array 110 is connected to DPE interfaces 302-1 and 302-2. DPE interface 302-1 includes a logical interface 304-1 and a physical interface 306-1. DPE interface 302-2 includes a logical interface 304-2 and a physical interface 306-2.

[0187] Die 106 includes physical interface 312-1 and physical interface 312-2. Physical interface 312-1 connects to physical interface 306-1. Physical interface 312-2 connects to physical interface 306-2. In one or more exemplary embodiments, physical interfaces 306-1, 312-1, 306-2, and 312-2 are implemented as the same interface (e.g., matching, as shown in one of Figures 10, 11, or 12). In one or more other exemplary embodiments, physical interfaces 306-1 and 312-1 are of the same type (e.g., matching, as shown in one of Figures 10, 11, or 12), while physical interfaces 306-2 and 312-2 are of the same type (e.g., matching), but different in type from physical interfaces 306-1 and 312-1.

[0188] In the example in Figure 14, the inclusion of an additional DPE interface increases the bandwidth to and from die 104. In this example, since the DPE array 110 is implemented as a single DPE array, each DPE 402 can communicate with each other. Communication between the DPE 402s and logical interfaces 304-1 and 304-2 occurs via the DPE 402 directly above tile 408. The example in Figure 14 allows a DPE 402 located above logical interface 304-1 to communicate with a DPE 402 located above logical interface 304-2, and vice versa. In such embodiments, a cluster of DPE 402s can be formed without limitation on whether logical interfaces 304-1 or 304-2 are used or whether they can be connected to a cluster. In other words, a cluster of DPE402 can include one or more DPE402 or DPE402 columns above logical interface 304-1 and one or more DPE402 or DPE402 columns above logical interface 304-2.

[0189] Figure 15 shows another exemplary embodiment including multiple DPE interfaces. The example in Figure 15 is similar to the example in Figure 13, except that IC 100 includes three dies. IC 100 includes dies 104, 106-1, and 106-2. Physical interface 312-1 is implemented in die 106-1. Physical interface 312-2 is implemented in die 106-2. Thus, DPE array 110-1 can communicate only with die 106-1, while DPE array 110-2 can communicate only with die 106-2. Furthermore, the additional DPE interfaces increase the bandwidth entering and leaving die 104.

[0190] Figure 16 shows another exemplary embodiment including multiple DPE interfaces. The example in Figure 16 is similar to the example in Figure 14, except that IC100 includes three dies. IC100 includes dies 104, 106-1 and 106-2. Physical interface 312-1 is implemented on die 106-1. Physical interface 312-2 is It is implemented within die 106-2. In the example in Figure 16, one or more of the DPE402s can communicate with die 106-1, die 106-2, or both. The additional DPE interface increases the bandwidth entering and leaving die 104.

[0191] Figure 17 shows another exemplary embodiment including multiple DPE interfaces. In the example of Figure 17, two dies 104, shown as die 104-1 and die 104-2, are shown including different DPE arrays. Dies 104-1 and 104-2 connect to die 106 of IC 100. Inter-die wires may be implemented as described in relation to Figure 1 or Figure 2. As shown, die 104-1 includes DPE array 110-1. Die 104-2 includes DPE array 110-2. DPE array 110-1 connects to DPE interface 302-1. DPE array 110-2 connects to DPE interface 302-2. DPE interface 302-1 includes a logical interface 304-1 and a physical interface 306-1. DPE interface 302-2 includes a logical interface 304-2 and a physical interface 306-2.

[0192] Die 106 includes physical interface 312-1 and physical interface 312-2. Physical interface 312-1 connects to physical interface 306-1. Physical interface 312-2 connects to physical interface 306-2. In one or more exemplary embodiments, physical interfaces 306-1, 312-1, 306-2, and 312-2 are implemented as the same interface (e.g., matching, as shown in one of Figures 10, 11, or 12). In one or more other exemplary embodiments, physical interfaces 306-1 and 312-1 are of the same type (e.g., matching, as shown in one of Figures 10, 11, or 12), while physical interfaces 306-2 and 312-2 are of the same type (e.g., matching), but different in type from physical interfaces 306-1 and 312-1.

[0193] In the example in Figure 17, the inclusion of an additional DPE interface increases the bandwidth entering and leaving each DPE array 110-1 and 110-2. Furthermore, the example in Figure 17 allows each DPE array 110 to operate independently of each other. This allows, for example, one application or user to utilize DPE array 110-1 while another different application and / or user uses DPE array 110-2, with each DPE array being physically isolated from the others.

[0194] The examples provided in relation to Figures 13 to 17 illustrate various multi-die IC embodiments including one or more DPE arrays. It should be understood that in one or more of the examples described herein, a die containing a DPE array may only include circuit elements for or corresponding to the DPE array and DPE interface contained therein. That is, such a die may be a dedicated or special-purpose DPE array die. In other examples, a die containing a DPE array and DPE interface may include additional circuit elements that operate in conjunction with the DPE array and / or DPE interface. Furthermore, the number of dies shown in the examples of Figures 13 to 17 is for illustrative purposes only. Additional DPE array dies and / or other dies may be included, each die capable of communicating with one or more other dies via appropriate interfaces described herein.

[0195] For explanatory purposes, and to provide a complete understanding of the various inventive concepts disclosed herein, specific nomenclature is described. However, it should be understood that the terminology used herein is merely for describing, and not limiting, certain aspects of the constructs of the invention.

[0196] As defined herein, the singular forms "a," "an," and "the" are intended to include the plural form unless the context explicitly indicates otherwise.

[0197] As defined herein, the terms “at least one,” “one or more,” and “and / or,” are open-ended expressions that are both conjunctive and disjunctive in their function unless otherwise specified. For example, each of the expressions “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, and C,” “one or more of A, B, or C,” and “A, B, and / or C” means A only, B only, C only, A and B, A and C, B and C, or A, B and C.

[0198] As defined herein, the term "automatically" means without human intervention. As defined herein, the term "user" means human being.

[0199] As defined herein, the term "if" means, depending on the context, "when," "in response to," or "in accordance with." Therefore, the phrase "if it is determined that" or "[the described condition or event] is detected" may be interpreted, depending on the context, as "upon determination," "in response to determination," "upon detection of [the described condition or event]," or "in response to detection of [the described condition or event]," or "in accordance with detection of [the described condition or event]."

[0200] As defined herein, the terms “in response to” and similar terms, such as “if,” “when,” or “in response to,” mean readily responding to or reacting to an action or event. The response or reaction is automatic. Therefore, when a second action is performed “in response to” a first action, there is a causal relationship between the occurrence of the first action and the occurrence of the second action. “In response to” indicates a causal relationship.

[0201] As defined herein, the term "processor" means at least one circuit capable of executing instructions contained in program code. The circuit may be an integrated circuit, or may be incorporated into an integrated circuit.

[0202] As defined herein, the term “substantially” means that the described characteristics, parameters, or values ​​do not need to be exactly achieved, but deviations or variations, including, for example, tolerances, measurement errors, measurement accuracy limits, and other factors known to those skilled in the art, may occur in an amount that does not negate the effect that the characteristic is intended to provide.

[0203] Terms such as "First," "Second," etc., may be used herein to describe various elements. These elements should not be limited by these terms, as they are used solely to distinguish one element from another, unless otherwise specified or the context clearly indicates otherwise.

[0204] All means-plus-function or step-plus-function elements that can be found in the attached claims are intended to include any structures, materials, or actions for performing a function in combination with other claimed elements specifically claimed.

[0205] In one or more exemplary embodiments, a multi-die IC includes an interposer and a first die coupled to the interposer. The first die includes a DPE array, and D A PE array includes multiple DPEs and DPE interfaces coupled to the multiple DPEs. The DPE interfaces have logical and physical interfaces. A multi-die IC may also include a second die coupled to an interposer and having a die interface. The DPE interfaces and die interfaces are configured to communicate through the interposer.

[0206] Each of the above and other embodiments may, individually or in combination, optionally include one or more of the following features. Some exemplary embodiments include all of the following features in combination.

[0207] In another embodiment, the logical interface of the DPE interface includes multiple tiles, each tile configured to communicate with a subset of multiple DPEs in the DPE array.

[0208] In another embodiment, the physical interface includes multiple circuit blocks coupled to multiple tiles of the logical interface.

[0209] In another embodiment, the multiple circuit blocks of the physical interface include at least a first circuit block implementing one or more parallel multibit channels and a second circuit block implementing a transceiver configured for serial operation.

[0210] In another embodiment, at least one of the multiple circuit blocks of the physical interface implements a parallel multi-bit channel.

[0211] In another embodiment, each circuit block of the physical interface is configured to operate independently.

[0212] In another embodiment, at least one of the multiple circuit blocks of the physical interface implements a high-bandwidth memory interface.

[0213] In another embodiment, at least one of the multiple circuit blocks of the physical interface includes a transceiver configured for serial operation.

[0214] In another embodiment, at least one of the circuit blocks of the physical interface includes a serializer / deserializer circuit coupled to a transceiver. The serializer / deserializer circuit is configured to generate first serialized data from a first data stream received from a selected tile of the logical interface and to provide the first serialized data to the transceiver. The serializer / deserializer circuit is also configured to generate a second data stream from second serialized data received from the transceiver and to provide the second data stream to a selected tile of the logical interface.

[0215] In another embodiment, the multi-die IC includes a package substrate coupled to an interposer.

[0216] In another embodiment, the first die and the second die are in different clock domains. In one or more other exemplary embodiments, a multi-die IC includes a package substrate, a first die coupled to the package substrate, the first die configured as an interconnection bridge, and a second die coupled to the package substrate and the first die. The second die includes a DPE array, the DPE array comprising a plurality of DPEs and The multi-die IC also includes a DPE interface coupled to multiple DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC may also include a package substrate and a third die coupled to the first die, the third die including a die interface. The DPE interface and the die interface are configured to communicate through the first die.

[0217] Each of the above and other embodiments may, individually or in combination, optionally include one or more of the following features. Some exemplary embodiments include all of the following features in combination.

[0218] In another embodiment, the logical interface of the DPE interface includes multiple tiles, each tile configured to communicate with a subset of multiple DPEs in the DPE array.

[0219] In another embodiment, the physical interface includes multiple circuit blocks coupled to multiple tiles of the logical interface.

[0220] In another embodiment, at least one of the multiple circuit blocks of the physical interface implements a parallel multi-bit channel.

[0221] In another embodiment, each circuit block of the physical interface is configured to operate independently.

[0222] In another embodiment, at least one of the multiple circuit blocks of the physical interface implements a high-bandwidth memory interface.

[0223] In another embodiment, at least one of the multiple circuit blocks of the physical interface includes a transceiver configured for serial operation.

[0224] In another embodiment, at least one of the circuit blocks of the physical interface includes a serializer / deserializer circuit coupled to a transceiver. The serializer / deserializer circuit is configured to generate first serialized data from a first data stream received from a selected tile of the logical interface and to provide the first serialized data to the transceiver. The serializer / deserializer circuit may also be configured to generate a second data stream from second serialized data received from the transceiver and to provide the second data stream to a selected tile of the logical interface.

[0225] In another embodiment, the first die and the third die are in different clock domains. The description of the configuration of the present invention provided herein is presented for illustrative purposes only and is not intended to be exhaustive or limited to the disclosed forms and examples. The terminology used herein has been selected to describe the principles of the configuration of the present invention, its practical applications, or technical improvements to the technology found in the market, and / or to enable other persons skilled in the art to understand the configuration of the present invention disclosed herein. Modifications and alterations will be apparent to those skilled in the art without departing from the scope and spirit of the configuration of the present invention described herein. Therefore, as to the scope of such features and embodiments, one should refer to the appended claims rather than the foregoing disclosure.

Claims

1. A multi-die integrated circuit, Interposer and, A first die coupled to the interposer, the first die includes a data processing engine (DPE) array, the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs, the DPE interface having a logical interface and a physical interface, and A second die coupled to the interposer and having a die interface Equipped with, A multi-die integrated circuit in which the DPE interface and the die interface are configured to communicate through the interposer.

2. The logical interface of the DPE interface includes a plurality of tiles, Each tile is configured to communicate with a subset of the multiple DPEs of the DPE array, The multi-die integrated circuit according to claim 1, wherein the physical interface includes a plurality of circuit blocks coupled to the plurality of tiles of the logical interface.

3. The multi-die integrated circuit according to claim 2, wherein the plurality of circuit blocks of the physical interface include at least one first circuit block implementing one or more parallel multi-bit channels and a second circuit block implementing a transceiver configured for serial operation.

4. The multi-die integrated circuit according to claim 2, wherein at least one of the plurality of circuit blocks of the physical interface implements a high-bandwidth memory interface.

5. At least one of the plurality of circuit blocks of the physical interface includes a transceiver configured for serial operation, At least one of the circuit blocks of the physical interface is A serializer / deserializer circuit coupled to the transceiver, A first serialized data is generated from a first data stream received from a selected tile of the logical interface, and the first serialized data is provided to the transceiver. A serializer / deserializer circuit is configured to generate a second data stream from second serialized data received from the transceiver and to provide the second data stream to the selected tile of the logic interface. A multi-die integrated circuit according to claim 2, comprising:

6. The multi-die integrated circuit according to claim 1, wherein the first die and the second die are in different clock domains.

7. The multi-die integrated circuit according to claim 1, wherein the first die and the second die are in different power domains.

8. The multi-die integrated circuit according to claim 1, wherein the first die and the second die are mounted using different process technologies.

9. A multi-die integrated circuit, Package substrate and A first die bonded to the package substrate, wherein the first die is configured as an interconnection bridge, and A second die coupled to the package substrate and the first die, the second die including a data processing engine (DPE) array, the DPE array including a plurality of DPEs and a DPE interface coupled to the plurality of DPEs, the DPE interface having a logical interface and a physical interface, A third die coupled to the package substrate and the first die, wherein the third die includes a die interface. Equipped with, A multi-die integrated circuit in which the DPE interface and the die interface are configured to communicate through the first die.

10. The logical interface of the DPE interface includes a plurality of tiles, Each tile is configured to communicate with a subset of the multiple DPEs of the DPE array, The multi-die integrated circuit according to claim 9, wherein the physical interface includes a plurality of circuit blocks coupled to the plurality of tiles of the logical interface.

11. The multi-die integrated circuit according to claim 10, wherein at least one of the plurality of circuit blocks of the physical interface implements a high-bandwidth memory interface.

12. At least one of the plurality of circuit blocks of the physical interface includes a transceiver configured for serial operation, At least one of the circuit blocks of the physical interface is A serializer / deserializer circuit coupled to the transceiver, A first serialized data is generated from a first data stream received from a selected tile of the logical interface, and the first serialized data is provided to the transceiver. A serializer / deserializer circuit is configured to generate a second data stream from second serialized data received from the transceiver and to provide the second data stream to the selected tile of the logic interface. A multi-die integrated circuit according to claim 10, comprising:

13. The multi-die integrated circuit according to claim 9, wherein the second die and the third die are in different clock domains.

14. The multi-die integrated circuit according to claim 9, wherein the second die and the third die are in different power domains.

15. The multi-die integrated circuit according to claim 9, wherein the second die and the third die are mounted using different process technologies.

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