Power-efficient synchronous-source data network

Abstract

Techniques and apparatuses are described for implementing a power-efficient synchronous-source data network. In an example aspect, a data network (112) provides a communication interface between a data source (110) and multiple subsystems (108) on a system-on-chip (106). The data network (112) includes pipeline circuits that can propagate multiple clock enable signals upstream from the multiple subsystems (108) towards the data source (110). The upstream propagation of these clock enable signals through the pipeline circuits enables the data network (112) to identify paths along which a data signal and a clock signal are to propagate downstream from the data source (110) towards the multiple subsystems (108). The clock enable signals can be asynchronous signals, which obviates the need for a synchronizer within the pipeline circuits. With the described techniques, dynamic power of the data network (112) can be reduced by at least 50% compared to other networks with "always-on" retimer circuits.

Description

POWER-EFFICIENT SYNCHRONOUS-SOURCE DATA NETWORKBACKGROUND

[0001] An electronic device can be implemented with a system-on-chip (SoC), which can provide many features of the electronic device. An example system-on-chip can include multiple subsystems, such as a central processing unit (CPU), a graphics processing unit (GPU), and / or an image processing unit (1PU). Technological advancements enable a system-on-chip to be designed with a larger quantity of subsystems to further expand feature capabilities of the electronic device. The larger quantity of subsystems, however, can increase a complexity for establishing communications between these subsystems.SUMMARY

[0002] Techniques and apparatuses are described for implementing a power-efficient synchronous-source data network. In example aspects, a data network provides a communication interface between a data source and multiple subsystems on a system-on-chip. The data network includes various pipeline circuits that can propagate multiple clock enable signals upstream from the multiple subsystems towards the data source. The upstream propagation of these clock enable signals through the pipeline circuits enables the data network to identify paths along which a data signal and a clock signal are to propagate downstream from the data source towards the multiple subsystems. The clock enable signals can be asynchronous signals, which obviates the need for a synchronizer within the pipeline circuits. With the described techniques, dynamic power of the data network can be reduced by at least 50% compared to other netw orks w ith “always-on” retimer circuits.

[0003] Aspects described below include a method performed by a power-efficient synchronous- source data network. The method includes receiving a first request signal from a first subsystem implemented on a system-on-chip. The first request signal indicates that the first subsystem requests data from a data source that is implemented on the system-on-chip. The method also includes generating a first clock enable signal based on the first request signal. The method additionally includes propagating the first clock enable signal upstream using a first set of pipeline circuits of a data network. The first set of pipeline circuits is coupled between the first subsystem and the data source. The method further includes receiving a data signal and a clock signal from the data source. The method also includes propagating the data signal and the clock signal downstream to the first subsystem using the first set of pipeline circuits based on the propagating of the first clock enable signal upstream using the first set of pipeline circuits.

[0004] Aspects described below also include another method performed by power-efficient synchronous-source data network. The method includes propagating a first set of clock enable signals upstream through a first set of pipeline circuits of the data network. The first set of clock enable signals corresponds to a first set of subsystems implemented on the system-on-chip. The first set of clock enable signals indicates that the first set of subsystems requests data from a data source that is implemented on the system-on-chip. The method also includes causing, based on the propagating of the first set of clock enable signals, the first set of pipeline circuits to be in a first state that is capable of propagating signals downstream to the first set of subsystems. The method additionally includes propagating a second set of clock enable signals upstream through a second set of pipeline circuits of the data network. The second set of clock enable signals corresponds to a second set of subsystems implemented on the system-on-chip. The second set of clock enable signals indicates that the second set of subsystems does not request the data from the data source. The method also includes causing, based on the propagating of second set of clock enable signals, at least a subset of the second set of pipeline circuits to be in a second state that blocks the propagating of the signals downstream to the second set of subsystems.

[0005] Aspects described below also include an apparatus with a system-on-chip including a data network. The system-on-chip is configured to perform, using the data network, any of the described methods.

[0006] Aspects described below also include a system with means for performing power-efficient synchronous-source data transfer.BRIEF DESCRIPTION OF DRAWINGS

[0007] Apparatuses for and techniques for implementing a power-efficient synchronous-source data netw ork are described with reference to the following drawings. The same numbers are used throughout the drawings to reference like features and components:FIG. 1 illustrates an example environment in which a power-efficient synchronous-source data netw ork can be implemented;FIG. 2 illustrates an example implementation of a computing device including a powerefficient synchronous-source data netw ork;FIG. 3 illustrates an example system-on-chip including a power-efficient synchronous- source data network;FIG. 4 illustrates example pipeline circuits and paths of a power-efficient synchronous- source data netw ork;FIG. 5 illustrates example types of pipeline circuits of a power-efficient synchronous- source data network;FIG. 6 illustrates an example passthrough pipeline circuit for implementing an aspect of a power-efficient synchronous-source data network;FIG. 7 illustrates an example gated pipeline circuit for implementing an aspect of a powerefficient synchronous-source data network;FIG. 8 illustrates an example branch-point pipeline circuit for implementing an aspect of a power-efficient synchronous-source data network;FIG. 9 illustrates an example mixed pipeline circuit for implementing an aspect of a powerefficient synchronous-source data network;FIG. 10 illustrates an example power-efficient synchronous-source data network implemented on a system-on-chip;FIG. 11 illustrates an example flow diagram for requesting and sending data via a powerefficient synchronous-source data network;FIG. 12 illustrates a first example method for operating a power-efficient synchronous- source data network;FIG. 13 illustrates a second example method for operating a power-efficient synchronous- source data network; andFIG. 14 illustrates an example computing system embodying, or in which techniques may be implemented that enable use of, a power-efficient synchronous -source data network.DETAILED DESCRIPTION

[0008] Technological advancements enable a system-on-chip (SoC) to be designed with a larger quantity of subsystems to further expand feature capabilities of an electronic device. The larger quantity of subsystems, however, can increase a complexity for establishing communications between these subsystems. As the various subsystems can be physically distributed across the system-on-chip, it can be challenging to ensure data reaches these subsystems at the appropriate time to perform a source-synchronous data transfer. Some techniques distribute retimer circuits across the various data propagation paths to compensate for the propagation delays. The retimer circuits synchronize the data to a clock signal and ensure the data is aligned to the clock signal at each subsystem.

[0009] In an example situation, one or more subsystems request data from the data source during a given time interval. To ensure the data reaches the subsystems that requested the data, the system-on-chip broadcasts the data to each subsystem, including the one or more subsystems that did not request the data. This means that the retimer circuits propagate the data and the clock signal even if the retimer circuits are not coupled between the data source and the subsystems thatrequested the data. The operation of these unnecessary retimer circuits wastes power and decreases a power efficiency of the system-on-chip.

[0010] To address this inefficiency, some techniques map different groups of retimer circuits to the different subsystems. This mapping can be stored by the system-on-chip and referenced to determine which retimer circuits to activate (or deactivate) for each data transfer. Although this can improve the power efficiency, it can add a significant amount of complexity to the design of the system-on-chip.

[0011] To address this challenge, techniques are described for implementing a power-efficient synchronous-source data network. In example aspects, a data network provides a communication interface between a data source and multiple subsystems on a system-on-chip. The data network includes various pipeline circuits that can propagate multiple clock enable signals upstream from the multiple subsystems towards the data source. The upstream propagation of these clock enable signals through the pipeline circuits enables the data network to identify paths along which a data signal and a clock signal are to propagate dow nstream from the data source towards the multiple subsystems. The clock enable signals can be asynchronous signals, which obviates the need for a synchronizer within the pipeline circuits. With the described techniques, dynamic power of the data network can be reduced by at least 50% compared to other networks with “always-on” retimer circuits.Operating Environment

[0012] FIG. 1 is an illustration of an example environment 100 in which a power-efficient synchronous-source data network can be implemented. In the example environment 100, a computing device 102 provides features and / or services for a user 104. Although depicted as a smartphone, the computing device 102 can include other types of devices, including those described with respect to FIG. 2. The computing device 102 includes at least one system-on- chip 106 (SOC 106). The system-on-chip 106 can be implemented with electronic circuitry, a microprocessor, memory, input-output (I / O) control logic, communication interfaces, firmware, and / or software useful to provide functionalities of the computing device 102.

[0013] The system-on-chip 106 includes multiple subsystems 108-1, 108-2... 108-S, where S represents a positive integer. In some implementations, the quantity of subsystems 108 within the system-on-chip 106 can be in the order of tens, hundreds, or more (e.g., 10, 50, 100, 150, 200, 500, and so forth). The subsystems 108 can also be referred to as agents, modules, intellectualproperty blocks (IP blocks), intellectual-property cores, or virtual components. Example subsystems 108 can include a central processing unit (CPU), a graphics processing unit (GPU),an image processing unit (IPU), a modem, a digital signal processor (DSP), a neural processing unit (NPU), a processor, a controller; a memory. a sensor, encoders, decoders, an analog circuit, a digital circuit, an input / output (I / O) device, components that handle application-specific processing functions, and so forth.

[0014] The system-on-chip 106 also includes at least one data source 110 and at least one data network 1 12. The data source 110 can send data to the subsystems 108 upon request. The data source 110 can also be considered another subsystem of the system-on-chip 106.

[0015] The data network 112 provides a communication interface between the data source 110 and the subsystems 108. To transfer data from the data source 110 to one or more subsystems 108, the data network 112 performs a source-synchronous data transfer 114. As such, the data network 112 can also be referred to as a source-synchronous data network.

[0016] The source-synchronous data transfer 114 synchronizes the data to a clock signal provided by the data source 110, and ensures the data is aligned to the clock signal at the subsystem 108. To improve the power efficiency of the source-synchronous data transfer 114 relative to other techniques, the data network 1 12 is implemented using pipeline circuits capable of propagating a clock enable signal upstream, as further described with respect to FIG. 3.

[0017] The components ofthe system-on-chip 106 (e.g., the subsystems 108, the data source 110, and the data network 112) may alternatively be implemented within other types of integrated circuits or embedded systems, such as a microchip, an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a digital signal processor (DSP), a programmable system-on-chip (PSoC), a system-in-package (SiP), and so forth. The computing device 102 is further described with respect to FIG. 2.

[0018] FIG. 2 illustrates an example computing device 102. The computing device 102 is illustrated with various non-limiting example devices including a desktop computer 102-1, a tablet 102-2, a laptop 102-3, a television 102-4, a computing watch 102-5, computing glasses 102-6, a gaming system 102-7, a microwave 102-8, and a vehicle 102-9. Other devices may also be used, such as a home service device, a smart speaker, a smart thermostat, a baby monitor, a Wi-Fi™ router, a drone, a trackpad, a drawing pad, a netbook, an e-reader, a home automation and control system, a wall display, and another home appliance. Note that the computing device 102 can be wearable, non-wearable but mobile, or relatively immobile (e.g., desktops and appliances).

[0019] The computing device 102 includes at least one system-on-chip 106. The system-on- chip 106 includes the subsystems 108-1 to 108-S, the data source 110, and the data netw ork 112. Example operations of the subsystems 108 are further described with respect to FIG. 3. In anexample implementation, the data source 110 is a repair controller 202 capable of sending repair data to any of the subsystems 108 via the data network 112. In other example implementations, the data source 110 represents a memory controller capable of sending data that is read from a memory array on the system-on-chip 106. Example implementations of the data network 112 are further described with respect to FIGs. 4 and 10.

[0020] The computing device 102 can also include a network interface 204 for communicating data over wired, wireless, or optical networks. For example, the network interface 204 may communicate data over a local-area-network (LAN), a wireless local-area-network (WLAN), a personal-area-network (PAN), a wire-area-network (WAN), an intranet, the Internet, a peer-to- peer network, point-to-point network, a mesh network, Bluetooth™, and the like. The computing device 102 may also include a display 206. A relationship between the subsystems 108, the data source 110, and the data network 112 is further described with respect to FIG. 3.Power-Efficient Synchronous -Source Data Network

[0021] FIG. 3 illustrates an example system-on-chip 106 including the data network 112, which represents a pow er-efficient synchronous-source data netw ork. In the depicted configuration, the data netw ork 112 is coupled between the subsystems 108-1, 108-2, 108-3, 108-4... 108-S and the data source 110. Each subsystem 108 can include a power manager 302 (PM 302) and a data reader 304. The power manager 302 controls an operational state of the subsystem 108. For example, the power manager 302 can cause the subsystem 108 to be in an active state 306 or an inactive state 308. While in the active state 306, the subsystem 108 consumes power. In the inactive state 308, the subsystem 108 does not consume power or consumes significantly less power compared to the active state 306. In some situations, the powder manager 302 can cause the subsystem 108 to be in the inactive state 308 when not in use to reduce power consumption of the system-on-chip 106.

[0022] The data reader 304 reads a header of the data that propagates to the subsystem 108 and determines if the data is intended for the subsystem 108. For example, the data reader 304 performs a comparison operation to determine if a block identification number, w hich is included as part of the header, matches a block identification of the subsystem 108. If it does, the data reader 304 passes the data to other components of the subsystem 108. Alternatively, if the data reader 304 determines that the data is not intended for the subsystem 108, the data reader 304 does not pass the data to the other components of the subsystem 108. With this logic, the data source 110 can broadcast data intended for different subsystems 108 across the data network 112 and the subsystems 108 can read the data that is intended for them.

[0023] During operation, each subsystem 108 can generate a request signal 310 (REQ 310). The request signal 310 includes an indicator to identify whether the subsystem 108 is requesting data from the data source 110. In general, subsystems 108 that are in the active state 306 can set this indicator to a first logic value (e.g., a logic value of " I ") to request data from the data source 110. The subsystems 108 that are in the inactive state 308 set this indicator to a second logic value (e.g., a logic value of “0”) to indicate that data is not requested from the data source 1 10. In some cases, multiple subsystems 108 can request data from the data source 110 during a same time interv al.

[0024] Consider an example in which the data source 110 is the repair controller 202. In this case, the request signal 310 can enable the subsystem 108 to request repair data from the repair controller 202. The data network 112 forwards the request signals 310 upstream 312 to the data source 110.

[0025] The data source 110 receives a clock signal 314 from the system-on-chip 106. The data source 110 passes the clock signal 314 and a data signal 316 to the data network 112 based on the request signals 310. The data signal 316 can include one or more packets of data. Each packet can be associated with one of the received requests and can include a header with a block identification number of the subsystem that requested the data. The data signal 316 is a synchronous signal, as indicated at 318. This means that a phase of the data signal 316 is aligned with a phase of the clock signal 314.

[0026] The data network 112 propagates the clock signal 314 and the data signal 316 dow nstream 320 from the data source 110 to the subsystems 108 that requested the data. The data network 112 also ensures that the data signal 316 remains aligned with the clock signal 314. In this manner, the data network 112 performs the source-synchronous data transfer 114. The one or more subsystems 108 that sent the request receive the clock signal 314 and the data signal 316. Using the clock signal 314, each of these subsystems 108 reads the information within the data signal 316. Each subsystem 108 can use the data provided by the data signal 316 to perform some type of operation. In an example situation in which the data signal 316 includes repair data, the subsystem 108 uses the repair data to perform a repair operation.

[0027] The data network 112 includes multiple pipeline circuits 322-1 to 322-P, where P represents a positive integer. The pipeline circuits 322 form paths between the data source 110 and the subsystems 108, as further described with respect to FIG. 4. During operation, the pipeline circuits 322 can propagate multiple clock enable signals 324 upstream 312 from the multiple subsystems 108 towards the data source 110. The data network 112 generates the clock enable signals 324 based on the request signals 310. In general, the clock enable signal 324 can have alogic value that represents a logic value of the indicator within the request signal 310. For example, if the indicator within the request signal 310 has the first logic value, the clock enable signal 324 can also have the first logic value. Alternatively, if the indicator within the request signal 310 has the second logic value, the clock enable signal 324 can also have the second logic value.

[0028] The upstream propagation of these clock enable signals 324 through the pipeline circuits 322 enables the data network 112 to identify paths along which the data signal 316 and the clock signal 314 are to propagate downstream 320 from the data source 110 towards the multiple subsystems 108. Based on the clock enable signals 324. the pipeline circuits 322 can propagate the clock signal 314 and the data signal 316 downstream 320 from the data source 1 10 to the set of subsystems 108 that requested the data. The pipeline circuits 322 also synchronize the data signal 316 to the clock signal 314.

[0029] Various implementations of the pipeline circuits 322 perform aspects of propagating 326, gating 328, merging 330, or some combination thereof based on the clock enable signals 324. In general, each pipeline circuit 322 can propagate a clock enable signal 324 upstream 312. Some pipeline circuits 322 use the clock enable signal 324 to gate downstream 320 propagation of the clock signal 314 and the data signal 316 to improve power efficiency. Still other pipeline circuits 322 merge multiple clock enable signals 324 together and propagate a composite form of the multiple clock enable signals 324 upstream 312. Example types of pipeline circuits 322 are further described with respect to FIG. 5.

[0030] The clock enable signals 324 can be asynchronous signals, as indicated at 332. This means that the clock enable signals 324 are not necessarily aligned in phase to the clock signal 314. The asynchronous nature of the clock enable signals 324 obviates the need for synchronizers to be integrated within the pipeline circuits 322. The asynchronous nature of the clock enable signals 324 also reflects the asynchronous nature in which the subsystems 108 can request the data from the data source 110.

[0031] With the upstream 312 propagation of the clock enable signals 324, the gating 328 performed by at least some of the pipeline circuits 322 is appropriately set to ensure the clock signal 314 and the data signal 316 propagate to the one or more subsystems 108 requesting data. The gating 328 also ensures that the clock signal 314 and the data signal 316 do not propagate further downstream to the remaining subsystems 108 that do not request the data. In this way, the data network 112 can conserve power and can represent a power-efficient synchronous-source data network. In some implementations, dynamic power of the data network 1 12 can be reduced by at least 50% compared to other networks with “always-on” retimer circuits. The describedtechniques also enable clock switching within the data network 112 to be reduced by at least 60% (and sometimes reduced up to 90%) compared to other networks. In this way, the system-on- chip 106 can conserve power and can be implemented within mobile devices that have limited power resources.

[0032] In the example shown in FIG. 3, the data network 112 is coupled to a single data source 110. Other implementations are also possible in which the data network 112 is coupled to multiple data sources 110 via a selection circuit, such as a multiplexer. An example arrangement of the pipeline circuits 322 within the data network 112 is further described with respect to FIG. 4.

[0033] FIG. 4 illustrates example pipeline circuits 322 and paths 402 of the data network 112. In the depicted configuration, the data network 112 includes pipeline circuits 322-1, 322-2, 322-3, 322-4, and 322-5. The data network 112 can include other pipeline circuits 322, which are not shown for simplicity. The pipeline circuit 322-1 is coupled to the data source 110 (not explicitly shown). The pipeline circuit 322-3 is coupled to the subsystem 108-1 (not explicitly shown), and the pipeline circuit 322-4 is coupled to the subsystem 108-2 (not explicitly shown). The pipeline circuit 322-5 can be indirectly coupled to other subsystems 108-3 to 108-S (not explicitly shown) on the system-on-chip 106.

[0034] As described above with respect to FIG. 3, different sets of the pipeline circuits 322 form different paths 402 between the subsystems 108 and the data source 110. These paths 402 enable the clock enable signals 324 to propagate upstream 312 and enable the clock signal 314 and the data signal 316 to propagate downstream 320. In example implementations, the quantity of paths 402 is equal to the quantity of subsystems 108. As such, each path 402 allows signals to flow between a corresponding subsystem 108 and the data source 110. The paths 402 can overlap and include a same subset of the pipeline circuits 322, as further descnbed below.

[0035] A first path 402-1 exists between the data source 110 and the subsystem 108-1 . The first path 402-1 includes the pipeline circuits 322-1, 322-2, and 322-3. A second path 402-2 exists between the data source 110 and the subsystem 108-2. The second path 402-2 includes the pipeline circuits 322-1, 322-2, and 322-4. The data network 112 can also include other paths, such as paths 402-3 to 402-S, which at least include the pipeline circuits 322-1, 322-2, and 322-5.

[0036] In this example, the paths 402-1 to 402-S share the pipeline circuits 322- 1 and 322-2. Each path 402 also includes other pipeline circuits 322 that are unique to that path 402. For example, the pipeline circuit 322-3 is included in the first path 402-1 and is not included in the other paths 402-2 to 402-S. Likewise, the pipeline circuit 322-4 is included in the second path 402-2 and is not included in the other paths 402-1 and 402-3 to 402-S.

[0037] All of the pipeline circuits 322-1 to 322-5 support the upstream 312 propagation 326 of the clock enable signals 324. A pipeline circuit 322 that is implemented upstream 312 of a branch node 404, such as the pipeline circuit 322-2, also performs merging 330. This means that the pipeline circuit 322-2 merges multiple clock enable signals 324 provided by the pipeline circuits 322-3, 322-4, and 322-5, which are connected to the branch node 404. The branch node 404 indicates a point where branching occurs. In general, the branch node 404 indicates a situation in which a pipeline circuit 322 is coupled to two or more other pipeline circuits. It also indicates a situation in which at least two paths 402 merge together in the upstream 312 direction or separate in the downstream 320 direction.

[0038] The pipeline circuits 322-3 and 322-4 perform gating 328 to selectively enable or disable the propagation of the clock signal 314 and the data signal 316 based on the clock enable signals 324. The pipeline circuit 322-5 can perform propagating 326, gating 328, and / or merging 330 depending on the downstream architecture of the data network 112. With the propagating 326 and the merging 330, the pipeline circuits 322 carry the clock enable signals 324 from multiple subsystems 108 upstream 312 towards the data source 110. The feedback provided by the propagation of the clock enable signals 324 ensures only the necessary paths 402 are activated for a requested data transfer, as further described below.

[0039] For simplicity, the upstream 312 propagation of the clock enable signals 324 and the downstream propagation of the data signal 316 and the clock signal 314 are generally represented by solid lines in FIG. 4. These solid lines connect the pipeline circuits 322 together, connect the pipeline circuit 322-1 to the data source 110, and connect some of the pipeline circuits 322 to the subsystems 108. In this example, the pipeline circuits 322-3, 322-4, and 322-5 pass corresponding clock enable signals 324 upstream 312 to the pipeline circuit 322-2. The pipeline circuit 322-2 passes a composite clock enable signal 324 upstream 312 to the pipeline circuit 322-1. In various implementations, the pipeline circuit 322-1 can be designed to pass or not pass the clock enable signal 324 to the data source 110. If the pipeline circuit 322-1 is the first pipeline circuit 322 downstream from the data source 110, the pipeline circuit 322 does not have to propagate the clock enable signal 324 further upstream 312 because there are no additional pipeline circuits 322 that need to be enabled for transferring data via one or more of the paths 402.

[0040] The pipeline circuit 322-1 receives the clock signal 314 and the data signal 316 from the data source 110. The pipeline circuit 322-1 passes the clock signal 314 and the data signal 316 downstream 320 to the pipeline circuit 322-2. The pipeline circuit 322-2 passes the clock signal 314 and the data signal 316 downstream 320 to the pipeline circuits 322-3, 322-4, and 322-5. The pipeline circuits 322-3 and 322-4 can pass the data signal 316 and the clock signal 314downstream 320 to the subsystems 108-1 and 108-2, respectively. The pipeline circuit 322-5 can pass the clock signal 314 and the data signal 316 downstream to the subsystems 108-3 to 108-S.

[0041] To improve power efficiency, the upstream 312 propagation of the clock enable signals 324 appropriately configures the gating 328 performed by the pipeline circuits 322-3 and 322-4. Consider an example in which the system 108-1 requests data from the data source 1 10 and the subsystems 108-2 to 108-S do not request data, in this case, the propagation of a first clock enable signal 324 along the first path 402-1 causes the pipeline circuit 322-3 to pass the clock signal 314 and the data signal 316 downstream 320 to the subsystem 108-1. The propagation of other clock enable signals 324 along the paths 402-2 to 402-S prevents the clock signal 314 and the data signal 316 from propagating downstream 320 to the subsystems 108-2 to 108-S. More specifically, the other clock enable signals 324 have an opposite logic value as the first clock enable signal 324 to activate the gating 328 at some point along the paths 402-2 to 402-S that is distinct from the first path 402-1 (e.g., at a point that is not part of the first path 402-1). In this case, any pipeline circuit 322 that performs the gating 328 along the paths 402-2 to 402-S and is not part of the first path 402-1 prevents further downstream propagation of the clock signal 314 and the data signal 316, thereby conserving power resources of the system-on-chip 106. To perform the various aspects of the propagating 326, the merging 330, and / or the gating 328, the pipeline circuits 322-1 to 322-5 can have different designs (e.g., can have different components), as further described with respect to FIG. 5.

[0042] FIG. 5 illustrates example types of pipeline circuits 322 of the data network 112. The pipeline circuits 322 shown in FIGs. 3 and 4 can be implemented using some combination of a passthrough pipeline circuit 502, a gated pipeline circuit 504, a branch-point pipeline circuit 506, and a mixed pipeline circuit 508. Each type of pipeline circuit 322 includes an n-bit pipeline 510. The n-bit pipeline 510 can be implemented using multiple flip-flops, which are connected together in series to form a pipeline. In this case, the variable n represents the quantity7of flip-flops or the quantity of stages within the pipeline. In general, an operation of the n-bit pipeline 510 in propagating and synchronizing a data signal 316 consumes power. This power consumption can reduce a power efficiency of the data network 112 if the n-bit pipeline 510 is active but not used to perform a source-synchronous data transfer 114. The techniques for implementing a powerefficient synchronous-source data network avoids this situation.

[0043] The pipeline circuits 322 also include a buffer 512 or a clock gate 514. The buffer 512 propagates the clock signal 314 downstream 320. The clock gate 514 can selectively enable or disable the propagation of the clock signal 314 downstream 320. This also gates the dow nstream 320 propagation of the data signal 316, as further show n in FIGs. 7 and 9.

[0044] The various pipeline circuits 322 additionally include an upstream passthrough 516 or a multi-input upstream passthrough 518. The upstream passthrough 516 propagates a clock enable signal 324 upstream 312, as further described with respect to FIGs. 6 and 7. The multi-input upstream passthrough 518 enables multiple clock enable signals 324 (e.g., clock enable signals 324 originating from different paths 402) to propagate upstream 312, as further described with respect to FIGs. 8 and 9.

[0045] The passthrough pipeline circuit 502 includes the n-bit pipeline 510, the buffer 512, and the upstream passthrough 516. The gated pipeline circuit 504 includes the n-bit pipeline 510, the clock gate 514. and the upstream passthrough 516. With the upstream passthrough 516, both the passthrough pipeline circuit 502 and the gated pipeline circuit 504 propagate a received clock enable signal 324 upstream. The passthrough pipeline circuit 502 also propagates the clock signal 314 and the data signal 316 downstream 320. The gated pipeline circuit 504 can selectively gate the clock signal 314 based on the clock enable signal 324 to improve the power efficiency of the data network 112. As such, the gated pipeline circuit 504 can selectively propagate the clock signal 314 and the data signal 316 downstream 320 based on the clock enable signal 314.

[0046] The branch-point pipeline circuit 506 includes the n-bit pipeline 510, the buffer 512, and the multi-input upstream passthrough 518. The mixed pipeline circuit 508 includes the n-bit pipeline 510. the clock gate 514, and the multi-input upstream passthrough 518. Both the branchpoint pipeline circuit 506 and the mixed pipeline circuit 508 can merge multiple clock enable signals 324 together using the multi -input upstream passthrough 518. The branch-point pipeline circuit 506 also propagates the clock signal 314 and the data signal 316 downstream 320, similar to the passthrough pipeline circuit 502. The mixed pipeline circuit 508 can selectively gate the clock signal 314 based on the multiple clock enable signals 324 to improve the power efficiency of the data network 112, similar to the gated pipeline circuit 504. As such, the mixed pipeline circuit 508 can selectively propagate the clock signal 314 and the data signal 316 downstream 320 based on the clock enable signal 314.

[0047] Each type of pipeline circuit 322 can include a data input 520, a data output 522, a clock input 524, a clock output 526, at least one upstream enable input 528, and an upstream enable output 530. For implementations of the pipeline circuit 322 that include the multi-input upstream passthrough 518, the pipeline circuit 322 can include multiple upstream enable inputs 528. The pipeline circuit 322 receives the data signal 316 at the data input 520 and can propagate the data signal 316 to the data output 522. At the clock input 524, the pipeline circuit 322 receives the clock signal 314. The pipeline circuit 322 can also propagate the clock signal 314 to the clock output 526. The pipeline circuit 322 receives the clock enable signal 324 at the upstream enableinput 528 and propagates the clock enable signal 324 to the upstream enable output 530. Example implementations of the passthrough pipeline circuit 502, the gated pipeline circuit 504, the branchpoint pipeline circuit 506, and the mixed pipeline circuit 508 are described with respect to FIGs. 6, 7, 8, and 9, respectively.

[0048] FIG. 6 illustrates an example passthrough pipeline circuit 502. In the depicted configuration, the passthrough pipeline circuit 502 includes the n-bit pipeline 510, the buffer 512, and the upstream passthrough 516. The n-bit pipeline 510 is coupled between the data input 520 and the data output 522. The buffer 512 is coupled to the clock input 524, the clock output 526, and the n-bit pipeline 510. The upstream passthrough 516 is implemented between the clock enable input 528 and the clock enable output 530. To implement the passthrough pipeline circuit 502, the upstream passthrough 516 can be implemented as a simple passthrough circuit, such as a wire or a signal routing path that directly connects the clock enable input 528 to the clock enable output 530.

[0049] During operation, the n-bit pipeline 510 propagates the data signal 316 downstream 320 based on the clock signal 314. The buffer 512 propagates the clock signal 314 downstream 320. The upstream passthrough 516 propagates the clock enable signal 324 upstream 312.

[0050] In some implementations of the data network 112, the passthrough pipeline circuit 502 can represent a first pipeline circuit 322 that is directly connected to the data source 110, such as the pipeline circuit 322-1 of FIG. 4. Additionally or alternatively, the data network 112 can include another passthrough pipeline circuit 502 further downstream 320, which can be coupled to a gated pipeline circuit 504. To improve power efficiency, the passthrough pipeline circuit 502 is positioned downstream 320 from the gated pipeline circuit 504 (e.g., the gated pipeline circuit 504 is upstream 312 from the passthrough pipeline circuit 502). In this way, the gated pipeline circuit 504 can prevent the downstream propagation of the clock signal 314 and the data signal 316 through the passthrough pipeline circuit 502 to conserve power. The gated pipeline circuit 502 is further described w ith respect to FIG. 7.

[0051] FIG. 7 illustrates an example gated pipeline circuit 504. In the depicted configuration, the gated pipeline circuit 504 includes the n-bit pipeline 510, the clock gate 514, and the upstream passthrough 516. The n-bit pipeline 510 is coupled between the data input 520 and the data output 522. The clock gate 514 is coupled to the clock input 524, the clock output 526, the n-bit pipeline 510. and the clock enable output 530. The upstream passthrough 516 is implemented between the clock enable input 528 and the clock enable output 530. The upstream passthrough 516 can be implemented in a similar manner as the upstream passthrough 516 described with respect to FIG. 6.

[0052] During operation, the n-bit pipeline 510 propagates the data signal 316 downstream 320 based on the clock signal 314. The clock gate 514 selectively gates the clock signal 314 based on the clock enable signal 324. The clock gate 514 can be in an enabled state 702 or a disabled state 704 based on the clock enable signal 324. In the enabled state 702. the clock gate 514 passes the clock signal 314 to the n-bit pipeline 510 and the clock output 526. In contrast, the clock gate 514 prevents the clock signal 314 from propagating to the n-bit pipeline 510 and the clock output 526 in the disabled state 704. The upstream passthrough 516 propagates the clock enable signal 324 upstream 312.

[0053] In some implementations of the data network 112, the gated pipeline circuit 504 can be implemented downstream 320 from a branching node 404. For example, the gated pipeline circuit 504 can implement the pipeline circuits 322-3, 322-4, and 322-5 of FIG. 4. Additionally or alternatively, the data network 112 can include gated pipeline circuits 504 that are unique to their corresponding paths 402. These gated pipeline circuits 504 exist within the corresponding paths 402 and are not shared by multiple paths 402 (e.g., do not exist within the remaining paths 402), such as the pipeline circuits 322-3 and 322-4 of FIG. 4. With these gated pipeline circuits 504, the data network 112 can prevent the clock signal 314 and the data signal 316 from propagating further downstream 320 along corresponding paths 402 of the gated pipeline circuits 504 to corresponding subsystems 108 of the paths 402. While the gated pipeline circuit 504 can implement aspects of gating 328, other pipeline circuits 322 can implement aspects of merging 330, as further described with respect to the branch-point pipeline circuit 506 of FIG. 8 and the mixed pipeline circuit 508 of FIG. 9.

[0054] FIG. 8 illustrates an example branch-point pipeline circuit 506. In the depicted configuration, the branch-point pipeline circuit 506 includes the n-bit pipeline 510, the buffer 512, and the multi-input upstream passthrough 518. The n-bit pipeline 510 is coupled between the data input 520 and the data output 522. The buffer 512 is coupled to the clock input 524, the clock output 526, and the n-bit pipeline 510. The multi -input upstream passthrough 518 is implemented between the clock enable inputs 528-1 to 528-M and the clock enable output 530. where M represents a positive integer that is less than or equal to S. In this example, the multi-input upstream passthrough 518 includes at least one logic gate 802. The logic gate 802 is shown as an OR gate in FIG. 8. Other ty pes and combinations of logic gates can alternatively be used to implement the functionality of the logic gate 802.

[0055] During operation, the n-bit pipeline 510 propagates the data signal 316 downstream 320 based on the clock signal 314. The buffer 512 propagates the clock signal 314 downstream 320. The multi -input upstream passthrough 518 generates a compositive clock enable signal 804 basedon a combination of the clock enable signals 324-1 to 324-M respectively provided at the clock enable inputs 528-1 to 528-M. For example, the logic gate 802 performs a logical OR operation on the clock enable signals 324-1 to 324-M to generate the composite clock enable signal 804. The multi -input upstream passthrough 518 propagates the composite clock enable signal 804 upstream 312 to the clock enable output 530.

[0056] In some implementations of the data network 1 12, the branch-point pipeline circuit 506 can be implemented upstream 312 of a branch node 404. For example, the pipeline circuit 322-2 can be implemented as a branch point pipeline circuit 506. While the branch-point pipeline circuit 506 can implement aspects of merging 330, other pipeline circuits 322 can implement aspects of merging 330 and gating 328, as further described with respect to the mixed pipeline circuit 508 of FIG. 9.

[0057] FIG. 9 illustrates an example mixed pipeline circuit 508. In the depicted configuration, the mixed pipeline circuit 508 includes the n-bit pipeline 510, the clock gate 514, and the multiinput upstream passthrough 518. The n-bit pipeline 510 is coupled between the data input 520 and the data output 522. The clock gate 514 is coupled to the clock input 524, the clock output 526, the n-bit pipeline 510, and the clock enable output 530. The multi-input upstream passthrough 518 is implemented between the clock enable inputs 528-1 to 528-M and the clock enable output 530. In this example, the multi-input upstream passthrough 518 includes at least one logic gate 802. The logic gate 802 is shown as an OR gate in FIG. 9. Other types and combinations of logic gates can alternatively be used to implement the functionality of the logic gate 802.

[0058] During operation, the n-bit pipeline 510 propagates the data signal 316 downstream 320 based on the clock signal 314. The clock gate 514 selectively gates the clock signal 314 based on the composite clock enable signal 804. The clock gate 514 can be in the enabled state 702 or the disabled state 704 based on the composite clock enable signal 804. In the enabled state 702, the clock gate 514 passes the clock signal 314 to the n-bit pipeline 510 and the clock output 526. In contrast, the clock gate 514 prevents the clock signal 314 from propagating to the n-bit pipeline 510 and the clock output 526 in the disabled state 704. The multi-input upstream passthrough 518 generates the compositive clock enable signal 804 based on a combination of the clock enable signals 324-1 to 324-M respectively provided at the clock enable inputs 528-1 to 528-M. The multi -input upstream passthrough 518 propagates the composite clock enable signal 324 upstream 312.

[0059] The mixed pipeline circuit 508 can be implemented at a node that is between two branch nodes 404. This node can also be between two branch-point pipeline circuits 506 or between abranch-point pipeline circuit 506 and at least on gated pipeline circuit 504. An example implementation of the data network 112 including a combination of the passthrough pipeline circuit 502, the gated pipeline circuit 504, the branch-point pipeline circuit 506, and the mixed pipeline circuit 508 is further described with respect to FIG. 10.

[0060] FIG. 10 illustrates an example datanetwork 112 of the system-on-chip 106. In the depicted configuration, the data network 1 12 is coupled between the data source 1 10 and the subsystems 108-1, 108-2, 108-3, 108-4, and 108-5. The data network 112 includes a passthrough pipeline circuit 502, gated pipeline circuits 504-1, 504-2, 504-3, 504-4, and 504-5, branch-point pipeline circuits 506-1 and 506-2. and a mixed pipeline circuit 508. The passthrough pipeline circuit 502 is coupled to the data source 1 10. The branch-point pipeline circuit 506-1 is coupled between the passthrough pipeline circuit 502 and a first branch node 404-1. The gated pipeline circuits 504-1 to 504-5 are respectively coupled to the subsystems 108-1 to 108-5. The gated pipeline circuits 504-1 and 504-2 are also coupled to the branch node 404-1. The mixed pipeline circuit 508 is coupled between the branch nodes 404-1 and 404-2, and is also coupled between the branch-point pipeline circuits 506-1 and 506-2. As shown in FIG. 10, the branch-point pipeline circuits 506-1 and 506-2 are respectively downstream from the branch nodes 404-1 and 404-2. The gated pipeline circuit 504-3 is also coupled to the branch node 404-2. The branch-point pipeline circuit 506-2 is coupled between the branch nodes 404-2 and 404-3. The gated pipeline circuits 504-4 and 504-5 are also coupled to the branch node 404-3.

[0061] During operation, the data source 110 can be in an idle state 1002 or a busy state 1004. In the idle state 1002, the data source 110 can receive and grant requests sent by the subsystems 108. In the busy state 1004, the data source 110 is unable to receive new requests. To communicate a state of the data source 1 10 to the subsystems 108, the data network 112 passes an idle flag 1006 from the data source 110 to the subsystems 108. The idle flag 1006 can be directly passed to the subsystems 108 via the datanetwork 112 and does not propagate through the pipeline circuits 322.

[0062] Each subsystem 108 can determine if it can send a request based on the idle flag 1006. If the idle flag 1006 indicates that the data source 110 is in the idle state 1002, the subsystem 108 can send a request to the data source 110. Alternatively, if the idle flag 1006 indicates that the data source 110 is in the busy state 1004, the subsystem 108 does not send a request to the data source 110.

[0063] The subsystems 108-1. 108-2, 108-3, 108-4, and 108-5 respectively generate the request signals 310-1, 310-2, 310-3, 310-4, and 310-5. In some situations, at least two of the request signals 310-1 to 310-5 can indicate that at least two of the corresponding subsystems 108-1 to 108-5 are requesting data. This can occur during a same time interval. The data netw ork 112 candirectly pass the request signals 310 from the subsystem 108 to the data source 110. In this case, the request signals 310 do not propagate through the pipeline circuits 322. However, the data network 112 passes the request signals 310 to at least the first upstream 312 pipeline circuit 322, such as the pipeline circuits 504-1 to 504-5. The pipeline circuits 504-1 to 504-5 can generate corresponding clock enable signals 324 based on the request signals 310-1 to 310-5.

[0064] The various pipeline circuits 502, 504-1 to 504-5, 506-1 , 506-2, and 508 propagate the multiple clock enable signals 324 upstream 312 towards the data source 110 (e.g., at least to the passthrough pipeline circuit 502). These clock enable signals 324 appropriately configure at least some of the pipeline circuits 322 (e.g., particularly the pipeline circuits 322 that perform the gating 328) to enable the clock signal 314 and the data signal 316 to propagate downstream 320 to the subsystems 108 that requested the data. In general, the connections shown using solid lines in FIG. 10 between the data source 110, the pipeline circuits 322, and the subsystems 108 can carry the clock enable signal 324 upstream 312 and can carry the clock signal 314 and the data signal 316 downstream 320, as shown in FIG. 4.

[0065] Consider an example in which the subsystems 108-1 and 108-3 request data from the data source 110 during a same time interval, and the subsystems 108-2, 108-4, and 108-5 do not request data. In an example situation, the subsystems 108-1 and 108-3 can be in the active state 306. and the subsystems 108-2, 108-4. and 108-5 can be in the inactive state 308. In this case, the subsystems 108-1 and 108-3 represents a first set of subsystems 108 that request the data, and the subsystems 108-2, 108-4, and 108-5 represent a second set of subsystems 108 that do not request the data.

[0066] Continuing with the above example, the propagation of the clock enable signals 324 upstream 312 from the gated pipeline circuits 504-1 and 504-3 to the passthrough pipeline circuit 502 causes the clock gates 514 of the gated pipeline circuits 504-1 and 504-3 to be in the enabled state 702, and also causes a clock gate 514 of the mixed pipeline circuit 508 to be in the enabled state 702. Additionally, the propagation of the clock enable signals 324 upstream 312 from the gated pipeline circuits 504-2, 504-4. and 504-5 to the passthrough pipeline circuit 502 causes the clock gates 514 of the gated pipeline circuits 504-2, 504-4, and 504-4 to be in the disabled state 704. Consequently, the data network 112 propagates the clock signal 314 and the data signal 316 downstream 320 through a first set of pipeline circuits 322 (e.g., pipeline circuits 502, 506-1. 504-1, 508, and 504-3) and to the subsystems 108-1 and 108-3. The datanetwork 112 also blocks the propagation of the clock signal 314 and the data signal 316 downstream 320 through a second set of pipeline circuits 322 (e.g., pipeline circuits 504-2, 506-2, 504-4, and 504- 5) and to the subsystems 108-2, 108-4, and 108-5. This blocking of the downstream 320propagation enables the data network 112 to conserve power relative to other data networks that utilize ’‘always-on” retimer circuits. Example operations of the subsystems 108 and the data source 110 are further described with respect to FIG. 11.

[0067] FIG. 11 illustrates an example flow diagram 1100 for requesting and sending data via the data network 112. A first set of operations is performed by the subsystem 108, and a second set of operations is performed by the data source 110.

[0068] At 1102, the subsystem 108 determines if the data source 110 is idle. For example, the subsystem 108 receives the idle flag 1006 from the data network 112. If the idle flag 1006 indicates that the data source 110 is in the busy state 1004, the subsystem 108 does not send a request, as indicated at 1104. Alternatively, if the idle flag 1006 indicates that the data source 110 is in the idle state 1002, the subsystem 108 can send a request at 1106. The data network 112 propagates a request signal 310 from the subsystem 108 to the data source 110. The request signal 310 can include an element that indicates that the subsystem 108 is requesting data or is not requesting data.

[0069] At 1108, the data source 110 determines if there is a new request. For example, the data source 110 can determine if one of the request signals 310 provided by the data network has changed to indicate that the corresponding subsystem 108 is requesting data. If the data source 110 determines that there is not a new request, the data source 110 can remain in the idle state and do nothing at 1 110. Alternatively, if the data source 110 determines that there is a new request, the data source 110 can wait a predetermined amount of time at 1112. This waiting period allow the data source 110 to receive other requests from other subsystems. In this way, the data source 110 can account for the asynchronous nature of the request signals 310 and differences in propagation delays to the different subsystems.

[0070] At 1114, the data source 110 updates its status to busy. For example, the data source 110 modifies the idle flag 1006 to indicate that the data source 110 is busy and is not accepting new' requests. The data network 112 propagates the updated idle flag 1006 to the subsystems 108. At 1116. the data source 110 sends the data to the subsystems 108 associated with the request. For example, the data source 110 generates the data signal 316, and the data network 112 propagates the data signal 316 and the clock signal 314 to the subsystems 108 associated with the request.Example Methods

[0071] FIGs. 12 and 13 depict example methods 1200 and 1300 for performing operations of a power-efficient synchronous-source data network. Methods 1200 and 1300 are shown as a set of operations (or acts) performed but not necessarily limited to the order or combinations in whichthe operations are shown herein. Further, any of one or more of the operations may be repeated, combined, reorganized, or linked to provide a wide array of additional and / or alternate methods. In portions of the following discussion, reference may be made to the environment 100 of FIG. 1, and entities detailed in FIG. 2 and 3, reference to which is made for example only. The techniques are not limited to performance by one entity or multiple entities operating on one device.

[0072] At 1202 in FIG. 12, a first request signal is received from a first subsystem implemented on a system-on-chip. The first request signal indicates that the first subsystem requests data from a data source that is implemented on the system-on-chip. For example, the data network 112 receives a first request signal 310 from a first subsystem 108 implemented on the system-on-chip, as shown in FIG. 3. The first request signal 310 indicates that the first subsystem 108 requests data from the data source 110 that is implemented on the system-on-chip 106. The data network 112 can directly send the first request signal 310 to the data source 110, as shown in FIG. 10.

[0073] At 1204, a first clock enable signal is generated based on the first request signal. For example, the first clock enable signal 324 is generated based on the first request signal 310. If the first request signal 310 indicates that the corresponding subsystem 108 is requesting data from the data source 110, the first clock enable signal 324 can be set to a first logic value (e g., a logic value of “1”) to indicate that the subsystem 108 is requesting data. For other subsystems 108 that are not requesting data, their corresponding clock enable signals 324 can be set to a second logic value (e.g., a logic value of “0”) to indicate an absence of a request (e.g., to indicate that the other subsystems 108 do not request the data). In an example implementation, the gated pipeline circuits 504 that are directly connected to the subsystems 108 can generate the corresponding clock enable signals 324 based on the corresponding request signals 310. In other implementations, the subsystems 108 can directly generate the clock enable signals 324 and pass them to the gated pipeline circuits 504 that are directly upstream 312.

[0074] At 1206, the first clock enable signal propagates upstream using a first set of pipeline circuits of the data network. The first set of pipeline circuits is coupled between the first subsystem and a data source that is implemented on the system-on-chip. For example, the data network 112 propagates the first clock enable signal 324 upstream 312 using a first set of pipeline circuits 322. The first set of pipeline circuits 322 is coupled between the first subsystem 108 and the data source 110, which is implemented on the system-on-chip 106. In the example shown in FIG. 4, the subsystem 108-1 can represent the first subsystem 108 and the pipeline circuits 322-1, 322-2, and 322-3 can represent the first set of pipeline circuits 322. Alternatively, thesubsystem 108-2 can represent the first subsystem 108 and the pipeline circuits 322-1, 322-2, and 322-4 can represent the first set of pipeline circuits 322 in FIG. 4.

[0075] At 1208, a data signal and a clock signal are received from the data source. For example, the data network 112 receives the data signal 316 and the clock signal 314 from the data source 110, as shown in FIG. 3.

[0076] At 1210, the data signal and the clock signal are propagated downstream to the first subsystem using the first set of pipeline circuits. The propagating of the data signal and the clock signal downstream is based on the propagating of the first clock enable signal upstream using the first set of pipeline circuits. For example, the data network 112 causes the data signal 316 and the clock signal 314 to propagate downstream 320 to the first subsystem 108 using the first set of pipeline circuits 322, which represent the same set of pipeline circuits 322 used to propagate the first clock enable signal 324 upstream 312.

[0077] At 1302 in FIG. 13, a first set of clock enable signals are propagated upstream through a first set of pipeline circuits of a data network. The first set of clock enable signals correspond to a first set of subsystems that is implemented on a system-on-chip. The first set of clock enable signals indicates that the first set of subsystems requests data from a data source that is implemented on the system-on-chip.

[0078] For example, the data network 112 propagates a first set of clock enable signals 324 upstream 312 through a first set of pipeline circuits 322, as shown in FIG. 4. The first set of clock enable signals 324 correspond to a first set of subsystems 108 implemented on the system-on- chip 106. The first set of clock enable signals 324 indicate that the first set of subsystems 108 request data from the data source 110 implemented on the system-on-chip 106.

[0079] At 1304, the first set of pipeline circuits are caused, based on the propagating of the first set of clock enable signals, to be in a first state that is capable of propagating signals downstream to the first set of subsystems. For example, the first set of pipeline circuits 322 are in a first state that is capable of propagating signals downstream 320 to the first set of subsystems 108 based on the propagating of the first set of clock enable signals 324 upstream 312.

[0080] At 1306, a second set of clock enable signals are propagated upstream through a second set of pipeline circuits of the data network. The second set of clock enable signals correspond to a second set of subsystems that is implemented on the system-on-chip. The second set of clock enable signals indicates that the second set of subsystems do not request data from the data source.

[0081] For example, the data network 112 propagates a second set of clock enable signals 324 upstream 312 through a second set of pipeline circuits 322, as shown in FIG. 4. The second set of clock enable signals 324 correspond to a second set of subsystems 108 implemented on thesystem-on-chip 106. The second set of clock enable signals 324 indicate that the second set of subsystems 108 do not request data from the data source 110.Example Computing System

[0082] FIG. 14 illustrates vanous components of an example computing system 1400 that can be implemented as any type of client, server, and / or computing device as described with reference to the previous FIGs. 2 and 3 to implement aspects of a power-efficient synchronous -source data network.

[0083] The computing system 1400 includes communication devices 1402 that enable wired and / or wireless communication of device data 1404 (e.g., received data, data that is being received, data scheduled for broadcast, or data packets of the data). The device data 1404 or other device content can include configuration settings of the device, media content stored on the device, and / or information associated with a user of the device. Media content stored on the computing system 1400 can include any type of audio, video, and / or image data. The computing system 1400 includes one or more data inputs 1406 via which any type of data, media content, and / or inputs can be received.

[0084] The computing system 1400 also includes communication interfaces 1408, which can be implemented as any one or more of a serial and / or parallel interface, a wireless interface, any type of network interface, a modem, and as any other type of communication interface. The communication interfaces 1408 provide a connection and / or communication links between the computing system 1400 and a communication network by which other electronic, computing, and communication devices communicate data with the computing system 1400.

[0085] The computing system 1400 includes one or more processors 1410 (e.g., any of microprocessors, controllers, and the like), which process various computer-executable instructions to control the operation of the computing system 1400. Alternatively or in addition, the computing system 1400 can be implemented with any one or combination of hardware, firmware, or fixed logic circuitry that is implemented in connection with processing and control circuits which are generally identified at 1412. Although not shown, the computing system 1400 can include a system bus or data transfer system that couples the various components within the device. A system bus can include any one or combination of different bus structures, such as a memory bus or memory controller, a peripheral bus, a universal serial bus. and / or a processor or local bus that utilizes any of a variety of bus architectures.

[0086] The computing system 1400 also includes a computer-readable medium 1414 (CRM 1414), such as one or more memory devices that enable persistent and / or non-transitoiy datastorage (i. e. , in contrast to mere signal transmission), examples of which include random access memory (RAM), non-volatile memory (e.g., any one or more of a read-only memory' (ROM), flash memory', EPROM, EEPROM, etc.), and a disk storage device. The disk storage device may be implemented as any type of magnetic or optical storage device, such as a hard disk drive, a recordable and / or rewriteable compact disc (CD), any type of a digital versatile drsc (DVD), and the like. The computing system 1400 can also include a mass storage medium device (storage medium) 1416.

[0087] The computer-readable medium 1414 provides data storage mechanisms to store the device data 1404, as well as various device applications and any other types of information and / or data related to operational aspects of the computing system 1400. For example, an operating system can be maintained as a computer application with the computer-readable medium 1414 and executed on the processors 1410. The device applications may include a device manager, such as any form of a control application, software application, signal-processing and control module, code that is native to a particular device, a hardware abstraction layer for a particular device, and so on.

[0088] The computing system 1400 also includes at least one system-on-chip 106. The systemon-chip 106 includes the subsystems 108, the data source, 110, and the data network 112. In some implementations, the processor 1410. the processing and control 1412. the computer-readable medium 1414, and / or the storage medium 1416 can be implemented using one or more of the subsystems 108. The data network 112 represents a power-efficient synchronous-source data network.Conclusion

[0089] Although techniques using, and apparatuses including, a power-efficient synchronous- source data network have been described in language specific to features and / or methods, it is to be understood that the subject of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as example implementations of a power-efficient synchronous-source data network.

[0090] Some Examples are described below.

[0091] Example 1 : A method performed by a data network of a system-on-chip, the method comprising: receiving a first request signal from a first subsystem implemented on the system-on-chip, the first request signal indicating that the first subsystem requests data from a data source implemented on the system-on-chip; generating a first clock enable signal based on the first request signal; propagating the first clock enable signal upstream using a first set of pipeline circuits of the data network, the first set of pipeline circuits being coupled between the first subsystem and the data source; receiving a data signal and a clock signal from the data source; and propagating the data signal and the clock signal downstream to the first subsystem using the first set of pipeline circuits based on the propagating of the first clock enable signal upstream using the first set of pipeline circuits.

[0092] Example 2: The method of example 1, wherein the first clock enable signal comprises an asynchronous signal.

[0093] Example 3: The method of example 1 or 2, wherein: each pipeline circuit within a subset of the first set of pipeline circuits comprises a clock gate coupled to an n-bit pipeline; the propagating of the first clock enable signal upstream comprises causing each clock gate within the subset of the first set of pipeline circuits to be in an enabled state based on the first clock enable signal; and the propagating of the data signal and the clock signal downstream comprises causing each clock gate to pass the clock signal downstream to the corresponding n-bit pipeline based on the enabled state of the clock gate.

[0094] Example 4: The method of example 3, further comprising: preventing other clock gates within other pipeline circuits of the data netw ork that are not coupled between the data source and the first subsystem from propagating the first clock signal downstream.

[0095] Example 5: The method of example 4, wherein the preventing comprises: receiving other request signals from other subsystems implemented on the system-on-chip, the other request signals indicating that the other subsystems do not request data from the data source; generating other clock enable signals based on the other request signals; propagating the other clock enable signals upstream using the other pipeline circuits; and causing the other clock gates within the other pipeline circuits to be in a disabled state based on other clock enable signals.

[0096] Example 6: The method of any previous example, wherein: the first set of pipeline circuits comprises a passthrough pipeline circuit; the propagating of the first clock enable signal upstream comprises passing the first clock enable signal from a clock enable input of the passthrough pipeline circuit to a clock enable output of the passthrough pipeline circuit; and the propagating of the data signal and the clock signal downstream comprises: passing the data signal from a data input of the passthrough pipeline circuit, through a n-bit pipeline of the passthrough pipeline circuit, and to a data output of the passthrough pipeline circuit; and passing the clock signal from a clock input of the passthrough pipeline circuit, through a buffer of the passthrough pipeline circuit, and to the n-bit pipeline of the passthrough pipeline circuit and a clock output of the passthrough pipeline circuit.

[0097] Example 7 : The method of example 6, wherein the passthrough pipeline circuit is coupled between the data source and remaining pipeline circuits of the first set of pipeline circuits.

[0098] Example 8: The method of any previous example, wherein: the first set of pipeline circuits further comprises a gated pipeline circuit; the propagating of the first clock enable signal upstream comprises passing the first clock enable signal from a clock enable input of the gated pipeline circuit to a clock enable output of the gated pipeline circuit and to an input of a clock gate of the gated pipeline circuit; and the propagating of the data signal and the clock signal downstream comprises: passing the data signal from a data input of the gated pipeline circuit, through a n- bit pipeline of the gated pipeline circuit, and to a data output of the gated pipeline circuit; and passing the clock signal from a clock input of the gated pipeline circuit, through the clock gate of the gated pipeline circuit, and to the n-bit pipeline of the gated pipeline circuit and a clock output of the passthrough pipeline circuit.

[0099] Example 9: The method of example 8, wherein the gated pipeline circuit is coupled between the first subsystem and other remaining pipeline circuits of the first set of pipeline circuits.

[0100] Example 10: The method of any previous example, further comprising: receiving a second request signal from a second subsystem implemented on the systemon-chip, the second request signal indicating that the second subsystem requests other data from the data source, the receiving of the second request signal occurring during a same time interval as the receiving of the first request signal; generating a second clock enable signal based on the second request signal; propagating the second clock enable signal upstream using a second set of pipeline circuits of the data network, the second set of pipeline circuits being coupled between the second subsystem and the data source; and propagating the data signal and the clock signal downstream to the second subsystem using the second set of pipeline circuits based on the propagating of the second clock enable signal upstream using the second set of pipeline circuits.[Old] Example 11 : The method of example 10. wherein the same time interval represents a time between the receiving of the first request signal and an operational state of the data source changing from an idle state to a busy state.

[0102] Example 12: The method of example 10 or 1 1, wherein a portion of the first set of pipeline circuits and a portion the second set of pipeline circuits comprise a same subset of pipeline circuits.

[0103] Example 13: The method of example 12, wherein: the same subset of pipeline circuits comprises a branch-point pipeline circuit; the propagating of the first clock enable signal and the second clock enable signal upstream comprises: generating, by the branch-point pipeline circuit, a composite clock enable signal based on the first clock enable signal and the second clock enable signal; and passing, by the branch-point pipeline circuit, the composite clock enable signal upstream; and the propagating of the data signal and the clock signal downstream comprises: passing the data signal from a data input of the branch-point pipeline circuit, through a n-bit pipeline of the branch-point pipeline circuit, and to a data output of the branch-point pipeline circuit; and passing the clock signal from a clock input of the branch-point pipeline circuit, through a buffer of the branch-point pipeline circuit, and to the n-bit pipeline of the branchpoint pipeline circuit and a clock output of the branch-point pipeline circuit.

[0104] Example 14: The method of example 12, wherein: the same subset of pipeline circuits comprises a mixed pipeline circuit; the propagating of the first clock enable signal and the second clock enable signal upstream comprises: generating, by the mixed pipeline circuit, a composite clock enable signal based on the first clock enable signal and the second clock enable signal; and passing, by the mixed pipeline circuit, the composite clock enable signal upstream and to an input of a clock gate of the mixed pipeline circuit; and the propagating of the data signal and the clock signal downstream comprises: passing the data signal from a data input of the mixed pipeline circuit, through an- bit pipeline of the mixed pipeline circuit, and to a data output of the mixed pipeline circuit; and passing the clock signal from a clock input of the mixed pipeline circuit, through a the clock gate of the mixed pipeline circuit, and to the n-bit pipeline of the mixed pipeline circuit and a clock output of the mixed pipeline circuit.

[0105] Example 15: The method of example 14, wherein the mixed pipeline circuit is coupled between two branch nodes of the data network.

[0106] Example 16: The method of any previous example, wherein: the data source comprises a repair controller; and the receiving of the data signal comprises receiving repair data from the repair controller.

[0107] Example 17: The method of any previous example, further comprising: passing an idle flag from the data source to the first subsystem.

[0108] Example 18: A method performed by a data network of a system-on-chip, the method comprising: propagating a first set of clock enable signals upstream through a first set of pipeline circuits of the data network, the first set of clock enable signals corresponding to a first set of subsystems implemented on the system-on-chip and indicating that the first set of subsystems requests data from a data source implemented on the system-on-chip; causing, based on the propagating of the first set of clock enable signals, the first set of pipeline circuits to be in a first state that is capable of propagating signals downstream to the first set of subsystems; propagating a second set of clock enable signals upstream through a second set of pipeline circuits of the data network, the second set of clock enable signals corresponding to a second set of subsystems implemented on the system-on-chip and indicating that the second set of subsystems do not request the data from the data source; and causing, based on the propagating of second set of clock enable signals, at least a subset of the second set of pipeline circuits to be in a second state that blocks the propagating of the signals dow nstream to the second set of subsystems.

[0109] Example 19: The method of example 18, wherein: the first set of pipeline circuits and the second set of pipeline circuits comprise a same subset of pipeline circuits; and the causing of at least a subset of the second set of pipeline circuits to be in the second state comprises causing other pipeline circuits of the second set of pipeline circuits that are not part of the same subset of pipeline circuits to be in the second state.

[0110] Example 20: An apparatus comprising: a system-on-chip comprising a data network, the system-on-chip configured to perform, using the data network, any one of the methods of examples 1 to 17 or any one of the methods of examples 18 and 19.

[0111] Example 21 : The apparatus of example 20, wherein the system-on-chip comprises: multiple subsystems; and a data source configured to broadcast data across the data network to at least some of the multiple subsystems.

[0112] Example 22: The apparatus of example 20 or 21 , wherein: the data network comprises a first set of pipeline circuits coupled between a first subsystem of the system-on-chip and a data source of the system-on-chip, the first set of pipeline circuits configured to: receive a first request signal from the first subsystem, the first request signal indicating that the first subsystem requests data from the data source; generate a first clock enable signal based on the first request signal; propagate the first clock enable signal upstream towards the data source; receive a data signal and a clock signal from the data source; and propagate the data signal and the clock signal downstream to the first subsystem based on the upstream propagation of the first clock enable signal.

[0113] Example 23: The apparatus of example 20 or 21, wherein: the data network comprises a first set of pipeline circuits coupled between a first set of subsystems of the system-on-chip and a data source of the system-on-chip, the first set of pipeline circuits configured to: propagate a first set of clock enable signals upstream towards the data source, the first set of clock enable signals indicating that the first set of subsystems requests data from the data source; and be in a first state that is capable of propagating signals downstream to the first set of subsystems based on the upstream propagation of the first set of clock enable signals; the data network comprises a second set of pipeline circuits coupled between a second set of subsystems of the system-on-chip and the data source, the second set of pipeline circuits configured to propagate a second set of clock enable signals upstream towards the data source, the second set of clock enable signals indicating that the second set of subsystems do not request the data from the data source; a first subset of the second set of pipeline circuits is configured to be in a second state that blocks the downstream propagation of the signals to the second set of subsystems based on the upstream propagation of the second set of clock enable signals; and a second subset of the second set of pipeline circuits is configured to be in the first state based on the upstream propagation of the first set of clock enable signals.

Claims

CLAIMSWhat is claimed is:

1. A method performed by a data network of a system-on-chip, the method comprising: receiving a first request signal from a first subsystem implemented on the system-on-chip, the first request signal indicating that the first subsystem requests data from a data source implemented on the system-on-chip; generating a first clock enable signal based on the first request signal; propagating the first clock enable signal upstream using a first set of pipeline circuits of the data network, the first set of pipeline circuits being coupled between the first subsystem and the data source; receiving a data signal and a clock signal from the data source; and propagating the data signal and the clock signal downstream to the first subsystem using the first set of pipeline circuits based on the propagating of the first clock enable signal upstream using the first set of pipeline circuits.

2. The method of claim 1, wherein the first clock enable signal comprises an asynchronous signal.

3. The method of claim 1 or 2, wherein: each pipeline circuit within a subset of the first set of pipeline circuits comprises a clock gate coupled to an n-bit pipeline; the propagating of the first clock enable signal upstream comprises causing each clock gate within the subset of the first set of pipeline circuits to be in an enabled state based on the first clock enable signal; and the propagating of the data signal and the clock signal downstream comprises causing each clock gate to pass the clock signal downstream to the corresponding n-bit pipeline based on the enabled state of the clock gate.

4. The method of claim 3, further comprising: preventing other clock gates within other pipeline circuits of the data network that are not coupled between the data source and the first subsystem from propagating the first clock signal downstream.

5. The method of claim 4, wherein the preventing comprises: receiving other request signals from other subsystems implemented on the system-on-chip, the other request signals indicating that the other subsystems do not request data from the data source; generating other clock enable signals based on the other request signals; propagating the other clock enable signals upstream using the other pipeline circuits; and causing the other clock gates within the other pipeline circuits to be in a disabled state based on other clock enable signals.

6. The method of any previous claim, wherein: the first set of pipeline circuits comprises a passthrough pipeline circuit; the propagating of the first clock enable signal upstream comprises passing the first clock enable signal from a clock enable input of the passthrough pipeline circuit to a clock enable output of the passthrough pipeline circuit; and the propagating of the data signal and the clock signal downstream comprises: passing the data signal from a data input of the passthrough pipeline circuit, through a n-bit pipeline of the passthrough pipeline circuit, and to a data output of the passthrough pipeline circuit; and passing the clock signal from a clock input of the passthrough pipeline circuit, through a buffer of the passthrough pipeline circuit, and to the n-bit pipeline of the passthrough pipeline circuit and a clock output of the passthrough pipeline circuit.

7. The method of claim 6, wherein the passthrough pipeline circuit is coupled between the data source and remaining pipeline circuits of the first set of pipeline circuits.

8. The method of any previous claim, wherein: the first set of pipeline circuits further comprises a gated pipeline circuit; the propagating of the first clock enable signal upstream comprises passing the first clock enable signal from a clock enable input of the gated pipeline circuit to a clock enable output of the gated pipeline circuit and to an input of a clock gate of the gated pipeline circuit; and the propagating of the data signal and the clock signal downstream comprises: passing the data signal from a data input of the gated pipeline circuit, through a n- bit pipeline of the gated pipeline circuit, and to a data output of the gated pipeline circuit; and passing the clock signal from a clock input of the gated pipeline circuit, through the clock gate of the gated pipeline circuit, and to the n-bit pipeline of the gated pipeline circuit and a clock output of the passthrough pipeline circuit.

9. The method of claim 8, wherein the gated pipeline circuit is coupled between the first subsystem and other remaining pipeline circuits of the first set of pipeline circuits.

10. The method of any previous claim, further comprising: receiving a second request signal from a second subsystem implemented on the system- on-chip, the second request signal indicating that the second subsystem requests other data from the data source, the receiving of the second request signal occurring during a same time interval as the receiving of the first request signal; generating a second clock enable signal based on the second request signal; propagating the second clock enable signal upstream using a second set of pipeline circuits of the data network, the second set of pipeline circuits being coupled between the second subsystem and the data source; and propagating the data signal and the clock signal downstream to the second subsystem using the second set of pipeline circuits based on the propagating of the second clock enable signal upstream using the second set of pipeline circuits.

11. The method of claim 10, wherein the same time interval represents a time between the receiving of the first request signal and an operational state of the data source changing from an idle state to a busy state.

12. The method of claim 10 or 11, wherein a portion of the first set of pipeline circuits and a portion the second set of pipeline circuits comprise a same subset of pipeline circuits.

13. The method of claim 12, wherein: the same subset of pipeline circuits comprises a branch-point pipeline circuit; the propagating of the first clock enable signal and the second clock enable signal upstream comprises: generating, by the branch-point pipeline circuit, a composite clock enable signal based on the first clock enable signal and the second clock enable signal; and passing, by the branch-point pipeline circuit, the composite clock enable signal upstream; and the propagating of the data signal and the clock signal dow nstream comprises: passing the data signal from a data input of the branch-point pipeline circuit, through a n-bit pipeline of the branch-point pipeline circuit, and to a data output of the branch-point pipeline circuit; and passing the clock signal from a clock input of the branch-point pipeline circuit, through a buffer of the branch-point pipeline circuit, and to the n-bit pipeline of the branchpoint pipeline circuit and a clock output of the branch-point pipeline circuit.

14. The method of claim 12, wherein: the same subset of pipeline circuits comprises a mixed pipeline circuit; the propagating of the first clock enable signal and the second clock enable signal upstream comprises: generating, by the mixed pipeline circuit, a composite clock enable signal based on the first clock enable signal and the second clock enable signal; and passing, by the mixed pipeline circuit, the composite clock enable signal upstream and to an input of a clock gate of the mixed pipeline circuit; and the propagating of the data signal and the clock signal downstream comprises: passing the data signal from a data input of the mixed pipeline circuit, through an- bit pipeline of the mixed pipeline circuit, and to a data output of the mixed pipeline circuit; and passing the clock signal from a clock input of the mixed pipeline circuit, through a the clock gate of the mixed pipeline circuit, and to the n-bit pipeline of the mixed pipeline circuit and a clock output of the mixed pipeline circuit.

15. The method of claim 14, wherein the mixed pipeline circuit is coupled between two branch nodes of the data network.

16. The method of any previous claim, wherein: the data source comprises a repair controller; and the receiving of the data signal comprises receiving repair data from the repair controller.

17. The method of any previous claim, further comprising: passing an idle flag from the data source to the first subsystem.

18. A method performed by a data network of a system-on-chip, the method comprising: propagating a first set of clock enable signals upstream through a first set of pipeline circuits of the data network, the first set of clock enable signals corresponding to a first set of subsystems implemented on the system-on-chip and indicating that the first set of subsystems requests data from a data source implemented on the system-on-chip; causing, based on the propagating of the first set of clock enable signals, the first set of pipeline circuits to be in a first state that is capable of propagating signals dow nstream to the first set of subsystems; propagating a second set of clock enable signals upstream through a second set of pipeline circuits of the data network, the second set of clock enable signals corresponding to a second set of subsystems implemented on the system-on-chip and indicating that the second set of subsystems do not request the data from the data source; and causing, based on the propagating of second set of clock enable signals, at least a subset of the second set of pipeline circuits to be in a second state that blocks the propagating of the signals downstream to the second set of subsystems.

19. The method of claim 18, wherein: the first set of pipeline circuits and the second set of pipeline circuits comprise a same subset of pipeline circuits; and the causing of at least a subset of the second set of pipeline circuits to be in the second state comprises causing other pipeline circuits of the second set of pipeline circuits that are not part of the same subset of pipeline circuits to be in the second state.

20. An apparatus comprising: a system-on-chip comprising a data network, the system-on-chip configured to perform, using the data network, any one of the methods of claims 1 to 17 or any one of the methods of claims 18 and 19.

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