Delay calibration method and delay calibration device for multiple fpga

Abstract

The application discloses a delay calibration method and device for multiple FPGAs. The method comprises the following steps: in response to a first delay calibration instruction sent by a host computer, a synchronization signal sent by a second FPGA is received; the second FPGA and the first FPGA are located on different circuit boards; a delay calibration process is performed on the synchronization signal to obtain a calibrated signal different from the synchronization signal, and a first delay value is determined according to the calibrated signal and the synchronization signal; a first delay calibration success signal is sent to the host computer; the host computer forwards the first delay calibration success signal to the second FPGA; a first trigger signal sent by the second FPGA based on the first delay calibration success signal is received; and a delay calibration process is performed on the first trigger signal according to the first delay value to obtain a first calibrated trigger signal. The application realizes the synchronous detection of trigger signals of multiple FPGAs.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a delay calibration method and a delay calibration device for multiple FPGAs. Background Technology

[0002] High-speed, high-bandwidth oscilloscopes mostly use multiple FPGAs for data acquisition, control, and trigger detection. When using multiple FPGAs for data acquisition, each FPGA needs to detect the trigger signal at the same time to process and splice the acquired data. Therefore, delay calibration and compensation are required for multi-channel triggering.

[0003] Currently, oscilloscopes generally employ two methods for delay calibration and compensation of multi-channel triggers. The first is manual delay adjustment, where an external signal source is manually controlled to send a signal before using the oscilloscope to perform a channel delay calibration. Then, after a period of time, the channel delay is recalibrated based on subsequent oscilloscope usage to ensure synchronization between different channels. This method is labor-intensive, and as oscilloscope bandwidth increases, the signal source also needs to be upgraded, increasing equipment costs. Furthermore, the external signal source needs to be calibrated before performing channel delay calibration, increasing the complexity of channel delay calibration and resulting in low efficiency. The second method uses memory space counting. Each channel simultaneously sends a trigger signal, which is stored in the corresponding memory space for each channel. By checking the address location of the trigger signal in the memory space, the relative delay value between channels can be calculated. This method requires filling the memory space corresponding to each channel, is time-consuming, and has low adjustment accuracy. Summary of the Invention

[0004] This application provides a delay calibration method and a delay calibration device for multiple FPGAs, which can realize the synchronous detection of trigger signals of multiple FPGAs.

[0005] On one hand, this application provides a delay calibration method for multiple FPGAs, wherein the multiple FPGAs include at least one synchronization board FPGA and at least two acquisition board FPGAs; each synchronization board FPGA and each acquisition board FPGA are communicatively connected to a host computer; the method is applied to a first FPGA, which is any one of the at least one synchronization board FPGA and the at least two acquisition board FPGAs, and the method includes: In response to the first delay calibration command sent by the host computer, a synchronization signal sent by the second FPGA is received; the second FPGA and the first FPGA are located on different circuit boards; The synchronization signal is subjected to delay calibration to obtain a calibrated signal that is different from the synchronization signal, and a first delay value is determined based on the calibrated signal and the synchronization signal. Send a first delayed calibration success signal to the host computer; so that the host computer forwards the first delayed calibration success signal to the second FPGA; Receive the first trigger signal sent by the second FPGA based on the first delay calibration success signal; The first trigger signal is subjected to delay calibration processing based on the first delay value to obtain the first calibrated trigger signal.

[0006] In one exemplary embodiment, the step of performing delay calibration processing on the synchronization signal to obtain a calibrated signal different from the synchronization signal, and determining a first delay value based on the calibrated signal and the synchronization signal, includes: The synchronization signal is subjected to serial-to-parallel conversion processing to obtain the first parallel signal; The synchronization signal is delayed for a preset duration to obtain the initial delayed signal, and the number of real-time delays is obtained. The initial delayed signal is subjected to serial-to-parallel conversion processing to obtain a second parallel signal; The first parallel signal and the second parallel signal are compared and processed to obtain the current comparison result; If the current comparison result indicates that the first parallel signal is different from the second parallel signal, the second parallel signal is used as the calibrated signal. The first delay value is determined based on the preset duration and the number of real-time extensions.

[0007] In one exemplary embodiment, after comparing the first parallel signal and the second parallel signal to obtain the current comparison result, the method further includes: If the current comparison result indicates that the first parallel signal and the second parallel signal are the same, the signal after the initial delay is further delayed for the preset duration to obtain a delayed parallel signal that is different from the first parallel signal, and the current number of delays corresponding to the delayed parallel signal is obtained; The delayed parallel signal is used as the calibrated signal; The first delay value is determined based on the preset duration and the current number of extensions.

[0008] In one exemplary embodiment, the first FPGA is the synchronization board FPGA, and the second FPGA is any one of the at least two acquisition board FPGAs; after performing delay calibration processing on the synchronization signal to obtain a calibrated signal different from the synchronization signal, and determining a first delay value based on the calibrated signal and the synchronization signal, the method further includes: Acquire the initial calibrated signal, initial delay value, and clock frequency of the first FPGA for each acquisition board FPGA; The host computer sends the initial calibration signal, initial delay value, and clock frequency corresponding to each FPGA acquisition board to the host computer; so that the host computer determines the delay clock frequency based on the clock frequency corresponding to the first FPGA; so that the host computer determines the first target delay value corresponding to each FPGA acquisition board based on the initial calibration signal, initial delay value, and delay clock frequency corresponding to each FPGA acquisition board; so that the host computer sends the first target delay value corresponding to each FPGA acquisition board to the first FPGA. Receive the first target delay value corresponding to each acquisition board FPGA sent by the host computer.

[0009] In one exemplary embodiment, after receiving the first target delay value corresponding to each acquisition board FPGA sent by the host computer, the method further includes: Send a second delayed calibration success signal to the host computer; so that the host computer forwards the second delayed calibration success signal to each of the acquisition board FPGAs; Receive the trigger signal sent by each of the acquisition board FPGAs based on the second delay calibration success signal; Based on the first target delay value corresponding to each acquisition board FPGA, the trigger signals sent by each acquisition board FPGA are subjected to delay calibration processing to obtain the calibrated signals corresponding to each acquisition board FPGA.

[0010] In one exemplary embodiment, after performing delay calibration processing on the trigger signals sent by each acquisition board FPGA according to the first target delay value corresponding to each acquisition board FPGA to obtain the calibrated signal corresponding to each acquisition board FPGA, the method further includes: Obtain the number of acquisition boards corresponding to each FPGA acquisition board; At a preset time, the calibrated signals corresponding to each FPGA acquisition board are detected and processed to obtain the real-time detection quantity value; If the real-time detection quantity value is equal to the acquisition board quantity value, a second trigger signal is generated; The second trigger signal is sent to each of the acquisition board FPGAs so that each acquisition board FPGA performs delay calibration processing on the second trigger signal.

[0011] In one exemplary embodiment, the method further includes: Receive the second target delay value sent by the host computer; Receive the third trigger signal sent by the second FPGA based on the second delay calibration command sent by the host computer; The third trigger signal is delayed by the second target delay value to obtain the second calibrated trigger signal.

[0012] On the other hand, a delay calibration device for multiple FPGAs is provided, wherein the multiple FPGAs include at least one synchronization board FPGA and at least two acquisition board FPGAs; each synchronization board FPGA and each acquisition board FPGA are communicatively connected to a host computer; the method is applied to a first FPGA, which is any one of the at least one synchronization board FPGA and the at least two acquisition board FPGAs; the device includes: A synchronization signal receiving module is used to receive a synchronization signal sent by the second FPGA in response to a first delay calibration command sent by the host computer; the second FPGA and the first FPGA are located on different circuit boards; The first delay value determination module is used to perform delay calibration processing on the synchronization signal to obtain a calibrated signal that is different from the synchronization signal, and to determine the first delay value based on the calibrated signal and the synchronization signal. The first delay calibration success signal sending module is used to send a first delay calibration success signal to the host computer, so that the host computer forwards the first delay calibration success signal to the second FPGA. The first trigger signal receiving module is used to receive the first trigger signal sent by the second FPGA based on the first delay calibration success signal; The first calibration trigger signal determination module is used to perform delay calibration processing on the first trigger signal according to the first delay value to obtain the first calibration trigger signal.

[0013] On the other hand, a delay calibration device is provided, including a host computer, at least one synchronization board FPGA and at least two acquisition board FPGAs; each synchronization board FPGA and each acquisition board FPGA are communicatively connected to the host computer; each synchronization board FPGA and each acquisition board FPGA are used to perform delay calibration of the multiple FPGAs by any of the above methods.

[0014] In one exemplary embodiment, the delay calibration device further includes a clock module that provides a synchronization clock for the at least one synchronization board FPGA and the at least two acquisition board FPGAs.

[0015] On the other hand, an electronic device is provided, the device including a processor and a memory, the memory storing at least one instruction or at least one program, the at least one instruction or the at least one program being loaded by the processor and executed as described above for the delay calibration method of multiple FPGAs.

[0016] On the other hand, a computer-readable storage medium is provided, wherein at least one instruction or at least one program is stored therein, the at least one instruction or at least one program being loaded and executed by a processor to implement the delay calibration method for multiple FPGAs as described above.

[0017] On the other hand, a computer program product or computer program is provided, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium, executes the computer instructions, and causes the computer device to perform the delay calibration method for multiple FPGAs as described above.

[0018] This application provides a delay calibration method and device for multiple FPGAs, which has the following technical effects: In response to a first delay calibration command sent by a host computer, this application receives a synchronization signal sent by a second FPGA; the second FPGA and the first FPGA are located on different circuit boards; the synchronization signal is subjected to delay calibration processing to obtain a calibrated signal different from the synchronization signal, and a first delay value is determined based on the calibrated signal and the synchronization signal; a first delay calibration success signal is sent to the host computer; the host computer then forwards the first delay calibration success signal to the second FPGA; a first trigger signal is received from the second FPGA based on the first delay calibration success signal; the first trigger signal is subjected to delay calibration processing according to the first delay value to obtain a first calibrated trigger signal. For at least one synchronization board FPGA and at least two acquisition board FPGAs, a synchronization signal is first sent, and the synchronization signal is delayed and adjusted until a calibrated signal different from the synchronization signal is obtained. Once the delay calibration is confirmed to be complete, a first delay calibration success signal is sent to the host computer, thereby enabling normal trigger signal transmission and delay processing. This allows the trigger signals uploaded by each acquisition board FPGA to be detected by the synchronization board FPGA at the same time, and the trigger signals sent by each acquisition board FPGA to be detected by the synchronization board FPGA at the same time, thus achieving synchronous detection of trigger signals from multiple FPGAs. Attached Figure Description

[0019] To more clearly illustrate the technical solutions and advantages in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating a delay calibration method for multiple FPGAs provided in the embodiments of this specification; Figure 2 This is a schematic diagram illustrating the connection between a synchronization board FPGA and multiple acquisition board FPGAs provided in the embodiments of this specification; Figure 3 This is a diagram illustrating a signal transmission structure between multiple FPGAs provided in the embodiments of this specification. Figure 4 This is a schematic diagram of the signal transmission process of a transmitting module 1 provided in an embodiment of this specification; Figure 5 This is a schematic diagram of the signal reception process of a receiving module 1 provided in an embodiment of this specification; Figure 6 This is a flowchart illustrating the first method for determining the first delay value provided in the embodiments of this specification; Figure 7 This is a delay calibration structure diagram between a single acquisition board FPGA and a single synchronization board FPGA provided in the embodiments of this specification; Figure 8 This is a flowchart illustrating the second method for determining the first delay value provided in the embodiments of this specification; Figure 9 This is a schematic diagram of the level of the first type of synchronization signal delay adjustment provided in the embodiments of this specification; Figure 10 This is a schematic diagram of the level of the second type of synchronization signal delay adjustment provided in the embodiments of this specification; Figure 11 This is a flowchart illustrating a method for determining a first target delay value provided in an embodiment of this specification; Figure 12 This is a schematic diagram of the level of a multi-signal delay calibration provided in the embodiments of this specification; Figure 13 This is a flowchart illustrating a method for determining the calibrated signals corresponding to each FPGA acquisition board, as provided in the embodiments of this specification. Figure 14This is a flowchart illustrating a method for sending a second trigger signal provided in an embodiment of this specification; Figure 15 This is a flowchart illustrating a method for sending a second trigger signal provided in an embodiment of this specification; Figure 16 This is a structural diagram of a delay calibration device provided in the embodiments of this specification; Figure 17 This is a schematic diagram of the delay calibration device for multiple FPGAs provided in the embodiments of this specification. Detailed Implementation

[0021] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0022] The following describes a delay calibration method for multiple FPGAs according to this application. Figure 1 This is a flowchart illustrating a delay calibration method for multiple FPGAs provided in the embodiments of this specification, as shown below. Figure 1 As shown, the multiple FPGAs include at least one synchronization board FPGA and at least two acquisition board FPGAs; each synchronization board FPGA and each acquisition board FPGA are communicatively connected to a host computer; the method is applied to a controller corresponding to a first FPGA, where the first FPGA is any one of the at least one synchronization board FPGA and the at least two acquisition board FPGAs, and the method includes: S101: In response to the first delay calibration command sent by the host computer, receive the synchronization signal sent by the second FPGA; the second FPGA and the first FPGA are located on different circuit boards.

[0023] In the embodiments described in this specification, multiple FPGAs include at least one synchronization board FPGA and at least two acquisition board FPGAs. For example, it may include one synchronization board FPGA and four acquisition board FPGAs. Figure 2 This is a schematic diagram illustrating the connection between a synchronization board FPGA and multiple acquisition board FPGAs provided in an embodiment of this specification. Figure 2As can be seen, the synchronization board FPGA and each acquisition board FPGA are connected to the host computer. The host computer sends configuration information to the acquisition board FPGA and the synchronization board FPGA. A high-precision synchronous clock is provided for the synchronization board FPGA and each acquisition board FPGA, ensuring that each FPGA operates on the same time base. This fundamentally reduces trigger delay errors caused by clock differences. Furthermore, the clock lines between the clock and each acquisition board FPGA and the synchronization board FPGA are of equal length, and an additional delay adjustment chip can be added to finely adjust the clock phase. Each acquisition board FPGA is connected to the synchronization board FPGA, and each acquisition board FPGA and the synchronization board FPGA have separate trigger signal upload and trigger signal download channels. Figure 2 As shown, FPGA1, FPGA2, FPGA3, and FPGA4 are all data acquisition boards (FPGAs), and FPGAM is a synchronization board (FPGA). A trigger signal upload channel 1 and a trigger signal download channel 1 are provided between data acquisition board FPGA1 and synchronization board FPGAM; a trigger signal upload channel 2 and a trigger signal download channel 2 are provided between data acquisition board FPGA2 and synchronization board FPGAM; a trigger signal upload channel 3 and a trigger signal download channel 3 are provided between data acquisition board FPGA3 and synchronization board FPGAM; and a trigger signal upload channel 4 and a trigger signal download channel 4 are provided between data acquisition board FPGA4 and synchronization board FPGAM. Specifically, Figure 3 This is a diagram illustrating a signal transmission structure between multiple FPGAs provided in this embodiment. Figure 3In this diagram, transmitting module 1 and receiving module 1 are modules in the acquisition board FPGA1, and transmitting module M1 and receiving module M1 are modules in the synchronization board FPGAM corresponding to the acquisition board FPGA1. Transmitting module 1 and receiving module M1 adjust the delay of the trigger signal upload channel 1 and the delay of the trigger signal transmission channel 1. Transmitting module 2 and receiving module 2 are modules in the acquisition board FPGA2, and transmitting module M2 and receiving module M2 are modules in the synchronization board FPGAM corresponding to the acquisition board FPGA2. Transmitting module 2 and receiving module M2 adjust the delay of the trigger signal upload channel 2 and the delay of the trigger signal transmission channel 2. Transmitting module 3 and receiving module 3 are modules in the acquisition board FPGA3, and transmitting module M3 and receiving module M3 are modules in the synchronization board FPGAM corresponding to the acquisition board FPGA3. Module M3 adjusts the delay of the trigger signal upload channel 3, while the sending module M3 and receiving module 3 adjust the delay of the trigger signal transmission channel 3. The sending module 4 and receiving module 4 are modules within the acquisition board FPGA4, and the sending module M4 and receiving module M4 are modules within the synchronization board FPGAM corresponding to the acquisition board FPGA4. Specifically, the sending module 4 and receiving module M4 adjust the delay of the trigger signal upload channel 4, and the sending module M4 and receiving module 4 adjust the delay of the trigger signal transmission channel 4. The trigger signal processing module is a module within the synchronization board FPGAM, used to receive trigger signals uploaded from each acquisition board FPGA, and then uniformly transmit the trigger signals to each acquisition board FPGA, i.e., receiving trigger signal 1 uploaded from acquisition board FPGA1, trigger signal 2 uploaded from acquisition board FPGA2, trigger signal 3 uploaded from acquisition board FPGA3, and trigger signal 4 uploaded from acquisition board FPGA4. Taking acquisition board FPGA1 as an example... Figure 4 As shown, Figure 4 This is a schematic diagram of the signal transmission process of the transmitting module 1 provided in an embodiment of this specification. S401: Transmit a synchronization signal; the transmitting module 1 transmits a synchronization signal to the receiving module M1 through the trigger signal upload channel 1. The synchronization signal is a periodic square wave signal. S402: Delay adjustment successful; the transmitting module 1 receives both the delay adjustment success signal from the receiving module M1 and the delay adjustment success signal from the receiving module 1, indicating that the delay adjustment was successful. S403: Transmit a trigger signal; the transmitting module 1 transmits a trigger signal to the receiving module M1 through the trigger signal upload channel 1. Figure 5 As shown, Figure 5This is a schematic flowchart of a signal receiving module 1 provided in an embodiment of this specification. S501: Receive synchronization signal; the receiving module 1 receives the synchronization signal sent by the transmitting module M1 through the trigger signal transmission channel 1. The synchronization signal is a periodic square wave signal. S502: Perform delay adjustment; the receiving module 1 performs delay adjustment on the trigger signal transmission channel 1. S503: Delay adjustment successful; the receiving module 1 successfully adjusts the delay of the trigger signal transmission channel 1. S504: Receive trigger signal; the receiving module 1 begins receiving the trigger signal sent by the transmitting module M1 through the trigger signal transmission channel. The second FPGA and the first FPGA are located on different circuit boards. The first FPGA responds to the first delay calibration command sent by the host computer and receives the signal sent by the second FPGA. Synchronization signal; specifically, if the first FPGA is a synchronization board FPGA and the second FPGA is a data acquisition board FPGA, then the first delay calibration command is an upload delay calibration command, and the first FPGA receives the synchronization signal sent by the second FPGA; wherein, the synchronization signal is a pre-set periodic synchronization signal, and the duty cycle, frequency, and high / low level of the synchronization signal sent by each data acquisition board FPGA to the synchronization board FPGA are the same, with only the transmission time being different; if the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, then the first delay calibration command is a download delay calibration command, and the first FPGA receives the synchronization signal sent by the second FPGA; similarly, the synchronization signal sent by the synchronization board FPGA to each data acquisition board FPGA is the same.

[0024] S103: Perform delay calibration processing on the synchronization signal to obtain a calibrated signal that is different from the synchronization signal, and determine a first delay value based on the calibrated signal and the synchronization signal.

[0025] In the embodiments of this specification, the synchronization signal sent by the second FPGA is subjected to delay calibration. During delay calibration, the synchronization signal can be delayed for a preset duration, and it is determined whether the calibrated signal meets the conditions for successful delay adjustment. When the calibrated signal is different from the synchronization signal, the calibrated signal at this time is determined as the calibrated signal. Based on the calibrated signal and the synchronization signal, the first delay value, that is, the delay value between the single acquisition board FPGA and the synchronization board FPGA, can be calculated.

[0026] In the embodiments of this specification, the synchronization signal is subjected to delay calibration processing to obtain a calibrated signal different from the synchronization signal, and a first delay value is determined based on the calibrated signal and the synchronization signal, such as... Figure 6 As shown, Figure 6 A flowchart illustrating the first method for determining the first delay value provided in the embodiments of this specification includes: S601: Perform serial-to-parallel conversion processing on the synchronization signal to obtain the first parallel signal.

[0027] In the embodiments described in this specification, such as Figure 7 As shown, Figure 7 This is a diagram illustrating a delay calibration structure between a single acquisition board FPGA and a single synchronization board FPGA, as provided in an embodiment of this specification. Figure 7 The transmitting module 1, receiving training module 2, delay adjustment module 2, serial-to-parallel conversion module 2, and signal output module 2 are all modules within the acquisition board FPGA, while the transmitting module 2, receiving training module 1, delay adjustment module 1, serial-to-parallel conversion module 1, signal output module 1, and trigger signal processing module are all modules within the synchronization board FPGA. For signal delay trigger calibration processing between a single acquisition board FPGA and a synchronization board FPGA, if the first FPGA is a synchronization board FPGA and the second FPGA is an acquisition board FPGA, the second FPGA, i.e. the acquisition board FPGA, sends a synchronization signal from the sending module 1 to the delay adjustment module 1 of the first FPGA through the trigger signal upload channel. At this time, the output signal of the sending module 1 is a synchronization signal. The delay adjustment module 1 sends the received synchronization signal to the signal output module 1. At this time, no delay adjustment is performed on the synchronization signal. Then, the signal output module 1 sends the synchronization signal to the serial-to-parallel conversion module 1. At this time, the signal output module 1 receives the downlink channel adjustment success signal sent by the host computer, which is invalid. The synchronization signal is a serial signal. The serial-to-parallel conversion module 1 performs serial-to-parallel conversion processing on the received synchronization signal to obtain the first parallel signal. If the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, the second FPGA, i.e. the synchronization board FPGA, sends a synchronization signal from the sending module 2 to the delay adjustment module 2 of the second FPGA through the trigger signal transmission channel. The delay adjustment module 2 sends the received synchronization signal to the signal output module 2. At this time, no delay adjustment is performed on the synchronization signal. Then, the signal output module 2 sends the synchronization signal to the serial-to-parallel conversion module 2. At this time, the signal output module 2 receives an invalid upload channel adjustment success signal sent by the host computer. The synchronization signal is a serial signal. The serial-to-parallel conversion module 2 performs serial-to-parallel conversion processing on the received synchronization signal to obtain the first parallel signal.

[0028] S602: Delay the synchronization signal for a preset duration to obtain the initial delayed signal, and obtain the real-time delay count.

[0029] In the embodiments of this specification, if the first FPGA is a synchronization board FPGA and the second FPGA is a acquisition board FPGA, the receiving training module 1 processes the first parallel signal. When the first parallel signal remains unchanged within a certain number of clock cycles, it is considered that the first parallel signal is stable. For example, a counter can be set. If the first parallel signal remains stable within the range of the count value 0-4000, then the first parallel signal is considered stable and recorded as D1. At this time, delay adjustment begins. A delay adjustment signal is sent to the delay adjustment module 1 to delay the synchronization signal by a preset duration TN. The TAP value of the cascaded primitives IDELAYE3 and ODELAYE3 in the synchronization board is incremented by 1. At this time, the synchronization signal is delayed by 4PS, that is, TN is approximately 4PS, and the initial delayed signal is obtained. The total number of delays, that is, the real-time delay count, is recorded as N1. When the adjustment is performed for the first time, N1 is 1.

[0030] If the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, the receiving training module 2 processes the first parallel signal. When the first parallel signal remains unchanged within a certain number of clock cycles, it is considered that the first parallel signal is stable. For example, a counter can be set. If the first parallel signal remains stable within the range of 0-4000, it is considered that the first parallel signal is stable and recorded as D3. At this time, delay adjustment begins. A delay adjustment signal is sent to the delay adjustment module 2, and the delay adjustment reference clock can be 500MHz. The synchronization signal is delayed by a preset duration TN. The TAP value of the cascaded primitives IDELAYE3 and ODELAYE3 in the data acquisition board is incremented by 1. At this time, the synchronization signal is delayed by 4PS, that is, TN is about 4PS, and the initial delayed signal is obtained. The total number of delays, that is, the real-time delay count, is recorded as N2. When the adjustment is performed for the first time, N2 is 1.

[0031] S603: Perform serial-to-parallel conversion processing on the initial delayed signal to obtain a second parallel signal.

[0032] In the embodiments of this specification, if the first FPGA is a synchronous board FPGA and the second FPGA is a data acquisition board FPGA, the delay adjustment module 1 sends the initial delayed signal to the signal output module 1, the signal output module 1 sends the initial delayed signal to the serial-to-parallel conversion module 1, the serial-to-parallel conversion module 1 performs serial-to-parallel conversion processing on the received initial delayed signal to obtain the second parallel signal, and sends the second parallel signal to the receiving training module 1.

[0033] If the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, the delay adjustment module 2 sends the initial delayed signal to the signal output module 2, the signal output module 2 sends the initial delayed signal to the serial-to-parallel conversion module 2, the serial-to-parallel conversion module 2 performs serial-to-parallel conversion processing on the received initial delayed signal to obtain the second parallel signal, and sends the second parallel signal to the receiving training module 2.

[0034] S604: Compare the first parallel signal and the second parallel signal to obtain the current comparison result.

[0035] In the embodiments of this specification, if the first FPGA is a synchronous board FPGA and the second FPGA is a data acquisition board FPGA, the receiving training module 1 processes the second parallel signal, that is, it determines whether the second parallel signal is stable within a certain number of clock cycles. Specifically, a counter can be set. For example, it determines whether the second parallel signal is stable within the range of the counter count value 0-4000. If the second parallel signal remains unchanged, it is considered that the second parallel signal is stable, the second parallel signal is recorded as D2, and the first parallel signal D1 and the second parallel signal D2 are compared and processed to obtain the current comparison result.

[0036] If the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, the receiving training module 2 processes the second parallel signal, that is, it determines whether the second parallel signal is stable within a certain number of clock cycles. Specifically, a counter can be set. For example, it can determine whether the second parallel signal is stable within the range of the counter count value 0-4000. If the second parallel signal remains unchanged, it is considered that the second parallel signal is stable, and the second parallel signal is recorded as D4. The first parallel signal D3 and the second parallel signal D4 are compared and processed to obtain the current comparison result.

[0037] In the embodiments of this specification, after comparing the first parallel signal and the second parallel signal to obtain the current comparison result, as follows: Figure 8 As shown, Figure 8 This is a flowchart illustrating a second method for determining a first delay value provided in an embodiment of this specification. The method further includes: S801: If the current comparison result indicates that the first parallel signal and the second parallel signal are the same, the initial delayed signal is further delayed for the preset duration to obtain a delayed parallel signal that is different from the first parallel signal, and the current extension count corresponding to the delayed parallel signal is obtained.

[0038] In the embodiments of this specification, if the first FPGA is a synchronization board FPGA and the second FPGA is a acquisition board FPGA, if the current comparison result indicates that the first parallel signal and the second parallel signal are the same, that is, D1 and D2 are equal, it indicates that the delay adjustment has not been successful. A delay adjustment signal is sent to the delay adjustment module 1, and the synchronization signal after the initial delay continues to be delayed for a preset duration TN. Each time a delay occurs, the extension count is incremented by 1, i.e., N1 = N1 + 1. N1 is continuously updated. After each delay, the delayed signal undergoes serial-to-parallel conversion processing and is compared with the first parallel signal until a delayed parallel signal different from the first parallel signal is obtained. The current extension count N1 corresponding to the delayed parallel signal is then obtained. For example, as shown... Figure 9 or Figure 10 As shown, Figure 9 This is a schematic diagram of the level of the first type of synchronization signal delay adjustment provided in the embodiments of this specification. Figure 9 In this diagram, 901 is the clock signal, 902 is the synchronization signal, 903 is the first 8-bit binary parallel signal obtained by serial-to-parallel conversion of the synchronization signal (e.g., '10101010'), 904 is the synchronization signal with one delay adjustment (i.e., the initial delayed signal), and 905 is the second binary parallel signal obtained by serial-to-parallel conversion of the initial delayed signal (e.g., '10101010'). The delay time is TN. It can be seen that the initial delay adjustment of the synchronization signal was unsuccessful; therefore, the delay adjustment process continues until the delayed parallel signal differs from the first parallel signal. Figure 9 In the diagram, 906 is the synchronization signal after successful delay adjustment, and 907 is the binary parallel data converted from the synchronization signal after successful delay adjustment, which can be '01010101'.

[0039] Figure 10 This is a schematic diagram of the level of the second type of synchronization signal delay adjustment provided in the embodiments of this specification. Figure 10 In this diagram, 1001 is the clock signal, 1002 is the synchronization signal, 1003 is the first parallel binary signal (01010101) obtained by converting the synchronization signal from serial to parallel, 1004 is the synchronization signal after one delay adjustment (the initial delayed signal), and 1005 is the second parallel binary signal (01010101) obtained by converting the initial delayed signal from serial to parallel. The delay time is TN. It can be seen that the initial delay adjustment of the synchronization signal was not successful, so the delay adjustment process continues until the delayed parallel signal is different from the first parallel signal. Figure 10In the diagram, 1006 is the synchronization signal after successful delay adjustment, and 1007 is the binary parallel data converted from the synchronization signal after successful delay adjustment, which can be '10101010'.

[0040] If the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, if the current comparison result indicates that the first parallel signal and the second parallel signal are the same, that is, D3 and D4 are equal, it indicates that the delay adjustment has not been successful. A delay adjustment signal is sent to the delay adjustment module 2, and the synchronization signal after the initial delay continues to be delayed for a preset duration TN. Each time the delay occurs, the extension count is incremented by 1, that is, N2 = N2 + 1. N2 is continuously updated. After each delay, the signal after the delay is converted from serial to parallel and compared with the first parallel signal until the parallel signal after the delay is different from the first parallel signal. The current extension count N2 corresponding to the parallel signal after the delay is obtained.

[0041] S802: Use the delayed parallel signal as the calibrated signal.

[0042] In the embodiments described in this specification, the delayed parallel signal is used as the calibrated signal D2.

[0043] S803: Determine the first delay value based on the preset duration and the current number of extensions.

[0044] In the embodiments of this specification, if the first FPGA is a synchronization board FPGA and the second FPGA is a data acquisition board FPGA, the first delay value TD1 can be calculated based on the preset duration TN and the current extension number N1, and TD1 = TN * N1.

[0045] If the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, the first delay value TD2 can be calculated based on the preset duration TN and the current extension count N2, where TD2 = TN * N2. By continuously adjusting the delay of the signal after the initial delay until a parallel signal with a different delay than the first parallel signal is obtained, the sampling point is gradually shifted backward on the time axis, dynamically determining the compensation delay required for the optimal sampling point, thus achieving adaptive calibration of the subsequent trigger signal.

[0046] S605: If the current comparison result indicates that the first parallel signal is different from the second parallel signal, the second parallel signal shall be used as the calibrated signal.

[0047] In the embodiments of this specification, if the first FPGA is a synchronization board FPGA and the second FPGA is a acquisition board FPGA, if the current comparison result indicates that the first parallel signal and the second parallel signal are different, that is, D1 and D2 are not equal, it indicates that the delay adjustment is successful at this time, and the second parallel signal is used as the calibrated signal.

[0048] If the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, if the current comparison result indicates that the first parallel signal and the second parallel signal are different, that is, D3 and D4 are not equal, it indicates that the delay adjustment is successful at this time, and the second parallel signal is used as the calibrated signal.

[0049] S606: Determine the first delay value based on the preset duration and the number of real-time extensions.

[0050] In the embodiments of this specification, if the first FPGA is a synchronization board FPGA and the second FPGA is a data acquisition board FPGA, the current backward delay value is kept unchanged, and the first delay value is determined according to the preset duration TN and the number of real-time extensions N1. The first delay value is TD1, and TD1 = TN * N1.

[0051] If the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, the current backward delay value remains unchanged, and the first delay value is determined based on the preset duration TN and the number of real-time delays N2. This first delay value is denoted as TD1, and TD2 = TN * N2. By automatically adjusting the received synchronization signal during FPGA operation until the delay is successful, and combining the preset duration and the number of real-time delays to determine the first delay value, reliable sampling between the data acquisition board FPGA and the synchronization board FPGA is ensured, achieving adaptive calibration of the signal sampling points.

[0052] In this embodiment of the specification, the first FPGA is the synchronization board FPGA, and the second FPGA is any one of the at least two acquisition board FPGAs; after performing delay calibration processing on the synchronization signal to obtain a calibrated signal different from the synchronization signal, and determining the first delay value based on the calibrated signal and the synchronization signal, as follows... Figure 11 As shown, Figure 11 This is a flowchart illustrating a method for determining a first target delay value provided in an embodiment of this specification. The method further includes: S1101: Obtain the initial calibrated signal, initial delay value, and clock frequency corresponding to the first FPGA for each acquisition board FPGA.

[0053] In the embodiments of this specification, after each acquisition board FPGA sends a synchronization signal to the synchronization board and performs delay calibration, the initial calibrated signal, initial delay value and clock frequency corresponding to the first FPGA are obtained for each acquisition board FPGA. In fact, the clock frequency of the synchronization board FPGA and each acquisition board FPGA is the same, which can be 125MHz for example.

[0054] S1102: Send the initial calibration signal, initial delay value, and clock frequency corresponding to the first FPGA to the host computer; so that the host computer determines the delay clock frequency according to the clock frequency corresponding to the first FPGA; so that the host computer determines the first target delay value corresponding to each FPGA according to the initial calibration signal, initial delay value, and delay clock frequency corresponding to each FPGA; so that the host computer sends the first target delay value corresponding to each FPGA to the first FPGA.

[0055] In the embodiments of this specification, the initial calibration signal, initial delay value, and clock frequency corresponding to the first FPGA of each acquisition board are sent to the host computer. This allows the host computer to determine the delay clock frequency, i.e., the sampling frequency multiplier clock, which can be twice the clock frequency of the first FPGA, based on the clock frequency of the first FPGA. The host computer performs joint debugging on all acquisition board FPGAs based on the initial calibration signal, initial delay value, and delay clock frequency of each acquisition board FPGA, ensuring that the synchronization signals sent by each acquisition board FPGA can be detected simultaneously at the same time. This determines the first target delay value for each acquisition board FPGA. The host computer sends the first target delay value of each acquisition board FPGA to the first FPGA, so that when subsequent acquisition board FPGAs send trigger signals to the synchronization board FPGA, the synchronization board FPGA performs delay processing on the trigger signals based on the first target delay value, enabling the synchronization board FPGA to detect the trigger signals sent by each acquisition board FPGA at the same time. For example, as shown... Figure 12 As shown, Figure 12 This is a schematic diagram of the level of a multi-signal delay calibration provided in an embodiment of this specification. 1201 is a clock signal, 1202 is a frequency-doubled clock signal, the frequency of clock signal 1202 is twice that of clock signal 1201, and 1203 is... Figure 9 The situation shown is the trigger signal after the synchronization signal delay adjustment is completed; 1204 is... Figure 10The scenario shown illustrates the trigger signal after the synchronization signal delay adjustment is complete. 1205 is the trigger signal for 1203 delayed by one clock cycle from clock 1202. Trigger signals 1204 and 1205 can be detected simultaneously by the rising edge of clock 1201. Specifically, a 125MHz clock can be used to sample the synchronization signal on both sides. The synchronization signal is a 125MHz square wave signal. Before delay adjustment, the sampled data stabilizes, and the resulting 8-bit wide binary parallel data is either '10101010' or '01010101'. Then, the synchronization signal is delayed by approximately 4 ps per adjustment until the parallel data changes from '10101010' to... If the data changes from '01010101' to '10101010' and remains stable for a certain number of clock cycles, the delay adjustment is considered successful. The synchronization signal edge is aligned with the clock edge to the maximum extent. Then, the channel signal whose sampled data changes from '10101010' to '01010101' is delayed by one clock cycle at 250MHz. This completes the delay calibration and compensation for each channel. The trigger signals of each channel can be detected simultaneously at the rising edge of the clock. That is, when each acquisition board FPGA sends a trigger signal to the synchronization board FPGA, the trigger signals sent by each acquisition board FPGA can be detected by the synchronization board FPGA at the same time.

[0056] S1103: Receive the first target delay value corresponding to each acquisition board FPGA sent by the host computer.

[0057] In the embodiments of this specification, the first target delay value corresponding to each acquisition board FPGA sent by the host computer is received so that the trigger signal sent by the acquisition board FPGA can be delayed and adjusted subsequently. Similarly, if the first FPGA is an acquisition board FPGA and the second FPGA is a synchronization board FPGA, each acquisition board also receives the synchronization signal sent by the synchronization board and performs joint debugging until the synchronously sent synchronization signal can be detected by each acquisition board FPGA at the same time, and the target delay value of the synchronization board FPGA relative to each acquisition board FPGA is obtained. So that when the synchronization board FPGA sends the trigger signal, each acquisition board FPGA can delay the trigger signal sent by the synchronization board FPGA based on the corresponding target delay value. By using a frequency-doubled clock to perform delay adjustment processing on multiple signals, the signal calibration accuracy is improved, and the delay of each channel trigger link and strict time alignment of multiple channels are achieved with higher time resolution.

[0058] In the embodiments of this specification, after receiving the first target delay value corresponding to each acquisition board FPGA sent by the host computer, as follows: Figure 13 As shown, Figure 13This is a flowchart illustrating a method for determining the calibrated signals corresponding to each FPGA acquisition board provided in an embodiment of this specification. The method further includes: S1301: Send a second delay calibration success signal to the host computer; so that the host computer forwards the second delay calibration success signal to each acquisition board FPGA.

[0059] In the embodiments of this specification, a second delayed calibration success signal is sent to the host computer so that the host computer forwards the second delayed calibration success signal to each acquisition board FPGA, that is, the sending module of each acquisition board FPGA.

[0060] S1302: Receive the trigger signal sent by each acquisition board FPGA based on the second delay calibration success signal.

[0061] In the embodiments of this specification, each acquisition board FPGA switches its signal source to a trigger signal based on the received second delay calibration success signal. Each acquisition board FPGA can drive multiple ADCs for data acquisition, and each acquisition board FPGA has a corresponding ADC data processing and trigger judgment module, capable of trigger judgment on the data of each ADC and generating a trigger signal. Each acquisition board FPGA can process the trigger signals of each ADC, integrate them into a single trigger signal, and transmit the trigger signal to the synchronization board FPGA through the trigger signal upload channel. For a single acquisition board FPGA and the synchronization board FPGA, the acquisition board FPGA switches its signal source to trigger signal 1 and sends trigger signal 1 to the delay adjustment module 1 through the trigger signal upload channel.

[0062] S1303: Perform delay calibration processing on the trigger signals sent by each acquisition board FPGA according to the first target delay value corresponding to each acquisition board FPGA to obtain the calibrated signal corresponding to each acquisition board FPGA.

[0063] In the embodiments of this specification, for a single acquisition board FPGA and a synchronization board FPGA, such as Figure 7As shown, the delay adjustment module 1 performs delay adjustment processing on the received trigger signal 1 according to the first target delay value to obtain the delayed trigger signal 2, and sends trigger signal 2 to the signal output module 1. At this time, the downlink channel adjustment success signal sent by the host computer to the signal output module 1 is valid, and the signal output module sends trigger signal 2 to the trigger signal processing module. At the same time, the trigger signal processing module also receives trigger signals 3, 4, and 5 sent by other acquisition board FPGAs; where trigger signals 2, 3, 4, and 5 are the calibrated signals corresponding to each acquisition board FPGA. By performing delay adjustment processing on the trigger signals sent by each acquisition board based on the first target delay value after joint debugging of each acquisition board, and receiving the delayed trigger signals sent by each acquisition board, it is helpful to achieve global trigger time alignment and establish a unified and accurate trigger event reference point on the synchronization board FPGA.

[0064] In this embodiment of the specification, after performing delay calibration processing on the trigger signals sent by each acquisition board FPGA according to the first target delay value corresponding to each acquisition board FPGA to obtain the calibrated signals corresponding to each acquisition board FPGA, as follows: Figure 14 As shown, Figure 14 This is a flowchart illustrating a method for transmitting a second trigger signal according to an embodiment of this specification. The method further includes: S1401: Obtain the number of acquisition boards corresponding to each acquisition board FPGA.

[0065] In the embodiments of this specification, the number of acquisition boards corresponding to each acquisition board FPGA is obtained, that is, how many acquisition boards FPGA are there in total.

[0066] S1402: At a preset time, the calibrated signals corresponding to each acquisition board FPGA are detected and processed to obtain the real-time detection quantity value.

[0067] In the embodiments of this specification, the calibrated signals corresponding to each acquisition board FPGA are detected and processed at a preset time, that is, the calibrated signals corresponding to each acquisition board FPGA are detected and processed at the same time to obtain the real-time detection quantity value; such as Figure 7 As shown, the trigger signal processing module detects the trigger signal at the same time.

[0068] S1403: If the real-time detection quantity value is equal to the acquisition board quantity value, a second trigger signal is generated.

[0069] In the embodiments of this specification, if the real-time detection quantity is equal to the acquisition board quantity, that is, the number of trigger signals detected at the same time is equal to the number of acquisition boards, it indicates that the trigger signals sent by each acquisition board FPGA are detected by the synchronization board FPGA at the same time after delay calibration. At this time, the trigger signal processing module generates a second trigger signal; Figure 7 As shown, the trigger signal processing module detects trigger signal 2, trigger signal 3, trigger signal 4 and trigger signal 5 at the same time, indicating that the trigger signals sent by the four acquisition board FPGAs are all acquired by the synchronization board FPGA, and the synchronization board FPGA generates trigger signal 6.

[0070] S1404: Send the second trigger signal to each of the acquisition board FPGAs; so that each of the acquisition board FPGAs performs delay calibration processing on the second trigger signal respectively.

[0071] In the embodiments of this specification, a second trigger signal is sent to each acquisition board FPGA, so that each acquisition board FPGA performs delay calibration processing on the second trigger signal with the delay value corresponding to each acquisition board FPGA, so that each acquisition board FPGA can detect the second trigger signal sent by the synchronization board FPGA at the same time. Figure 7 As shown, the trigger signal processing module generates trigger signal 6 and sends it to the sending module 2. The sending module 2 then sends trigger signal 6 to each acquisition board FPGA through the trigger signal sending channel, enabling each acquisition board FPGA to perform delay calibration processing on trigger signal 6. By generating a second trigger signal after the synchronization board detects the trigger signals sent by each acquisition board FPGA at the same time and then sending it to each acquisition board FPGA, an absolutely unified global event occurrence time point is identified on the synchronization board FPGA, bypassing uplink differences. This eliminates the adverse effects of differences in the local generation time of the original event and uplink transmission delays of each acquisition board FPGA, achieving global coordination and ensuring that all acquisition board FPGAs execute critical actions at the same time.

[0072] S105: Send a first delayed calibration success signal to the host computer; so that the host computer forwards the first delayed calibration success signal to the second FPGA.

[0073] In the embodiments of this specification, after the delay adjustment of the trigger signal upload channel and trigger signal download channel between each acquisition board FPGA and the synchronization board FPGA is completed, i.e., after obtaining the first delay value, the first FPGA sends a first delay calibration success signal to the host computer. Wherein, if the first FPGA is the synchronization board FPGA and the second FPGA is the acquisition board FPGA, then the first delay calibration success signal is an upload delay calibration success signal; if the first FPGA is the acquisition board FPGA and the second FPGA is the synchronization board FPGA, then the first delay calibration success signal is a download delay calibration success signal; after receiving the first delay calibration success signal, the host computer forwards the first delay calibration success signal to the second FPGA.

[0074] S107: Receive the first trigger signal sent by the second FPGA based on the first delay calibration success signal.

[0075] In the embodiments of this specification, after receiving the first delay calibration success signal, the second FPGA sends a first trigger signal to the first FPGA; specifically, if the first FPGA is a synchronization board FPGA and the second FPGA is a data acquisition board FPGA, then the first FPGA receives the first trigger signals sent by each data acquisition board FPGA; if the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, then the first FPGA receives the first trigger signal generated and sent by the synchronization board FPGA.

[0076] S109: Perform delay calibration processing on the first trigger signal according to the first delay value to obtain the first calibrated trigger signal.

[0077] In the embodiments of this specification, the first FPGA performs delay calibration processing on the received first trigger signal based on the first delay value to obtain the first calibrated trigger signal.

[0078] In the embodiments described in this specification, such as Figure 15 As shown, Figure 15 This is a flowchart illustrating a method for transmitting a second trigger signal according to an embodiment of this specification. The method further includes: S1501: Receive the second target delay value sent by the host computer.

[0079] In the embodiments of this specification, if the first FPGA is a synchronization board FPGA and the second FPGA is a data acquisition board FPGA, the first FPGA receives a successful channel adjustment signal and a fixed delay parameter, i.e., a second target delay value, sent by the host computer. The second target delay value is a fixed delay value of the synchronization board FPGA relative to each data acquisition board FPGA. Figure 7As shown, the signal output module 1 in the first FPGA receives the downlink channel adjustment success signal sent by the host computer, and the delay adjustment module 1 receives the fixed delay parameter 2 sent by the host computer, which is the second target delay value.

[0080] If the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, the first FPGA receives a successful upload channel adjustment signal and a fixed delay parameter, i.e., the second target delay value, sent by the host computer. The second target delay value is a fixed delay value for each data acquisition board FPGA relative to the synchronization board FPGA. Figure 7 As shown, the signal output module 2 in the first FPGA receives the upload channel adjustment success signal sent by the host computer, and the delay adjustment module 2 receives the fixed delay parameter 1 sent by the host computer, which is the second target delay value.

[0081] S1502: Receive the third trigger signal sent by the second FPGA based on the second delay calibration command sent by the host computer.

[0082] In the embodiments of this specification, if the first FPGA is a synchronization board FPGA and the second FPGA is a data acquisition board FPGA, the second FPGA receives the upload channel adjustment success signal sent by the host computer, i.e., the second delay calibration command, and the second FPGA sends a third trigger signal to the first FPGA; if Figure 7 As shown, the sending module 1 in the second FPGA receives the upload channel adjustment success signal sent by the host computer. The second FPGA switches the signal source to trigger signal 1, and the sending module 1 sends trigger signal 1 to the delay adjustment module 1 of the first FPGA through the trigger signal upload channel.

[0083] If the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, the second FPGA receives the channel adjustment success signal sent by the host computer, i.e., the second delay calibration command, and then sends the third trigger signal to the first FPGA; if... Figure 7 As shown, the sending module 2 in the second FPGA receives the upload channel adjustment success signal sent by the host computer, and the sending module 2 in the second FPGA sends the trigger signal 6 to the delay adjustment module 2 of the first FPGA through the trigger signal sending channel.

[0084] S1503: The third trigger signal is delayed by the second target delay value to obtain the second calibrated trigger signal.

[0085] In the embodiments of this specification, if the first FPGA is a synchronization board FPGA and the second FPGA is a data acquisition board FPGA, the first FPGA performs delay processing on the third trigger signal with a second target delay value to obtain the second calibrated trigger signal. Figure 7As shown, the delay adjustment module 1 in the first FPGA performs a backward delay processing on the third trigger signal according to the second target delay value sent by the host computer, to obtain the second calibrated trigger signal, i.e., trigger signal 2, and sends the second calibrated trigger signal to the signal output module 1. The signal output module 1 sends the second calibrated trigger signal to the trigger signal processing module. At this time, the channel adjustment signal sent by the host computer to the signal output module 1 is valid. At the same time, the trigger signal processing module also receives the delayed trigger signals sent by other acquisition board FPGAs, such as trigger signal 3, trigger signal 4 and trigger signal 5 in the figure. It jointly judges the trigger signals 2, 3, 4 and 5. If the trigger condition is met, trigger signal 6 is generated and sent to the sending module 2.

[0086] If the first FPGA is a data acquisition board FPGA and the second FPGA is a synchronization board FPGA, the first FPGA performs a delay processing on the third trigger signal with a second target delay value to obtain the second calibrated trigger signal. For example... Figure 7 As shown, the delay adjustment module 2 in the first FPGA delays the third trigger signal backward according to the second target delay value sent by the host computer, obtaining the second calibrated trigger signal, i.e., trigger signal 7. This second calibrated trigger signal is then sent to the signal output module 2, which outputs the second calibrated trigger signal. At this point, the channel adjustment signal sent from the host computer to the signal output module 2 is valid. By setting the second target delay value, precise delay compensation is added independently to each link, achieving precise inter-channel delay compensation and centralized management and dynamic configuration of multiple FPGAs in scenarios with relatively stable latency.

[0087] In one exemplary implementation, such as Figure 16 As shown, Figure 16 This specification provides a structural diagram of a delay calibration device according to an embodiment, comprising a host computer, at least one synchronization board FPGA, and at least two acquisition board FPGAs. Each synchronization board FPGA and each acquisition board FPGA is communicatively connected to the host computer. Each synchronization board FPGA and each acquisition board FPGA is used to perform delay calibration of the multiple FPGAs according to the method described above. The delay calibration device also includes a clock module, which provides a synchronization clock for the at least one synchronization board FPGA and the at least two acquisition board FPGAs.

[0088] The delay calibration device includes multiple acquisition board FPGAs, one synchronization board FPGA, a high-precision unified clock source, and a host computer. Each acquisition board FPGA and the synchronization board FPGA have trigger signal upload and download channels. Information exchange channels are established between the host computer, the clock source, each acquisition board FPGA, and the synchronization board FPGA. The clock source provides high-precision clock signals to each acquisition board FPGA and the synchronization board FPGA, ensuring that each FPGA operates on the same time base, fundamentally reducing trigger delay errors caused by clock differences. The clock lines between the clock source and each acquisition board FPGA and the synchronization board FPGA are of equal length, and the clock phase can be finely adjusted via a delay adjustment chip. The multiple acquisition board FPGAs form a parallel data acquisition architecture, and each FPGA can drive multiple ADCs for data acquisition. Each FPGA internally has corresponding ADC data processing and trigger judgment functions. The module can trigger and judge the data of each ADC and generate a trigger signal. Each acquisition board FPGA can process the trigger signals of each ADC, integrate them into a single trigger signal, and transmit the trigger signal to the synchronization board FPGA through the trigger signal upload channel. It also receives the trigger signal uniformly transmitted by the synchronization board FPGA through the trigger signal transmission channel. The number of trigger signal upload channels and trigger signal transmission channels is consistent with the number of acquisition board FPGAs. The synchronization board FPGA receives the trigger signals uploaded by each acquisition board FPGA, integrates them, and then transmits them uniformly. Each acquisition board FPGA and synchronization board FPGA has a trigger signal transmission module and a trigger signal reception module, which can complete the functions of signal transmission, reception, and delay adjustment. The host computer can transmit and read configuration information for each acquisition board FPGA and synchronization board FPGA, transmit delay adjustment status signals, and assist in the information exchange between each acquisition board FPGA and synchronization board FPGA.

[0089] This manual also provides delay calibration devices for multiple FPGAs, such as... Figure 17 As shown, the multiple FPGAs include at least one synchronization board FPGA and at least two acquisition board FPGAs; each synchronization board FPGA and each acquisition board FPGA are communicatively connected to a host computer; the method is applied to a first FPGA, which is any one of the at least one synchronization board FPGA and the at least two acquisition board FPGAs; the apparatus includes: The synchronization signal receiving module 1701 is used to receive the synchronization signal sent by the second FPGA in response to the first delay calibration command sent by the host computer; the second FPGA and the first FPGA are located on different circuit boards. The first delay value determination module 1702 is used to perform delay calibration processing on the synchronization signal to obtain a calibrated signal that is different from the synchronization signal, and to determine the first delay value based on the calibrated signal and the synchronization signal. The first delay calibration success signal sending module 1703 is used to send a first delay calibration success signal to the host computer, so that the host computer forwards the first delay calibration success signal to the second FPGA. The first trigger signal receiving module 1704 is used to receive the first trigger signal sent by the second FPGA based on the first delay calibration success signal; The first calibration trigger signal determination module 1705 is used to perform delay calibration processing on the first trigger signal according to the first delay value to obtain the first calibration trigger signal.

[0090] In some embodiments, the first delay value determination module further includes: The first parallel signal determination submodule is used to perform serial-to-parallel conversion processing on the synchronization signal to obtain the first parallel signal; The real-time delay count acquisition submodule is used to delay the synchronization signal for a preset duration to obtain the initial delayed signal and acquire the real-time delay count. The second parallel signal determination submodule is used to perform serial-to-parallel conversion processing on the initial delayed signal to obtain the second parallel signal. The current comparison result determination submodule is used to compare the first parallel signal and the second parallel signal to obtain the current comparison result. The post-calibration signal determination submodule is used to take the second parallel signal as the post-calibration signal if the current comparison result indicates that the first parallel signal is different from the second parallel signal. The first delay value determination submodule is used to determine the first delay value based on the preset duration and the number of real-time extensions.

[0091] In some embodiments, the apparatus further includes: The current extension count acquisition module is used to, if the current comparison result indicates that the first parallel signal and the second parallel signal are the same, continue to delay the initial delayed signal for the preset duration to obtain a delayed parallel signal that is different from the first parallel signal, and acquire the current extension count corresponding to the delayed parallel signal; A post-calibration signal determination module is used to take the delayed parallel signal as the post-calibration signal; The determining module is used to determine the first delay value based on the preset duration and the current number of extensions.

[0092] In some embodiments, the apparatus further includes: The acquisition module is used to acquire the initial calibrated signal, initial delay value and clock frequency corresponding to the first FPGA of each acquisition board FPGA; The sending module is used to send the initial calibration signal, initial delay value, and clock frequency corresponding to each acquisition board FPGA to the host computer; so that the host computer determines the delay clock frequency based on the clock frequency corresponding to the first FPGA; so that the host computer determines the first target delay value corresponding to each acquisition board FPGA based on the initial calibration signal, initial delay value, and delay clock frequency corresponding to each acquisition board FPGA; and so that the host computer sends the first target delay value corresponding to each acquisition board FPGA to the first FPGA. The first target delay value receiving module is used to receive the first target delay value corresponding to each acquisition board FPGA sent by the host computer.

[0093] In some embodiments, the apparatus further includes: The second delay calibration success signal sending module is used to send a second delay calibration success signal to the host computer, so that the host computer forwards the second delay calibration success signal to each acquisition board FPGA; The trigger signal receiving module is used to receive the trigger signals sent by each acquisition board FPGA based on the second delay calibration success signal; The calibration signal determination module is used to perform delay calibration processing on the trigger signals sent by each acquisition board FPGA according to the first target delay value corresponding to each acquisition board FPGA, so as to obtain the calibration signal corresponding to each acquisition board FPGA.

[0094] In some embodiments, the apparatus further includes: The acquisition board quantity value acquisition module is used to acquire the acquisition board quantity value corresponding to each acquisition board FPGA; The real-time detection quantity determination module is used to detect and process the calibrated signals corresponding to each acquisition board FPGA at a preset time to obtain the real-time detection quantity value. The second trigger signal generation module is used to generate a second trigger signal if the real-time detection quantity value is equal to the acquisition board quantity value. The second trigger signal sending module is used to send the second trigger signal to each of the acquisition board FPGAs, so that each acquisition board FPGA performs delay calibration processing on the second trigger signal.

[0095] In some embodiments, the apparatus further includes: The second target delay value receiving module is used to receive the second target delay value sent by the host computer; The third trigger signal receiving module is used to receive the third trigger signal sent by the second FPGA based on the second delay calibration command sent by the host computer; The second calibration trigger signal determination module is used to delay the third trigger signal with the second target delay value to obtain the second calibration trigger signal.

[0096] The apparatus and method embodiments described herein are based on the same inventive concept.

[0097] This specification provides an electronic device including a processor and a memory. The memory stores at least one instruction or at least one program, which is loaded and executed by the processor to implement the delay calibration method for multiple FPGAs as provided in the above method embodiments.

[0098] Embodiments of this application also provide a computer storage medium, which can be disposed in a terminal to store at least one instruction or at least one program related to implementing a delay calibration method for multiple FPGAs in the method embodiment. The at least one instruction or at least one program is loaded and executed by the processor to implement the delay calibration method for multiple FPGAs provided in the above method embodiment.

[0099] Embodiments of this application also provide a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the delay calibration method for multiple FPGAs provided in the above-described method embodiments.

[0100] The memory described in the embodiments of this specification can be used to store software programs and modules. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory. The memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, application programs required for the functions, etc.; the data storage area may store data created according to the use of the device, etc.

[0101] The delay calibration method for multiple FPGAs provided in this specification can be executed in a mobile terminal, computer terminal, server, or similar computing device.

[0102] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A delay calibration method for multiple FPGAs, characterized in that, The multiple FPGAs include at least one synchronization board FPGA and at least two acquisition board FPGAs; each synchronization board FPGA and each acquisition board FPGA are communicatively connected to a host computer; the method is applied to a first FPGA, which is any one of the at least one synchronization board FPGA and the at least two acquisition board FPGAs, and the method includes: In response to the first delay calibration command sent by the host computer, a synchronization signal sent by the second FPGA is received; the second FPGA and the first FPGA are located on different circuit boards; The synchronization signal is subjected to delay calibration to obtain a calibrated signal that is different from the synchronization signal, and a first delay value is determined based on the calibrated signal and the synchronization signal. Send a first delayed calibration success signal to the host computer; so that the host computer forwards the first delayed calibration success signal to the second FPGA; Receive the first trigger signal sent by the second FPGA based on the first delay calibration success signal; The first trigger signal is subjected to delay calibration processing based on the first delay value to obtain the first calibrated trigger signal.

2. The method according to claim 1, characterized in that, The step of performing delay calibration on the synchronization signal to obtain a calibrated signal different from the synchronization signal, and determining a first delay value based on the calibrated signal and the synchronization signal, includes: The synchronization signal is subjected to serial-to-parallel conversion processing to obtain the first parallel signal; The synchronization signal is delayed for a preset duration to obtain the initial delayed signal, and the number of real-time delays is obtained. The initial delayed signal is subjected to serial-to-parallel conversion processing to obtain a second parallel signal; The first parallel signal and the second parallel signal are compared and processed to obtain the current comparison result; If the current comparison result indicates that the first parallel signal is different from the second parallel signal, the second parallel signal is used as the calibrated signal. The first delay value is determined based on the preset duration and the number of real-time extensions.

3. The method according to claim 2, characterized in that, After comparing the first parallel signal and the second parallel signal to obtain the current comparison result, the method further includes: If the current comparison result indicates that the first parallel signal and the second parallel signal are the same, the signal after the initial delay is further delayed for the preset duration to obtain a delayed parallel signal that is different from the first parallel signal, and the current number of delays corresponding to the delayed parallel signal is obtained; The delayed parallel signal is used as the calibrated signal; The first delay value is determined based on the preset duration and the current number of extensions.

4. The method according to claim 1, characterized in that, The first FPGA is the synchronization board FPGA, and the second FPGA is any one of the at least two acquisition board FPGAs; after performing delay calibration processing on the synchronization signal to obtain a calibrated signal different from the synchronization signal, and determining a first delay value based on the calibrated signal and the synchronization signal, the method further includes: Acquire the initial calibrated signal, initial delay value, and clock frequency of the first FPGA for each acquisition board FPGA; The host computer sends the initial calibration signal, initial delay value, and clock frequency corresponding to each FPGA acquisition board to the host computer; so that the host computer determines the delay clock frequency based on the clock frequency corresponding to the first FPGA; so that the host computer determines the first target delay value corresponding to each FPGA acquisition board based on the initial calibration signal, initial delay value, and delay clock frequency corresponding to each FPGA acquisition board; so that the host computer sends the first target delay value corresponding to each FPGA acquisition board to the first FPGA. Receive the first target delay value corresponding to each acquisition board FPGA sent by the host computer.

5. The method according to claim 4, characterized in that, After receiving the first target delay value corresponding to each FPGA acquisition board sent by the host computer, the method further includes: Send a second delayed calibration success signal to the host computer; so that the host computer forwards the second delayed calibration success signal to each of the acquisition board FPGAs; Receive the trigger signal sent by each of the acquisition board FPGAs based on the second delay calibration success signal; Based on the first target delay value corresponding to each acquisition board FPGA, the trigger signals sent by each acquisition board FPGA are subjected to delay calibration processing to obtain the calibrated signals corresponding to each acquisition board FPGA.

6. The method according to claim 5, characterized in that, After performing delay calibration processing on the trigger signals sent by each acquisition board FPGA according to the first target delay value corresponding to each acquisition board FPGA to obtain the calibrated signals corresponding to each acquisition board FPGA, the method further includes: Obtain the number of acquisition boards corresponding to each FPGA acquisition board; At a preset time, the calibrated signals corresponding to each FPGA acquisition board are detected and processed to obtain the real-time detection quantity value; If the real-time detection quantity value is equal to the acquisition board quantity value, a second trigger signal is generated; The second trigger signal is sent to each of the acquisition board FPGAs so that each acquisition board FPGA performs delay calibration processing on the second trigger signal.

7. The method according to claim 1, characterized in that, The method further includes: Receive the second target delay value sent by the host computer; Receive the third trigger signal sent by the second FPGA based on the second delay calibration command sent by the host computer; The third trigger signal is delayed by the second target delay value to obtain the second calibrated trigger signal.

8. A delay calibration device for multiple FPGAs, characterized in that, The multiple FPGAs include at least one synchronization board FPGA and at least two acquisition board FPGAs; each synchronization board FPGA and each acquisition board FPGA are communicatively connected to a host computer; the method is applied to a first FPGA, which is any one of the at least one synchronization board FPGA and the at least two acquisition board FPGAs; the apparatus includes: A synchronization signal receiving module is used to receive a synchronization signal sent by the second FPGA in response to a first delay calibration command sent by the host computer; the second FPGA and the first FPGA are located on different circuit boards; The first delay value determination module is used to perform delay calibration processing on the synchronization signal to obtain a calibrated signal that is different from the synchronization signal, and to determine the first delay value based on the calibrated signal and the synchronization signal. The first delay calibration success signal sending module is used to send a first delay calibration success signal to the host computer, so that the host computer forwards the first delay calibration success signal to the second FPGA. The first trigger signal receiving module is used to receive the first trigger signal sent by the second FPGA based on the first delay calibration success signal; The first calibration trigger signal determination module is used to perform delay calibration processing on the first trigger signal according to the first delay value to obtain the first calibration trigger signal.

9. A time-delay calibration device, characterized in that, It includes a host computer, at least one synchronization board FPGA and at least two acquisition board FPGAs; each synchronization board FPGA and each acquisition board FPGA are communicatively connected to the host computer; each synchronization board FPGA and each acquisition board FPGA are used to perform delay calibration of the multiple FPGAs according to any one of claims 1-7.

10. The delay calibration device according to claim 9, characterized in that, The delay calibration device also includes a clock module, which provides a synchronization clock for the at least one synchronization board FPGA and the at least two acquisition board FPGAs.

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