Controllable phase delay circuit, multi-stage phase delay system, chip and device

Abstract

This application discloses a controllable phase delay circuit, a multi-stage phase delay system, a chip, and a device, belonging to the field of high-speed clock circuit technology for data communication. It addresses the technical problems of existing phase delay circuits, such as phase errors caused by process, voltage, and temperature (PVT) factors, narrow adjustable range, small single-stage delay, and difficulty in adapting to multiple frequency rates. The core solution of this application includes: a programmable phase delay circuit, a square wave signal sinusoidalization circuit, a fixed-ratio phase interpolation circuit, and a phase error elimination circuit. Wide-range continuous capacitance adjustment is achieved through a programmable capacitor array, and a single-stage circuit completes a large phase delay. Simultaneously, the delayed clock signal is sinusoidally sinusoidally interpolated. This application can eliminate phase disturbances caused by PVT, output high-precision clock phase, and adapt to high-speed circuit scenarios with multiple rates and frequencies.

Description

Technical Field

[0001] This application relates to the field of high-speed integrated circuit clock signal processing technology, specifically to a controllable phase delay circuit, a multi-level phase delay system, a chip and device, which are applicable to data communication application scenarios such as high-speed interfaces such as serializers / deserializers (SerDes) and differential clock multi-phase generation. Background Technology

[0002] Phase delay circuits are core components in high-speed integrated circuits for generating multi-phase clock signals, and are widely used in high-speed data transmission, clock synchronization, and other circuit systems. In practical applications of integrated circuits, three objective factors—process, voltage, and temperature (PVT)—can have irreversible effects on phase delay circuits: process corner deviations in chip manufacturing lead to inconsistent delay parameters within the same batch of circuits; voltage noise in the power supply chain interferes with circuit stability; and ambient temperature fluctuations alter the electrical characteristics of components. The combined effect of these three factors causes phase errors in the preset fixed phase delay, severely degrading the performance of high-speed circuits.

[0003] In multi-phase clock construction scenarios, traditional fixed-phase delay circuits have poor compatibility and cannot adapt to multi-rate and multi-frequency operating requirements. The duty cycle of a fixed-phase delay changes with the clock frequency, and a single fixed delay parameter can only adapt to a specific frequency clock signal, lacking versatility.

[0004] The existing improvement scheme has obvious technical defects: the traditional scheme uses voltage-controlled resistors and voltage-controlled capacitors to fine-tune the delay, and the adjustment range of capacitors and resistors is limited, resulting in a narrow adjustable delay range; the mainstream current mode logic (CML) differential delay circuit has a very small single-stage phase delay, and multiple stages of circuits need to be connected in series to meet the large delay requirements, resulting in circuit redundancy, increased power consumption, and increased hardware costs. Summary of the Invention

[0005] To address the technical shortcomings of current phase delay circuits in high-speed circuits, such as PVT phase disturbances, narrow adjustable range, small single-stage delay, and poor multi-frequency adaptability, this application proposes a novel controllable phase delay circuit, a multi-stage phase delay system, a chip, and a device. On one hand, a programmable capacitor array is introduced to broaden the phase delay adjustment range, achieving large phase delay in a single-stage circuit and adapting to multi-rate and multi-frequency application scenarios. On the other hand, instead of directly using the original phase signal of the delay circuit, interpolation processing is performed on the output phase to shield phase disturbances caused by PVT factors, achieving high-precision, high-quality clock phase output.

[0006] In a first aspect, this application provides a programmable controllable phase delay circuit, which differs from a traditional CML differential circuit. The controllable phase delay circuit has a first differential branch, a second differential branch, and a constant current source unit arranged symmetrically. The first differential branch includes a first NMOS transistor and a first variable impedance unit, and the second differential branch includes a second NMOS transistor and a second variable impedance unit. The gates of the first NMOS transistor and the second NMOS transistor are respectively connected to the positive and negative inputs of the differential clock signal; the constant current source unit is a third NMOS transistor, the drain of the third NMOS transistor is connected to the source of the first NMOS transistor and the second NMOS transistor, the source of the third NMOS transistor is grounded, and the gate is connected to a constant bias voltage; The first and second variable impedance units have the same structure and are both connected between the drain of the corresponding NMOS transistor and the positive power supply; the variable impedance unit includes a PMOS transistor, a bias resistor, and a programmable capacitor array. The programmable capacitor array consists of a fixed capacitor bank and a voltage-controlled variable capacitor connected in parallel, with each fixed capacitor connected in series with an independent MOS switch; the voltage-controlled variable capacitor is equipped with an on / off control switch to achieve continuous adjustment of the capacitance value.

[0007] By adjusting the capacitor array in the controllable phase delay circuit, the impedance can be continuously varied, thereby adjusting the clock phase delay.

[0008] Furthermore, in the variable impedance unit, the source of the PMOS transistor is connected to the positive power supply, and the drain is connected to the drain of the corresponding NMOS transistor; a programmable capacitor array is connected between the source and gate of the PMOS transistor, and a bias resistor is connected between the gate and drain of the PMOS transistor.

[0009] Furthermore, the fixed capacitor group forms a geometric sequence with a common ratio of 2, starting from the second term and using the basic capacitance value C as the first term; the programmable capacitor array has a capacitance adjustment range of C to 128C, and the real-time capacitance values ​​of the two programmable capacitor arrays remain consistent; the capacitance value variation range of the voltage-controlled variable capacitor is close to 0 to C.

[0010] In a second aspect, this application provides a high-precision multi-stage phase delay system. This system is based on a cascade of multi-stage controllable phase delay circuits, combined with a sinusoidal circuit and a phase interpolation circuit, to perform inverse interpolation processing on a delayed clock signal with PVT error, thereby eliminating the phase error term. At the same time, the output signal is optimized through a CML differential circuit to improve the anti-interference capability of the high-speed interface.

[0011] The multi-stage phase delay system includes: a multi-stage controllable phase delay circuit, a multi-stage sinusoidalization circuit, and at least two stages of phase interpolation circuit; The multi-stage controllable phase delay circuits are cascaded to delay the input differential clock signal step by step. A single-stage controllable phase delay circuit has a phase error caused by a fixed ideal delay angle and process voltage and temperature PVT factors. The sinusoidal circuit is connected to the output of the controllable phase delay circuit in a one-to-one correspondence, and is used to convert the square wave clock signal into a sinusoidal waveform. The phase interpolation circuit is connected to the output terminals of two sinusoidal circuits spaced m apart. m = 180° / single-stage ideal delay angle; the phase interpolation circuit adopts the inverse interpolation method to eliminate PVT phase error and output a high-precision differential clock signal.

[0012] Furthermore, the sinusoidal circuit includes several delay units and several small-current clock CML differential circuits; the delay units adopt traditional CML differential circuits to apply a fixed-duration delay to the clock signal; the multiple small-current differential signals are delayed and superimposed to form a sinusoidal waveform.

[0013] Furthermore, the number of parallel small-current clock CML differential circuits inside the sinusoidal circuit is N, and the output current amplitude of a single circuit is one-Nth of the original signal; a high-frequency filter capacitor is connected to the output terminal of the sinusoidal circuit to filter out high-frequency noise in the waveform.

[0014] Furthermore, the phase interpolation circuit is a CML current-type parallel architecture, which includes two differential pairs and a common load resistor; the two differential pairs are respectively connected to sinusoidal clock signals of different phases, and the intermediate phase signal is synthesized by adjusting the tail current weight.

[0015] Furthermore, the total tail current of the phase interpolation circuit is constant, the left tail current I1=xI0, and the right tail current I2=(Mx)I0; by adjusting the bias voltage to change the value of x, proportional interpolation in the range of 0~M is achieved.

[0016] Furthermore, a CML differential circuit is added to the system input terminal and each signal output terminal; the CML differential circuit includes a positive phase circuit and an inverting phase circuit.

[0017] Furthermore, the ideal delay angle of the single-stage controllable phase delay circuit is 45°, and the preset number of stages m=4; the system includes 7-stage controllable phase delay circuits, 8-stage sine wave circuits, and 4-stage phase interpolation circuits, realizing single-channel input and 8-channel high-precision differential clock output.

[0018] Based on another aspect of this application, this application also provides a chip that integrates the controllable phase delay circuit as described above or the multi-stage phase delay system as described above.

[0019] Based on another aspect of this application, this application also provides a computer device that uses a chip that integrates the controllable phase delay circuit as described above or the multi-stage phase delay system as described above.

[0020] The technical solution provided in this application has the following technical effects: 1. Wide range of adjustable phase delay: The controllable phase delay circuit adopts a combination of fixed capacitor array and voltage-controlled variable capacitor to realize continuous capacitor adjustment, and the phase delay control range is wide, which is compatible with multi-protocol and multi-rate communication circuits. 2. Simplified circuit structure: A single-stage controllable phase delay circuit can achieve a large-angle phase delay without the need for multiple stages in series, thus reducing circuit redundancy and power consumption; 3. It can basically eliminate PVT error: The multi-stage phase delay system is based on a sinusoidal + inverse interpolation architecture, which eliminates phase errors caused by process, voltage and temperature, and greatly improves clock phase accuracy; 4. Strong compatibility: The circuit provided in this application can be applied to the SerDes high-speed interface, and the differential signal output mode has excellent noise immunity and is applicable to a wide range of scenarios.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the controllable phase delay circuit structure provided in Embodiment 1 of this application; Figure 2 This is a detailed structural diagram of the controllable phase delay circuit provided in Embodiment 1 of this application; Figure 3 This is a schematic diagram of the differential clock signal sinusoidalization circuit structure provided in Embodiment 2 of this application; Figure 4 The diagram shows the waveform changes of the sinusoidal circuit in this application: (a) the original differential clock waveform, (b) the sawtooth waveform before filtering, and (c) the sinusoidal waveform after filtering. Figure 5 This is a schematic diagram of the fixed-ratio phase interpolation circuit structure provided in Embodiment 3 of this application; Figure 6 This is a schematic diagram of the overall architecture of the high-precision multi-level phase delay system provided in Embodiment 4 of this application; Figure 7 This is a detailed application structure diagram of the high-precision multi-level phase delay system provided in Embodiment 5 of this application. Detailed Implementation

[0023] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0024] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. The singular forms “a,” “described,” and “the” used in this specification are also intended to include the plural forms unless the context clearly indicates otherwise. This specification may use terms such as “first,” “second,” “third,” etc., to describe various information or structural modules for the purpose of more clearly describing the solution, and should not be construed as indicating or implying relative importance or implicitly specifying the number, order, or position of the indicated technical features. Thus, a feature defined with “first,” “second,” “third,” etc., may explicitly or implicitly include one or more of that feature.

[0025] Example 1 Figure 1 This is a schematic diagram of the circuit structure of a controllable phase delay circuit according to an embodiment of this application. The structure of the controllable phase delay circuit (100) is as follows: The positive P terminal (CLK_P) and negative N terminal (CLK_N) of the differential clock signal are connected to the gate G terminals of the first NMOS (110) and the second NMOS (120), respectively. In order to maintain signal symmetry and stability, a third NMOS (150) is introduced as a constant current source. The drain D terminal of the third NMOS (150) is connected to the source S terminal of the first NMOS (110) and the second NMOS (120). The S terminal of the third NMOS (150) is grounded, and the G terminal is connected to a constant bias voltage (Vbias). Variable impedance units are symmetrically arranged at both ends of the differential clock signal: one end of the first variable impedance unit (130) is connected to the drain terminal of the first NMOS (110), and the other end is connected to the positive power supply (VDD); one end of the second variable impedance unit (140) is connected to the drain terminal of the second NMOS (120), and the other end is connected to the positive power supply (VDD). The variable impedance unit consists of a programmable capacitor array, a PMOS transistor, and resistors.

[0026] In the first variable impedance unit (130), the source (S) terminal of the first PMOS (132) is connected to VDD, and the drain (D) terminal is connected to the D terminal of the first NMOS (110); one end of the first programmable capacitor array (131) is connected to the S terminal of the first PMOS (132), and the other end is connected to the G terminal of the first PMOS (132); the first resistor (133) is connected to the G terminal and the D terminal of the first PMOS (132) respectively.

[0027] The second variable impedance unit (140) adopts a symmetrical structure. The source (S) terminal of the second PMOS (142) is connected to VDD, and the drain (D) terminal is connected to the drain (D) terminal of the second NMOS (120). One end of the second programmable capacitor array (141) is connected to the S terminal of the second PMOS (142), and the other end is connected to the G terminal of the second PMOS (142). The second resistor (143) is connected to the G and D terminals of the second PMOS (142) respectively. The resistance values ​​of the first resistor (133) and the second resistor (143) are both... .

[0028] In one embodiment of this application, both the first programmable capacitor array (131) and the second programmable capacitor array (141) are composed of capacitors with different capacitance values ​​connected in parallel (for example, based on the basic capacitance value C, the capacitance values ​​of the parallel capacitors can be selected as C, C, 2C, 4C, ..., 64C, ..., and the specific number of items in the array can be increased or decreased according to the circuit design requirements). Each capacitor in the capacitor array is connected in series with a MOS switch (for example, corresponding to the capacitors are switches S1, S2, S3, ..., S8, ...). The MOS switches are used to control the connection and disconnection of the series capacitors. By controlling the opening and closing of each MOS switch, discrete capacitance values ​​from C to 128C can be generated.

[0029] To compensate for the discontinuity caused by discretization, a parallel variable capacitor (Cvar) is built into both the first programmable capacitor array (131) and the second programmable capacitor array (141). The variable capacitor is a voltage-controlled MOS capacitor, and the connection and disconnection of the variable capacitor are controlled by a MOS switch (S0). The capacitance value of the variable capacitor changes with the input voltage.

[0030] The combination of a fixed capacitor array and a variable capacitor allows the first programmable capacitor array (131) and the second programmable capacitor array (141) to achieve a continuous change in capacitance value from a base capacitance value to a preset upper limit capacitance value (e.g., from the base capacitance value C to 128C). The capacitance values ​​of the first programmable capacitor array (131) and the second programmable capacitor array (141) remain consistent, and the total capacitance is denoted as [missing value]. C t .

[0031] The working principle of the variable impedance unit is explained below. Taking the first variable impedance unit (130) as an example, its working principle is explained as follows: Modeling the PMOS as a first-order model, with the transconductance / amplification factor of the MOS transistor being g, then according to circuit theory, it consists of a first PMOS, a first programmable capacitor array (131), and a first resistor (133). RThe equivalent impedance of the circuit topology constructed by 1 is Z. in : (1) Where ω = 2πf is the operating angular frequency of the differential clock signal, and f is the frequency of the differential clock signal. C t The equivalent total capacitance of the first programmable capacitor array (131) is... R for The first resistor (133) is the resistance value of the bias resistor. In actual circuits, the amplification factor g ≥ 100, and the bias resistor... R The selection of makes PMOS (132) in the on state, so the imaginary part of formula (1) is >0.

[0032] Decompose formula (1) into its real and imaginary parts: (2a) (2b) After the current signal passes through this circuit, the resulting output voltage signal will have a phase change with the input current signal. The amount of phase change (phase delay) is as follows. Determined by the phase angle of the impedance: (2c) In formula (2b) X in and R in Substituting into formula (2c) yields: (2d) To achieve a fixed phase delay, it is necessary to... X in / R in The ratio is a constant.

[0033] When the aforementioned controllable phase delay circuit (100) generates a preset phase delay degree At 45°, X in / R in If the ratio is 1, then the formula can be obtained: (2e) The left side of equation (2e) is the operating angular frequency of the differential clock signal. oh Equivalent total capacitance of programmable capacitor array C t The product of these factors is directly related to the circuit's reactance. The right side only depends on the circuit's fixed parameters: the amplification factor is g, and the bias resistor. RThe value of ω is related to the value of ω, which is a constant. Therefore, for a specific angular frequency ω, only the equivalent total capacitance of the programmable capacitor array needs to be adjusted. C t If the value satisfies formula (2e), a phase delay of 45° can be generated.

[0034] Based on formula (2d), for any target phase The required solution can be obtained through this equation. C t Value. Therefore, it can be seen that the total capacitance of the programmable capacitor array can be adjusted by programming the opening and closing of the MOS switches in the programmable capacitor array. C t This allows for a wide range of adjustment of the phase delay of the differential clock signal.

[0035] This application addresses the shortcomings of traditional delay circuits, such as narrow adjustable range, small single-stage delay, the need for multiple stages in series, and inability to adapt to multi-frequency clock signals. It proposes a controllable delay circuit solution. This solution optimizes the CML differential circuit structure, designs a symmetrical variable impedance unit, and employs a combination of capacitor array and voltage-controlled variable capacitor to achieve continuous programmable capacitor control. Using this controllable delay circuit, a single stage can achieve a large-angle phase delay without the need for multiple stages in series. It offers a wide delay adjustment range and is adaptable to high-speed differential clock circuits with multiple rates and frequencies.

[0036] like Figure 2 This is a schematic diagram of a controllable phase delay circuit structure provided in an embodiment of this application. N1, N2, and N3 are all NMOS transistors, which are components of the CML differential circuit. N3 acts as a constant current source; when the bias voltage Vbias is constant, the total pull-down current remains unchanged. The CLK_P / CLK_N terminals of the clock signal are connected to the gate (G) terminals of N1 and N2, respectively. When the differential clock signal changes, current signals are generated at the drain (D) terminals of N1 and N2, respectively.

[0037] like Figure 2In the example, the pull-down resistors of the CML differential circuit are replaced with variable impedance units (130, 140). The first variable impedance unit (130) consists of a first PMOS transistor (P1), a first bias resistor (R1), and a first programmable capacitor array (131). The first programmable capacitor array (131) contains parallel capacitors C1, C2, ..., 64C and a first variable capacitor (Cvar1). The second variable impedance unit (140) consists of a second PMOS transistor (P2), a second bias resistor (R2), and a second programmable capacitor array (141). The second programmable capacitor array (141) contains parallel capacitors C1, C2, ..., 64C and a second variable capacitor (Cvar2). The variable capacitors (Cvar1, Cvar2) are controlled by the input voltage, and their capacitance values ​​change with the input voltage, with the capacitance value ranging from 0 to C.

[0038] The programmable capacitor arrays (131 and 141) configure the MOSFET switches in a single initial phase and do not dynamically modify them during operation. The combination of a fixed capacitor array and a variable capacitor allows the programmable capacitor arrays (131 and 141) to generate capacitance values ​​that continuously vary from C to 128C. In multi-protocol, multi-rate communication circuits, high-speed frequencies are often divided to obtain lower-speed communication. In this case, the total capacitance of the programmable capacitor array can be programmed to jump from a smaller value to a preset multiple (e.g., 2 times), thus maintaining the fixed phase delay of the original differential clock signal.

[0039] Example 2 Figure 3 One embodiment of this application provides a differential clock signal sinusoidalization circuit (300) for preparing for subsequent precise phase interpolation. The sinusoidalization circuit (300) consists of several delay units (320) and several low-current clock CML differential circuits (310). The delay units (320) can be implemented using conventional CML differential circuits.

[0040] The structure of the low-current clock CML differential circuit (310) is as follows: The positive input (CLK_P) and negative input (CLK_N) of the differential clock input signal are connected to the gate (G) terminals of the fourth NMOS (N4) and the fifth NMOS (N5) respectively. The source (S) terminals of the fourth and fifth NMOS are connected to the drain (D) terminal of the sixth NMOS (N6). The gate (G) terminal of the sixth NMOS is connected to a fixed bias voltage (Vbias), and its source (S) terminal is grounded. The sixth NMOS is used as a constant current source for the CML differential circuit. The drain (D) terminals of the fourth and fifth NMOS are connected to the third pull-down resistor (R3) and the fourth pull-down resistor (R4) of the CML differential circuit respectively. The negative phase (CLKOUT_N) and positive phase (CLKOUT_P) of the differential clock output signal are respectively led out from the D terminals of the fourth and fifth NMOS; each small current clock CML differential circuit (310) outputs a differential clock signal with the same frequency as the differential clock input signal (CLK_P, CLK_N), but its current amplitude is only one-Nth of the original signal, where N is the number of small current clock CML differential circuits (310) in the sinusoidal circuit (300), such as Figure 3 In the example, N is 6. In specific application scenarios, the value of N can be selected and determined according to actual needs.

[0041] The sinusoidal circuit (300) is implemented by delaying and superimposing N small-current differential clock signals, resulting in a differential clock signal with an amplitude identical to the original input differential clock signal. (Reference) Figure 3 For example, the differential clock input signal of the small current clock CML differential circuit (310) is delayed by a delay unit (320) for each stage or every two stages, for example, by 0.25T0 for each stage, where T0 is the duration of one symbol of the original clock signal. Figure 4 Figure (a) shows the waveforms of the differential clock input signals (CLK_P, CLK_N). By applying a delay to the differential clock input signals, without adding a small-capacity capacitor (Cvar) for high-frequency filtering in the low-current clock CML differential circuit (310), the waveforms of the positive phase (CLKOUT_P) and negative phase (CLKOUT_N) of the output differential clock signal are similar to the sawtooth waveforms of a sine wave, such as... Figure 4 As shown in (b).

[0042] In this embodiment, a small capacitor (Cvar3) is connected between the positive phase input (CLKOUT_P) and the negative phase input (CLKOUT_N) of the differential clock output signal for high-frequency filtering. This makes the differential clock output signal smoother, thus smoothing the stepped rising and falling edges, approximating a sinusoidal curve, thereby achieving sinusoidal output of the differential clock signal. Figure 4Example (c) shows the effect of sinusoidalization. The purpose of sinusoidalization is to improve the accuracy of phase interpolation, so that the phase interpolation circuit can still function properly under conditions of large phase errors.

[0043] In summary, square wave clock signals have steep edges, resulting in low phase interpolation accuracy. When the error is large, the interpolation circuit cannot function properly. To address this issue, this application proposes the aforementioned sinusoidalization circuit. By superimposing multiple small-current differential signals with delays and using a high-frequency filter capacitor, the square wave differential clock signal is sinusoidally processed. This sinusoidal processing optimizes the clock waveform, reduces the difficulty of phase interpolation, and thus significantly improves phase interpolation accuracy and broadens the fault tolerance range of the interpolation circuit.

[0044] Example 3 Figure 5 This is a schematic diagram of the phase interpolation circuit used in one embodiment of this application. The function of the phase interpolation circuit (500) is to superimpose two differential clock signals with different phases according to current weights to synthesize a differential clock signal with an intermediate phase. The phase interpolation circuit (500) is a CML structure current-type phase interpolation circuit, which adopts a structure of two CML differential circuits connected in parallel and sharing a load. The left differential pair includes the seventh NMOS (N7), the eighth NMOS (N8), and the ninth NMOS (N9). The differential clock input signal of the left differential pair is (CLK_P1 / CLK_N1), and N9 serves as the tail current source. The right differential pair includes the tenth NMOS (N10), the eleventh NMOS (N11), and the twelfth NMOS (N12). The differential clock input signal of the right differential pair is (CLK_P2 / CLK_N2), and N12 serves as the tail current source. The left and right differential circuits share a pair of load resistors, namely the fifth resistor (R5) and the sixth resistor (R6), and share a power supply VDD. The phase interpolation circuit (500) outputs differential clock signals (CLKOUT_P / CLKOUT_N). The phase interpolation circuit (500) is a fixed-ratio phase interpolation circuit. The current ratio of the input differential clock signal is controlled by constant current sources N9 and N12 respectively. The corresponding current ratio can be obtained by changing the first bias voltage (V_bias1) and the second bias voltage (V_bias2) of the constant current sources of the left and right differential pairs.

[0045] like Figure 5 For example, if the phase of the left-side differential clock input signal (CLK_P1 / CLK_N1) is... 1. The phase of the right-side differential clock input signal (CLK_P2 / CLK_N2) is... 2, 2 and 1. There is a fixed angular difference (e.g., typically 90° or 180°). Tail current of the left path: I1 = x·I0, tail current of the right path: I2 = (M - x)·I0, total tail current: I total = M·I0 (constant, ensuring stable common - mode output). By controlling the value of x to vary within the preset natural number range, the ratio of the two currents can be changed. Taking the Figure 5 value of M as 4 in as an example, when M = 4, it means the tail current is divided into 4 parts: 2 When x = 0: I1 = 0, I2 = 4I0 → The output is completely determined by the right - hand signal, phase = 1 When x = 4: I1 = 4I0, I2 = 0 → The output is completely determined by the left - hand signal, phase = 1 2. When 0 < x < 4: I1 = xI0, I2 = (M - x)I0, both signals act simultaneously, and the output phase is between 1 and

[0046] 2, thus realizing interpolation of the differential clock signal. The resolution of phase interpolation is:

[0047] Example 4 Based on the foregoing embodiments, it can be seen that using the controllable phase - delay circuit (100) proposed in this application can achieve the preset degree of phase delay of the input differential clock signal. However, in actual situations, due to the process deviation in chip manufacturing, voltage noise used, and environmental temperature (Process, Voltage, Temperature, PVT) factors, the actual phase delay of the phase - delay circuit is + Dth , where Dth is the phase error caused by PVT factors. If multiple - stage cascading is used, the phase difference of the differential clock signal (CLK_P, CLK_N) output after passing through multiple - stage phase - delay circuits for the initially input differential clock signal is successively + Dth , 2 + 2 Dth3 +3 Dth ..., each phase delay circuit generates a relationship between its input and output. + Dth The phase difference is such that traditional phase delay circuits cannot eliminate the phase error. Dth .

[0048] To improve the phase delay accuracy of phase delay circuits, this application creatively proposes a new design scheme for a high-precision multi-stage phase delay system. This scheme is based on a multi-stage controllable phase delay circuit (100) and utilizes a phase interpolation circuit (500) to essentially eliminate the phase error caused by PVT factors in the phase delay circuit, thereby eliminating the phase error that traditional phase delay circuits cannot eliminate. D θ.

[0049] Figure 6 This is a schematic diagram of the basic structure of a high-precision multi-stage phase delay system provided in one embodiment of this application. In the high-precision multi-stage phase delay system (600) provided in this embodiment, the input differential clock signals (CLK_P, CLK_N) should ideally be delayed by exactly 180° (m) after passing through an m-stage controllable phase delay circuit (100). =180°, where (This refers to the phase delay generated by a single-stage controllable phase delay circuit.) Due to phase errors caused by PVT factors, the actual delay is 180°+m. Dth ,like Figure 6 Example of phase at phase 1 and phase (m+1) positions. This embodiment uses a phase interpolation circuit (500) to invert the phase difference between two differential clock signals with an m-stage phase delay and sinusoidal processing. The phase difference between the differential clock signals (such as CLKOUT_P and CLKOUT_N of phase 1' and phase 2') output by two adjacent phase interpolation circuits (such as 500-1 and 500-2) is... Compared to Figure 6 The phase difference between the input and output positions (such as phase 1 and phase 2) of the top single-stage controllable phase delay circuit (100) is... + Dth It can be seen that the phase error caused by the PVT factor is eliminated in the two adjacent differential clock signals output after processing by the high-precision multi-stage phase delay system (600) provided in this application. Dth This greatly improves the phase delay accuracy.

[0050] The high-precision multi-stage phase delay system (600) provided in this embodiment includes: At least m+1 stages of controllable phase delay circuits (e.g., 100-1, ..., 100-m, 100-(m+1)) are used to cascade the phase delay of the input differential clock signals (CLK_P, CLK_N), with each stage having a phase delay of... The phase error caused by the PVT factor is Dth ; m is a preset series, and the value of m is related to the phase delay. Correlation equals 180° with phase delay The quotient. For example, when the phase delay degree... When the angle is 45°, then m = 180° / 45° = 4; when the phase delay is in degrees... When the angle is 22.5°, then m = 180° / 22.5° = 8. For example... Figure 6 For example, the phase of the P terminal of the differential clock signal at phase 1 is 0. 0 The phase of the differential clock signal at the P terminal at phase m+1 after stage m is m. +m Dth , where m =180°.

[0051] At least m+2 stages of sinusoidalization circuitry (300) are used to sinusoidalize the differential clock signal of each stage; At least two phase interpolation circuits (500) are used to perform inverted phase difference processing on the differential clock signals output by the i-th and i+m-th stage sinusoidal circuits (300) to output differential clock signals (CLKOUT_P, CLKOUT_N); where i is an integer greater than or equal to 0; the inverted phase difference processing refers to: performing phase interpolation between the positive phase P terminal signal of the i-th stage sinusoidal differential clock signal and the negative phase N terminal signal of the (i+m)-th stage sinusoidal differential clock signal, and performing phase interpolation between the negative phase N terminal signal of the i-th stage sinusoidal differential clock signal and the positive phase P terminal signal of the (i+m)-th stage sinusoidal differential clock signal.

[0052] In one embodiment of this application, in order to improve the noise immunity in the high-speed interface of SerDes (Serializer / Deserializer), a CML differential circuit (601) is connected to the input terminals (CLK_P, CLK_N) of the high-precision multi-stage phase delay system (600), and a CML differential circuit (602, 603) is also connected to each output terminal (CLKOUT_P, CLKOUT_N).

[0053] In summary, due to phase errors caused by PVT, the errors accumulate stage by stage in a series of multi-stage controllable phase delay circuits, significantly reducing clock phase accuracy. This application creatively proposes a solution to eliminate phase errors by using cascaded delay circuits combined with a sinusoidal circuit and employing a cross-stage inverting interpolation architecture to cancel out the errors, thereby completely eliminating phase errors caused by PVT, eliminating the problem of error accumulation, and significantly improving the phase output accuracy of multi-stage delay circuits.

[0054] Example 5 Figure 7 This is a schematic diagram of the high-precision multi-stage phase delay system provided in one embodiment of this application. This embodiment uses at least seven stages of controllable phase delay circuits with identical configurations (100-1, 100-2, ..., 100-7). Each stage of the controllable phase delay circuit achieves a 45° phase delay, and the phase error caused by the PVT factor of each stage of the controllable phase delay circuit is... Dth Starting from stage 0, each stage of the controllable phase delay circuit has a sinusoidal circuit (300-1, 300-2, ..., 300-8) connected to both its input and output. The output signal of the sinusoidal circuit is provided to the phase interpolation circuit (500-1, 500-2, 500-3, 500-4). The differential clock signal output from the phase interpolation circuit is split into two paths: one is connected to a positive-phase CML differential circuit, and the other is connected to a CML differential inverting circuit. The two paths are 180° out of phase, thus forming a high-precision multi-stage phase delay system consisting of 7 stages of controllable phase delay circuits, 8 stages of sinusoidal circuits, and 4 stages of phase interpolation circuits. This system can achieve a high-precision multi-stage phase delay from one input differential clock signal (CLK_P, CLK_N) to 8 output differential clock signals (such as the output signals of phase 1', phase 2', ..., phase 8'). Compare the phase difference (45°+) of each stage at phase 1, phase 2, ..., phase 8. Dth The phase difference (45°) at each stage at positions 1', 2', ..., 8' shows that the circuit has the technical advantages of wide-range adjustable phase delay (using controllable phase delay unit), high precision (basically eliminating phase error caused by PVT factor), and support for multi-rate, multi-frequency differential clock signal output.

[0055] In this embodiment, the two differential clock signals, each with an interval of m=4 stages, are sinusoidally processed by a sinusoidal circuit, and then one signal is in positive phase and the other in negative phase. These signals are then fed into a phase interpolation circuit for phase difference calculation. Specifically, the positive P-terminal signal of the i-th stage controllable phase delay circuit is interpolated with the negative N-terminal signal of the (i+m)-th stage controllable phase delay circuit to obtain the result after removing phase errors. DthThe new positive-phase P-terminal signal is obtained; similarly, the negative-phase N-terminal signal of the i-th stage controllable phase delay circuit and the positive-phase P-terminal signal of the (i+m)-th stage controllable phase delay circuit are interpolated to obtain the signal after removing the phase error. Dth The new negative phase N-terminal signal. Where i is an integer greater than or equal to 0, m is the minimum preset level, m=180° / 45°=4.

[0056] refer to Figure 7 Examples of commonly used phase interpolation results are listed below: The initial differential clock signal (stage 0 at phase 1) negative N-terminal signal is interpolated with the P signal output from the 4th stage controllable phase delay circuit (stage 5 of 100-4). The interpolation current ratio is 0:4, and the result is: (4a) The N signal output from the first-stage controllable phase delay circuit (100-1 phase 2) is interpolated with the P signal output from the fifth-stage controllable phase delay circuit (100-5 phase 6). The interpolation current ratio is 1:3, and the result is: (4b) In (4b), the calculation process neglected to include Dth The second-order small quantity, Dth When it is smaller, cos( Dth It is close to 1.

[0057] The N signal output from the second-stage controllable phase delay circuit (100-2 phase 3) is interpolated with the P signal output from the sixth-stage controllable phase delay circuit (100-6 phase 7). The interpolation current ratio is 1:1, and the result is: (4c) In the calculation of (4c), the following was ignored: Dth The second-order minor quantity.

[0058] The N signal output from the third-stage controllable phase delay circuit (100-3 phase 4) is interpolated with the P signal output from the seventh-stage controllable phase delay circuit (100-7 phase 8). The interpolation current ratio is 3:1, and the result is: (4d) In the calculation of (4d), the following was ignored: Dth The second-order small quantity, Dth When it is smaller, cos( D θ) is close to 1.

[0059] Comparing (4a), (4b), (4c), and (4d), the interpolated results show a phase difference of 45° between adjacent phases. Compared to the phase output directly using the controllable phase delay circuit, the phase error term has been eliminated. Dth .

[0060] Although in (4b) and (4d), the phase error Dth cos( Dth The amplitude is transferred to the form of I. Since subsequent circuits still need to pass through a CML differential circuit or a CML differential inverting circuit, and the CML differential circuit itself has the function of limiting and amplifying the amplitude of the input signal, the amplitude will recover to I after passing through the subsequent CML differential circuit. clk It will not affect subsequent circuits.

[0061] This embodiment integrates all the core circuits proposed in this application, adopts 4-stage cross-stage inverting interpolation, and is equipped with CML limiting circuit to optimize output, stably outputting 8 error-free differential clock signals with precise and controllable phase spacing, taking into account adjustability, high precision and multi-frequency adaptability, and adapting to commercial scenarios of SerDes high-speed interface.

[0062] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A controllable phase delay circuit, characterized in that, include: A first differential branch, a second differential branch, and a constant current source unit are symmetrically arranged; the first differential branch includes a first NMOS transistor and a first variable impedance unit, and the second differential branch includes a second NMOS transistor and a second variable impedance unit. The gates of the first NMOS transistor and the second NMOS transistor are respectively connected to the positive and negative inputs of the differential clock signal; the constant current source unit is a third NMOS transistor, the drain of the third NMOS transistor is connected to the source of the first NMOS transistor and the second NMOS transistor, the source of the third NMOS transistor is grounded, and the gate is connected to a constant bias voltage; The first and second variable impedance units have the same structure and are both connected between the drain of the corresponding NMOS transistor and the positive power supply; the variable impedance unit includes a PMOS transistor, a bias resistor, and a programmable capacitor array. The programmable capacitor array consists of a fixed capacitor bank and a voltage-controlled variable capacitor connected in parallel, with each fixed capacitor connected in series with an independent MOS switch; the voltage-controlled variable capacitor is equipped with an on / off control switch to achieve continuous adjustment of the capacitance value.

2. The controllable phase delay circuit according to claim 1, characterized in that: In the variable impedance unit, the source of the PMOS transistor is connected to the positive power supply, and the drain is connected to the drain of the corresponding NMOS transistor; a programmable capacitor array is connected between the source and gate of the PMOS transistor, and a bias resistor is connected between the gate and drain of the PMOS transistor.

3. The controllable phase delay circuit according to claim 1, characterized in that: The fixed capacitor bank starts with the basic capacitance value C as the first term, and forms a geometric sequence with a common ratio of 2 starting from the second term; The programmable capacitor array has a capacitance adjustment range of C to 128C, and the real-time capacitance values ​​of the two programmable capacitor arrays remain consistent; the capacitance value of the voltage-controlled variable capacitor changes from approximately 0 to C.

4. A multi-stage phase delay system, characterized in that, The controllable phase delay circuit according to claim 1 includes: a multi-stage controllable phase delay circuit, a multi-stage sinusoidalization circuit, and at least two stages of phase interpolation circuit. The multi-stage controllable phase delay circuits are cascaded to delay the input differential clock signal step by step. A single-stage controllable phase delay circuit has a phase error caused by a fixed ideal delay angle and process voltage and temperature PVT factors. The sinusoidal circuit is connected to the output of the controllable phase delay circuit in a one-to-one correspondence, and is used to convert the square wave clock signal into a sinusoidal waveform. The phase interpolation circuit is connected to the output terminals of two sinusoidal circuits with an interval of m, where m = 180° / ideal delay angle of a single stage; the phase interpolation circuit adopts an inverse interpolation method to eliminate PVT phase error and output a high-precision differential clock signal.

5. The multi-stage phase delay system according to claim 4, characterized in that: The sinusoidal circuit includes several delay units and several small-current clock CML differential circuits; the delay units adopt traditional CML differential circuits to apply a fixed-duration delay to the clock signal; the multiple small-current differential signals are superimposed after delay to form a sinusoidal waveform.

6. The multi-stage phase delay system according to claim 5, characterized in that: The number of parallel small-current clock CML differential circuits inside the sinusoidal circuit is N, and the output current amplitude of a single circuit is one-Nth of the original signal; a high-frequency filter capacitor is connected to the output terminal of the sinusoidal circuit to filter out high-frequency noise in the waveform.

7. The multi-stage phase delay system according to claim 4, characterized in that: The phase interpolation circuit is a CML current-type parallel architecture, which includes two differential pairs and a common load resistor. The two differential pairs are respectively connected to sinusoidal clock signals of different phases, and the intermediate phase signal is synthesized by adjusting the tail current weight.

8. The multi-stage phase delay system according to claim 7, characterized in that: The total tail current of the phase interpolation circuit is constant, with the left tail current I1=xI0 and the right tail current I2=(Mx)I0; by adjusting the bias voltage to change the value of x, proportional interpolation in the range of 0~M can be achieved.

9. The multi-stage phase delay system according to claim 4, characterized in that: A CML differential circuit is added to the system input terminal and each signal output terminal; the CML differential circuit includes a positive phase circuit and an inverting phase circuit.

10. The multi-stage phase delay system according to claim 4, characterized in that: The ideal delay angle of the single-stage controllable phase delay circuit is 45°, and the preset number of stages is m=4. The system includes 7-stage controllable phase delay circuits, 8-stage sine wave circuits, and 4-stage phase interpolation circuits, realizing single-channel input and 8-channel high-precision differential clock output.

11. A chip, characterized in that, The chip integrates the controllable phase delay circuit as described in claim 1 or the multi-stage phase delay system as described in claim 4.

12. A computer device, characterized in that, The device uses the chip described in claim 11.

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