System on chip and method of debugging a system on chip

Abstract

A system on chip (SoC) includes a plurality of blocks each including an input terminal and an output terminal and each including a plurality of synchronous circuits connected by a scan chain, a test data input (TDI) line, a test data output (TDO) line connected to the output terminal, a test access port (TAP) controller that controls operations of the blocks based on a TDI signal, a TDO signal, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal, a power management unit that controls power gating of the blocks, and a clock management unit that controls a clock signal supplied to the blocks. The TAP controller includes a first register that stores first data used to generate a first control signal that controls the power and clock management unit, the power and clock management unit controlling operations of the blocks based on the first control signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0174728, filed on November 29, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The example embodiments relate to a system-on-a-chip and a debugging method for a system-on-a-chip. Background Technology

[0004] JTAG is an industry standard established by the Joint Test Action Group for testing printed circuit boards (PCBs) and integrated circuit chips (IC chips), and is codified in IEEE Standard 1149.1. The scan dump method can perform debugging on-chip systems by repeating the same sequence while testing the same scenario after removing values ​​loaded into the scan chain. Summary of the Invention

[0005] Example embodiments of this disclosure provide a system-on-a-chip that can perform debugging via a scan dump method without adding pads.

[0006] Example embodiments of this disclosure relate to a debugging method for a system-on-a-chip (SoC) that enables debugging via a scan dump method without adding pads.

[0007] According to some example embodiments of this disclosure, the system-on-chip includes multiple blocks, each including input terminals and output terminals and each including multiple synchronous circuits connected by a scan chain; a test data input (TDI) line; a test data output (TDO) line connected to the output terminals; a test access port (TAP) controller configured to control the operation of the multiple blocks based on a TDI signal input to the TDI line, a TDO signal input to the TDO line, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal; a power management unit configured to control the power gating of the multiple blocks; and a clock management unit configured to control clock signals provided to the multiple blocks. The TAP controller includes a first register configured to store first data for generating a first control signal configured to control the power management unit and the clock management unit, and the power management unit and the clock management unit configured to control the operation of the multiple blocks based on the first control signal received from the TAP controller.

[0008] According to some example embodiments of this disclosure, the system-on-chip includes multiple blocks, each including input terminals and output terminals and each including multiple synchronous circuits connected by a scan chain, a power management unit, a clock management unit, and a test access port (TAP) controller. The power management unit is configured to control power gating for the multiple blocks, the clock management unit is configured to control clock signals supplied to the multiple blocks, and the test access port (TAP) controller is configured to control the operation of the multiple blocks based on a test data input (TDI) signal synchronized with a test clock (TCK) signal and a test mode select (TMS) signal. The TAP controller includes a first register configured to store first data for controlling the power management unit and the clock management unit. The TAP controller is configured to generate a first control signal for controlling the power management unit and the clock management unit based on the TMS signal and the first data. The power management unit is configured to turn on the power supplied to the multiple blocks based on the first control signal, and the clock management unit is configured to stop the clock signal supplied to the multiple blocks based on the first control signal.

[0009] According to some example embodiments of this disclosure, a debugging method for a system-on-a-chip includes multiple blocks, each including input terminals and output terminals and each including multiple synchronous circuits connected by a scan chain. The debugging method includes receiving a debug request signal by a Test Access Port (TAP) controller; the TAP controller sending a first control signal generated based on a Test Mode Select (TMS) signal and first data to a power management unit and a clock management unit based on the debug request signal; the power management unit turning on power supplied to the multiple blocks based on the first control signal; and the clock management unit stopping all clock signals supplied to the multiple blocks based on the first control signal. The TAP controller includes a first register storing first data for controlling the power management unit and the clock management unit.

[0010] According to some example embodiments, a system-on-a-chip includes: a plurality of blocks, each including input terminals and output terminals and each including a plurality of synchronization circuits connected by a scan chain; an active block configured to control the operation of the plurality of blocks; the active block including a power management unit configured to control power gating of the plurality of blocks; a clock management unit configured to control clock signals provided to the plurality of blocks; a test mode block including a latch circuit configured to receive a test mode enable signal from a first pad; a selection circuit configured to receive a test reset signal from a second pad and provide an output to the latch circuit; and a Joint Test Action Group (JTAG) port configured to control the operation of the active block based on a test data input (TDI) signal synchronized with a test clock (TCK) signal and a test mode select (TMS) signal; and including a first register configured to store first data for generating a first control signal for controlling the power management unit and the clock management unit. The power management unit and the clock management unit are configured to control the operation of the plurality of blocks based on the first control signal received from the JTAG port. According to some example embodiments, the JTAG port further includes a second register configured to store second data different from the first data. The JTAG port is configured to generate a second control signal for controlling the operation of multiple blocks based on the TDI signal and the second data, and the JTAG port is configured to select a target block from the multiple blocks based on the second control signal to perform a scan-dump method. According to some example embodiments, the JTAG port further includes a third register configured to store third data different from each of the first and second data. The JTAG port is configured to generate a third control signal for controlling the operation of multiple blocks based on the third data, and the JTAG port is configured to send a scan-dump enable signal to the multiple blocks based on the third control signal to set the multiple blocks to scan-dump mode. According to some example embodiments, the JTAG port is configured to shift out values ​​loaded into the scan chain of the target block based on a scan dump enable signal. The JTAG port also includes a fourth register storing fourth data that is different from each of the first, second, and third data. The JTAG port is configured to generate a fourth control signal for controlling the operation of the target block based on the fourth data, and the JTAG port is configured to output the values ​​shifted out from the scan chain of the target block through the output terminal of the target block based on the fourth control signal.

[0011] According to some example embodiments, the electronic system includes a processor and a computer-readable storage medium communicatively coupled to the processor. The processor is implemented as a system-on-a-chip and includes multiple blocks, each including input terminals and output terminals and each including multiple synchronous circuits connected via a scan chain; a test data input (TDI) line; a test data output (TDO) line connected to the output terminals; a test access port (TAP) controller configured to control the operation of the multiple blocks based on a TDI signal input to the TDI line, a TDO signal input to the TDO line, a test clock (TCK) signal, a test reset (TRST) signal, and a test mode select (TMS) signal; a power management unit configured to control the power gating of the multiple blocks; and a clock management unit configured to control clock signals provided to the multiple blocks. The TAP controller includes a first register configured to store first data for generating a first control signal. The first control signal is configured to control the power management unit and the clock management unit. The power management unit and the clock management unit are configured to control the operation of the multiple blocks based on the first control signal received from the TAP controller.

[0012] The purposes of this disclosure are not limited to those mentioned above, and those skilled in the art will clearly understand from the following description of this disclosure any additional purposes not mentioned herein. Attached Figure Description

[0013] The above and other aspects and features of this disclosure will become clearer from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0014] Figure 1 This is a schematic block diagram showing a JTAG cell with a scan chain.

[0015] Figure 2 This is a diagram illustrating a system-on-a-chip according to some example embodiments.

[0016] Figure 3 This illustrates some example embodiments. Figure 2 A diagram of the instruction register of the system-on-a-chip.

[0017] Figure 4 This illustrates some example embodiments. Figure 2 A diagram of the instruction register set of the system-on-a-chip.

[0018] Figure 5 This illustrates output from the JTAG interface according to some example embodiments. Figure 2 A graph showing the values ​​of the scan chain removed from the target block of the on-chip system.

[0019] Figure 6 This illustrates some example embodiments. Figure 2A diagram of the JTAG port.

[0020] Figure 7 This is a flowchart illustrating a debugging method for a system-on-a-chip according to some example embodiments.

[0021] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 This illustrates a method for using, according to some example embodiments. Figure 7 A diagram illustrating the debugging method for a system-on-a-chip.

[0022] Figure 14 This is a diagram illustrating an electronic system including a system-on-a-chip according to some example embodiments.

[0023] Figure 15 This is a diagram illustrating an electronic system including a system-on-a-chip according to some example embodiments. Detailed Implementation

[0024] As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of…” modify the entire list of elements when following it and do not modify individual elements of the list. For example, “at least one of A, B, and C” and similar language (e.g., from “at least one selected from the group consisting of A, B, and C”, “at least one of A, B, or C”) can be interpreted as only A, only B, only C, or any combination of two or more of A, B, and C, such as ABC, AB, BC, and AC.

[0025] As described herein, when an operation is described as to be performed, or when an effect such as a structure is described as being established “by” or “through” the performance of additional operations, it should be understood that the operation and / or the effect / structure can be performed “based on” the additional operations, which may include performing the additional operations alone or in combination with other further additional operations.

[0026] In the following description, a system-on-a-chip and a debugging method for the system-on-a-chip according to some example embodiments will be described with reference to the accompanying drawings.

[0027] Figure 1 This is a schematic block diagram showing a JTAG unit 10 with a scan chain.

[0028] refer to Figure 1JTAG unit 10 may include scan chain 12, and boundary scan unit (BSC) 14 is connected to scan chain 12. Test data input (TDI) signals can be input to boundary scan unit 14 to perform operations on the system-on-chip 100 including JTAG unit 10 (see [link to relevant documentation]). Figure 2 The test.

[0029] The test clock (TCK) signal and test mode select (TMS) signal can be used to control JTAG unit 10. The TCK and TMS signals can be input to the test access port (TAP) controller 170 (see [link to controller 10]). Figure 2 This controls the operation of JTAG unit 10. After completing the operation of JTAG unit 10, the system-on-chip 100 can output the result of the operation as a Test Data Output (TDO) signal. In some example embodiments, the TMS signal and TDI signal can be synchronized with the TCK signal.

[0030] For the purposes of discussion, "signal" can refer to a digital signal that may include one or more bits, or it can refer to data.

[0031] Such a JTAG unit 10 can be embedded in many types of integrated circuit chips and systems-on-a-chip. For example, the JTAG unit 10 can be embedded in microprocessors, microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs). However, current JTAG units are standard not only for testing the internal workings of a chip but also for programming the flash memory within the chip. For example, JTAG units are used for FPGA image rendering, etc.

[0032] Figure 2 This is a diagram illustrating a system-on-chip 100 according to some example embodiments.

[0033] refer to Figure 2 The system-on-chip 100 may include multiple blocks BLK1 to BLK(n) labeled 110-1 to 110-n, a JTAG interface 180, a JTAG port 140, a power management unit 120, and a clock management unit 130.

[0034] The multiple blocks 110-1 to 110-n can be functional blocks of an on-chip system (where "n" is an integer of 2 or greater). Each of the multiple blocks 110-1 to 110-n can be on-chip logic to be tested for debugging and can be referred to as core logic or unit under test.

[0035] For the sake of brevity, block 110-1 will be described below, and the description of block 110-1 also applies to blocks 110-2 through 110-n.

[0036] Block 110-1 may include an input terminal IT and an output terminal OT, and may include multiple synchronous circuits 101-1 to 101-m (where “m” is an integer of 2 or greater) connected by a scan chain.

[0037] Each of the sequentially connected synchronous circuits 101-1 to 101-m can be, for example, a scan flip-flop. The output terminal of the current (or given) scan flip-flop can be connected to the input terminal of the next (or subsequent) scan flip-flop. The current scan flip-flop can transfer the stored value to the next flip-flop based on the TCK and TMS signals in scan test mode and / or scan dump mode. Each scan flip-flop includes input and output terminals, and combinational logic can be included between the output terminal of the current scan flip-flop and the input terminal of the next scan flip-flop.

[0038] Each of the multiple synchronization circuits 101-1 to 101-m can be a digital circuit that can operate synchronously with the TCK signal, and can be implemented as a flip-flop or a scan flip-flop. For example, each of the multiple synchronization circuits 101-1 to 101-m can operate based on the TCK signal and the TMS signal.

[0039] Figure 1 JTAG unit 10 can correspond to Figure 2 One of the multiple blocks 110-1 to 110-n, and Figure 1 Each of the boundary scan units 14 can correspond to Figure 2 Each of the synchronization circuits 101-1 to 101-m.

[0040] JTAG interface 180 is a special 4-pin or 5-pin interface added to system-on-chip 100. JTAG interface 180 may include TDO pin 185, TCK pin 182, TDI pin 181 and TMS pin 183, and may optionally further include test reset (TRST) pin 184.

[0041] The pins 181 to 185 of the JTAG interface 180 and the signals input and output through pins 181 to 185 will be understood with reference to the Institute of Electrical and Electronics Engineers (IEEE) 1149.1 standard. Although the term "pin" is used in this disclosure, a pin can refer to a pad or solder ball, which can indicate an external interface of the chip.

[0042] JTAG port 140 may include TAP controller 170, instruction register 150, and data register 160. JTAG port 140 is an IEEE 1149.1 standard JTAG port. For each rising edge of the TCK signal, one bit of data sent from TDI pin 181 can be serially written through JTAG port 140 into multiple synchronization circuits 101-1 to 101-m connected by a scan chain. Furthermore, for each rising edge of the TCK signal, one bit of data serially read from the multiple synchronization circuits 101-1 to 101-m connected by a scan chain can be output through JTAG port 140 to TDO pin 185.

[0043] The TAP controller 170 can control the operation of each of the multiple blocks 110-1 by using the TDO signal, TCK signal, TDI signal, TRST signal, and TMS signal.

[0044] Each module within the system-on-a-chip 100 may expose or include a Test Access Port (TAP). Therefore, the response server 300 can manipulate, modify, or control the TMS, TDI, and TCK signals via JTAG port 140, and can read the result value via TDO pin 185 to perform communication with the TAP. In some example embodiments, the response server 300 may be the host of the system-on-a-chip 100.

[0045] Each JTAG port 140 may include a single instruction register 150 and multiple data registers 160. The number of bits in the data registers 160 may vary for each JTAG port 140. The data registers 160 may be combined with the TDI and TDO signals to form a shift register.

[0046] The input terminal IT of block 110-1 can be connected to the TDI pin 181 via the TDI line IL and the JTAG port 140, and the output terminal OT of block 110-1 can be connected to the TDO pin 185 via the TDO line OL and the JTAG port 140.

[0047] The power management unit 120 can perform power management operations on a plurality of blocks, cells, and modules included in the system-on-chip 100. In some example embodiments, power management operations may refer to operations that control the power supply to a specific or given circuit or device. For example, the power management unit 120 can perform power management operations on a plurality of blocks, cells, and modules included in the system-on-chip 100 by using power gating of power transistors.

[0048] Referring to Figure 2, the system-on-chip 100 can be divided into multiple power domains PWD1 to PWD(n). For example, block BLK1 can operate in the first power domain PWD1, and blocks 110-n can operate in the power domain PWD(n). The multiple blocks 110-1 to 110-n included in the system-on-chip 100 can each correspond to a different power domain. Therefore, the power management unit 120 can individually manage the power supplied to each of the multiple blocks 110-1 to 110-n. For example, the power management unit 120 can turn on the power supply to at least one of the multiple blocks 110-1 to 110-n, turn off the power supply to other blocks, and / or reduce the power supplied to other blocks. Additionally or alternatively, the power management unit 120 may connect to power to one or more of the plurality of blocks 110-1 to 110-n, disconnect power to one or more of the plurality of blocks 110-1 to 110-n, and / or reduce the power supplied to one or more of the plurality of blocks 110-1 to 110-n.

[0049] For example, the TAP controller 170 may send a first control signal CS1, which is used to manage the power supplied to each of the plurality of blocks 110-1 to 110-n, to the power management unit 120 based on at least one of the TDO signal TDO, TCK signal TCK, TDI signal TDI, or TMS signal TMS received from the JTAG port 140, and the power management unit 120 may individually manage the power supplied to each of the plurality of power domains PWD1 to PWD(n) based on the first control signal CS1 received from the JTAG port 140.

[0050] although Figure 2 The power domain of the system-on-chip 100 is shown to comprise a single block, but the example embodiment is not limited thereto. For example, the system-on-chip 100 may further include, in addition to Figure 2 In addition to the components shown, it may include one or more other components, and may further include a power domain, which may include one or more other components. Alternatively or additionally, the power domain may include more than one block.

[0051] Clock management unit 130 can control the clock signals provided to multiple blocks 110-1 to 110-n. For example, TAP controller 170 can send a first control signal CS1 for managing the clock signals provided to each of the multiple blocks 110-1 to 110-n based on at least one of TDO signal TDO, TCK signal, TDI signal TDI, or TMS signal received from JTAG interface 180, and clock management unit 130 can individually manage the clock signals provided to each of the multiple blocks 110-1 to 110-n based on the first control signal CS1 received from JTAG port 140.

[0052] Debugger 200 can send a debug request signal DRS to JTAG port 140. The debug request signal DRS may include a TDI signal, a TCK signal, a TRST signal, and / or a TMS signal. JTAG port 140 can receive JTAG signals from debugger 200, such as TDI, TCK, TRST, and / or TMS signals. Furthermore, the TDO signal processed in JTAG port 140 can be output to debugger 200 via the TDO pin 185.

[0053] The response server 300 can be a host that allows the debugger 200 to perform debugging for the system-on-chip 100. Although Figure 2 The response server 300 is shown to be separate from the debugger 200, but in some example embodiments, the response server 300 may be included in the debugger 200.

[0054] Figure 3 It is shown Figure 2 The diagram shows the instruction register 150 of the system-on-chip. Figure 4 It is shown Figure 2 A diagram of the instruction register set of the system-on-chip. Refer to the following text. Figure 3 and Figure 4 Description includes Figure 2 The instruction register in JTAG port 140.

[0055] For ease of explanation, Figure 3 Multiple instruction registers 150-1, 150-2, 150-3, and 150-4 are shown included in JTAG port 140, but each JTAG port 140 may include, as shown in the reference... Figure 2 The single instruction register 150 is described. In the following text, it is assumed that the TESTSETUP instruction register 150-1, SELPARTITION instruction register 150-2, SCANDUMP instruction register 150-3, and TDOBYPASS instruction register 150-4 are all contained in a JTAG port 140.

[0056] Instructions for the TAP controller 170 to perform debugging on the system-on-chip 100 can be stored in each of the instruction registers 150-1, 150-2, 150-3, and 150-4 in the form of bit data (or bit pattern) in response to a debugging request from the response server 300. For example, the TAP controller 170 can determine the debugging method based on the TDO signal, TCK signal, TDI signal, and / or TMS signal (optionally, TRST signal) received from the JTAG interface 180, and can generate control signals based on the data stored in the instruction register 150 and the data register 160 according to the determined debugging method, thereby performing debugging operations on multiple blocks 110-1 to 110-n.

[0057] The TESTSETUP instruction register 150-1 can store data indicating that all clock signals supplied to multiple blocks 110-1 to 110-n are stopped and that power is fully supplied to multiple blocks 110-1 to 110-n. The TESTSETUP instruction register 150-1 can have the bit mode "10011".

[0058] The SELPARTITION instruction register 150-2 can store data indicating the selection of a target block for debugging from multiple blocks 110-1 to 110-n. The SELPARTITION instruction register 150-2 can have a bit pattern of "00011".

[0059] SCANDUMP instruction register 150-3 may store data indicating that a scan dump enable signal is sent to a plurality of blocks 110-1 to 110-n. In some example embodiments, the scan dump enable signal may be a signal for setting the plurality of blocks 110-1 to 110-n to scan dump mode. In some example embodiments, when the scan dump enable signal is applied to each of the plurality of blocks 110-1 to 110-n, values ​​loaded into the scan chain included in each of the plurality of blocks 110-1 to 110-n may be shifted out. The scan dump instruction register 150-3 may have a bit pattern of "00100".

[0060] TDOBYPASS instruction register 150-4 can store data indicating the connection of target blocks from multiple blocks 110-1 to 110-n to JTAG pads 220 (see [link]). Figure 8 When the target block and JTAG pad 220 are connected to each other via the TDOBYPASS instruction, the value shifted out of the scan chain from the target block can be output externally from the on-chip system 100 via the TDO pin 185. The TDOBYPASS instruction register 150-4 can have the bit mode "01100".

[0061] Figure 4The bit patterns of the corresponding instruction registers 150-1, 150-2, 150-3 and 150-4 shown are merely examples, and the bit patterns of the corresponding instruction registers 150-1, 150-2, 150-3 and 150-4 may vary depending on the application and / or design.

[0062] refer to Figure 3 JTAG port 140 may also include selection circuitry 190. Selection circuitry 190 can receive signals from SELPARTITION instruction register 150-2 and other instruction registers 150-1, 150-3, and 150-4, respectively, and can select one of the received signals and output the selected signal from system-on-chip 100 via TDO pin 185. Selection circuitry 190 can send data to the outside of system-on-chip 100 regarding which of the plurality of blocks 110-1 to 110-n is used as the target block to perform the current debug operation in system-on-chip 100, or regarding which instruction stored in one of instruction registers 150-1, 150-3, and 150-4 is currently being executed in system-on-chip 100.

[0063] Figure 5 This is a diagram showing the values ​​shifted out of the scan chain of the target block from the on-chip system of 2 via the JTAG interface. The following section will describe, as an example, the case where block 110-n out of multiple blocks 110-1 to 110-n is selected as the target block.

[0064] For example, the response server 300 can send a debug request signal DRS to the system-on-chip 100, allowing the debugger 200 to select block 110-n as the target block from a plurality of blocks 110-1 to 110-n included in the system-on-chip 100. The debug request signal DRS can be sent to the TAP controller 170 as a TDI signal via the TDI pin 181. The TAP controller 170 can select block 110-n as the target block based on the received TDI signal. When block 110-n is selected as the target block, the value shifted out of the scan chain of block 110-n can be output from the system-on-chip 100 to the outside via the TDO pin 185.

[0065] The data register 160 corresponding to the SELPARTITION instruction register 150-2 can store data corresponding to each of the plurality of blocks 110-1 to 110-n. For example, assuming that each of the plurality of blocks 110-1 to 110-n stores 4 bits of data and the total number of blocks included in the system-on-chip 100 is 30, the data register 160 corresponding to the SELPARTITION instruction register 150-2 can store 120 bits of data.

[0066] Figure 6 It is shown Figure 2The diagram shows JTAG port 140.

[0067] Referring to reference 6, the system-on-chip 100 may further include an activity block BLK_A. The activity block BLK_A may be a block used to control the operation of multiple blocks 110-1 to 110-n included in the system-on-chip 100. The activity block BLK_A may include a test mode block 210, a power management block 120, and / or a clock management unit 130. The test mode block 210 may include a latch circuit 211 and a selection circuit 212. A test mode enable signal TEST_EN may be input to the test mode block 210 via a first pad P1, and a test reset signal TEST_RESET may be input to a second pad P2. The test mode enable signal TEST_EN may be input to the latch circuit 211, and the test reset signal TEST_RESET may be input to the selection circuit 212. The selection circuit 212 may selectively provide the latch circuit 211 with either the test reset signal TEST_RESET or a signal "0" based on the output signal from the fourth circuit 146. The latch circuit 211 can store the test reset signal TEST_RESET or the signal "0" in response to the test mode enable signal TEST_EN. The latch circuit 211 can provide the stored signal to the JTAG interface 180. The JTAG interface 180 can provide the TMS signal, TCK signal, TDI signal, and TRST signal to the JTAG port 140 according to the signals received from the latch circuit 211.

[0068] JTAG port 140 may include TAP controller 170, first circuit 143, multiple synchronization circuits 141 and 142, second circuit 144, third circuit 145, fourth circuit 146, selection circuit 147, TESTSETUP instruction register 150-1, and data register 160 corresponding to TESTSETUP instruction register 150-1.

[0069] The first circuit 143 can be implemented as an OR gate. The first circuit 143 can receive the signal SPIDEN and the output signal of the second synchronization circuit 142. In some example embodiments, the signal SPIDEN can be a signal generated at a core site, etc., so that external users do not need to use the scan dump function via JTAG port 140. The signal output from the first circuit 143 can be input to the first synchronization circuit 141. The TCK signal input from TCK pin 182 can be input to the first synchronization circuit 141. The first synchronization circuit 141 and the second synchronization circuit 142 can be connected sequentially. Each of the first synchronization circuit 141 and the second synchronization circuit 142 can be or include a flip-flop. The output terminal of the first synchronization circuit 141 can be connected to the input terminal of the second synchronization circuit 142. The value stored in the first synchronization circuit 141 can be sent to the second synchronization circuit 142 based on the TCK signal.

[0070] The output signals of the first synchronization circuit 141 and the second synchronization circuit 142 can be input to the second circuit 144, respectively. The second circuit 144 can be implemented as an AND gate. The output signals of the second circuit 144 can be input to the third circuit 145 and the fourth circuit 146, respectively. The third circuit 145 and the fourth circuit 146 can be implemented as AND gates, respectively.

[0071] Selection circuit 147 can selectively provide the TMS signal and signal "1" received from TMS pin 183 to TAP controller 170 based on the output signal from third circuit 145. TAP controller 170 can send control signals to third circuit 145 and fourth circuit 146 in response to the signals received from selection circuit 147. The output signal of fourth circuit 146 can be provided to selection circuit 212 of active block BLK_A.

[0072] The TAP controller 170 can execute instructions stored in the TESTSETUP instruction register 150-1 based on JTAG signals received from the JTAG interface 180. Therefore, the TAP controller 170 can generate a first control signal CS1 based on the data SCAN_DUMP_CLK_STOP stored in the data register 160 corresponding to the TESTSETUP instruction register 150-1, and can send the generated first control signal CS1 to the clock management unit 130 and power management unit 120 of the active block BLK_A.

[0073] The clock management unit 130 can stop providing all clock signals to the multiple blocks 110-1 to 110-n in response to receiving the first control signal CS1. In addition, the power management unit 120 can fully turn on the power supply provided to the multiple blocks 110-1 to 110-n.

[0074] In this way, the TAP controller 170 can generate a first control signal CS1 for controlling the clock management unit 130 and the power management unit 120 based on the TMS signal and the data SCAN_DUMP_CLK_STOP stored in the data register 160.

[0075] According to some example embodiments, signals for controlling the power management unit 120 and the clock management unit 130 during debugging of a target block can be generated by using the TESTSETUP instruction register 150-1 included in JTAG port 140 and the data register 160 corresponding to the TESTSETUP instruction register 150-1, without having to add other pads besides the first pad P1 and the second pad P2 to the system-on-chip 100.

[0076] Figure 7 The accompanying drawings are flowcharts illustrating a debugging method for a system-on-a-chip according to some example embodiments. Figures 8 to 13 It is shown that it is used for Figure 7 A diagram illustrating the debugging method for the system-on-chip. It should be understood that additional embodiments of this method may be implemented... Figure 7 Additional operations are provided before, during, and after the operations described below, and some operations can be replaced or eliminated. The order of operations / procedures can be interchangeable, or two or more operations can be performed simultaneously. References will be made below. Figures 7 to 13 The accompanying drawings describe a debugging method for a system-on-a-chip according to some example embodiments.

[0077] First, refer to Figure 8 The TESTSETUP instruction can be stored in the instruction register 150, and the data SCAN_DUMP_CLK_STOP corresponding to the TESTSETUP instruction can be stored in the data register 160. Based on the TMS signal TMS and the data SCAN_DUMP_CLK_STOP stored in the data register 160, the TAP controller 170 can generate a first control signal CS1 and send the generated first control signal CS1 to the clock management unit 130 and power management unit 120 of the active block BLK_A.

[0078] The active block BLK_A may also include a JTAG pad 220. The JTAG pad 220 can receive signals output from the output terminal of a block selected as the target block from a plurality of blocks 110-1 to 110-k (where k is an integer of 2 or greater) included in the system-on-chip 100. The JTAG pad 220 can send the received output signal to the TDO pin 185 in the form of a TDO signal.

[0079] Subsequently, reference Figure 7, Figure 9 and Figure 10 The power management unit 120 can send a signal Sig1 to multiple blocks 110-1 to 110-k to turn on the power supply of the multiple blocks 110-1 to 110-k based on the first control signal CS1, and the clock management unit 130 can send a signal Sig2 to multiple blocks 110-1 to 110-k to stop the supply of the clock signal based on the first control signal CS1 (S100).

[0080] Subsequently, reference Figure 7 and Figure 11 The TAP controller 170 can select the target block (S110) from multiple blocks 110-1 to 110-k to perform the scan-dump method. The SELPARTITION instruction can be stored in the instruction register 150, and the data corresponding to the SELPARTITION instruction can be stored in the data register 160. The TAP controller 170 can generate a second control signal CS2 based on the TDI signal and the data stored in the instruction register 150 and the data register 160, and the TAP controller 170 can select, for example, block 110-2 as the target block based on the second control signal CS2.

[0081] Subsequently, reference Figure 7 and Figure 12 The TAP controller 170 can set multiple blocks 110-1 to 110-k to scan-dump mode (S120). The SCANDUMP instruction can be stored in the instruction register 150, and the data corresponding to the SCANDUMP instruction can be stored in the data register 160. The TAP controller 170 can generate a third control signal based on the data stored in the instruction register 150 and the data register 160 to set the multiple blocks 110-1 to 110-k to scan-dump mode, and the TAP controller 170 can send a scan-dump enable signal SCANDUMP_EN to the multiple blocks 110-1 to 110-k based on the third control signal. Therefore, the TAP controller can remove the values ​​loaded into each scan chain of the multiple blocks 110-1 to 110-k, including the target block 110-2.

[0082] Subsequently, reference Figure 7 and Figure 13 The TAP controller 170 can connect the target block to the JTAG pad 220 (S130). Therefore, the value removed from the scan chain of the target block (e.g., block 110-2) can be sent from the output terminal of the target block (e.g., block 110-2) to the TDO pin 185 in the form of a TDO signal.

[0083] refer to Figures 1-3 , Figure 5 , Figure 6 and Figures 8-14 Any or all of the elements described may be related to the reference. Figures 1-3 , Figure 5 , Figure 6 and Figures 8-14 Communication with any or all other elements described. For example, any element may communicate unidirectionally and / or bidirectionally and / or broadcastly with any or all other elements in any of the accompanying drawings to transmit and / or exchange and / or receive information such as, but not limited to, data and / or commands via a bus such as a wireless and / or wired bus in a serial and / or parallel manner. The information may be encoded in various formats, such as analog and / or digital formats, but is not limited thereto.

[0084] Figure 14 This is a diagram illustrating an electronic system including a system-on-a-chip according to some example embodiments.

[0085] include Figure 1 The electronic system digital 400 of the system-on-chip 100 shown can be implemented as a portable electronic device capable of using or supporting the Mobile Industry Processor Interface (MIPI®). The portable electronic device can be implemented as a smartphone, tablet PC, or mobile internet device.

[0086] Electronic system 400 may include application processor (AP) 410, image sensor 401, and display 430. Figure 14 The AP 410 can be implemented as Figure 1 The system-on-chip 100 shown is shown.

[0087] The camera serial interface (CSI) host 413 implemented in AP 410 can perform serial communication with the CSI device 403 of image sensor 401 via the camera serial interface CSI.

[0088] According to some example embodiments, the deserializer (DES) can be implemented in the CSI host 413, and the serializer (SER) can be implemented in the CSI device 403. The Display Serial Interface (DSI) host 411 implemented in the AP 410 can perform serial communication with the DSI device 431 of the display 430 via the display serial interface.

[0089] According to some example embodiments, the serializer SER can be implemented in the DSI host 411, and the deserializer DES can be implemented in the DSI device 431. Each of the deserializer DES and the serializer SER can process electrical signals or optical signals.

[0090] The electronic system 400 may also include a radio frequency (RF) chip 440 capable of performing communication with the AP 410. The physical layer (PHY) 415 of the AP 410 and the PHY 441 of the RF chip 440 may exchange data according to MIPI DigRF. The AP 410 may include a DigRF master 414 that initiates and controls communication, while the RF chip 440 may include a DigRF slave 442 that responds to commands and exchanges RF data accordingly.

[0091] Electronic system 400 may also include a GPS receiver 450, a memory 451, a data storage device 453, a microphone 455, and / or a speaker 457. The memory 451 and data storage device 453 may be “one or more computer-readable media” storing computer-readable program code for execution by AP 410. Such media can take many forms, including but not limited to non-volatile and volatile media. Non-volatile media include, for example, optical discs, magnetic disks, or flash memory (e.g., NAND flash memory). Volatile media include dynamic memory, such as dynamic random access memory (DRAM). Other forms of machine-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tape, any other magnetic media, CD-ROMs, DVDs, any other optical media, punched cards, paper tape, any other physical media with a perforated pattern, RAM, PROMs, EPROMs, flash memory EPROMs, any other memory chips or cartridges, or any other media that a processor (or computer) can read.

[0092] Electronic system 400 can communicate with external devices by using at least one communication protocol (or communication standard) such as Global Microwave Access Interoperability (WiMAX) 459, Wireless LAN (WLAN) 461, Ultra Wideband (UWB) 463 or Long Term Evolution (LTE) 465.

[0093] The electronic system 400 can communicate with external wireless communication devices using Bluetooth or WiFi.

[0094] Figure 15 This is a diagram illustrating an electronic system including a system-on-a-chip according to some example embodiments.

[0095] Electronic systems 500, 600, or 700 can be implemented as personal computers (PCs), data servers, or portable electronic devices. For example, electronic system 500 can be implemented as a laptop computer, electronic system 600 can be implemented as a smartphone or tablet PC, and electronic system 700 can be implemented as a digital camera.

[0096] Each electronic system 500, 600, or 700 is merely an example, and each electronic system 500, 600, or 700 can be implemented as a portable electronic device as follows.

[0097] Portable electronic devices can be implemented as laptops, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, portable multimedia players (PMPs), personal navigation devices (PNDs), handheld game consoles, mobile internet devices (MIDs), or e-readers.

[0098] Electronic systems 500, 600, or 700 include a processor 10-1, a power supply 510, a storage device 520, a memory 530, an input / output port 540, an expansion card 550, a network device 560, and / or a display 570.

[0099] Electronic system 500, 600, or 700 may also include camera module 580. Processor 10-1 may include... Figure 1 The system-on-a-chip 100 shown is a processor 10-1, which may be a multi-core processor.

[0100] The processor 10-1 can control the operation of at least one of the elements 510 to 580. The power supply 510 can supply operating voltage to at least one of the elements 10-1 and 520 to 580. The storage device 520 can be implemented as a hard disk drive or a solid-state drive (SSD). The memory 530 can be implemented as a non-volatile memory capable of storing program code that controls the operation of the processor 10-1, or as a volatile memory capable of storing data.

[0101] For example, non-volatile memory can be flash memory, embedded multimedia card (eMMC), or universal flash storage (UFS). Alternatively, volatile memory can be dynamic random access memory (DRAM).

[0102] According to some example embodiments, a memory controller capable of controlling data access operations (e.g., read operations, write operations, or programming operations) or erase operations of memory 530 may be integrated or embedded in processor 10-1.

[0103] According to some example embodiments, the memory controller may be implemented between the processor 10-1 and the memory 530.

[0104] Input / output port 540 may refer to a port capable of sending data to electronic system 500, 600, or 700, or sending data output from electronic system 500, 600, or 700 to an external device. For example, input / output port 540 may be a port for accessing pointing devices such as a computer mouse and touchpad, a port for accessing output devices such as a monitor 570 or printer, a port for accessing input devices such as a keypad or keyboard, or a port for accessing a USB flash drive.

[0105] The expansion card 550 can be implemented as a Secure Digital (SD) card, a Multimedia Card (MMC) card, or an eMMC card. According to some example embodiments, the expansion card 550 can be a Subscriber Identity Module (SIM) card or a Universal Subscriber Identity Module (USIM) card.

[0106] Network device 560 can refer to a device that can connect electronic system 500, 600 or 700 to a wired or wireless network for communication between electronic system 500, 600 or 700 and the outside world.

[0107] The display 570 can display data output from storage device 520, memory 530, input / output port 540, expansion card 550 or network device 560.

[0108] Camera module 580 can refer to a module capable of converting optical images into electrical images. Therefore, the electrical images output from camera module 580 can be stored in storage device 520, memory 530, or expansion card 550. Furthermore, the electrical images output from camera module 580 can be displayed on display 570.

[0109] As described herein, any device, system, module, part, unit, controller, circuit and / or part and / or any portion thereof (including but not limited to JTAG interface 180, JTAG port 140, power management unit 120, clock management unit 130, TAP controller 170, instruction register 150, data register 160, debugger 200, response server 300, multiple blocks 110-1 to 110-n, active block BLK_A, test mode block 210, electronic system 400, application processor (AP) 410, image sensor 401 and display 430, camera serial interface (CSI) host 413, display serial interface (DSI) host 411, radio frequency (RF) chip 440, physical layer (P... The following components may include: HY) 415, DigRf master controller 414, DigRf slave controller 442, GPS receiver 450, microwave access (WiMAX) 459, wireless LAN (WLAN) 461, ultra-wideband (UWB) 463, long-term evolution (LTE) 465, processor 101, power supply 510, storage device 520, memory 530, input / output port 540, expansion card 550, network device 560, display 570, and camera module 580, and any part thereof) may include one or more instances of processing circuitry, may be included in one or more instances of processing circuitry, and / or may be implemented by one or more instances of processing circuitry, such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field-programmable gate array (FPGA) and programmable logic units, a microprocessor, an application-specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., a memory), such as a solid-state drive (SSD), storing instruction programs, and a processor (e.g., a CPU) configured to execute instruction programs to implement functions and / or methods performed by some or all of any device, system, module, section, unit, controller, circuit, and / or portions thereof according to any example embodiment.

[0110] Any of the elements and / or functional blocks disclosed above may include or be implemented in processing circuitry, such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. Processing circuitry may include at least one electronic component, such as a transistor, a resistor, a capacitor, etc. Processing circuitry may include electrical components, such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

[0111] While several embodiments have been provided in this disclosure, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of this disclosure. These examples are intended to be illustrative rather than restrictive and are not intended to be limited to the details given herein. For example, various elements or components may be combined or integrated into another system, or certain features may be omitted or not implemented.

Claims

1. A system-on-a-chip, comprising: Multiple blocks, each including input terminals and output terminals, and each including multiple synchronization circuits connected by a scan chain; Test data input to TDI line; The test data output TDO line is connected to the output terminal; The Test Access Port (TAP) controller is configured to control the operation of the plurality of blocks based on the TDI signal input to the TDI line, the TDO signal input to the TDO line, the Test Clock (TCK) signal, the Test Reset (TRST) signal, and the Test Mode Selection (TMS) signal. A power management unit is configured to control the power gating of the plurality of blocks; and The clock management unit is configured to control the clock signals provided to the plurality of blocks, wherein, The TAP controller includes a first register configured to store first data for generating a first control signal, the first control signal being configured to control the power management unit and the clock management unit. The power management unit and the clock management unit are configured to control the operation of the plurality of blocks based on the first control signal received from the TAP controller.

2. The system-on-a-chip according to claim 1, wherein, The power management unit is configured to switch on power to the plurality of blocks based on the received first control signal, and The clock management unit is configured to stop providing clock signals to the plurality of blocks based on the received first control signal.

3. The system-on-a-chip according to claim 1, wherein, The TAP controller further includes a second register configured to store second data for generating a second control signal, the second control signal being configured to control the operation of the plurality of blocks. The TAP controller is configured to select the target block from the plurality of blocks to perform the scan dump method based on the second control signal, and The second data is different from the first data.

4. The system-on-a-chip according to claim 3, wherein, The TAP controller further includes a third register configured to store third data for generating a third control signal, the third control signal being configured to control the operation of the plurality of blocks. The TAP controller is configured to send a scan dump enable signal to the plurality of blocks based on the third control signal, for setting the plurality of blocks to scan dump mode. The TAP controller is configured to remove the value loaded into the scan chain of the target block based on the scan dump enable signal, and The third data is different from each of the first data and the second data.

5. The system-on-a-chip according to claim 4, wherein, The TAP controller further includes a fourth register configured to store fourth data for generating a fourth control signal configured to control the operation of the target block. The TAP controller is configured to output the value removed from the scan chain of the target block via the TDO line connected to the output terminal of the target block based on the fourth control signal. The fourth data is different from each of the first data, the second data, and the third data.

6. The system-on-a-chip of claim 1, further comprising an active block configured to control the operation of the plurality of blocks. in, The active block includes: The power management unit; and The clock management unit.

7. The system-on-a-chip according to claim 6, wherein, The active block also includes a Joint Test Action Group (JTAG) pad, which is configured to send signals from the output terminal to the TDO line.

8. The system-on-a-chip according to claim 6, wherein, The active block also includes: The pads are configured to receive a test mode enable signal for entering test mode; and The latch circuit is configured to receive the test mode enable signal.

9. A system-on-a-chip, comprising: Multiple blocks, each including input terminals and output terminals, and each including multiple synchronization circuits connected by a scan chain; A power management unit is configured to control the power gating of the plurality of blocks; A clock management unit is configured to control the clock signals provided to the plurality of blocks; and The Test Access Port (TAP) controller is configured to control the operation of the plurality of blocks based on a Test Data Input (TDI) signal synchronized with the Test Clock (TCK) signal and the Test Mode Selection (TMS) signal, and includes a first register configured to store first data for controlling the power management unit and the clock management unit, wherein... The TAP controller is configured to generate a first control signal, which is configured to control the power management unit and the clock management unit based on the TMS signal and the first data. The power management unit is configured to switch on power to the plurality of blocks based on the first control signal, and The clock management unit is configured to stop providing clock signals to the plurality of blocks based on the first control signal.

10. The system-on-a-chip of claim 9 further includes a Joint Test Action Group (JTAG) interface, the JTAG interface including a TDI pin to which the TDI signal is input, a Test Data Output (TDO) pin to which the TDO signal is output, a TCK pin to which the TCK signal is input, and a TMS pin to which the TMS signal is input.

11. The system-on-a-chip according to claim 9, wherein, The TAP controller further includes a second register configured to store second data that is different from the first data. The TAP controller is configured to generate a second control signal, which is configured to control the operation of the plurality of blocks based on the TDI signal and the second data. The TAP controller is configured to select the target block from the plurality of blocks to perform the scan dump method based on the second control signal.

12. The system-on-a-chip according to claim 11, wherein, The TAP controller further includes a third register configured to store third data that is different from each of the first data and the second data. The TAP controller is configured to generate a third control signal, which is configured to control the operation of the plurality of blocks based on the third data. The TAP controller is configured to send a scan dump enable signal to the plurality of blocks based on the third control signal, for setting the plurality of blocks to scan dump mode.

13. The system-on-a-chip according to claim 12, wherein, The TAP controller is configured to remove values ​​loaded into the scan chain of the target block based on the scan dump enable signal. The TAP controller further includes a fourth register that stores fourth data that is different from each of the first data, the second data, and the third data. The TAP controller is configured to generate a fourth control signal, which is configured to control the operation of the target block based on the fourth data. The TAP controller is configured to output the value removed from the scan chain of the target block to the TDO pin via the output terminal of the target block based on the fourth control signal.

14. The system-on-a-chip of claim 13, further comprising an active block configured to control the operation of the plurality of blocks. in, The active block also includes a Joint Test Action Group (JTAG) pad configured to send the value removed from the scan chain of the target block out of the on-chip system, wherein the value removed from the scan chain of the target block is output from the output terminal of the target block.

15. The system-on-a-chip according to claim 14, wherein, The active block also includes: The power management unit; and The clock management unit.

16. A debugging method for an on-chip system, the on-chip system comprising multiple blocks, each including an input terminal and an output terminal and each including multiple synchronous circuits connected by a scan chain, the debugging method comprising: The debug request signal is received by the test access port (TAP) controller; The TAP controller sends a first control signal, generated based on the test mode selection TMS signal and the first data, to the power management unit and the clock management unit based on the debug request signal; The power supplied to the plurality of blocks is turned on by the power management unit based on the first control signal; and The clock management unit stops providing all clock signals to the plurality of blocks based on the first control signal. The TAP controller includes a first register that stores first data for controlling the power management unit and the clock management unit.

17. The debugging method according to claim 16, further comprising: The TAP controller generates a second control signal for controlling the operation of the plurality of blocks based on the test data input TDI signal and second data that is different from the first data; and The TAP controller selects the target block from the plurality of blocks to perform the scan dump method based on the second control signal. The TAP controller further includes a second register for storing the second data.

18. The debugging method according to claim 17, further comprising: The TAP controller generates a third control signal for controlling the operation of the plurality of blocks based on third data that is different from each of the first data and the second data; The TAP controller sends a scan dump enable signal to the plurality of blocks based on the third control signal to set the plurality of blocks to scan dump mode; and The TAP controller removes the value loaded into the scan chain of the target block based on the scan dump enable signal.

19. The debugging method according to claim 18, further comprising: The TAP controller generates a fourth control signal for controlling the operation of the target block based on fourth data that is different from each of the first data, the second data, and the third data; and The TAP controller outputs the value removed from the scan chain of the target block via the TDO line connected to the output terminal of the target block based on the fourth control signal.

20. The debugging method according to claim 19, wherein, The system-on-a-chip also includes a Joint Test Action Group (JTAG) pad, and the debugging method further includes sending signals output from the output terminals of the plurality of blocks via the JTAG pad to the TDO line. The value removed from the scan chain of the target block by the JTAG pad is sent to the TDO line.

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